L05 – Logic Synthesis 16.004 - Fall 2002 9/19/02

Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs

I 00

I 01

I 10

I 11

AB

AB

AB

AB

Y

Decoder Selector Multiplexerscan be partitionedinto two sections. A DECODER thatidentifies thedesired input,and a SELECTOR that

enables that input

onto the output.

A decodergeneratesall possibleproductterms fora set ofinputs

0

1

2

3

L05 – Logic Synthesis 26.004 - Fall 2002 9/19/02

Shared Decoding Logic

0 2 3 4 5 6 71

A B Cin

S

Cout

There’s anextra levelof inversion

that isn’tnecessary

in the logic. However,it reduces

the capacitiveload on the

module drivingthis one.

These are just “DeMorgan”ized

NOR gates

Made from PREWIRED connections , and CONFIGURABLEconnections that can be either connected or not connected

We can build a general purpose “table-lookup” device calleda Read-Only Memory (ROM), from which we can implementany truth table and, thus, any combinational device

Decoder

Configurable Selector

This ROM stores 16 bitsin 8 words of 2 bits.

Fixed “AND plane”

Configurable “OR plane”

L05 – Logic Synthesis 36.004 - Fall 2002 9/19/02

ROM-Based Design

• Once we’ve written out the truth table we’ve basically finished the design

Possible optimizations:

- Addressing tricks

Truth Table for a 7-sided Die

- Eliminate redundant outputs

A B C T U V W X Y Z

0 0 0 0 0 0 0 0 0 00 0 1 0 0 0 1 0 0 00 1 0 0 1 0 0 0 1 00 1 1 0 1 0 1 0 1 01 0 0 1 1 0 0 0 1 11 0 1 1 1 0 1 0 1 11 1 0 1 1 1 0 1 1 11 1 1 1 1 1 1 1 1 1

T

V X

U

Y Z

W

L05 – Logic Synthesis 46.004 - Fall 2002 9/19/02

Standard Cells• First, a library of fixed-pitch logic cells (gates,

registers, muxes, adders, I/O pads, …) are created. A data sheet for each cell describes its function, area, power, propagation delay, output rise/fall time as function of load, etc.

AOI.21A B C

Z

D Q

DREG

L07 – FSMs 56.004 – Fall 2002 9/26/02

Now put it in Hardware!

ROM 16x4

unlock

Next stateCurrent state

IN

Trigger update periodically (“clock”)

33

4 inputs 24 locationseach location supplies 4 bits

We assume inputs are

synchronized with clock…