cec 220 digital circuit design timing diagrams, muxs, and buffers friday, february 14 cec 220...
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CEC 220 Digital Circuit DesignTiming Diagrams, MUXs, and Buffers
Friday, February 14 CEC 220 Digital Circuit Design Slide 1 of 18
Lecture Outline
Friday, February 14 CEC 220 Digital Circuit Design
• Timing Diagrams• Multiplexers• Tri-State Buffers
Slide 2 of 18
Timing Diagrams
Friday, February 14 CEC 220 Digital Circuit Design
• Problem: Real signals do NOT change instantaneously Real hardware (i.e. gates) do not respond immediately
• Resolution: Look at the signals vs time Timing diagrams!!
Slide 3 of 18
Timing DiagramsEffect of Gate Delays
Friday, February 14 CEC 220 Digital Circuit Design
• Consider the simple circuit: Assume that all gates have
a 10 ns delay
The outputs may not be defined at the start!!Slide 4 of 18
0 50 100 150
Timing DiagramsHazards in Combinational Logic
Friday, February 14 CEC 220 Digital Circuit Design
• Glitches: The inverter has a 10 ns delay The AND gate has a 5 ns delay
A
B
C
Ideally, . In the “real world” glitches occur!!
Slide 5 of 18
Timing DiagramsHazards in Combinational Logic
Friday, February 14 CEC 220 Digital Circuit Design Slide 6 of 18
A Static 1-Hazard A Static 0-Hazard
Dynamic Hazards
MultiplexersA 2:1 Multiplexer
Friday, February 14 CEC 220 Digital Circuit Design
• A Multiplexer (or data selector) uses a control input(s) to select one of multiple inputs.
Z = I0 if is true, orZ = I1 if is true
Z = I0 + I1
Z
I0
I1
Slide 7 of 18
Multiplexers4:1 and 8:1 Multiplexers
Friday, February 14 CEC 220 Digital Circuit Design
2n inp
ut d
ata
lines
n select lines0 1 2 3Z I AB I AB I AB I AB
Slide 8 of 18
4:1 MUX
0
1
2
30S
1S
I0
I1
I2
I3
A B
Z
Dat
a In
puts
Control Inputs
MultiplexersAn Example
Friday, February 14 CEC 220 Digital Circuit Design
• Problem: Use an 8:1 MUX to implement the following truth table.
A B C Z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Slide 9 of 18
Buffers
Friday, February 14 CEC 220 Digital Circuit Design
• Problem: Real world gates have limited output current drive
capability
The OR gate may NOT be able toDrive all of the AND gates
Solution: Use a buffer
Slide 10 of 18
Tri-State Buffers
Friday, February 14 CEC 220 Digital Circuit Design
• A Tri-State or Three-State buffer Output can be low, high, or high impedance (High-Z)
Slide 11 of 18
Tri-State Buffers
Friday, February 14 CEC 220 Digital Circuit Design
• Four kinds of Tri-State State buffers Output can be low (0), high (1), or high impedance (Z)
Slide 12 of 18
Tri-State Buffers
Friday, February 14 CEC 220 Digital Circuit Design
• Can use tri-state buffers to build a MUX:
When B is low select A, orWhen B is high select C
Slide 13 of 18
Tri-State Buffers
Friday, February 14 CEC 220 Digital Circuit Design
• Problem: IC’s have a limited number of pins Can use a given pin for either input or output
Slide 14 of 18
Examples
Friday, February 14 CEC 220 Digital Circuit Design
• Realize a 4:1 MUX, using an 8:1 MUX.
Slide 15 of 18
Examples
Friday, February 14 CEC 220 Digital Circuit Design
• Make an 8:1 MUX, using four 2:1 & one 4:1 MUX
Slide 16 of 18
Examples
Friday, February 14 CEC 220 Digital Circuit Design
• Use an 8:1 MUX to implement the function f = A’B’C’ + A’BC’ + A’BC + ABC.
A B C f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Slide 17 of 18
Examples
Friday, February 14 CEC 220 Digital Circuit Design
• Use an 4:1 MUX to implement the function f = A’B’C’ + A’BC’ + A’BC + ABC.
A B C f
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Slide 18 of 18
Next Lecture
Friday, February 14 CEC 220 Digital Circuit Design
• Decoders and Encoders• Read-Only Memories (ROMs)
Slide 19 of 18