kgd or ptd? - global semiconductor alliance · kgd – a die that is as good as a packaged part...
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John Carulli, TM Mak For GSA 3D workgroup, July 15, 2015
KGD or PTD?
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GLOBALFOUNDRIES Confidential 2
2.5D, 3D? What?, Ira Feldman, SVTC2011
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KGD – a die that is as good as a packaged part
GLOBALFOUNDRIES Confidential 3
2.5D, 3D? What?, Ira Feldman, SVTC2011
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With KGD, a high yielding 2.5D/3D module is possible
GLOBALFOUNDRIES Confidential 4
2.5D, 3D? What?, Ira Feldman, SVTC2011
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Wafer sort: making a good (temporary) electrical contact?
5
Tungsten Needle
12...35µm
1. Touch the pad or bump. 2. In order to get a good
electrical contact between needle and pad or bump the wafer moves up about 75µm = 75µm overdrive. 75 / 100µm
Cobra Needle
Al / Cu Pad
Bump
80 - 100µm
75µm
Silicon 60 x 80µm²
Prober Chuck
100 x 100µm²
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The sort hardware stack
GLOBALFOUNDRIES Confidential 6
lower die
upper die
MLC / MLO
PCB
Wafer this side
ATE (tester) this side
No impedance control, inductive
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Probe Card Technologies
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Cantilever Probe Cards Rows of needles,
mostly on Al-Pads, Pitch 50 – 500um
Pogo Pin Appl.: WLCSP
led & led free bumps Pitch 250 – 500um
Cobra Appl.: BGA
led & led free bumps Pitch 135 – 245um
Vertical MEMS Appl.: Cu-Pillar w & w/o Cap
Pitch 130 – 80um
Vertical MEMS Appl.: TSV, MicroB.
not in prod. Pitch 40 – 60um
Advanced Probe Cards For Arrays
Proven Technology New Technology
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KGD is possible for DRAM
• Low power (relatively), inductive probes not a concern
• Low pincount Test port (with DFT) to test internal arrays
• Already highly parallel sort (>256); WLBI (Wafer Level Burn-In) possible
• Bad cells are repaired
• Low IO speed (DFT self test possible)
GLOBALFOUNDRIES Confidential 8
For products with similar attributes, KGD is possible
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But Moore’s Law invisible hand….
Integration ↑ >> functionality ↑ >> higher IO count ↑ >> tighter pitch ↓
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Probing trend
July 20, 2015 10 Confidential
Solder bump
Copper pillar
0
20
40
60
80
100
120
140
160
10100Process node (nm)
Pitch (um)Diameter (um)
HBM/WideIO
Probe also must shrink along with pitch !
Microbumps/ landpads
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Probe contact area
0.050.0
100.0150.0200.0250.0300.0350.0400.0450.0500.0
0 10 20 30
11
~10%
Probe diameter
Probe x-sectional area
10-12g
5mil
4mil 3.5mil
3mil
2.5mil
2mil 1.5mil
9-11g 7-9g 5-7g 3-4g 12-15g 16-20g
180 210 95 120 140 165 75 75 100 125 150 175 200 225 Target Pitch
Min. Pitch
Little HVM experience Generally Proven Diameter Gram Force
May not work ? ! ?
Probe contact area shrink at square of pitch !!
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Fighting physics
• Probes have to be strong yet highly conductive – Conductive metals are all “soft” – Strong hard metal are much worse
with conductance – Metallurgy challenge (multi-layers)
• To provide good conductance, the probe have to indent/scrub away some material to get below the surface – SnAg may be mass reflow to re-
surface – Other bump/pad material (e.g. Cu
or NiAu) not so; potentially a much bigger issue
July 20, 2015 12
Probe Technology does not scale well
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Why wafer probe cannot match packaged part test?
• Inductive power probes worsen PDN (power distribution network) – Gate slow down with sudden gate activities –
scan shift; launch/capture – Multiple MBIST running – Depopulation of probes (forced by cost
reduction) make it even worse
• Inductive probes and ATE limitation also impact signal integrity – Uncontrolled impedance – Long route to ATE pin-electronics – ATE loading far exceed HBM/WIO2 loading
• Prober cannot control individual die temperature
• ATE cannot match HBM’s pincount – 4 HBM is >5000 pins
• ATE/handler/prober cannot handle 2 sided probing (3D or silicon interposer)
GLOBALFOUNDRIES Confidential 13
Probe chuck: Limited temperature sensing spot
IO area: 220(row)x24(col)
HBM ASIC xPU
Single HBM site
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“Promising” technologies abound…
July 20, 2015
Advantest’s MEMS beam array
Cascade’s RBI FormFactor’s NanoPierceTM
Some have very short (high performance) probes
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BUT there are limitations & issues
• Light probe force – Good probe marks, no impact to
assembly – Poor Rcontact (or Cres) – Cannot deliver high A – Uniformity of probe contact across
die also can cause current crowding, which lead to probe burns
• Probe card with 30,000 probes will be very expensive – Average 30-50k µbumps would be
common – Designer taking advantage of these
many bumps as well – With ~$10/probe, >> $300K-$500K
per card; Care for signing M$ PO for probe cards?
GLOBALFOUNDRIES Confidential 15
GPU gems 2 : programming techniques for high-performance graphics and general-purpose computation / edited by Matt Pharr, et. al
With Vcc < 1V; pushing 200A !
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2.5D is largely driven by performance segment
• Bandwidth/Performance driven architecture – 1TB/s is the holy grail – 512B*2 Gbps -- Go wide rather go
narrow – 4 HBM stacks is 512B (4096DQ
with 1024 DQ per stack)
• 2.5D ASIC/xPU are – Large die – High µbump counts (30-50,000) – High power, requires >200A – Runs hot
GLOBALFOUNDRIES Confidential 16
AND you want KGD for your 2.5D module?
AMD’s Fiji
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Promising Tested Die (PTD) methodology
• Probe on sacrificial pads (or test pads) instead of µbumps – Use regular probes (keep cost down) – Fewer pads than µbumps; but keep ratio above 10%
• Low toggle ATPG; fewer scan chains tested simultaneously – Test time would be longer
• MBIST run at lower speed and/or fewer arrays run simultaneously
• Non-contact IO DFT to cover for low power (weak) die-to-die IO – HBM IO
• Defer speed/power binning tests to partial module test – Bond ASIC/xPU die to interposer first before other HBM bonding
• Burn-in at the full module level with HBM powered down
GLOBALFOUNDRIES Confidential 17
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Déjà vu, have we seen this before?
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Back to the future?
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IBM’s MCM
With a carrier, dies can be tested (in a real package), burnt-in, before removal for mounting in a MCM
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KGD, Sandia Lab?
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Can you imagine that even government lab is there to help you with KGD?
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DieMate die carrier
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Roadmaps of Packaging Technology 1997, Chapter 12, Multichip Modules (MCMs), ICE http://smithsonianchips.si.edu/ice/cd/PKG_BK/CHAPT_12.PDF
It is a museum piece now
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Die Carrier based testing re-surfaced?
GLOBALFOUNDRIES Confidential 22
Getting to Known Good Stacks, G. Fleeman, SVTC 2012
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Shown at Advantest Expo…not vaporware?
GLOBALFOUNDRIES Confidential 23
Getting to Known Good Stacks, G. Fleeman, SVTC 2012
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Redundancy & repair – not just for memory
GLOBALFOUNDRIES Confidential 24
AMD’s Triple core Phenom
nVidia Fermi 480 cores from 512 physical cores
8 physical SPE, 7 used by OS/Apps
Up to 10 cores! 6, 8 cores SKU as well
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Infield self test and re-configuration – in lieu of burn-in
GLOBALFOUNDRIES Confidential 25
Chip as shipped (no BI)
operation POST Periodic
self-test p
Re-configura
ble? Re-
configurable? y y
n n
p
f f
System down System down
Architecture that includes POST/Periodic self-test (before failure) & reconfigure itself to allow continuous operation (maybe at a degraded performance level)
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We cannot test our way out for KGD; architecture (redundancy/POST/P-ST) & design (DFT) will enable Promising Tested Die (PTD) to support 2.5/3D integration
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Backup
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Cascade Microtech’s RBI
• Rocking Bucking I?
• Enhanced version of “Pyramid” – Pyramid is now on a small beam
that allows it to rock a little – Scalable tip pitch (down to ~20um) – Low probe force (<1gf/tip) – Scrub mark a PASS
28 Direct Micro-Bump Probing on Wide-I/O 1; Erik Jan Marinissen, IMEC, Aug 20, 2013
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Material is also compliant (i.e. compressible)
Very Low Damage Direct Testing of Microbumps for 3D IC Integration Onnik Yaglioglu, 3D Test Workshop 2013
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Advantest’s MEMS probe
• Aims to have enough probe compliance to manufacturing variance for DUT wafers or probe card fabrication
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A Low-Force MEMS Probe Solution For Fine-Pitch 3D-SIC Wafer Test Matthew W. Losey, Touchdown Technologies, Advantest, 3D Test Workshop 2011