keysight 1gc1-4180 dc to 12 ghz multi-modulus prescaler
TRANSCRIPT
Keysight 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler
Data Sheet
Features – Multi-modulus (ECL selectable)•
Divide by 2,4,8, or 16 plus pass-through mode
– Input frequency range: 0.07 to 12 GHz (sinewave input) DC to 12 GHz (squarewave input)
– Two selectable, differential inputs – Six differential outputs – On-chip 50 Ω matching – High input power sensitivity:
On-chip pre- and post-amps –20 to +10 dBm (typ. 0.07 to 6 GHz) –15 to +10 dBm (typ. 6 to 9 GHz) –10 to +10 dBm (typ. 9 to 12 GHz)
– Variable Pout [Vout] control: < -25 through 6.0 dBm [< 0.025 to 1.0 Vp–p]
– Input disable function – Low Phase noise:•
–153 dBc/Hz @ 100 kHz offset – Single, negative bias supply
operation:•wide –4.5 to –5.5 volt operating range
– Chip size: 2210 x 860 um (87.0 x 33.9 mils)
– Chip Size tolerance: ±10 um (±0.4 mils)
– Chip thickness: 127 ±5 um (5 ±0.6 mils)
– Pad dimensions: 70 x 70 um (2.8 x 2.8 mils)
Description
The 1GC1-4180 prescaler offers broadband frequency translation for use in commu-nications and EW systems incorporating high-frequency PLL oscillator circuits and signal–path down conversion applications. The selectable, dual-differential input prescaler provides multiple–modulus division and input signal pass–through capabilities to each of six differential outputs as well as a large input sensitivity window, and low phase noise. In addition to the features listed above the device offers variable output amplitude control and an input disable contact pad to eliminate any false triggers or self–oscillation conditions. It is fabricated using the Keysight Technologies, Inc. InGaP/GaAs HBT process, which combines high performance with instrument grade reliability.
Absolute maximum ratings
Continuous operation1 Damage limit2
Symbol Parameters/conditions Min Max Min Max Units
VEE1,2,3 Bias supply voltage –5.5 +0.5 Volts
VSEL RF input select voltage –5.5 +0.5 Volts
VA1,A2,A3 Modulus select voltage VEE +0.5 Volts
VADJ(1-6) RF output amplitude control voltage VEE +0.5 Volts
VDISABLE Pre-amp disable voltage VEE +0.5 Volts
VLOGIC Logic threshold voltage –1.5 –1.2 Volts
Pin(CW) CW RF input power +10 dBm
VRFin1,2 DC input voltage (@ RFin1,2 or RFin1,2, ports)
±1.0 Volts
Tbs Chip backside temperature −40 +65 °C
Tstg Storage temperature –65 +150 °C
Tmax Maximum assembly temp. (for 60 minutes maximum)
+150 °C
1. Parameters specified for continuous operation at Tbs ≤ 65 °C., Operation in excess of any one of these conditions may result in performance and reliability degradation to this component. MTTF degrades by a factor 2 for every 10 degree increase in operating temperature greater than Max. Tbs
2. Operation in excess of any one of these conditions may result in permanent damage to this component.
02 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
DC specifications/physical properties1,2
(TA = 25 °C, VEE = −5.0 volts, unless otherwise listed)
Symbol Parameters/conditions Min Nom Max Units
VEE1,2,33 Bias supply operating voltage range –4.5 –5.0 –5.5 Volts
IEE Total bias supply current (VADJ1-6 = O.C.) 280 mA
VSELECT3 Input port select control voltage –5.0 0.0 Volts
ISELECT Input select current (VSEL = VEE) 0.0 0.5 mA
VA1,A2,A33 Modulus select control voltage –5.0 0.0 Volts
IA1,A2,A3 Modulus select current (VA1,2,3 = VLOGIC – 2.0) 1.0 0.0 mA
VADJ(1-6)3 Output amplitude adjust voltage –5.0 5.0 Volts
IADJ(1-6) Amplitude adjust current (VADJ1-6 = VEE) 1 mA
VDISABLE Input disable control voltage –2.7 Volts
IDISABLE Input disable current (VDISABLE = VEE) 1 mA
VRFin,RFout(q) Quiescent DC voltage appearing at all RF ports 0.0 Volts
VLOGIC Nominal ECL logic level (On-chip, self–biased ECL–threshold voltage) –1.5 –1.35 –1.2 Volts
1. Parameters specified at TA= 25 °C, except for temperature specs. All current polarities positive into MMIC. O.C. = Open Circuit.2. Prescaler will operate over full specified supply voltage range. V2.EE not to exceed limits specified in Absolute maximum ratings section.3. VEE2,3 are additional, optional contact pads that can be used to feed the supply voltage to the device to reduced DC resistive losses
Frequency-domain RF specifications1
(TA = 25 °C, RLOAD = 50 Ohms at all RF ports to 0 V, bias: VEE = −5.0 V, VADJ = VDISABLE = O.C.)
Symbol Parameters/conditions Min Nom Max Units
NRatio Divide modulus, N: ƒout = ƒin/N, pass-through: N = 1 1,2,4,8, or 16 GHz
ƒRFin(max) Maximum input frequency of operation2 (Pin = 0 dBm, modulus = 1) 8 GHz
Maximum input frequency of operation (Pin = 0 dBm, modulus ≥ 2) 14 GHz
ƒRFin(min) Minimum input frequency of operation3 (Pin = 0 dBm) 0.07 0.3 GHz
ƒSelf–Osc Output self-oscillation frequency4 13.6 / N GHz
RL Small-signal input/output return loss (@ƒin < 12 GHz) 15 dB
S12 Small-signal reverse isolation (@ƒin < 12 GHz) 30 dB
PRFin DC, (square-wave input) –35 to > +10 +10 dBm
ƒin= 500 MHz, (sine–wave input) –35 to > +10 +10 dBm
ƒin = 0.5 to 1 GHz –10 –34 to > +10 +10 dBm
ƒin = 1 to 4 GHz –10 –27 to > +10 +10 dBm
ƒin = 4 to 8 GHz –10 –17 to +10 +10 dBm
ƒin = 8 to 12 GHz –11 to +4.5 dBm
POUT ƒout< 1 GHz, 0.5 dBm
ƒout = 4 GHz –3.0 0.5 dBm
ƒout = 8 GHz 0.5 dBm
PSPITBACK Output frequency power level appearing at RFin or RFin ports. (@ ƒin 12 GHz, N > 1, unused RFout unterminated)
–35 dBm
Power level of output signal appearing at RFin or RFin ports. (@ ƒin 12 GHz, N>1, Unused RFout terminated into 50 W)
–55 dBm
PFEEDTHRU Power level of input signal appearing at RFout or RFout (@ ƒin= 12 GHz, Pin = 0 dBm, Referred to Pin(ƒin), N > 1)
25 dBc
H2 Second harmonic distortion output level (@ ƒout = 3.0 GHz, Referred to Pout(ƒout)) 22 dBc
1. All data obtained via single-ended I/O operating mode with unused RF I/O ports terminated into 50 ohms. S.E. = Single-Ended, DIff. = Differential..2. For output amplitudes with less than 3 dB roll–off from 1 GHz output power values. RF ports are DC coupled. Device may be operated continuously in a fully switch 2.manner at DC.3. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.4. N = Divide Modulus. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of
the Pre-amp Disable (VDISABLE) feature, or the Differential Input de-biasing techniques.
03 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Figure 1. 1GC1-4180 simplified schematic
MUXMUXMUX
* Refer to 1GC1-4021 Data Sheet for detailed schematic
Divide by 1,2,4,8,16 Multi-modulus divider core*
Disable VEE VLOGIC
A1 A2 A3
VADJ 1-5
VADJ 6
SEL
RFin 1
RFin 1
RFin 2
RFin 2
Out 1
Out 1
Out 2
Out 2
Out 3
Out 3
Out 4
Out 4
Out 5
Out 5
Out 6
Out 6
Time-domain AC specifications1
(TA = 25 °C, RLOAD = 50 Ohms at all RF ports to 0 V, bias: VEE = −5.0 V, VADJ = VDISABLE = O.C., VRFin, VRFin = −0.25 V [unless otherwise specified])
Symbol Parameters/conditions Min Nom Max Units
Clock rate All full-rate clock frequencies through OC–192 NRZ 0 12 GHz
|VOUT(P–P)| ƒout < 1 GHz (squarewave output) 500 mV
ƒout = 4 GHz (squarewave output) 350 500 mV
ƒout = 8 GHz (sinewave output) 670 mV
Tr/TF Rise and fall time 35 pSec
JINT(RMS) Additive random (intrinsic) RMS jitter (50% data crossing point, 8 GHz, 1010 pattern)
390 fSec
JINT(P–P) Additive random (intrinsic) peak–peak jitter(50% data crossing point, 8 GHz, 1010 pattern)
2.2 pSec
1. Data obtained via Keysight 81250 43 Gb/s parBERT series Data Pattern Generator and Keysight 86100B Digital Communications Analyzer with low jitter time base option and 86118A 70 GHz remote sampler head plug-in module. Jitter and rise/fall times listed are deconvolved from measurements using the following formula: Tr/Tf DUT actual = [(tr/tf DUT Meas.)2 – (tr/tf System)2]1/2. Test equipment Tr/Tf limit ~5.4 pSec. System jitter RMS limit ~300 fSec(1010 pattern).
04 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Applications
The 1GC1-4180 is designed for use in high frequency communication systems and EW radar systems where Multi I/O, low phase-noise PLL control circuitry or broad-band frequency translation is required.
Device Architecture
The simplified schematic of the device is shown in Figure 1.
One of two independent differential input ports can selected to drive an internal multi-mod-ulus prescaler with the ability to pass the input signal to the output without division or divide the signal by either 2,4,8, or 16, depending on the A1, A2, A3 selection line bias.
The output of the prescaler drives six identical differential output ports simultaneously however the output amplitude can be adjusted via the VADJ control lines for all output ports. Two independent amplitude control lines are provided, one for outputs 1-5 and a separate line for output 6.
An additional DISABLE contact is also provided to lock the input preventing the device from false triggering or producing any unwanted self-oscillation output signals.
All RF I/O ports are DC-coupled and terminated to GND via on-chip 50 Ω resistors, however, the device will operate with AC coupling on any of the RF ports.
Basic Biasing and RF Operation
Since VCC is grounded on-chip (via conductive back-side vias), the device operates from a single, negative bias supply, connected to the VEE contact. A unique bias-leveling topology, employed on-chip, allows the device to operate with any voltage between –4.5 to –5.5 volts applied to VEE.
The device will provide pass- through or prescaling for either sinusoidal or square-wave input signals between 70 MHz and 12 GHz with good input sensitivity above 300 MHz. The output amplifier response provides flat output power over a DC to 6 GHz bandwidth with an upper –3 dB point of ~ 9 GHz. Below 300 MHz, the prescaler input is slew–rate limited requiring larger amplitudes or fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to DC when driven with a square-wave as along as the slew-rate is greater than 0.14 V/nS or 10% - 90% edge speeds of ~ 5 nS.
05 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Control Features
The 1GC1-4180 provides several signal routing and conditioning control features including RF input select, divider modulus select, RF input disable, and variable output power control. Several of these controls have specific logic state conditions and bias ranges restrictions and are summarized in Table 1.
Modulus selectBy applying a Logic “1” (High) voltage of 0.0V or Logic “0” (Low) voltage equal to VEE, the device will operate in either pass–through mode (with unity divide modulus) or at any of four different divide ratios including 2,4,8, or 16 according to following table:
Input selectTwo independent differential RF input ports are available on the 1GC1-4180. The RF path is connected to the “RFin 1” port by default when no external bias is supplied to the SELECT control line (O.C.) or, when the VSELECT line is pulled to Logic “0” (Low). Applying bias to VSELECT equivalent to a Logic “1” (High) state, selects the RFin 2 port. Both selected and unselected input ports are terminated through on-chip 50 Ω resistors to GND. Note: due to limited on-chip isolation through the input selector topology and the high sensitivity on the first divider stage, it is possible for the prescaler to produce an output signal even when the non-driven input is selected. To prevent this condition, decrease the input amplitude present at the non-driven port or utilize the Input Disable funciton described later in this section.
VLogic ECL contact padUnder normal conditions, no external bias or connection is required to this contact and it is self–biased to the on–chip ECL logic threshold voltage of ~ –1.35 v. The user can provide an external bias to this lead (between –1.5 to –1.2 volts) to force the prescaler to operate at a system generated logic threshold voltage.
Table 1. 1GC1-4180 recommended operating conditions and ECL-compatible input logic threshold values1 (TA = 25 °C)
Function Symbol Conditions Valid input control levels and resulting current values (volts/mA)
Input select VSELECT(RFin1)2 Logic “0” (low) state (VLOGIC + 0.25) through GND
VSELECT(RFin2) Logic “1” (high) state (VEE through VLOGIC – 0.25)
Modulus select VA1, A2, A3 High2 Logic “1” (high) state (VLOGIC + 0.25) through GND
VA1, A2, A3 Low Logic “0” (low) state (VEE through VLOGIC – 0.25)
IA1, A2, A3 Logic “0” or “1” states (VA1, A2, A3 – VEE)/5000
Input disable VDISABLE High [Disabled] Logic “1” (high) state (VLOGIC + 0.25) through GND
VDISABLE Low [Enabled]2 Logic “0” (low) state VEE through (VLOGIC –0.25)
IDISABLE VDISABLE > VEE+3 (VDISABLE – VEE –3)/5000
VDISABLE < VEE+3 0
1. See DC specifications and physical properties table for nominal O.C. values2. Default open circuit (O.C.) or nominal condition
1GC1-4180 modulus select lines1
Divide modulus A1 A2 A3
Pass thru 0 0 0
÷ 2 0 0 1
÷ 4 0 1 0
÷ 8 0 1 1
÷ 16 1 X2 X2
1. See Table 1 for logic level voltages2. X = Either logic level
06 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Control Features continuedVariable output power featureBy default, when the VADJ contacts are left open circuited (O.C.), all six outputs are active and will provide typical output power (voltage swing) of 0.0 dBm (0.5 Vp–p). The nominal O.C. voltage appearing at the VADJ contacts is –1.8 Volts.
Supplying a less negative bias to the VADJ control lines (between –1.8 V and GND) will increase the output amplitude of each port proportional to the applied voltage to as high as +6.0 dBm (1.0 Vp-p).
Supplying a more negative bias to the VADJ control lines (between –1.8 V and VEE) will decrease the output amplitude of each port proportional to the applied voltage until the output amplitude is < – 25 dBm (– 50 dBm at low frequencies) or effectively 0.0 Vp-p.
VADJ 1-5 controls the output amplitudes of ports 1-5 simultaneously whereas VADJ 6 controls the amplitude only on output port 6. The total current IEE drawn from the main bias supply will also change proportionally to the VADJ 1-6 control line bias.
Input disable feature:By applying an external bias to this contact pad (more positive than –1.1 v), the input preamplifier stage is locked preventing division and self–oscillation.
Input DC Offset:Another method used to prevent false triggers or self–oscillation conditions is to apply a 20 to 100 mV DC offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider.
Assembly Techniques
Figures 2 and 3 show the chip bond pad locations and typical assembly diagram for differential I/O operation through 12 GHz. To prevent bias instabilities, the VEE contact should be connected to a 100 pF or greater bypass chip capacitor located near the die. All bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. For operation at frequencies below 1 GHz, a large value capacitor (> 400 pF) must be added to provide proper RF bypassing.
Subsequent bypassing with a 10 nF or greater feedthrough capacitor located at the hybrid microcircuit bias pin is also recommended.
The 1GC1-4180 may be operated with direct DC connections to all RF ports but in general, AC coupling capacitors are recommended on the RFin and RFout connections to the device.
Due to on–chip 50 Ω matching resistors present on-chip at all sixteen RF ports, no external termination is required. However, improved input sensitivity and reverse Spitback performance (~15 dB) can be achieved by terminating the unused RFout port to GND through 50 Ω.
The 1GC1-4180 die is fabricated using a GaAs-based HBT semiconductor material structure which allows the device to be attached to hybrid microcircuit housing or to thermal shims using either traditional AuSn solder, epoxy-based die-attach materials and processes (such as 84-1LMI), and newer RoHS assembly temperatures, where required.
07 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
ESD and Handling Precautions
GaAs MMICs in either chip or SMT packages are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly.
MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability. Keysight Technologies GaAs MMIC ESD, Die Attach and Bonding Guidelines - Application Note, literature number 5991-3484EN provides basic information on these subjects.
RoHS Compliance
This device is RoHS Compliant. This means the component meets the requirements of the European Parliament and the Council of the European Union Restriction of Hazard-ous Substances Directive 2011/65/EU, commonly known as RoHS. The six regulated substances are lead, mercury, cadmium, chromium VI (hexavalent), polybrominated biphenyls (PBB) and polybrominated biphenyl ethers (PBDE). RoHS compliance implies that any residual concentration of these substances is below the RoHS Directive’s maximum concentration values (MVC); being less than 1000 ppm by weight for all substances except for cadmium which is less than 100 ppm by weight.
08 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Notes: – Gold pad and backside metalization
– Dimensions to center of bonding pad
– Chip dimension tolerance: X/Y ±10 um (± 0.4 mils)
– Chip thickness: 127 ±15 um (5 ±0.6 mils)
– Standard bonding pad dimensions: 70 x 70 um (2.8 x 2.8 mils)
– Nominal RF pad pitch: 150 um (27.8 mils)
– No connection required to VCC or GND pads due to on-chip backside vias
– Several bonding pads are oversized to facilitate multiple bonds to allow lower Inductance/resistance interconnects. Table 2 lists the maximum number of bonds per pad.
0
2210
V L
OG
IC 22
5
Dis
able
62
5
A1
775
A2
925
A3
1075
V EE1
12
65
OU
T 6
1700
OU
T 6
1800
OU
T 5
1900
OU
T 5
2000
V AD
J 6
1590
860
680 Out 3580 Out 3
430 GND
280 Out 4
225
In 2
375
V CC
1 (N
/C)
525
In 2
995
V CC
2 (N
/C)
1590
V A
DJ 1
-517
00
OU
T 1
1800
O
UT
119
00
OU
T 2
2000
O
UT
221
00
V EE3
75
In 1 590
GND 440
In 1 290
N/C 800
SEL 780
180 Out 4
75
2135
V EE2
21
00
1440
tem
p. d
iode
Figure 2. 1GC1-4180 bonding pad locations & chip dimensions (dimensions in microns)
A1
DISABLE
≥ 100 pF RF bypass capacitors connected to device pads
Input/output thin film circuit (coupled microstrip transmission line circuits shown)
Connected to ≥ 10 nF RF bypass capacitors for all static bias/control lines.
5 mil thick Au-plated, Molybdenum shim
A2 A3
VADJ 6VEE1
Out 3
Out 3
Out 4
Out 4
Out
1
Out
1
Out
2
Out
2
Out
6
Out
6
Out
5
Out
5
VEE3 (optional)VADJ 1-5SEL
In 1
In 1
In 2
In 2
Bypass cap as bonding island (optional for SEL)
Bypass cap as bonding island
(optional for DISABLE, A1, A2, A3)
VEE2 (optional)
Figure 3. 1GC1-4180 bonding and assembly diagram
Table 2. Oversized pad dimensions: (microns)
Pad labelX
Dimen.Y
Dimen. # Bonds
VEE1 150 70 2
VEE2 105 70 1
VEE3 105 70 1
VCC2 330 70 N/C
Notes: – DC/RF ground connections: Device
backside metalization is DC and RF ground therefore connection to topside GND pads are not required.
– Die attach: Device may be die-attached to the Au-Mo shim using 84-1LMI (or equiv.) epoxy (< 13 microns thick) cured for 1 hour @ 150 °C to achieve optimum thermal management.
– All bonds should be as short as possible to limit interconnect inductance. 0.7 mil diameter ball bonds or thermosonic wedge bonds recommended on all device bonding pads.
– 1.0 mil or larger diameter bonds recom-mended for all bias/control lines from DC feedthrough capacitors interconnects.
– Multiple single wire bonds stacked •on device VEE pad and addition of optional VEE2, VEE3 bonds recommended to decrease resistive losses.
– For single-ended RF operation, all •unused I/O traces may be left open circuited or terminated into 50 W
09 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
Input frequency, ƒIN (GHz)
Inpu
t po
wer
Pin
(dB
m)
−30
−40
−20
−10
10
DC 2 4 6 8 10 12 14
0
16 18
20
(VEE = -5.0 V, TA = 25 °C)
30
Figure 4. Input sensitivity window
Output frequency, ƒOUT (GHz)
Out
put
pow
er. P
out
(dB
m)
−30
−40
−20
−10
DC 2 4 6 8 10 12
0
(VEE = -5.0 V, TA = 25 °C)5
−35
−25
−15
−5
Figure 5. Output power response (pass-through mode)
100
150
200
250
300
350
400
450
500
0.5 GHz 8 GHz IEE (total)
Vadj (1-6) Voltage (Volts)
Pout
(dB
m)
(VEE = -5.0 V, TA = 25 °C)
Tota
l sup
ply
curr
ent
(mA
)
−5.0 −4.0 −3.0 −2.0 −1.0 −0.5 0.0−1.5−2.5−3.5−4.5
−30
−40
−20
−10
10
0
−50
−60
−70
Figure 6. Output power vs. amplitude control voltage
140
190240
290340
390440
490540
590640
690
0.5 GHz 8 GHz IEE (total)
Vadj (1-6) Voltage (Volts)
Vout
(p-p
) (vo
lts)
(VEE = -5.0 V, TA = 25 °C)
Tota
l sup
ply
curr
ent
(mA
)
−5.0 −4.0 −3.0 −2.0 −1.0 −0.5 0.0−1.5−2.5−3.5−4.5
1.00.9
−0.1
0.60.50.40.30.20.10.0
0.80.7
Figure 7. Output voltage vs. amplitude control voltage
Offset from carrier, (Hz)
SS
B p
hase
noi
se (d
Bc/
Hz)
10 100 1K 10K 100K 1M 10M
(PIN = 0 dBm , FCARRIER = 6.0 GHz, TA = 25 °C)
−103
−163
−83
−3
−43
−63
−23
−143
−123
Figure 8. Phase noise performance
(VRFin = 500 mVp-p, F IN = 8 GHz, TA = 25 °C)
Pass-through (@ F OUT = 8 GHz)
÷16 mode (@ FOUT = 500 MHz)
Figure 9. Output pulse response @ 8 GHz (pass-through and ÷16 modes)
Supplemental Data1
1. All data obtained via single-ended I/O operating mode with unused RF I/O ports terminated into 50 ohms., All data taken at TA = 25 °C, except where noted.
10 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. Customers considering the use of this, or other Keysight Technologies GaAs ICs, for their design should obtain the current production specifications from Keysight. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact Keysight at [email protected].
The product described in this data sheet is RoHS Compliant. See RoHS Compliance section for more details.
11 | Keysight | 1GC1-4180 DC to 12 GHz Multi-Modulus Prescaler - Data Sheet
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This information is subject to change without notice.© Keysight Technologies, 2016Published in USA, October 29, 20165992-1921ENwww.keysight.com
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