Digital ElectronicsChapter 10. BiCMOS Logic

By: FARHAD FARADJI, Ph.D.

Assistant Professor, Electrical and Computer Engineering, K. N. Toosi University of Technology

http://wp.kntu.ac.ir/faradji/DigitalElectronics.htm

Reference:

DIGITAL INTEGRATED CIRCUITS: ANALYSIS and DESIGN, 2005, John E. Ayers

1

K. N. Toosi University of Technology

BBBByyy::: FFFFAAAARRRHHHHAAAADDD FFAAAARAAAADDDDJJJJIIII, PPPPhh.D.Assistant Professor,,

Electrical and Computer Engineering

10.1. Introduction CMOS is preferred for most applications because of: – its low standby dissipation, – high packing density, – rail-to-rail voltage swing, – and excellent speed.

Bipolar circuitry outperforms CMOS in terms of off-chip data rates.

Bipolar-CMOS (BiCMOS) logic was developed to achieve advantages of both types of logic gates.

High-performance BiCMOS circuits have been developed based on Si and SiGe technology.

Chapter 10. BiCMOS Logic 2 Digital Electronics

KNTU

try outperforms CMOS in terrms of offfff-ccchhhiiippp d

S ((BBiiiCCCCMMMMOOOOSSSS)) lloooogggiiiccc wwwwaassss dddeeeevvveeeelllooooppppeeedddd to aaaaccchhhievvveee alooggggiic gaaattteees.

ance BiCMOS circuits have been developed b

10.1. Introduction A number of different versions of BiCMOS logic gates are available.

They all share salient features of inverter shown.

2 important design features of this circuit are: 1. CMOS-type logic circuitry and 2. a totem-pole output using 2 npn BJTs.

CMOS logic circuitry provides low standby power dissipation.

BJTs at output provide superior performance with highly capacitive loads.

Packing density of BiCMOS can be excellent because relatively large BJTs are only needed to drive output connections.

BiCMOS ICs are really just CMOS on inside.

Chapter 10. BiCMOS Logic 3 Digital Electronics

KNTU

ype logic circuitry andpole ouutput usinggg 2 nnnpn BBBJTTTssss.

rcuuuiitttrrryyyy ppprrrooovvvviiddddeeesss lllooowww sssttttaaaanddddbbbbyyyy atiooonnn.

d i f h

10.2. Voltage Transfer Characteristic With logic zero (0 V) at input: – MN1 and MN3 are cut off. – MP1 is linear. – VB of QP is equal to VDD. – MN2 is linear. – QO is cut off. – QP is forward active. –

Chapter 10. BiCMOS Logic 4 Digital Electronics

KNTU

ear. off.

warrrrddd aaactttiivvveee.

10.2. Voltage Transfer Characteristic With logic one (VDD V) at input: – MN1 and MN3 are linear. – MP1 is cut off. – VB of QP is equal to 0. – QP is cut off – MN2 is cut off. – QO is forward active. –

Chapter 10. BiCMOS Logic 5 Digital Electronics

KNTU

offt off. warrrrddd aaacctttiiivvveee.

10.2. Voltage Transfer Characteristic Logic swing of conventional BiCMOS circuits is about 1.4 V less than supply voltage:

Drive to lower supply voltages makes this 1.4-V degradation increasingly important.

With a VDD = 1.8 V, logic swing of BiCMOS is a mere 0.4 V.

Conventional BiCMOS circuits are undesirable for VDD < 2.5 V.

Chapter 10. BiCMOS Logic 6 Digital Electronics

KNTU

l lt k

10.3. Rail-to-Rail BiCMOS A limitation of BiCMOS is reduced logic swing compared to CMOS.

Simplest way to achieve rail-to-rail operation is to use a parallel CMOS output driver.

Dynamic rail-to-rail performance becomes limited by MOSFETs.

For VDD -VBEA VOUT VDD : – QP is cut off. – QP provides no benefit to dynamic performance.

For VOUT VBEA : – QO is cut off. – QO provides no benefit to dynamic performance.

Chapter 10. BiCMOS Logic 7 Digital Electronics

KNTU

to-rail ppperformanccce tedd bbbyyyy MMMMOOOOSSSFFFFEEETTTsss.

VVVOOOUUUUTTTVV VVVDDDDDD VV :: off

10.3. Rail-to-Rail BiCMOS With a VDD = 1.8 V, BJTs conduct only for 0.7 V VOUT 1.1 V.

This version offers no real advantage over CMOS for VDD < 2.5 V.

Chapter 10. BiCMOS Logic 8 Digital Electronics

KNTU

10.3. Rail-to-Rail BiCMOS Another strategy to achieve rail-to-rail BiCMOS is to use passive shunts.

2 passive (resistive) shunts are placed across BE junctions of BJTs.

Shunt resistor R1 allows VOUT to swing all way to VDD while QP is cut off.

Dynamically, this means that load capacitance must charge through R1 for VOUT > VDD - VBEA.

R2 allows output to swing all way to 0.

Chapter 10. BiCMOS Logic 9 Digital Electronics

KNTU

r R1 allows VOUTVV to swing D while QQP is cut offff.

thiiisss mmmeeeaaannnsss tttthhhhaattt lllloooaaaddd cccaaaapacccciiittttaaannncccceee thrroouuuggghh RRR11 fffooorr VVVOOOOUUUUTTT > VVVVDDDDDDD VVVV - VVVBBBEEEAAAVV ..

ll

10.3. Rail-to-Rail BiCMOS Other versions of rail-to-rail BiCMOS exist.

They all suffer from this same basic limitation.

It appears that shunting BJT is not answer!

BJTs cannot boost dynamic performance of gate unless they are conducting.

Idea behind shunting is that it allows BJTs to turn off, while shunt elements allow VBE to approach 0.

A limitation of BiCMOS is its use in low-voltage circuits.

Chapter 10. BiCMOS Logic 10 Digital Electronics

KNTU

re conducting.

huuntttiiinnnngggg iiisss tthhhaaaattt iitttt aaaallllloooowwwwssss BBJJJJTTTTssss hillleeee shuuunnnttt eeellleeemmmmennnts aaallllllow VVVBEVV to

10.3. Rail-to-Rail BiCMOS BiCMOS has been used in dual voltage applications.

Dual voltage is:

– using a low voltage supply for CMOS core • to minimize power dissipation,

– using a higher voltage supply for BiCMOS output drivers

• for greater logic swing and improved off-chip bit rates.

This practical solution has been implemented in commercial products such as microprocessors.

Chapter 10. BiCMOS Logic 11 Digital Electronics

KNTU

nimize power dissipation,

gheerrr vvvvooooltaaagggeee suuppppppppllllyyy ffffooorrr outtttppppuutt dddrrriiivvverrrsssseaaattteeeerrr llloooggggiiicccc ssswwwwiiinnnngggg aaannndddd

d ff hi bit t

10.4. Logic Design NAND function is formed by paralleling p-channel MOSFETs and forming series combinations of n-channel MOSFETs.

If either input goes low: – associated MP1 conducts. – MN2 conducts. – associated MN1 is cut off. – associated MN3 is cut off. – QP conducts. – QO is cut off. – Output will go high.

Chapter 10. BiCMOS Logic 12 Digital Electronics

KNTU

d MP1 conducts. ucts.. d MMMNNN1 isss cccuuuttt oooofffff. d MMMNNNN33 iisss ccccuutttt oofffffff... cts

10.4. Logic Design If both inputs are logic one: – Both MP1 are cut off. – Both MN1 conduct. – Both MN3 conduct. – MN2 is cut off. – QP is cut off. – QO conducts. – output will go low.

Chapter 10. BiCMOS Logic 13 Digital Electronics

KNTU

off.ctss.ill ggggooo lowww.

10.4. Logic Design M-input BiCMOS NAND gate requires: – M p-MOSFETs in parallel, – 2 series combinations

of M n-MOSFETs, – 2 BJTs, – discharge MOSFET MN2.

M-input BiCMOS NAND gate requires (3M+1) MOSFETs and 2 BJTs.

Chapter 10. BiCMOS Logic 14 Digital Electronics

KNTU

MOSFEEET MNNNN2222. MOOOSSS NNNAAAANNNDDD ggggaaaatte +1))) MMMMOOOSSSFFFEEEETTTss aaaannnnddd

10.4. Logic Design 2-input BiCMOS NOR gate is implemented by placing p-MOSFETs in series and forming parallel combinations of n-MOSFETs.

If either input goes high: – associated MP1 is turn off. – MN2 is cut off. – associated MN1 conducts. – associated MN3 conducts. – QP is cut off. – QO conducts. – Output will go low.

Chapter 10. BiCMOS Logic 15 Digital Electronics

KNTU

d MP1 is turn off. t off.. d MMMNNN1 cccooonnnddduuuucccctts. d MMMNNNN33 cccoooonnnddduuuccttttssss.... off

10.4. Logic Design If both inputs are logic zero: – Both MP1 conduct. – Both MN1 are cut off. – Both MN3 are cut off. – MN2 conducts. – QP conducts. – QO is cut off. – output will go high.

M-input BiCMOS NOR gate requires (3M+1) MOSFETs and 2 BJTs, like M-input NAND gate.

More complex AND–OR–INVERT functions may be implemented in BiCMOS by forming more complex pull-up and pull-down networks.

Chapter 10. BiCMOS Logic 16 Digital Electronics

KNTU

cts.offf..ill ggggooo higgghhh.

MOS NOR gate requires