jvc 2000 basic dvc models technical guide
TRANSCRIPT
VIDEO TECHNICAL GUIDE
COPYRIGHT © 2000 VICTOR COMPANY OF JAPAN, LTD.
No. 86056September 2000
2000 Basic DVC Models
DIGITAL VIDEO CAMERA
INDEX
INDEX-1
SECTION 1 OUTLINE OF THE PROCUCTS1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1
1.1.1 Comparison table of DV models specification by products year .....................................1-11.1.2 Specification of the DVC models....................................................................................1-3
SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT2.1 CIRCUIT OUTLINE ..............................................................................................................2-1
2.1.1 Basic block diagram.......................................................................................................2-1
2.2 CCD (ICX220AK/ICX221BK)................................................................................................2-22.2.2 CCD Image Sensor........................................................................................................2-32.2.3 Numbers of pixel for main models..................................................................................2-6
2.3 EXPLANATION OF CAMERA CIRCUIT ...............................................................................2-72.3.1 Present AW / AE control system ....................................................................................2-72.3.2 AF (Auto Focus) control .................................................................................................2-132.3.3 EIS (Electric Image Stabilizer) control ............................................................................2-14
2.4 CAMERA SYSREM IC'S FUNCTION ...................................................................................2-152.4.1 Camera DSP (IC4301: JCY0120) function .....................................................................2-15
2.5 EXPLANATION OF DECK CIRCUIT ....................................................................................2-222.5.1 Deck system overall structure ........................................................................................2-222.5.2 PB equalizer and ATF ....................................................................................................2-232.5.3 PLL operation ................................................................................................................2-242.5.4 Basic principle of Viterbi detection .................................................................................2-252.5.5 Audio recording mode....................................................................................................2-262.5.6 Audio signal processing .................................................................................................2-272.5.7 Clock system for audio data...........................................................................................2-282.5.8 Deck DSP IC function ....................................................................................................2-292.5.9 Audio AMP IC function...................................................................................................2-35
2.6 SYSCON CPU .....................................................................................................................2-382.6.1 Contents of SYSCON CPU processing ..........................................................................2-382.6.3 System composition.......................................................................................................2-392.6.4 SYSCON CPU block diagram ........................................................................................2-402.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions..................................................2-41
2.7 DECK CPU...........................................................................................................................2-442.7.1 Contents of DECK CPU processing ...............................................................................2-442.7.2 DECK system composition.............................................................................................2-442.7.3 Tracking Error information..............................................................................................2-452.7.4 1394 interface control ....................................................................................................2-462.7.5 JLIP Video Capture........................................................................................................2-462.7.6 DECK CPU block diagram .............................................................................................2-472.7.7 Deck CPU (IC1401: MN103004KRH) pin functions........................................................2-48
INDEX-2
SECTION 3 HEAD CLOG WARNING3.1 HEAD CLOG WARNING OF DVC........................................................................................3-1
3.1.1 Structure of Sync Blocks and Error correction................................................................3-13.1.2 Error Rate of DVC..........................................................................................................3-33.1.3 Previous method of head clog detection ........................................................................3-43.1.4 New method of head clog detection ...............................................................................3-5
SECTION 4 DOCTOR SYSTEM4.1 WHAT IS DOCTOR PROGRAM?.........................................................................................4-1
4.1.1 Matching of Doctor Program with Microcomputer Program ............................................4-14.1.2 Use of Doctor Program for Camcorder...........................................................................4-24.1.3 Revision of Service Support System Software for Doctor Program ................................4-24.1.4 Procedure to Rewrite Doctor Program ...........................................................................4-3
4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES .............................4-54.2.1 ON/OFF address and Program address.........................................................................4-54.2.2 Writing function of EEPROM data ..................................................................................4-74.2.3 Upgrade of the service support system..........................................................................4-7
SECTION 1OUTLINE OF THE PROCUCTS
1-1
1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR1.1.1 Comparison table of DV models specification by products year (1/2)
ModelFunctionBattery BN-V11 Ni-Cd
(6V, 1100 mAh)BN-V12 Ni-Cd (6V, 1200 mAh)BN-V20 Ni-MH (6V, 2000 mAh)
Continuous shooting time:when VF is used:BN-V12: 1hr.10min.BN-V20: 1hr.50min.
when LCD is used:BN-V12: 1hr.BN-V20: 1hr.40min.
BN-V207 Lithium-ion (7.2V, 700 mAh)BN-V214 Lithium-ion (7.2V, 1400 mAh)
Continuous shooting time:when VF is used:BN-V207: 1hr.BN-V214: 2hrs.20min.BN-V856: 8hrs.30min.
when LCD is used:BN-V207: 50min.BN-V214: 1hr.55min.BN-V856: 7hrs.
BN-V408 Lithium-ion (7.2V, 800 mAh)BN-V416 Lithium-ion (7.2V, 1600 mAh)BN-V428 Lithium-ion (7.2V, 2800 mAh)
Continuous shooting time:when VF is used:BN-V408: 1hr.15min.BN-V416: 2hrs.30min.BN-V428: 4hrs.20min.BN-V856: 8hrs.40min.
when LCD is used:
Charging the battery Charging time: AA-V15 used 70 min. (BN-V11) 70 min. (BN-V12) 110 min. (BN-V20)
Charging time: AA-V20 used 90 min. (BN-V207) 180 min. (BN-V214)
Charging time: AA-V40 used 90 min. (BN-V408) 120 min. (BN-V416) 200 min. (BN-V428)
Viewfinder Color LCD 0.55" 113k pixelsB/W CRT
Color LCD 0.55" 113k pixelsB/W LCD 0.24" 76k pixels
Color LCD 0.44" 113k pixelsB/W LCD 0.24" 76k pixels
LCD monitor Non2.5" 480 × 234 = 112k pixels3" 480 × 234 = 112k pixelsHorizontal resolution: 240 linesAmorphous silicon transistor
2.5" 480 × 234 = 112k pixels3" 480 × 234 = 112k pixels3.5" 480 × 234 = 112k pixelsHorizontal resolution: 240 linesAmorphous silicon transistor
←
Image device 1/4"Total 766 × 596 = 460k pixels (*799 × 711 = 540k pixels)Effective aria 611 × 480 = 290k pixels (*601 × 576 = 350k pixels)
1/4"Total 998 × 677 = 680k pixels (*998 × 797 = 800k pixels)Effective aria 711 × 485 = 340k pixels (*702 × 575 = 400k pixels)
←
Horizontal resolution 360 Lines 400 Lines ←Electric imagestabilizer
Yes ← ←
Sensitivity 10 lux (*12 lux)50 IRE Level, Slow Shutter off
16 lux (*18 lux)50 IRE Level, Slow Shutter off
18 lux50 IRE Level, Slow Shutter off
Lens specification F1.6 f = 3.9 to 62.4 mm ← F1.8 f = 3.6 to 36.0 mm
Tele macro Yes ← ←
Zoom ratio Optical zoom: 16×Digital zoom: 4×/10× or 8×/20×Max. zoom: 160× or 320×
← Optical zoom: 10×Digital zoom: 4×/10×,25× or 45×Max. zoom: 100× ,250× or 450×
Snapshot 5 modeWith frameFullPin-upPin-up 4-divisionPin-up 9-division
← ←
Playback snapshot Yes ← ←Playback digital zoom Yes 10×
RM-V712UYes 4×RM-V711U
Yes 10× or 25×RM-V716U
2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model
Table 1-1-1 Comparison table of DV models specification by products year (1/2)
1-2
•••• Comparison table of DV models specification by products year (2/2)
ModelFunctionSlow motion Yes
RM-V712UYes (Frame Advance)RM-V711U (optional: GR-DVF11U)
Yes (Frame Advance)RM-V716U
Video auto light Yes Yes ( /No) YesAudio 2ch(48kHz,16-bit) /4ch(32kHz,12-bit) ← ←Snapshot search No ← ←Record end search No ← ←Audio dubbing No (Yes:PAL model,32kHz only,RCU
only)Yes (32kHz only,RCU only) ←
V.insert editing No ← Yes (SP only)Time code Yes ← ←Headphone terminal No ← ←AV output terminal RCA
(Video Audio L/R)← Ø3.5 mini
S output terminal Yes ← ←JLIP terminal Yes ← ←
PC terminal No Yes (No: GR-DVF11U) Yes(No: GR-DVF10,DVL100U,DVL305U,DVL307U)
Digital still image outputterminal
No Yes (No: GR-DVF11U) Yes(No: GR-DVF10,DVL100U,DVL305U,DVL307U)
DV terminal No Yes (EG/EK Model Output only) Yes(Output only: GR-DVL100EG/EK,DVL108EG/EK,DVL200EG/EK,DVL300EG/EK,DVL308EG/EK)
JLIP relatedsoftware
GV-CB3 JLIP video capture box (optional) JLIP video capture Ver.2.0 JLIP video producer Ver.1.13
Provided CD-ROM or optional HS-V4KIT(No: GR-DVF11U) JLIP video capture Ver.3.0 JLIP video producer Ver.1.16
Provided CD-ROM or optional HS-V14KIT(No: GR-DVF10,DVL100U,DVL305U,DVL307U) JLIP video capture Ver.3.1 JLIP video producer Ver.2.0 Picture Navigator (DSC model only)
JLIP ID number 06 ← ←Remote control sensor Yes ← ←
Button battery(only for clock backup)
Yes: CR-2025 type Yes: CR-2032 type (built-in) ←
2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model
Table 1-1-1 Comparison table of DV models specification by products year (2/2)
1-3
1.1.2 Specification of the DVC models
MODELSIGNALFORMAT
CCD VFLDC
MONIDV
TERMINAL
DIGITALSTILL
OUTPUTDSC MMC
DIGITALZOOM
GR-DVF10 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 XGR-DVA10 NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 100 XGR-DVA11/K NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES DSC MMC 100 XGR-DVL100U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT - - - 250 XGR-DVL300U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 XGR-DVL305U NTSC 1/4" 680K COLOR 2.5 INCH IN/OUT - - - 250 XGR-DVL307U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 XGR-DVL500U NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 250 XGR-DVL505U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 XGR-DVL507U NTSC 1/4" 680K B/W 3.5 INCH IN/OUT YES - - 250 XGR-DVL805U NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 XGR-DVL300UM NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 XGR-DVL505UM NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 XGR-DVL805UM NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 XGR-DVL300KR NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 XGR-DVL805KR NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 XGR-DVL100EG PAL 1/4" 800K B/W 2.5 INCH OUT ∗OPTION - - 100 XGR-DVL107EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 100 XGR-DVL108EG PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC MMC 100 XGR-DVL109EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC MMC 100 XGR-DVL200EG PAL 1/4" 800K B/W 3.0 INCH OUT YES DSC - 100 XGR-DVL300EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 XGR-DVL307EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 100 XGR-DVL308EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC MMC 100 XGR-DVL309EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC MMC 100 XGR-DVL100EK PAL 1/4" 800K B/W 2.5 INCH OUT ∗OPTION - - 100 XGR-DVL107EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT ∗OPTION - - 100 XGR-DVL108EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC MMC 100 XGR-DVL109EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC MMC 100 XGR-DVL200EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC - 100 XGR-DVL300EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 XGR-DVL308EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC MMC 100 XGR-DVL105A PAL 1/4" 800K B/W 2.5 INCH IN/OUT ∗OPTION - - 450 XGR-DVL300A PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 XGR-DVL800A PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 XGR-DVL105A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT ∗OPTION - - 450 XGR-DVL300A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 XGR-DVL800A-S PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 XGR-DVL100EA PAL 1/4" 800K B/W 2.5 INCH IN/OUT ∗OPTION - - 450 XGR-DVL300EA PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 450 XGR-DVL300ED PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 XGR-DVL400ED PAL 1/4" 800K B/W 3.0 INCH IN/OUT YES - - 450 XGR-DVL500ED PAL 1/4" 800K COLOR 3.0 INCH IN/OUT YES - - 450 XGR-DVL600ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES - - 450 XGR-DVL707ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES DSC - 450 XGR-DVL800ED PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 XCC9370 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X∗OPTION: HS-V14KITE (CD-ROM and Cables)
Table 1-1-2 Specification of the DVC models
SECTION 2EXPLANATION OF ELECTRICAL CIRCUIT
2-1
2.1 CIRCUIT OUTLINE2.1.1 Basic block diagram
C C D
IC4301C A M E R A _ D S P
IC4302FIELD
M E M O R Y
TMY(8)TMC(4)
T GV . D R V
IC5501
F O C U SD R I V E R
&Z O O M
D R I V E R
IC4851
IRISD R I V E R
&H A L LA M P
IC4802- IC4805
S Y S C O NC P U
IC1001
DYO(4) ,DCO(4)
BU
S(1
6)
IR IS_O/C
D A T A _ O U T
IC3001
D E C K _ D S P
IC3002
1 6 MD R A M
IC3501
R E C A M P&
P B A M P
IC1401D E C KC P U
IC3201
D V E Q
IC3301
D V A N A
H S E
A U D I OA M P
IC2201
RD(16)
RA(10)
MIC UNIT
INT
_MIC
/ L
INT
_MIC
/ R
A_OUT / R
A_OUT / L
MA IN10
FMY(8)FMC(4)
H1, H2, RG
XAVD, XAHD
IC1003
E 2P R O M
IC1004
R T C32kHz
X1002
ANA_ IO
S_DT_IN
AD(16)
S_DT_ IN
S _ D T _ O U T
O NS C R E E N
IC1002
DRIVE+, -
FOCUS (4 )
ZOOM (4)
IC1601
M D A M
M
M
C A P S T A NM O T O R
D R U MM O T O R
L O A D I N GM O T O R
VIDEOH E A D
IRIS PWM
AID
AT
DO
DA
T
AID
AT
DO
DA
T
M D A _ I N
ATF_GAIN, M_VCOCTL, PBVCOCTL, FSPLLCTL
DV
_C
L C D _ R - Y
DA
TA
_OU
T
CLK27 ,CLK18 ,CLK13
OPT ICALB L O C K
C C D _ O U T C D S / A G CA/D
IC4201
C A M _ A D ( 1 0 )
5 4 M H z
X5501
1394PHY
IC3101TPA+,TPA-TPB+,TPB-
D A T A _ O U T
S U B
S _ D T _ O U T
L O A D _ F W DL O A D _ R E V
V1,V2,V3,V4
PD(4)DYI(4),DCI(4)
H S E
P B D A T A
ADDT(16)
AD
DT
(16)
AD
DT
(16)
ANA_ IO
SP
K+
,SP
K-
S P
P B _ E N V
P B _ E N V
IRIS PWM
R E C C _ A D J
R E C C _ A D J
H_G
AIN
,H_O
FF
SE
T
H_GAIN ,H_OFFSET
M D A _ I N
C C D40
J U N C T I O N50
D _ C O I L _ UD _ C O I L _ VD _ C O I L _ W
C _ C O I L _ UC _ C O I L _ VC _ C O I L _ W
1F1 S2F2 S
P B O
A T F O
IC5001
DA
TA
_OU
T
L C DD R I V E R
IC7601
M O N IL C D
RGB
S W
IC7604
V FL C D
RGB
M O N I T O R20
L C DD R I V E R
IC7101
V FL C D
EE PR O M
RX
D
TX
D
S R V _ T X
IF_RX
IC8001
DSC_ IF
M32_R/DC P U
IC8002
IC8003
1 6 M bF L A S H
D S C01
R E A R70
P CRX
GNDJ552
TX
JLIP
RX
TX
GND
EDITJ553
IC1302
IC1014
IF_RX
IF_TX
TXD
R X D
EDIT_CTL
JLIP_L
M32_DTIN
P C _ R X
P C _ T X
JLIP_RX
JLIP_TX
32D(16)
32A(25) 32A(19)
J A C K60
ATF_GAIN , M_VCOCTLPBVCOCTL , FSPLLCTL
LCD_B-Y
L C D _ Y
M 3 2 _ D T O U T
TXD
R X D
M32
_DT
OU
T
M32
_DT
IN
V I D E OO U T
DV
_Y
MY
(8),
MC
(4)
D V _ C
D V _ YV _ O U T
Y_OUT
C _ O U TS _ O U T
A VO U T
D V
A V _ D E T
MY
(8),
MC
(4)
IC7603
A_OUT / R
A_OUT / L
DA
TA
_OU
T
VF
_R, V
F_G
, VF
_B, V
BLK
VC
1, B
LK1
D R U M _ R E FC A P _ R E F
D R U M _ P GD R U M _ F G
C A P _ F G
J501
J503
J502
*only for B/W VF model
D A T A _ O U T
J A C K60
PD(4)
M14D2 Ser ies
OS
D_D
AT
A
Fig. 2-1-1 Basic block diagram
2-2
2.2 CCD (ICX220AK/ICX221BK)This IC functions as an interline CCD (ChargeCoupled Device = one of solid-state pickupdevices). Since this CCD conforms to the SDmode of the DV standard, it has an optimumnumber of vertical pixels for the MPEG2 main leveland it realizes a horizontal resolution of 450 TVlines. As same as general CCD's currently in use,this CCD is capable of camera shaking correctionand electronic panning and tilting owing to theextension area of 33 percent extra in both thevertical and horizontal directions.Moreover, this CCD provides high quality widepicture whose aspect ratio is exactly 16:9 withoutvertical interpolation.High sensitivity and low dark current are realizedthanks to adoption of the Super HAD CCDtechnology with the color filters of yellow, cyan,magenta and complementary green mosaic filters.This CCD has an electronic shutter function that isable to vary charge storage time by the field periodread system.Frame period read system is realized by joint useof the newly developed TG IC.
HØ
1
HØ
2
ØR
G
ØS
UB
VØ
1
VØ
2
VØ
3
VD
D
PhotoSensor
VØ
4
1
Ye
G
Ye
M g
Ye
G
C y
M g
C y
G
C y
M g
Ye
G
Ye
M g
Ye
G
Horizontal-Register
Ver
tical
-Reg
iste
r
14131211108 9
7 6 5 4 3 2
GN
D
VO
UT
TE
ST
∗
C y
M g
C y
G
C y
M g
GN
D
VL
∗
Fig. 2-2-1 CCD block diagram
ELEMENT STRUCTURE Interline type CCD image sensor
Optical size 1/4 inch size format
Total pixels NTSC: 998 (H) × 677 (V) approx. 680,000 pixels, PAL: 998×797 approx. 800,000 pixels
Effective pixels NTSC: 962 (H) × 654 (V) approx. 630,000 pixels, PAL: 962×774 approx. 740,000 pixels
4:3 NTSC NTSC: 711 (H) × 485 (V) approx. 340,000 pixels, PAL: 702×575 approx. 400,000 pixels
16:9 18MHZ NTSC: 948 (H) × 485 (V) approx. 460,000 pixels, PAL: 936×575 approx. 540,000 pixels
16:9 5fsc NTSC: 942 (H) × 485 (V) approx. 460,000 pixels, PAL: 922×575 approx. 530,000 pixels
H direction: Front 4 pixels, Rear 32 pixels
V direction: Front 11pixels, Rear 12 pixels
Board material Silicon
OB
Table 2-2-1 CCD functions
Pin No. Label In/Out Description Pin No. Label In/Out Description
1 Vφ4 In Vertical register transfer clock 8 VOUT Out Video signal output
2 Vφ3 In Vertical register transfer clock 9 GND - Ground
3 Vφ2 In Vertical register transfer clock 10 φRG In Reset gate clock
4 Vφ1 In Vertical register transfer clock 11 Hφ1 In Horizontal register transfer clock
5 GND - Ground 12 Hφ2 In Horizontal register transfer clock
6 TEST - Open 13 φSUB In Substrate clock
7 VDD - Power supply 14 VL - Protect transistor bias
Table 2-2-2 CCD pin function
2-3
2.2.2 CCD Image SensorMain difference in CCD adopted with DVC and VHS-C.
(Pixel)
7.15µ m
5.55
µ m
(Pixel)
3.80µ m
4.15
µ m
33% EIS Area
962(H)
711(H)
485(
V)
654(
V)
P icture Area
13.5MHz
18MHz
510(H)
492(
V)
9 .54545MHz
(Pixel)
7.3µ m
4.7 µ
m
500(H)58
2(V
)
9 .45833MHz
(Pixel)
4.85µ m
4.65
µ m
752(H)
582(
V)
14 .1875MHz
(Pixel)
3.85µ m
3.50
µ m
33% EIS Area
962(H)
702(H)
575(
V)
774(
V)
P icture Area
13.5MHz
18MHz
NTSC: ef fect ive 630,000 ( Image 340,000) p ixels PAL: ef fect ive 740,000 (Image 400,000) p ixels
NTSC: ef fect ive250,000 p ixels PAL: ef fect ive 290,000 pixels
PAL (760H- type) : ef fect ive 440,000 pixels
510H-type/760H-type 1/4" CCD for VHS-C
960H-type 1/4" CCD (w/ EIS area) for DVC(GR-DVX7, GR-DVF31/DVL40, GR-DVL300 e tc . )
NTSC PAL NTSC PAL PAL (760H)9.54545MHz910fH × 2/3910fH = 4 × fsc
Horizontal drivefrequency
9.45833MHz908fH × 2/3
14.1875MHz908fH
DVC VHS-C
18MHz: 1144fHPicture area:13.5MHz: 858fH13.5MHz = 18MHz × 3/4
13.5MHz: DVC format Y signal sampling frequencyfH = 15.734264KHz (PAL: 15.625KHz): Horizontal sync frequency
fSC = 3.579545MHz (PAL: 4.433618MHz): Color sub-carrier frequency
Fig. 2-2-2 Pixel number and pixel size of various CCD
2-4
1. Feature of CCD for this modelThis CCD adopts the drive frequency and the number of pixels conforming to the DVC format. Thehorizontal drive frequency is 18MHz based on 13.5MHz that is Y signal sampling frequency of the DVCformat. And the number of pixels secures the horizontal resolution of 400 lines that conforms to the highresolution DVC format. Moreover, to keep resolution even if EIS is switched on, the CCD having EIS(Electric Image Stabilizer) area (approx. 33% in area) is adopted.Adoption of the usual 1/4”-type CCD realizes miniaturization of the lens unit with keep the zoom ratio of 10times, and it also realizes miniaturization of whole body.On the other hand, a pixel size gets smaller as the evil effect of miniaturization and large numbers of pixel.It becomes unfavorable in the point of CCD sensitivity and dynamic range. For such reason, the minimumobject illumination is determined as 18 Lux EIA standard.
2. Improvement of the CCD for DVCIt is elaborated the following idea to make up for the decline of the sensitivity of CCD at all.
1) Optimization of the on-chip microlensLoss of incident light is minimized by reduction of ineffective area between microlenses on the pixels.
Photoshielding AI
LightIneffective
Effective
Transfersection
On-chip microlens On-chip microlens
SensorTransfersection
IneffectiveLight
Photoshielding AI
Transfersection
Transfersection
Effective
Fig. 2-2-3 Structural drawing of CCD image sensor
2-5
2) Construction of internal lensSince the internal lens is constructed between the color filter and gobo, the light condensationefficiency is improved even for inclined incident light.
Sensor V. Register
On-chipmicrolens
Color f i l ter
Poly Si
Gobo
V. Register
Poly Si
Internal lens
On-chipmicrolens
Color f i l ter
Gobo
Sensor
Fig. 2-2-4 Structural drawing of internal lens
2-6
2.2.3 Numbers of pixel for main models
Models Optical size Total pixelsEffective pixels
(EIS)practical pixels
GR-DV1GR-DVM1GR-DVX
1/3” approx. 570,000908H � 616V
approx. 530,000858H � 614V
approx. 350,000704H � 499V
GR-DVL /DVL9000UGR-DVL7 /DVL9600U
1/3”Progressivescan
approx. 380,000758H � 504V
–
approx. 360,000724H � 494V
GR-DVYGR-DVM5U /DV3UGR-DVF10U /20U
1/4” approx. 460,000766H � 596V
approx. 420,000724H � 582V
approx. 290,000611H � 480V
GR-DVX7GR-DVM70U /50UGR-DVA1 /F1GR-DVF11 /21 /31UGR-DVA10 /F10 /A11GR-DVL100 /200 /300U
1/4” approx. 680,000998H � 677V
approx. 630,000962H � 654V
approx. 340,000711H � 485V
GR-DVL700GR-DVL9800U
1/3”Progressivescan
approx. 680,0001002H � 662V
approx. 630,000962H � 654V
approx. 340,000720H � 480VDSC XGA: 630,000962H � 654V
GR-DV1EGR-DVM1EGR-DVXE
1/3” approx. 670,000908H � 728V
approx. 620,000858H � 726V
approx. 420,000704H � 594V
GR-DVL9000EGR-DVL9500E /9600E
1/3”Progressivescan
approx. 450,000758H � 592V
–
approx. 420,000724H � 582V
GR-DVM5E /DV3EGR-DVF1E /DVF10E
1/4” approx. 540,000766H � 711V
approx. 500,000724H � 697V
approx. 530,000601H � 576V
GR-DVX4E /DVX7EGR-DVL20 /30 /40EGR-DVL100 /200 /300EGR-DVL9200E
1/4” approx. 800,000998H � 797V
approx. 740,000962H � 774V
approx. 400,000702H � 575V
GR-DVL9700E /9800E 1/3”Progressivescan
approx. 800,0001002H � 782V
approx. 740,000962H � 774V
approx. 420,000720H � 576VDSC XGA: 740,000962H � 774V
GR-SXM46 /SX41EGR-SXM26 /SX21E
1/4” approx. 470,000795H � 596V –
approx. 440,000752H � 582V
GR-FX11 /FXM16EGR-FX102 /FXM106S
1/4” approx. 320,000537H � 597V –
approx. 290,000500H � 582V
VHS-CNTSC
GR-AXM220UGR-SXM920U
1/4” approx. 270,000537H � 505V –
approx. 250,000510H � 492V
DVCPAL
DVCNTSC
VHS-CPAL
Table 2-2-3 Numbers of pixel for main models
2-7
2.3 EXPLANATION OF CAMERA CIRCUIT2.3.1 Present AW / AE control systemThe signal-processing block of the present camera system is composed as shown below (Fig. 2-3-1)
CCD A/D
CO
LOR
SE
PA
RA
TIO
N
LPF
MA
TR
IXE
NC
OD
ER
PR
OC
ES
S
A G C
G C A
G C A
Y
R
G
B
Y
C
TGDRIVE
IRIS DRIVE
CAMERA CPU
IR SENSOR
∗1∗2
∗3∗4 ∗5
∗1 Iris control∗2 Shutter speed setting∗3 Analog amp gain (AGC gain)∗4 WB setting (RED gain, BLUE gain)∗5 Parameter for picture compensation (color reproducibility, S/N ratio…)
Fig. 2-3-1 Camera block configuration
2-8
1. AE (Auto Exposure) controlThe luminance level of camera output picture is controlled to always be proper exposure regardless of thebrightness and illumination of the object.
1) AE input information• Average of luminance level divided a frame picture into 48 blocks passed through the LPF.• The area ratio of the sections having luminance components higher than a certain level to the
whole sections.
AE control
Weight ing ofsect ioned data
Caluculat ion ofevaluat ion value
Target > Evaluat ion?
AGC gain down↓
Slow shut ter OFF↓
Ir is close
Ir is open↓
AGC gain up↓
Slow shut ter ON
R E T
Fig. 2-3-2 AE control flow chart
2) Weighting of data on sectionsThough the respective data on 48 sections are weighted, the basic setting is to weight the center parthigh.
Low
Low
High
High LowLow
Fig. 2-3-3 Weighting of data on sections
2-9
3) AE control and output luminance signal levelGain-up mode: AUTO (OFF and AGC modes are the same as the VHS-C camcorder)
100 IRE
Open
0 IRE5000 lux 300 lux 40-50 lux 10 lux
Close
M A X
MIN
1/30
1/60
1/240
O N
O F F
50 IRE
L U M I N A N C E
IRISA P E R T U R E
A G CGAIN
S H U T T E RS P E E D
A U T OLIGHT
ILLUMINATIONBRIGHT D A R K
(2)
(1)
(3)(4)
(5)
(6)
Fig. 2-3-4 AE control and output luminance signal level
2-10
(1) When the intensity of illumination is high and iris aperture is stopped down, the iris is opened forcompensating drop of the signal level by changing the shutter speed to high (1/250 sec).
(2) Since raising the AGC gain deteriorates the S/N ratio, the E-E level is slightly lowered in theexposure compensation by controlling the AGC as compared with the iris control mode.
(3) As the intensity of illumination becomes low and AGC gain rises to maximum, the camera entersthe slow shutter mode (1/30 sec).
(4) When the camera enters the slow shutter mode, the signal level rises by 6 dB and the AGC gaindrops in inverse proportion to the signal level.
(5) The auto-light is turned on when the illumination turns down a little more after the camera enteredthe slow shutter mode and AGC gain rose to the maximum. There is a hysteresis to preventhunting as the auto-light is switched on/off.
(6) The intensity of illumination shown in the figure is just an example and it varies depending on theobject, angle of view, etc.
2-11
2. AW (Auto White balance) controlAW control compensates the Red component gain and Blue component gain shown in the camera blockdiagram to keep the white balance in the camera picture under every kind of light source.Basic input data for AW control are three of the following.
(1) R, G, B levels of sections divided a picture into 48 sections.
(2) Data on existence/absence of infrared rays in the light source. This data is used for judging thesort of the light source.
(3) Illumination judged with the exposure compensation parameters (iris/ AGC gain/ shutter speed).
The white balance is controlled by the following setting referring to the R, G, B data on the section that isjudged as a white (uncolored) part of the picture according to the three kinds of data mentioned above.
Red component gain = Green level / Red levelBlue component gain = Green level / Blue level
Besides the white balance control, balance among color phases is controlled by the parameter control inthe color signal processing from RGB to C signal depending on the light source.
1) Light source judging process
IR FLICKER BRIGHT LIGHTDC component AC component (Over 4000 Lx) SOURCE
Yes Yes Yes HAROGEN
Yes Yes No ∗Yes No Yes OUT DOOR
Yes No No OUT DOOR
No Yes Yes FL LIGHT
No Yes No FL LIGHT
No No Yes FL LIGHT
No No No FL LIGHT
∗: OUT DOOR or HAROGEN (not FL LIGHT)
Table 2-3-1 Light source judging process
2-12
2) AWB control algorithm
AWB con t ro l
L ight source judgment(Gain l imiter sett ing)
Sunl ight?
Gain calculat ion f rom whi te b lock data(Calculat ion value = Target gain)
Gain set t ing (adjustment) for the sunl ight(Adjustment va lue = Target va lue)
Opt imum t ime constant set t ing for gaincontro l
Is the WB deviat ing tob lue?
R-gain up / B-gain downIs the WB deviat ing to
red?
R-gain down / B-gain up
R E T
Y E S
N O
N O
N O
Y E S
Y E S
The upper and lower l imi ts of each gain are set according tothe ra t io between R and B components and judgment o f thel ight source by the infrared sensor.
Sett ing of the control t ime constant to avoid unnatural colorvar iat ion.
Fig. 2-3-5 AW control flow chart
The light source of the natural light (sunlight), halogen lamp (indoor) or fluorescent lamp is judgedaccording to data of the infrared sensor and data on the illumination.Since the gain to be compensated by the white balance control greatly varies depending on thedevice used (CCD, IR cut filter, lens, etc.) and parameter for color separation, settings of limiter,control time constant and color reproducing parameters differ from model to model.
2-13
2.3.2 AF (Auto Focus) control1. Auto Focus operation during slow shutter modeThough the basic Auto Focus operation is the same as usual, the interval of Auto Focus operation variesconforming to the timing of the picture data renewal when the camera is in the slow shutter mode. Forexample, in case the Gain-up mode is set to Auto, the shutter speed is changed to 1/30(2V) according tothe illumination of the object. Therefore, the Auto Focus operation also works every 2V. The Auto focusoperation works every 4V in Slow-4X mode and every 10V in Slow-10X in the same way.
1/60
DataRenewal/processing
1/30
V D
Focusoperat ion
2V
Fig. 2-3-6 AF operation timing in slow shutter mode
2. Improvement of the Low-contrast performanceTo improve the AF performance in the low contrast subject (such as the man's face), a route that has lowstage filter (HPF1) is added newly. The low contrast subject contains the frequency element that is notcomparatively high.
BPF HPF2 Rectif ierPeak
Addit ion
HPF1 Rectif ierPeak
Addit ion
HPF2 Rectif ierPeak
Addit ion
AFEH P E
HPF1
HPF2
BPF
HPF1 Rectif ierPeak
Addit ion
HPF1 Rectif ierPeak
Addit ion
HPF2 Rectif ierPeak
Addit ion
AFE1HPE1
HPF1
HPF2
HPF2 Rectif ierPeak
Addit ionAFE2HPE2
HPF1: 500KHzHPF2: 1 .7MHz
Previous
New
Fig. 2-3-7 Addition of AFE low stage filter
2-14
2.3.3 EIS (Electric Image Stabilizer) controlThe accurate compensation without picture quality deterioration is possible by using CCD with expansionarea and correcting it two times.
C C D CDS / AGC /A D C I W D F M C
V R A M
TG/V_DRIVER C P U
13.5 MHz18 MHz
Vector
(1) (2)
(3)
(4)
D S P
Fig. 2-3-8 EIS system block diagram
962
654(
*774
)
800
240(
*288
)
720
245(
*292
)(1) Cutt ing out at TG (2) Cutt ing out at IWD
(3) Cutt ing out at Field Memory (4) Camera output
2 l ines mixing transfer
Fig. 2-3-9 EIS operation
2-15
2.4 CAMERA SYSTEM IC'S FUNCTION2.4.1 Camera DSP (IC4301: JCY0120) function1. Camera DSP (IC4301: JCY0120) internal block diagram
C L K 4 5
ADIN [9:0]YO
C L R
SSG1
EIS/FMCVRAM Conto lVector Detect
ID
C L K Y C A
C L K 1 3C L K 1 3 X
YOUT
SSG for TG/YCA
SSG2
C L K 1 3
Main SSG
AUTO
C L K Y C A
Auto operationprocess
CLK18ICLK13ICLK27I CLKGEN
Clock generate
T V S E L 0
Y/C
C L K Y C A
Y/C signalprocess
IWD
C L K 1 4
Frequencyconverter
KIZUWhite noise
compensation
SELECT
C L K 1 3
ANA I/F
C L K 1 3
Analog inputinterface
N T S C / P A LColor Encoder
C L K E N C 2
ENC
C L K E N C 1
CVF
C L K 1 3
Interface for ColorViewfer
KASHA
C L K 1 3
Shutter soundoccurrence
D/A Converter
C L K E N C 1
YDAC
C O
D/A Converter
C L K E N C 2
CDAC
D/A Converter
C L K 1 3
Y2DAC
Y2O
D/A Converter
C L K 1 3
RYDAC
D/A Converter
C L K 1 3
BYDAC
D/A Converter
KDAC
RYO
RYO
K O
B E N DP W M
A F B E N D
AYO [3:0]ACO [3:0]
C O U T
Y2OUT
R Y O U T
B Y O U T
K O U T
C L K Y C A
IRSI
H D Y C AV D Y C A
F L D Y C A
V B D A T
V B S T A R T
Test signal generator / Wipe / OSD mixHadamard NR / Mix / Signal select
C S Y N CH D A N AV D A N A
C S Y N C 1
DYI [3:0]DCI [3:0]
EOUT1 EOUT5 EOUT9EOUT2 EOUT6 EOUT10EOUT3 EOUT7 EOUT11EOUT4 EOUT8 EOUT12
C L K 2 7
INHAINVA A N A C N T
FMY [7:0]FMC [3:0]
TMY [7:0]TMC [3:0]
IE1 FMRE1 FMWE1IE2 FMRE2 FMWE2
O M T
MCLK RADF M W R W A DR A E 1 W A E 1R A E 2 W A E 2
DSC I/F
C L K 1 3
DSC interface
F L D D S CC L K D S C
H D D S C VDDSC
C L K Y C A
DSYO [7:0]DSCO [7:0]
DSYI [7:0]DSCI [7:0]
EDAC
12ch EVR DAC
ESSG
C L K 1 3
SSG for Encoder
C B L KC S Y N CB FL S WH R S T 4 TV R S T 4 T
VBGEN
C L K 1 3
V B I D / W S SGenerator
YCIN
L H F O
A D Y C
C L K Y C AA D K Z
H D T GV D T G
S L E N
OSD I/F
C L K 1 3C L K 1 3 X
OSD Interface
DVC I/F
C L K 1 3
DVC Interface
C L K 2 7
D V S L S L D V
S L C V
F M S LS L F MD S S LS L D S
V B L K 0BLK10BLK20
OSY_V OSY_1OSR_V OSY_2O S B _ V
DYO [3:0]DCO [3:0]
INHINV
O U T HO U T V
VR VBLKVG BLK1VB BLK2
V C 1V C 2
H D O S DV D O S D
C L K O S D
H D A N A 1 3V D A N A 1 3
H D F M CV D F M C
F L D F M C
O U T H 1 3O U T V 1 3
C L K Y C AC L K 1 3
C L K 1 3 XC L K E N C 1C L K E N C 2
RE DSTBL W E H W E
C S R W S E LALE USEL0
U S E L 1
BUS [15:0]
CPU I/F
CPU Interface
C O N T R O L S I N G N A L
DBI[15:0]
V D M D AH D C P U V D C P U
FRP FLDCPU
Fig. 2-4-1 Camera DSP (IC4301: JCY0120) internal block diagram
2-16
2. Camera DSP (IC4301: JCY0120) pin functions (1/6)
Pin No. Label In/Out Description100 VDMDA Out Vertical reference signal output for MDA 158 PWM Out PWM output20 CLK45 Out 4.5MHz output1 VSS - Ground for Digital
251 VDDE - Power supply for Digital (I/O)255 CSYNCI191 HDANA117 VDANA36 ANACNT33 AY00
113 AY01186 AY0232 AY0335 AC0034 AC01
187 AC02114 AC03188 INHA115 INVA138 ADDVSS - Ground for add Digital 256 VDDE - Power supply for Digital (I/O)64 VSS - Ground for Digital69 ADDVDDE - Power supply for add Digital (I/O)
137 DSYO0208 DSYO1270 DSYO261 DSYO3
136 DSYO4207 DSYO560 DSYO659 DSYO7
140 DSCO0210 DSCO1272 DSCO2142 DSCO3139 DSCO4209 DSCO563 DSCO662 DSCO7
211 CLKDSC Out Clock for DSC141 HDDSC Out Horizontal reference pulse output for DSC212 VDDSC143 FLDDSC70 ADDVSS - Ground for add Digital
271 VDDE - Power supply for Digital (I/O)146 DSYI0215 DSYI1145 DSYI2
Not used-
Not used-
Out Vertical reference pulse output for DSC
In Digital luminance signal input for DSC
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (1/6)
2-17
•••• Camera DSP (IC4301: JCY0120) pin functions (2/6)
Pin No. Label In/Out Description65 DSYI3
276 DSYI4214 DSYI5144 DSYI6213 DSYI7217 DSCI0148 DSCI168 DSCI2
278 DSCI3216 DSCI467 DSCI5
147 DSCI666 DSCI730 TVSEL In TV system select (L: NTSC, H: PAL)
112 CPUSEL0 In CPU select (L: n, H: M)185 CPUSEL1 In CPU select 1 (L: MN2_H: MN3)273 VDDI - Power supply for Digital (I/O, internal)275 ADDVDDE - Power supply for add Digital (I/O)106 TCK178 TMS245 TRST In Test terminal (for JTAG with pull-up)179 TDIN105 TDOUT31 ADDVSS - Ground for add Digital
252 VDDI - Power supply for Digital (I/O, internal)21 ADDVSS - Ground for add Digital 22 VSS - Ground for Digital
125 DACTEST In Test terminal for DAC184 AVDDA - Power supply for Analog sound250 DVDDM - Power supply for DAC248 AVDDV2 - Power supply Analog video249 AVSSA - Ground for Analog sound26 AVSSV2 - Ground for Analog video28 VREFHK In Reference voltage input, top side (for shutter sound)
111 VREFLK In Reference voltage input, bottom side (for shutter sound)29 K_OUT Out Shutter sound output 25 IREFVF In/Out Reference register terminal for current adjustment, (for VF signal)
110 VREFVF In Reference voltage input terminal for adjustment, (for VF signal)27 B-Y_OUT Out B−Y signal output for VF
182 R-Y_OUT Out R−Y signal output for VF24 IREFC In/Out Reference register terminal for current adjustment,(for chromatic signal)
247 VREFC In Reference voltage input terminal for adjustment,(for chromatic signal)109 C_OUT Out Modulation color signal output23 IREFY In/Out Reference register terminal for current adjustment,(for luminance signal)
107 VREFY In Reference voltage input terminal for adjustment,(for luminance signal)181 Y_OUT Out Luminance signal output183 Y2_OUT Out Luminance signal output for VF108 AVSSV1 - Ground for Analog video
Not used-
In Digital luminance signal input for DSC
In Digital color difference signal input for DSC
Not used-
Not used-
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (2/6)
2-18
•••• Camera DSP (IC4301: JCY0120) pin functions (3/6)
Pin No. Label In/Out Description246 AVDDV1 - Power supply for Analog video180 NC - Not used222 AVSSE3 - Ground for EVR79 VREFL3 In Reference voltage input for bottom side75 VREFH3 - Power supply for EVR78 AVDDE3 - Power supply for EVR
223 DVDDM - Power supply for DAC220 AVSSE2 - Ground for EVR221 VREFL2 In Reference voltage input for bottom side74 VREFH2 In Reference voltage input for top side75 AVDDE2 - Power supply for EVR
279 NC - Not used71 AVSSE1 - Ground for EVR
150 VREFL1 In Reference voltage input for bottom side218 VREFH1 In Reference voltage input for top side72 AVDDE1 - Power supply for EVR
149 EOUT1 Out EVR output 1280 EOUT2 Out EVR output 2219 EOUT3 Out EVR output 373 EOUT4 Out EVR output 4
281 EOUT5 Out EVR output 5151 EOUT6 Out EVR output 6152 EOUT7 Out EVR output 7282 EOUT8 Out EVR output 877 EOUT9 Out EVR output 9
153 EOUT10 Out EVR output 10283 EOUT11 Out EVR output 11154 EOUT12 Out EVR output 12162 ADDVDDE - Power supply for add Digital (I/O)126 ADDVSS - Ground for add Digital 167 ADDVDDE - Power supply for add Digital (I/O)284 VSS - Ground for Digital286 VDDE - Power supply for Digital (I/O)269 VSS - Ground for Digital266 VDDE - Power supply for Digital (I/O)254 VSS - Ground for Digital263 ADDVDDE - Power supply for add Digital (I/O)192 ADDVSS - Ground for add Digital 177 ADDVDDE - Power supply for add Digital (I/O)101 NAND2_O Out NAND 2 output 102 NAND2_B In NAND 2 input B176 NAND2_A In NAND 2 input A175 NAND1_O Out NAND 1 output 242 NAND1_B In NAND 1 input B103 NAND1_A In NAND 1 input A15 ADDVDDE - Power supply for add Digital (I/O)
274 VSS - Ground for Digital267 VDDI - Power supply for Digital (I/O, internal)
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (3/6)
2-19
•••• Camera DSP (IC4301: JCY0120) pin functions (4/6)
Pin No. Label In/Out Description99 CSYNC Out Internal composite sync. Signal output238 ADDVSS - Ground for add Digital 174 DYO018 DYO119 DYO2240 DYO3239 VSS - Ground for Digital243 VDDI - Power supply for Digital (I/O, internal)16 DCO017 DCO197 DCO298 DCO3173 INH Out Horizontal reference pulse output for DVC REC172 INV Out Vertical reference pulse output for DVC REC13 DYI014 DYI1169 DYI212 DYI3277 VDDI - Power supply for Digital (I/O, internal)244 VSS - Ground for Digital95 DCI0170 DCI194 DCI211 DCI3171 OUTH In Horizontal reference pulse input for DVC PB96 OUTV In Vertical reference pulse input for DVC PB241 VDDE - Power supply for Digital (I/O)203 MCLK Out Clock output for field memory49 IE1 Out Input enable 130 FMWE1 Out Memory write enable48 WAD Out Write address200 RAD Out Read address 201 FMRE1 Out Memory read enable50 RAE1 Out Read address enable129 FMWR Out Memory write transfer265 WAE1 Out Write address enable258 VDDI - Power supply for Digital (I/O, internal)259 VSS - Ground for Digital206 ADDVDDE - Power supply for add Digital (I/O)51 IE2131 FMWE2202 FMRE252 RAE253 WAE2134 TMY0205 TMY156 TMY255 TMY3
Not used-
In Digital luminance signal input for DVC
In Digital colon difference signal input for DVC
Out Digital luminance signal output for DVC
Out Digital luminance signal output for field memory
Out Digital colon difference signal output for DVC
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (4/6)
2-20
•••• Camera DSP (IC4301: JCY0120) pin functions (5/6)
Pin No. Label In/Out Description204 TMY4133 TMY554 TMY6
132 TMY7135 TMC058 TMC1
268 TMC257 TMC347 ADDVDDE - Power supply for add Digital (I/O)
128 ADDVSS - Ground for add Digital 261 FMY0197 FMY1260 FMY2196 FMY3195 FMY4194 FMY5193 FMY6257 FMY7199 FMC046 FMC1
127 FMC2198 FMC3262 VDDI - Power supply for Digital (I/O, internal)236 VDDE - Power supply for Digital (I/O)237 VDDI - Power supply for Digital (I/O, internal)43 VSS - Ground for Digital
190 ADDVDDE - Power supply for add Digital (I/O)44 CLK2742 CLK1845 CLK13
123 ID In Line discriminate pulse input189 VDTG Out Vertical reference pulse output for TG116 HDTG Out Horizontal reference pulse output for TG 253 LHFO Out LHF signal output86 ADDVDDE - Power supply for add Digital (I/O)
264 VSS - Ground for Digital118 ADIN937 ADIN8
119 ADIN738 ADIN6
120 ADIN539 ADIN4
121 ADIN340 ADIN2
122 ADIN141 ADIN0
232 VDDI - Power supply for Digital (I/O, internal)7 ADDVSS - Ground for add Digital
Digital colon difference signal input form field memory
Digital luminance signal intput form field memory
In
In Clock input
Out Digital colon difference signal output for field memory
In
In Digital signal input from A/D
Out Digital luminance signal output for field memory
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (5/6)
2-21
•••• Camera DSP (IC4301: JCY0120) pin functions (6/6)
Pin No. Label In/Out Description6 ADDVDDE - Power supply for add Digital (I/O)9 RE In Read enable
235 HWE In High address write enable 8 LWE In Low address write enable
168 ALE In Address latch enable230 BUS1587 BUS14
163 BUS13231 BUS12
2 BUS1188 BUS10
164 BUS989 BUS83 BUS7
90 BUS64 BUS5
165 BUS4233 BUS3
5 BUS291 BUS1
166 BUS0234 VSS - Ground for Digital124 CLR In Clear input160 VDCPU Out Vertical reference pulse output for CPU228 HDCPU Out Horizontal reference pulse output for CPU159 FRP Out Frame detect pulse output 227 OMT Out EIS read-out data enable flag output85 AFBEND Out CPU interrupt pulse output
161 FLDCPU Out Field discriminate pulse output for CPU287 BEND Out Block average data interrupt pulse output229 VSS - Ground for Digital92 DSTB In Data strobe
104 VPD In Test pin for pull-up10 CS In Chip select93 RWSEL In Read write select
288 VDDI - Power supply for Digital (I/O, internal)157 CLKOSD Out Clock output for OSD84 HDOSD Out Horizontal reference signal for OSD
226 VDOSD Out Vertical reference signal for OSD225 BLK1 In Blank signal 1156 BLK2 In Blank signal 281 VC1 In Character signal 1
224 VC2 In Character signal 2155 VR In Character signal 3R82 VG In Character signal 3G
285 VB In Character signal 3B80 VBLK In Blank signal 383 ADDVSS - Ground for add Digital
In/Out CPU bus I/O
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (6/6)
2-22
2.5 EXPLANATION OF DECK CIRCUIT2.5.1 Deck system overall structureThe DVC deck system has such the IC construction as shown in Fig. 2-5-1. The DV-MAIN IC (IC3001)serves as the center IC of the deck system IC construction, and this system has been incorporated in themodels of the GR-DVX7 and after.In recording, the deck system processes image data input from the camera section by shuffling and DVcompression and adds parity codes to it as well as the audio data and sub code data input to the decksystem, and saves those data as sync blocks.The formatter inside the DV-MAIN IC serves as the 24-25 converter for generating ATF pilot signal and thedata column converter for adapting the data to the digital magnetic recording/playback system (scrambledinterleaved NRZI), and it outputs the processed data to the PRE/REC IC as recording data.In playback the playback signal transmitted from the PRE/REC IC is input to the DV-ANA (IC3301) andDV-EQ (IC3201) for waveform equalization, and then supplied to the DV-MAIN IC as playback data. TheDV-EQ IC takes charge of various functions such as playback clock generation, VITERBI decoding, ATFdetection, and so on. For details of its functions, refer to the next page.The DV-MAIN IC processes playback data by the reverse procedure of recording and it transmits playbackdata to the camera section and audio section. Since the DV-MAIN IC has the 1394 LINK function, it inputsand outputs DV data from/to the camera through the 1394 PHY IC (IC3101).The 16-Mbits DRAM (IC3002) is used as the memory for shuffling/de-shuffling and ECC error correction.
IC3001DV_MAIN
Shuff l ing / De-shuff l ingCompress / De-compress
ECC Encode / DecodeFormatter / Deformatter
1394 LINK
IC3201D V _ E QAuto EQ
ViterbiPLL det
IC3301D V _ A N A
A G CPB VCO
IC3501PRE/REC H E A D
C A M E R A
AUDIO
IC30021 6 M D R A M
IC31011394 PHY
D VIN/OUT
Fig. 2-5-1 DVC deck IC structure
2-23
2.5.2 PB equalizer and ATF
LPFA G C
B P FG C A
A D 1A U T O
E Q1+DVITERBI
PLLD E T 2 C H
D A CP W M
A D 2ATF
C P UI/F
J I G C O N NP B _ V C O
IC3202
P B _ E N V
DISCRI
R E C C L K
P B _ D A T A
P B _ C L K
R E C C T L
A D D T0:15
To:D E C KC P U
IC3301IC3201 D V _ A N AD V _ E Q
41.85MHz
41 .85MHz
+-
P B O
A T F O
P L L O
C L K
V O A
V O B R E F V
P L L E
A I N A D 2
A I N A D 1
A T F _ G A I N
D I S C RC T L 1
D T R
R E C : H
S W
V C O
PB:H
V C O C
C L K O
To:D VM A I N
Fig. 2-5-2 PB equalizer and ATF block diagram
In the playback mode the PB ENV signal output from the PB amplifier is branched into two in the IC3301DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output throughthe LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal outputthrough the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF.In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTOEQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed asmentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuitconstructed in this circuitry controls phase correction in order to generate the PB clock synchronizing withthe playback signal. The 41.85MHz signal oscillated by the internal VCO of the IC3301 is output as the PBclock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switchis turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, inthe Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator(DISCRI) compares the 41.85MHz signal oscillated from the VCO with the other 41.85MHz signalproduced from the 81MHz of the main clock in order to detect a difference between the two frequencies. Inthe general playback mode, the discriminator outputs a Low-level signal when the frequency difference is+1% or more or a High-level signal when the difference is −1% or more. In the other modes, a Low-levelsignal is output when the frequency difference is +3% or more or a High-level signal is output when thedifference is −3% or more. When the frequency difference is within ±1% in the general playback mode orwithin ±3% in the other modes, the output signal has high impedance. Therefore, a frequency difference, ifthere is, is roughly corrected.Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from theplayback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detectionresult is transmitted to the servo CPU.
2-24
2.5.3 PLL operation
X5501
54MHz
T GV.DRV
IC5501
V C X O
V C O
X3301
81MHz
PH
YC
LK
P W M 4 0 5
IC3001CLK
27
V C O V C O A U DP W M A U D
V C O A U D
ANA_PD
X3001
24.576MHz
MAIN_VCO
MAIN_VCOADJ
FS_PLLADJ
J IG CONN
IC3301
FS_PLLJ IG CONN
CLKO S C
P C
FRPG E N
81MHz
41.85MHz Serial I /F
FromD E C K _ C P U
12.288MHz11.289MHz8.192MHz
D V D S P
D V A N A
FRPG E N
MAIN CLK
1394LINK
REF
1394P H Y
P C
REF
27MHz FRP
FRP
D O M C K
40.5MHz Not used
REC CLK
IC3101
ANA_DATA
VC
O40
5I
VCO405
IC3007
Fig. 2-5-3 PLL operation block diagram
The main clock for the deck section operates at a frequency of 40.5MHz, which is equivalent to 18MHz forthe previous models. Since two memories of the SHUFFLE memory and the ECC memory that areneeded for the previous models are integrated into one DRAM, the clock frequency is raised in order toincrease the processing speed. For setting the clock duty ratio exactly at 50%, 40.5MHz clock is producedfrom the 81MHz clock. The PLL circuit of the main clock system produces 81MHz clock by the X'TALX3301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse producedfrom the 81MHz pulse as the comparison signal of the PLL, the frame pulse (29.97Hz in NTSC or 25Hz inPAL) is produced from the 27MHz pulse output from the camera and this frame pulse is used as thereference signal of the PLL in the general recording and playback modes. However, the frame pulseproduced by decoding the input DV signal is used as the PLL reference signal for phase comparison in the1394 input mode. A phase error is output as the PWM405 signal, which passes through the filter circuitand controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2V ±0.1V) of the tolerance in the condition that the PLL is locked.There are three audio sampling frequencies (32kHz, 44.1kHz and 48kHz) provided, therefore, masterclocks (8.192MHz, 11.289MHz and 12.288MHz) are produced by the VCO in the IC3301 for therespective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjustingthe FS-PLL, the respective frequencies are adjusted in the free-run status.
2-25
2.5.4 Basic principle of Viterbi detection
Record ingsignal
1 V
-1V
0 V
Threshold level
"1"
"0"
"-1"
P Bsignal
"1" "0" "0" "1" "0"Usual detect ion
(Hard decis ion)
Vi terb i decoder
0.01.0 -0.4 0.8 0.0 (V)
ERROR ! !
A /D converter
"1" "0" "0" "1" "0"
"1" "0" "-1" "1" "0"
Select the mostrel iable l ine
point A
Threshold level
Fig. 2-5-4 Basic principle of Viterbi detection
Fig. 2-5-4 is a conceptual chart showing the basic principle of Viterbi decoding method. Decoding means aternary decision that judges differential waveform at the identification point by the ternary criteria whenNRZI-recorded signal is played back.The previous detection method is based on the ternary criteria of the preset identification level, and thismethod is called the hard decision because of the fixed identification level. By this method, for example,the identification value at the point "A" (in Fig.2-5-4) is "0", which represents an error occurrence.On the other hand, the Viterbi decoding adopts the soft decision method. In the Viterbi decoding, playbacksignal is converted from analog to digital data and then the signal level is read. If the signal level is 0.4V atthe point "A" by ways of example, the previous method judges it as "0", but the Viterbi decoding methoddetects a possibility that it may be "0" or "1" and it assumes two kinds of bit strings of "10010" and "10110".Next, the Viterbi method introduces another criterion in decision. In the NRZI recording, there is aregularity in the recording signal and playback waveform. That is to say, there is a fall point between tworise points in the recording signal. This means that there must be "−1" between "1" and "1". According tothis principle, the bit string of "10010" is theoretically non-existent, and "10110" is consequently selected.As mentioned above, the Viterbi decoding method utilizes the regularity between bits or the redundancy ofNRZI-recorded signal for error correction. The above explanation of the Viterbi decoding method is just aconceptual description, and a high degree of data processing system such as to select the most possiblebit string from a great deal of probabilities is introduced in the actual Viterbi decoding.
2-26
2.5.5 Audio recording modeThere are four basic modes in the DVC audio mode as shown in Table 2-5-1, and it is recommended thatthe DVC can cover all of the four basic modes by the specifications.
Mode Channel Sampling frequency Quantiazation
48K mode 48kHz
44.1K mode 44.1kHz
32K mode 32kHz
32K-4ch mode 4 32kHz 12-bit non- linear
2 16-bit linear
Table 2-5-1 Audio basic modes
CH 1 CH 2
V I D E O
A U D I O
1 Frame (10 Tracks)
Tape travel
Head m
otion
CH 1 CH 2
V I D E O
A U D I O
1 Frame (12 Tracks)
Tape travel
Head m
otion
NTSC 525/60 sys tem
PAL 625/50 sys tem
Fig. 2-5-5 Audio track pattern
2-27
The audio recording system of this model is as follows. In the 2-channel mode, quantiazation is linearlyprocessed in a data unit of 16-bits and the sampling frequency is 48kHz. In regard to the recording pattern,the first 5 tracks (6 tracks in PAL) of 10 tracks (12 tracks in PAL) in a frame is used for CH1 recording andthe second 5 tracks in a frame is used for CH2 recording. Since audio data for one channel is interleavedextending over 5 tracks (6 tracks in PAL), it is possible to interpolate audio data by 1/5 (or 1/6 in PAL) ifthere is a data error in a track.In the 4-channel mode, quantiazation is non-linearly processed to convert 16-bits input data into 12-bitdata and the sampling frequency is 32kHz. In regard to the recording pattern, the CH1 is used forrecording sound-1 while the CH2 is used for recording sound-2 which is used for audio dubbing. Theprevious models show the audio mode by the sampling frequency of 48kHz or 32kHz, however, the recentmodels show it by 16-BIT or 12-BIT to meet the market trend.
Sound mode Sampling
(MENU) frequency
L chR chL ch AudioR ch dubbing
L ch
R ch
Channel
16 BIT 48kHzCH 1
CH 2
SOUND 1
SOUND 212 BIT 32kHz
CH1
CH2
Table 2-5-2 Channel format
2.5.6 Audio signal processingThis model adopts a new audio signal processing IC, which comes equipped with AD and DA converter.
Rch
Lch
P H A S EE Q
E Q
H P F
H P F
A L C
A L CP H A S E
A D CA U D I O
I/FD A C
M U T E
M U T E
V O L
V O LMIX
MIX
MIX
A DI/F
D AI/F
C L K
MIX
MIX
16 → 12bitsC O N V E R T
12 → 16bitsC O N V E R T
F A D E R
D R A MI/F
S P
SHUTTER
IC2201 Audio & A/D_D/A
IC3001 DECK DSP
MIC
C H 1
C H 2
C H 1
C H 2
AIDAT
D O D A T
D O M C KD O B C K
D O L R C K
OFF
O N
OFF
O N
EE/REC
PB
PB
EE/REC
A/V OUT
Fig. 2-5-6 Audio block diagram
2-28
2.5.7 Clock system for audio dataDOMCK (Master Clock)
Sampling frequency DOMCK
48kHz 256fs: 12.288MHz
32kHz 384fs: 12.288MHz
48kHz 256fs: 12.288MHz
44.1kHz 256fs: 11.2896MHz
32kHz 256fs: 8.192MHz
A. Dubbing 32kHz 256fs: 8.192MHz
REC
PLAY
DOBCK (Serial Clock)Sampling frequency DOBCK
48kHz 36fs: 1.536MHz
32kHz 36fs: 1.024MHz
48kHz 36fs: 1.536MHz
44.1kHz 36fs: 1.4112MHz
32kHz 36fs: 1.024MHz
A. Dubbing 32kHz 36fs: 1.024MHz
REC
PLAY
DOLRCK (LR Clock)Sampling frequency DOLRCK
48kHz 48kHz
32kHz 32kHz
48kHz 48kHz
44.1kHz 44.1kHz
32kHz 32kHz
A. Dubbing 32kHz 32kHz
REC
PLAY
Table 2-5-3 Clock frequencies
15 14 13 012 15 14 13 012
1 20 13 14 15 1 20 13 14 15
L ch DATA R ch DATA
D O L R C K
D O B C K
D O D A TAIDAT
M S B LSB
Fig. 2-5-7 Timing chart
2-29
2.5.8 Deck DSP IC function1. Deck DSP (IC3001: JCY0106-2) pin functions (1/6)
Pin No. Label In/Out Description
69 VDD - Power supply
1 GND - Ground
134 PWMAUDO Out Audio PLL control signal, (To DVANA: IC3301)
70 VDDS
2 VDD
71 VCOAUDI In PB audio b PLL input, (From DVANA: IC3301)
3 VCOAUDO Out PB audio b PLL adjustment voltage output
135 GND - Ground
189 VDD - Power supply
226 OSC32I - L: Fixed (Not used)
72 - - Not used
4 OSC32O - Open (Not used)
136 OSC44I - L: Fixed (Not used)
73 OSC44O - Open (Not used)
190 OSC48I In 24.5MHz clock input
5 OSC48O Out 24.5MHz clock output
227 GND - Ground
137 AUDIOTESTI - L: Fixed
74 AUDIOTESTIO - H: Fixed
6 VDDS - Power supply
191 DILRCK
138 DIBCK
75 DIMCK
7 DIDAT
8 AILRCK Out Serial I/O interface channel clock for ADC, (To ADC: IC2101)
76 AIBCK Out Audio serial data clock, (To ADC: IC2101)
139 AIMCK Out Audio master clock, (To ADC: IC2101)
192 PHYCLK Out IEEE 1394 crystal oscillator output (27MHz), (To 1394 PHY: IC3101)
228 GND - Ground
9 AIDAT [0]
77 AIDAT [1]
140 DOLRCK
193 DOBCK
229 DOMCK
10 DODAT
78 VDD - Power supply
141 AOLRCK
230 AOBCK
194 AOMCK
11 AODAT [0] Out Audio serial data output, (To ADC: IC2101)
79 AODAT [1] - Open (Not used)
142 VDDS - Power supply
231 GND - Ground
Open (Not used)-
L: Fixed (Not used)-
Audio serial data input, (From ADC: IC2101)In
- Power supply
Open (Not used)-
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (1/6)
2-30
•••• Deck DSP (IC3001: JCY0106-2) pin functions (2/6)
Pin No. Label In/Out Description
195 - - Not used
12 YSO [0]
80 YSO [1]
143 YSO [2]
232 YSO [3]
13 BRSO [0]
81 BRSO [1]
196 BRSO [2]
144 BRSO [3]
14 - - Not used
233 VDDS - Power supply
82 YSI [0]
197 YSI [1]
145 YSI [2]
15 YSI [3]
83 BRSI [0]
16 BRSI [1]
146 BRSI [2]
84 BRSI [3]
17 VDD - Power supply
147 OUTH Out Horizontal reference pulse output for DVC PB, (To CAMERA DSP: IC4301)
85 OUTV Out Vertical reference pulse output for DVC PB, (To CAMERA DSP: IC4301)
18 INH In Horizontal reference pulse input for DVC REC, (From CAMERA DSP: IC4301, )
148 INV In Vertical reference pulse input for DVC REC, (From CAMERA DSP: IC4301)
86 GND - Ground
19 VDD - Power supply
87 OSC27I In 27MHz clock input, (From CAMERA DSP: IC4301)
20 OSC27O - Open (Not used)
149 GND - Ground
196 VDD - Power supply
234 - - Not used
88 RAMADRS [0]
21 RAMADRS [1]
150 RAMADRS [2]
89 RAMADRS [3]
199 VDDS - Power supply
22 RAMADRS [4]
235 RAMADRS [5]
151 RAMADRS [6]
90 RAMADRS [7]
23 GND - Ground
200 RAMADRS [8]
152 RAMADRS [9]Out DRAM address output, (To 16M_DRAM: IC3002)
Out DRAM address output, (To 16M_DRAM: IC3002)
Out DRAM address output, (To 16M_DRAM: IC3002)
Out DVC playback digital luminance signal output, (To CAMERA_DSP: IC4301)
DVC playback digital color difference signal output, (To CAMERA_DSP: IC4301)Out
DVC record digital luminance signal input(From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801)
DVC record digital color difference signal input(From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801)
In
In
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (2/6)
2-31
•••• Deck DSP (IC3001: JCY0106-2) pin functions (3/6)
Pin No. Label In/Out Description
91 - - Not used
24 VDD - Power supply
25 RAMWE Out Write enable output, (To 16M_DRAM: IC3002)
92 RAMRAS Out Lower address strobe, (To 16M_DRAM: IC3002)
153 RAMCAS [0] Out Address strobe (Lower bit), (To 16M_DRAM: IC3002)
201 RAMCAS [1] Out Address strobe (Upper bit), (To 16M_DRAM: IC3002)
235 RAMOE Out Output enable (L: active), (To 16M_DRAM: IC3002)
26 VDDS - Power supply
93 RAMDATA [0]
154 RAMDATA [1]
202 RAMDATA [2]
237 RAMDATA [3]
27 RAMDATA [4]
94 RAMDATA [5]
155 RAMDATA [6]
238 RAMDATA [7]
203 VDD - Power supply
28 - - Not used
95 RAMDATA [8]
156 RAMDATA [9]
239 RAMDATA [10]
204 RAMDATA [11]
29 RAMDATA [12]
96 RAMDATA [13]
157 RAMDATA [14]
240 RAMDATA [15]
30 GND - Ground
97 XRESET In Reset pulse input, (From DECK CPU: IC1401)
205 GND - Ground
158 CPUALE In Bus address strobe signal input, (From DECK CPU: IC1401)
31 XCPUDSTB [0] In Bus memory write enable signal input, (From DECK CPU: IC1401)
241 XCPUDSTB [1] In Bus memory read enable signal input, (From DECK CPU: IC1401)
98 XCPURW In Bus read/write select signal input, (From DECK CPU: IC1401)
206 XCPUCS In Chip select input, (From DECK CPU: IC1401)
159 - - Not used
32 XINT - Open (Not used)
99 CPUWAIT In Wait command, (From DECK_CPU: IC1401)
33 CPUAD [0]
160 CPUAD [1]
100 CPUAD [2]
34 CPUAD [3]
161 VDD - Power supply
101 CPUAD [4] In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)
In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (3/6)
2-32
•••• Deck DSP (IC3001: JCY0106-2) pin functions (4/6)
Pin No. Label In/Out Description
35 CPUAD [5]
162 CPUAD [6]
102 CPUAD [7]
36 GND - Ground
103 - - Not used
37 CPUAD [8]
163 CPUAD [9]
207 CPUAD [10]
242 CPUAD [11]
104 VDDS - Power supply
38 CPUAD [12]
164 CPUAD [13]
105 CPUAD [14]
208 CPUAD [15]
39 VDD - Power supply
243 CPUWAITH - H: Fixed (Not used)
165 VDD - Power supply
106 TESTIO [0]
40 TESTIO [1]
209 TESTIO [2]
166 TESTIO [3]
107 TESTIO [4]
41 TESTIO [5]
42 TESTIO [6]
108 TESTIO [7]
167 - - Not used
210 VDDS - Power supply
244 TESTIO [8]
43 TESTIO [9]
109 TESTIO [10]
168 TESTIO [11]
211 TESTIO [12]
245 TESTIO [13]
44 TESTIO [14]
110 TESTIO [15]
169 GND
246 GND
212 TESTIO [16]
45 TESTIO [17]
111 TESTIO [18]
170 TESTIO [19]
247 TESTIO [20]
213 TESTIO [21]
In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
Open (Not used)-
In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
Ground -
Open (Not used)-
Open (Not used)-
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (4/6)
2-33
•••• Deck DSP (IC3001: JCY0106-2) pin functions (5/6)
Pin No. Label In/Out Description
46 TESTIO [22]
112 TESTIO [23]
171 VDD - Power supply
248 - - Not used
47 SCANENABLE
113 SCANMODE
214 TRST In Reset signal input for boundary scan
172 TDI - H: Fixed (Not used)
48 TCK - L: Fixed (Not used)
249 TMS - H: Fixed (Not used)
114 TDO - Open (Not used)
215 TEST - L: Fixed (Not used)
173 VDD - Power supply
49 PHYDATA [3]
115 PHYDATA [2]
50 PHYDATA [1]
174 PHYDATA [0]
116 VDDS - Power supply
51 SCLK Out IEEE1394 system clock (49.152MHz), (To 1394PHY:IC3101)
175 LOCONT - H: Fixed
117 XPHYISO Out Link interface isolation status (H: Enable), (To 1394PHY: IC3101)
52 PHYCTL [1]
176 PHYCTL [0]
118 PHYLREQ - IEEE1394 link request signal output, (To 1394PHY:IC3101)
53 GND - Ground
119 VDD - Power supply
54 EXTCLKIN
177 EXREQ
216 EXRW - H: Fixed (Not used)
250 EXREADEMPTY
120 EXWRITEFULL
55 VDDS - Power supply
178 - - Not used
121 EXTDATA [0]
217 EXTDATA [1]
56 EXTDATA [2]
251 EXTDATA [3]
179 EXTDATA [4]
122 EXTDATA [5]
57 EXTDATA [6]
218 EXTDATA [7]
180 VDD - Power supply
123 GND - Ground
In/Out Link interface data input/output, (From/To 1394PHY: IC3101)
Open (Not used)-
L: Fixed (Not used)-
L: Fixed (Not used)-
Link interface control (H: output), (From/To 1394PHY: IC3101)In/Out
Open (Not used)-
Open (Not used)-
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (5/6)
2-34
•••• Deck DSP (IC3001: JCY0106-2) pin functions (6/6)
Pin No. Label In/Out Description
58 PWM405O Out 40.5MHz (PLL control output) 1/2 frequency of VCO405I, (To DVANA: IC3301)
59 VDDS
124 VDD
181 VCO405I In 81MHz VCO reference clock input, (From DVANA: IC3301)
219 VCO405O - Open (Not used)
252 GND - Ground
60 VDD - Power supply
125 CLK81SEL In H: Fixed (Not used)
182 FRRES - L: Fixed
220 FRREF In Frame reference signal input, (From DECK CPU: IC1401)
253 SERVOFRREF - Open (Not used)
61 TRKREF In Drum servo reference signal input (150Hz), (From DECK CPU: IC1401)
126 SERVOTRKREF - Open (Not used)
183 GND - Ground
254 - - Not used
221 PF [0]
62 PF [1]
127 SBE Out Sync block error (Error pulse output)
184 HID
255 HSP
222 - - Not used
63 PBDATA In VITERBI processing termination playback data input, (From DVEQ: IC3201)
128 PBCLK In VITERBI processing termination playback clock input, (From DVEQ: IC3201)
185 VDDS - Power supply
256 TPNO [0]
64 TPNO [1]
129 TPNO [2]
223 RECDATA Out HSE (record data) output, (To PRE/REC: IC3501)
186 RECCTL Out Recording current control (H: ON), (To DVANA: IC3301)
65 SPA Out Pulse output for ATF sample, (To DVEQ: IC3201)
225 RECCLK Out Recording reference clock 41.85MHz
130 GND - Ground
224 VCCA - Power supply
187 VCO4185 - Constant for 41.85MHz VCO
66 GNDA
131 GND
67 OSC4185I - L: Fixed (Not used)
188 OSC4185O - Open (Not used)
132 VDD
68 VDD
133 GND - Ground
Head switch pulse (CH1: H, CH2: L), (To DECK CPU: IC1401)Out
Power supply-
Open (Not used)-
Ground-
Power supply-
Open (Not used)-
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (6/6)
2-35
2.5.9 Audio AMP IC function1. Audio AMP (IC2201: AK4560VQ) pin locations and block diagram
E Q _ N _ R
P R E _ O _ R
P R E _ N _ R
INT MIC Rch
M R F
M V C M 2 V
GND (MVDD)
M V D D
INT MIC Lch
EXT MIC Lch
MA BIAS 2V
P R E _ N _ L
P R E _ O _ L
E Q _ N _ L
EQ
_P_R
EQ
_O_R
HP
F_P
_R
HP
F_O
_R
MIC
_IN
_R
MIC
SE
L
SP
K-
ND
SP
K+
PD
MC
LK
LRC
K
BC
LK
CC
LK
HP
F_P
_L
HP
F_O
_L
MIC
_IN
_L
VC
OM
1.5
V
VR
EF
1.5V
GN
D (
VA
)
VA
3V
LIN
E O
UT
2 R
ch
OP
GR
LIN
E O
UT
2 Lc
h
OP
GL
BE
EP
SH
T
AV
R O
UT
C S
D A T A
SDTI
S D T O
GND (VD)
VD 3V
A _ M U T E
HP OUT Lch
HP OUT Rch
HVDD 4 .8V
HVCM 2 .4V
LINE OUT Rch
LINE IN Rch
LINE OUT Lch
LINE IN Lch
SP IN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
M P W R 3 . 3 V
EXT MIC Rch
EQ
_O_L
EQ
_P_L
GN
D (
SV
DD
)
SV
DD
4.8
VContro l
Regis terI/F
MIX
Audio I /FControl ler
H P FA/D Conver ter
D/A Conver ter
C lockDiv ider
MIX
MIX
H P FO F F O N
E X T
INT
VOL . VOL .A V RO U T
B E E P S I G
B E E P
S I G
L c h A L C A M P
M I C L INE
R c h A L C A M P
M I C L INE
O NH P FO F F
INT
E X T
INTE X T
E X T INT
Fig. 2-5-8 Audio AMP (IC2201: AK4560VQ) pin locations and block diagram
2-36
2. Audio AMP (IC2201: AK4560VQ) pin functions (1/2)
Pin No. Label In/Out Description
1 EQ_P_L In L-ch EQ-Amp positive input
2 EQ_O_L Out L-ch EQ-Amp output
3 HPF_P_L In L-ch HPF-Amp positive input
4 HPF_O_L Out L-ch HPF output
5 MIC_IN_L In L-ch MIC input
6 VCOM (1.5V) Out Common voltage output, (1/2VA)
7 VREF (1.5V) Out ADC, DAC reference level, (1/2VA)
8 GND (VA) - Analog ground
9 VA (3V) - Analog power supply, (3.0V)
10 LINE OUT2 (Rch) Out R-ch No. 2 line output -5.5dBV×VA=2.8V
11 OPGR In R-ch analog volume input
12 LINE OUT2 (Lch) Out L-ch No. 2 line output , -5.5dBV´VA=2.8V
13 OPGL In L-ch analog volume input
14 BEEP In Beep signal input
15 SHT In Shutter signal input
16 AVR OUT Out Analog mixing output
17 SP IN In ALC2 input
18 LINE IN (Lch) In L-ch line input
19 LINE OUT (Lch) Out L-ch No. 1 line output, +2dBV×VA=2.8V, VOL=+7.5dB
20 LINE IN (Rch) In R-ch line input
21 LINE OUT (Rch) Out R-ch No. 1 line output, +2dBV×VA=2.8V, VOL=+7.5dB
22 HVCM (2.4V) Out LINEOUT & HP-Amp common voltage output, (1/2HVDD)
23 HVDD (4.8V) - LINEOUT & HP-Amp power supply, (4.8v)
24 HP OUT (Rch) Out R-ch Headphone-Amp output
25 HP OUT (Lch) Out L-ch Headphone-Amp output
26 A_MUTE In Mute control, (L: Normal operation, H: Mute)
27 VD (3V) - Digital power supply, (3.0V)
28 GND (VD) - Digital ground
29 SDTO Out Audio serial data output
30 SDTI In Audio serial data input
31 DATA In/Out Control data I/O
32 CS In Chip select
Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (1/2)
2-37
•••• Audio AMP (IC2201: AK4560VQ) pin functions (2/2)
Pin No. Label In/Out Description
33 CCLK In Control clock input
34 BCLK In Audio serial data clock
35 LRCK In Input/Output channel clock
36 MCLK In Master clock input
37 PD In Power down & reset, (L: Power- down & reset, H: Normal operation)
38 SPK+ Out Speaker Amp positive output
39 ND In Noise decrease (L: Disable, H: Enable)
40 SPK- Out Speaker Amp negative output
41 MIC SEL In Internal/External MIC detect, (L: Internal MIC, L: External MIC)
42 GND (SVDD) - Speaker Amp ground
43 SVDD (4.8V) - Speaker Amp power supply, (4.8V)
44 MIC_IN_R In R-ch MIC input
45 HPF_O_R Out R-ch HPF output
46 HPF_P_R In R-ch HPF-Amp positive input
47 EQ_O_R Out R-ch EQ-Amp output
48 EQ_P_R In R-ch EQ-Amp positive input
49 EQ_N_R In R-ch EQ-Amp negative input
50 PRE_O_R Out R-ch Pre-Amp output
51 PRE_N_R In R-ch Pre-Amp negative input
52 MPER (3.3V) - Not used
53 EXT MIC (Rch) In External MIC Rch input
54 INT_MIC (Rch) In Internal MIC Rch input
55 MRF Out MIC power supply ripple filter
56 MVCM (2V) Out MIC block common voltage output
57 GND (MVDD) - MIC block ground
58 MVDD (4V) - MIC block power supply
59 INT_MIC (Lch) In Internal MIC Lch input
60 EXT_MIC (Lch) In External MIC Lch input
61 MA_BIAS (2V) In MIC-Amp bias
62 PRE_N_L In L-ch Pre-Amp negative input
63 PRE_O_L Out L-ch Pre-Amp output
64 EQ_N_L In L-ch EQ -Amp negative input
Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (2/2)
2-38
2.6 SYSCON CPU2.6.1 Contents of SYSCON CPU processing
1) User I/F control• Recognition of Operation Keys and Menu• Holding the User Configurations
2) Camera signal process control• TG/CDS IC• Camera DSP IC (Y/C Process, Special Effect, Encoder, OSD Mix, EVR etc.)
3) Camera Auto system control• Transferring Auto system data with Camera DSP IC• AF / AE / AW / EIS control• Lens MDA control
4) Audio control 5) VF / LCD Monitor control 6) Servo CPU control 7) PC I/F control (TCCS / JLIP) 8) Remote control 9) Power control (Power ON / OFF)10) RTC, Auto Light, RAE and others
2.6.2 Power ON process
S T A R T
S W Stable ?
SW Pos i t ion
D C / D CConver ter ON
C A M E R A D S PReset re lese
VD Pulse ?
Sleep modesett ing
E N D
1
1
Reset start ?
E E P R O MData read
PrepheralsC P U
Initialize
V D Pulse ?
E N D
Yes
N o
O N
O F F
Yes
N o
N o
Yes
N o
Yes
Fig. 2-6-1 Power ON process flow chart
2-39
2.6.3 System compositionSYSCON CPU adopted with this model has five data communication systems and communicates witheach peripheral device using those ports. There are three synchronous serial communication systems;one of these is used only for the model having DSC function. The communication with the Camera DSP isrequired a high-speed performance for transferring the information and command of camera autoprocessing. Therefore, it is adopted the 16-bit parallel bus communication. And the asynchronous serialcommunication (UART) is used for communication with external (PC, etc.).
S Y S C O NC P U
T GV.DRV
CDS / AGCA D C
F O C U SZ O O MM D A
AUDIOVF / LCD
D R V E R
C A M E R AD S P
P O W E RSUPPLY
R E M O T E
KEY
PC I/F(TCCS / JLIP)
R T C E E P R O MD E C KC P U
D E C KD S P
M D A M E C H A
16-bitMult iplex bus
Synchronous Ser ia l Communicat ion
Back UpBuilt- in LithiumBattery
U A R T
DSC IF
M32 R/DC P U
F R A S HR O M
*DSC model only
Synchronous Ser ia l Communicat ion Synchronous Ser ia l Communicat ion
Fig. 2-6-2 SYSCON CPU system structure
2-40
2.6.4 SYSCON CPU block diagram
IC1001 SYSCON CPU
C A M E R AD S P
IC4001
C D S / A G CA/D
IC5601
T GV.DRIVER
IC5502
IRIS DRV&
H A L L A M P
F O C U S /Z O O M
D R I V E R
IC4851
IC1004
EE P R O M
IC1003
R T C
IC8001
DSC_ IFM32_R/D
C P U
IC8002 IC8003
16Mbits(2MB)
FLASHR O M
61 CLK_OUT60 DATA_OUT80 TG_CS
124 CDS_CS
28 F/Z_CS114 F/Z_RST
120 IRIS_O/C
77 HOLE_AD
3-6,9-1518-22
16BUS0-15
94 CLWE95 CHWE96 CRE
115 RWSEL117 KRST/CLR
S_DT_OUT 57S_DT_IN 56
EEPROM_CS 49
RTC_CS 92
39 VD33 MFLD40 OMT
122 TG_RST
124 CCD_KIZU
IR_A/D 76WB_IR_DET 27
M32_CLK 67M32_DOUT 66
M32_CS 41
1624
PC_ IF
TXD 63
RXD 62
JLIP_INT 38
79 F_PTR_ADO P T I C A LB L O C K
RTC_INT 44
Z O O MUNIT
D E C K _ O P E
PHOTO_SW 36
DIAL_MN 102DIAL_AUTO 103
DIAL_OFF 104DIAL_PLAY 105
TRIG_SW 101
SEL_SW 100
108 MONITOR_SW
73 KEY_A
KEY_ASTOPR E WFFPLAY/PAUSED S C
KEY_BLIGHT_SW
E E PR O M
IC7603
59 DATA_IN
L I G H T _ S W
LAMP_ON 2
R E G D CL I G H T
Li +
LITHIUM
X1002
111 LCD_CS1
L C DD R V
IC7601
47 LCD_LOAD
A U D I O
64 AUDIO_CS
CLK4M5C A M _ V D
IRIS
_PW
M
78 Z_PTR_AD82 OP_THRMO
S_CLK 58
IC1401
D E C KC P U
SRV_CS 26SRV_RST 89
DSC_ IF
REG_4.8V
P W R _ L E D
MENU_SET_SW 91MENU_P_B 110
MENU_P_A 42
Z O O M _ S W 7 5
74 KEY_B
97 CALE
ODD_EVEN 125
JL IP
P C
EDIT_CTL 118JLIP_L 93
SRV_RDY 17
M32_DIN 65
DSC_RST 81DSC_PCTL 88
126 ND_H127 PD_L
128 A_MUTE123 S_MUTE
V_MUTE 37
M O N I T O R85 MONI_RVS
1 EL_CTL
54 MONI_UD53 MONI_CTL46 VF_MONI
PWR_CTL 16BATT_CHK 72
VF_CTL 48
V O U T 113 ASPECT1116 ASPECT2
J U N C T I O NEJECT_SW 106CAS_SW 107 M E C H A
R S TIC1010
3 VIC1009
RST 35
R E A RBATT_SW 84
J A C KREMOTE 55TALLY 52
AV_DET 45S_DET 43
Fig. 2-6-3 SYSCON CPU block diagram
2-41
2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)
Pin No. Label In/Out Description1 EL_CTL Out Strobe emission control (To EL driver: IC756)2 LAMP_ON Out Video light ON/OFF3 BUS04 BUS15 BUS26 BUS37 VDD - Power supply8 VSS - GND9 BUS4
10 BUS511 BUS612 BUS713 BUS814 BUS915 BUS1016 PWR_CTL Out Power control17 SRV_RDY In Ready signal (From DECK_CPU: IC1401)18 BUS1119 BUS1220 BUS1321 BUS1422 BUS1523 MODE0 In L: Fixed24 MODE1 In L: Fixed25 MODE2 In H: Fixed (VDD)26 SRV_CS Out Chip select (To DECK_CPU: IC1401)27 WB_IR_DET In Flicker detect28 F/Z_CS Out Chip select (To F/Z DRIVER: IC4851)29 VDD - Power supply30 OSCI In System clock (24MHz)31 OSCO Out System clock (24MHz)32 VSS - GND33 MFLD In Field discrimination signal34 NMI In H: Fixed35 RST In Reset36 PHOTO_SW In Snap shot switch input37 V_MUTE Out Video mute38 JLIP_INT In JLIP interrupt39 VD In Vertical sync signal40 OMT In EIS data readout timing41 M32_CS In Chip select (From DSC_IF: IC800)42 MENU_P_A In Menu dial pulse43 S_DET In S terminal connection detect signal input
Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
Address/data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
In/Out
In/Out Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
In/Out
Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)
2-42
•••• SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3)
Pin No. Label In/Out Description44 RTC_INT In Clock 1 sec. Interrupt45 AV_DET In AV plug connection detect signal input46 VF_MONI Out VF/MONI select signal47 LCD_LOAD Out LCD data load pulse48 VF_CTL Out VF_REG4.8V ON/OFF control49 EEPROM_CS Out Chip select signal (To EEPROM: IC1003)50 VDD Out Power supply51 TIMER_OUT - Not used52 TALLY Out Tally lamp53 MONI_CTL Out MONI_LCD back light control54 MONI_UD Out MONI_LCD L/R UP/DOWN reverse control55 REMOTE In Remote control input56 S_DT_IN In Serial data input (From DECK_CPU EEPROM RTC)57 S_DT_OUT Out Serial data output (To DECK_CPU TG/VDRIV CDS/AGC/ADC EEPROM RTC)58 S_CLK Out Serial clock59 DATA_IN In Serial data input (From: IC7603 LCD_SD)60 DATA_OUT Out Serial data output 61 CLK_OUT Out Serial clock output 62 RXD Out RS232C data input63 TXD In RS232C data output64 AUDIO_CS Out Chip select signal to AUDIO IC220065 M32_DIN In Serial data input (From DSC_IF: IC8001)66 M32_DOUT Out Serial data output (To DSC_IF: IC8001)67 M32_CLK In Serial clock input (From DSC_IF: IC8001)68 VDD - Power supply69 VSS - GND70 AVSS - GND71 VRefL - Reference power supply72 BATT_CHK In Battery DC input73 KEY_A In Deck operation switch input74 KEY_B In Camera operation switch input75 ZOOM_SW In Zoom switch input76 IR_AD In AWB IR sensor AD input77 HALL_AD In Iris hall generator AS input78 Z_PTR_AD In ZOOM position sensor AD input79 F_PTR_AD In FOCUS position sensor AD input80 TG_CS Out Chip select signal to TG/V.DRV IC550181 DSC_R_ST Out Reset signal output (To DSC_IF: IC8001)82 OP_THRMO In OP thermo detect signal input83 - - Not used84 BATT_SW In DC pulg installation detect85 MONI_RVS In LCD reverse switch input86 VRefH - ADC power supply (REG3V)
Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3)
2-43
•••• SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3)
Pin No. Label In/Out Description87 AVDD - Power supply88 DSC_PCTL Out Power control (To DSC_IF: IC8001)89 SRV_RST Out Reset signal (To DECK_CPU: IC1401)90 OEM_REG5_CTL Out Not used91 MENU_SET_SW In Menu set switch input92 RTC_CS Out Chip select signal (To RTC: IC1004)93 JLIP_L Out PC connection terminal switch (L: JLIP terminal, H: PC terminal)94 CLWE Out Write enable95 CHWE Out Write enable96 CRE In Read enable97 CALE Out Address latch enable98 VDD - Power supply99 VSS - GND
100 SEL_SW In Snap shot mode switch101 TRIG_SW In Trigger switch102 DIAL_MANUAL In Dial MANUAL103 DIAL_AUTO In Dial AUTO104 DIAL_OFF In Dial OFF105 DIAL_PLAY In Dial PLAY106 EJECT_SW In EJECT switch detect107 CAS_SW In Cassette switch detect108 MONITOR_SW In Monitor OPEN/CLOSE switch detect109 - - Not used110 MENU_P_B In Menu dial pulse111 LCD_CS1 Out Chip select signal (To LCD EEPROM: IC7603)112 RESERVE - L: fixed113 ASPECT1 Out S2 terminal output114 F/Z_RST Out Reset signal (To F/Z DRIVER: IC4851)115 RWSEL Out Read and write select (To CAMERA_DSP: IC4301)116 ASPECT2 Out S2 terminal output117 KRST/CLR Out Shutter sound reset/clear signal (To CAMERA_DSP: IC4301)118 EDIT_CTL Out JLIP remote pause output terminal (Edit terminal)119 VDD(VPP) - Power supply120 IRIS_O/C Out Iris OPEN/CLOSE121 CDS_CS Out Chip select signal (To CDS/AGC/AD: IC5601)122 TG_RST Out Reset signal (To TG/V.DRV: IC5501)123 S_MUTE Out Shutter sound mute124 CCD_KIZU Out Blanking ON/OFF control (at white noise adjustment)125 ODD_EVEN In Odd/Even field discrimination signal at slow playback 126 ND_H Out Noise decreasing circuit control (L: OFF, H: ON)127 PD_L Out Power down signal output (L: power down)128 A_MUTE Out Audio mute
Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3)
2-44
2.7 DECK CPU2.7.1 Contents of DECK CPU processing
1) Mechanism control• Loading motor control• Drum motor control• Capstan motor control
2) Deck LSI control• DV DSP IC control• PRE / REC IC control
3) OSD control• On screen process
4) 1394 control5) Sensor control
• Tape sensor• Reel sensor• DEW sensor• Emergency process
2.7.2 DECK system composition
S Y S C O NC P U
M D A
M E C H A
D E C KD S PD V _ E Q
O NS C R E E N PC I /F
U A R T
D V _ A N A
PRE / REC
1394P H Y
D VTermina l
D E C KC P U
1 6 MD R A M
16-bi tParal le l bus
Synchronous Ser ia lCommun ica t ion
Synchronous Ser ia lCommun ica t ion
16-bi tMul t ip lex bus
Fig. 2-7-1 DECK CPU system structure
2-45
2.7.3 Tracking Error information
( 0 )( 9 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 0 ) ( 1 )
Flame Pulse
Track Pulse(Track reference
Number)
HID(HEAD SW)
Tape pattern(Pilot signal)
( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 )
H E A D
FFh
80h
00h
Tracking Error
Tracking is thecenter
Tracking is off (1) Tracking is off (2)
(CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2)
Fig. 2-7-2 Tracking Error explanation (NTSC)
Fig. 2-7-2 shows the tracking error detection method. The DVC multirecords three kinds of pilot signals off0 (0), f1 (465 kHz) and f2 (697.5 kHz) on each track. When the CH1 head traces the track on which the f0pilot signal is recorded in playback, the crosstalk component of the pilot signals of f1 and f2 recorded onthe preceding and following tracks are detected and compared. When the tracking is well controlled, theerror rate is 80h that is the intermediate value between 00h and FFh. When the tracking deviates in the f1track side, the error rate is lower than 80h. When the tracking deviates in the f2 track side, the error rate ishigher than 80h. When the CH2 head is tracing the track, the error rate is 00h or FFh because only the f1or f2 component is detected.Such the tracking error information is digitally processed by the ATF inside the DV-EQ IC and theprocessed data is transmitted to the DECK CPU through the 16-bit bus. The DECK CPU controls thecapstan servo according to the data transmitted from the DV-EQ IC.
2-46
2.7.4 1394 interface controlThe DECK CPU has the function of the host microcomputer of the 1394 interface. It mainly controls theLINK IC, PHY IC and 1394 bus besides AV/C command processing. The AV/C command is classified intothe VCR control commands such as for PLAY, STOP, FF, REW, REC operations and for status informationsuch as time code, mode status, etc.For details of the 1394 interface (i.LINK), refer to the Technical Guide to the i.LINK.
D E C KC P U
D E C K _ D S P
1394PHY
D VTerminal
1394LINK
IC1401
IC3001
IC3101
Fig. 2-7-3 1394 interface block
2.7.5 JLIP Video CaptureThe DECK CPU incorporates the asynchronous serial communication (UART) port for communication withexternal equipment (personal computer, etc.). The UART port is used for image data transmission forinputting DVC playback picture that is captured by use of the JLIP Video Capture into a personal computer.When a DVC playback picture is captured, playback data for 1 frame is once held by the DRAM and thentransmitted to the DECK CPU through the 16-bit bus and it is finally output from the UART port to apersonal computer. The image data transmitted to a personal computer is formatted in the DV stream, andthe personal computer encodes the DV data with the software.
D E C KC P U
D E C K _ D S PPC IFP C
Terminal16M
D R A M
IC1401IC3001
IC3002
16-bitParal lel bus
U A R T
Fig. 2-7-4 JLIP Video Capture output
2-47
2.7.6 DECK CPU block diagram
IC1401 DECK CPU
IC3001
D E C K _ D S P
D V _ E Q
IC3201
IC1601
M D A
IC3301
D V _ A N AANA_CLK 109ANA_OUT 93
ANA_CS 14
MDA_CS 195
M E C H AS E N S O R
135 REC_SAFE
148 CAM0132 CAM1136 CAM2
230 S_REEL
189 T_REEL
134 REEL_LED
187 TAPE_LED
199 S_SENS182 E_SENS
DRUM_FG 238DRUM_PG 196
DRUM_REF 191
CAP_FG 173CAP_REF 221
CAP_BRAKE 1
P R E / R E C
IC3501
72 OSCI
D E WS E N S O R
200 DEW_SENS
A_REG_3V
16
DV_CS 104
ADM0-15
EQ_CS 85
WE0 12RE 24
OK 37
RWSEL 5AS 47
DV_RST 99
EQ_RST 120EQ_TRST 83
IC3101
1394P H Y
PHY_PD 3PHY_RST 61
PHY_CNA 15 D V
HID 207
FRP 190TSR 218TSR 231SPA 174
HID_IN 219
42
PD0-3PC0-1
ANA_IN 108
MDA_IN 94MDA_CLK 91
DRUM_FG 201DRUM_FG 229
LD_ON 27
T GV . D R V
IC5501
S Y S C O NC P U
IC1001
89 SYS_CLK74 SYS_OUT78 SYS_IN
180 MSELECT
237 SRV_RDY55 RESET
100 ODD_EVEN16 VMUTE_IN
C A M E R AD S P
IC4301
188 VD
O NS C R E E N
28 OSD_CS75 OSD_CLK58 OSD_DATA
IC1002
PBH 117REC_I 116HID_3 119
V_PB_L 84 REG_4.8V
184 BCID1181 BCID2183 BCID3
42 MIC_SDA57 MIC_SCL
29 MIC_CTL
A_REG_3V
16M
-DR
AM
SYSCONC A S _ S WEJT_SW
R O T A R YE N C O D E R
PC_IF
DSC_ IF
JLIP
P C 59 RXD
77 TXD
16
10
JUN
CT
ION
DV_INT 226DV_INT 204
ANA_PD 45 V C O A U D
R E G 65 D_GAIN
Fig. 2-7-5 DECK CPU block diagram
2-48
2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)
Pin No. Label In/Out Description
1 CAP_BRK Out Capstan motor brake control27 LD_ON Out Loading motor ON/OFF control14 ANA_CS Out Chip select signal (To DV_ANA: IC3301)28 OSD_CS Out Chip select signal (To OSD: IC1002)2 VSS - GND
29 MIC_CTL Out Power supply control to MIC3 PHY_PD Out Power down control (To PHY: IC3101)
61 PHY_RST Out Reset output (To PHY: IC3101)15 PHY_CNA In IEEE1394 connection detect (Connect: L)45 ANA_PD Out Power down control (To DV_ANA: IC3301)16 VMUTE_IN In Video mute input46 -4 -
30 VDDH - Power supply (REG_3V)31 -62 -5 RWSEL Out Read/write select signal of Bus
47 AS Out Address strobe signal of Bus17 -63 -49 -32 VSS - GND18 -79 -6 -
48 -64 -7 -
65 D_GAIN Out Drum error gain control19 VDDB - Power supply (REG_3V)33 ADM1520 ADM1482 ADM1350 ADM1266 ADM118 ADM10
67 ADM951 ADM834 VSS - GND9 ADM7
35 ADM621 ADM552 ADM410 ADM336 ADM222 ADM123 ADM0
In/Out
In/Out
Not used-
Not used-
Not used-
Not used-
Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)
Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)
2-49
•••• Deck CPU (IC1401: MN103004KRH) pin functions (2/5)
Pin No. Label In/Out Description
11 VDDB - Power supply (REG_3V)37 DK(L) In Servo CPU ready signal (Low: Deck mode)24 RE(L) Out Read enable signal38 WE1(L) - Test terminal (TL1401)12 WE0(L) Out Write enable signal40 PVDD - Power supply (REG_3V)53 PVSS - GND56 MMOD1 -54 MMOD0 -55 RESET(L) In Reset input (From SYSCON CPU: IC1001)70 FRQS - L: fixed71 VSS - GND69 EXMOD1 - H: fixed68 EXMOD0 - H: fixed72 OSCI In 27MHz clock input (Form TG/V.DRV: IC5501)88 OSCO - Test terminal (TL1423)86 VDDH - Power supply (REG_3V)87 SYSCLK - Test terminal (TL1433)85 EQ_CS Out Chip select signal (To DV_EQ: IC3201)
104 DV_CS Out Chip select signal (To DECK_DSP: IC3001)102 CS1(L) - Test terminal (TL1402)103 CS0(L) - Test terminal (TL1403)101 VDD - Power supply (REG_3V)100 ODD_EVEN Out Odd/Even field discrimination signal at slow playback (FRAME ADVANCE)84 V_PB_L Out Video track area recording off signal99 DV_RST Out Reset signal output (To DECK_DSP: IC3001)83 EQ_TRST Out Reset signal output (To DV_EQ: IC3201) (For Boundary scan)
120 EQ_RST Out Reset signal output (To DV_EQ: IC3201)118 VSS - GND119 HID_3 Out Head switch pulse (control of recording current measure circuit)116 REC_I Out ON/OFF control for recording circuit (To PRE/REC IC)117 PBH Out ON/OFF control for playback circuit (To PRE/REC IC)134 REEL_LED Out Reel sensor LED control135 REC_SAFE In REC safety switch133 VDDH - Power supply (REG_3V)136 CAM2132 CAM1148 CAM0149 AVSS - GND152 -150 -151 -147 -
In
- Not used
Control port for FLASH CPU
Mechanism position detect from rotary encoder
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (2/5)
2-50
•••• Deck CPU (IC1401: MN103004KRH) pin functions (3/5)
Pin No. Label In/Out Description
164 -166 -167 -163 -168 -165 -183 BCID3181 BCID2184 BCID1200 DEW_SENS In Dew sensor detect182 E_SENS In End sensor detect199 S_SENS In Start sensor detect198 VREFH - Reference voltage216 AVDD - Power supply (REG_3V)214 ADTRG(L) In H: fixed239 NMI(L) In H: fixed213 VSS - GND240 -197 -227 -212 -226 DV_INT In DV_DSP interrupt signal196 DRUM_PG In Drum PG238 DRUM_FG In Drum FG180 MSELECT In DECK_CPU chip select input (Form SYSCON CPU: IC1001)225 VDD Power supply (REG_3V)195 MDA_CS Out Chip select signal to MDA IC1601237 SRV_RDY Out DECK_CPU ready signal output (To SYSCON CPU: IC1001)179 AGC_RST Out Video output clamp control (To A/V OUT SECTION)211 -210 -236 -194 -224 -209 VSS - GND235 -178 -223 -193 -208 -
- Not used
Not used-
-
In
- Not used
Cassette tape ID board information
Not used
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (3/5)
2-51
•••• Deck CPU (IC1401: MN103004KRH) pin functions (4/5)
Pin No. Label In/Out Description
162 -222 -177 -234 -192 VDDH - Power supply (REG_3V)207 HID Out Head switch pulse output176 - - Not used233 - - Not used191 DRUM_REF Out Drum offset voltage output (To MDA: IC1601)221 CAP_REF Out Capstan offset voltage output (To MDA: IC1601)175 -232 -159 -220 -206 VSS - GND231 STR In HID reference (Drum 150Hz reference)190 FRP In Frame pulse (From DECK_DSP: IC3001)204 DV_INT In DV_DSP interrupt signal174 SPA In Pulse for ATF sample219 HID_IN In Head switch pulse input205 VDD - Power supply (REG_3V)230 S_REEL In SUP reel pulse189 T_REEL In TU reel pulse218 STR In HID reference (Drum 150Hz reference)173 CAP_FG In Capstan FG229 DRUM_FG In Drum FG203 - - Not used201 DRUM_FG In Drum FG187 TAPE_LED Out Tape sensor LED control185 VSS - GND188 VD In Vertical reference pulse (Form CAMERA_DSP: IC4301)186 -171 -169 -172 -170 VDD - Power supply (REG_3V)158 -154 -156 -153 -157 -155 VSS - GND
- Not used
Not used-
- Not used
Not used-
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (4/5)
2-52
•••• Deck CPU (IC1401: MN103004KRH) pin functions (5/5)
Pin No. Label In/Out Description
140 -138 -142 -139 -141 -137 -124 VDDH - Power supply (REG_3V)122 -123 -121 -125 -106 VPP - Power supply (REG_3V)107 BR(L) - H: fixed105 VSS - GND109 ANA_CLK Out Serial clock (To DV_ANA: IC3301)108 ANA_IN Out Serial data bus output (To DV_ANA: IC3301)93 ANA_OUT In Serial data bus input (From DV_ANA: IC3301)91 MDA_CLK Out Serial clock (To MDA: IC1601)94 MDA_IN Out Serial bus data output (To MDA: IC1601)90 VDD Power supply (REG_3V)92 MDA_OUT In Serial bus data input (From MDA: IC1601)89 SYS_CLK In Serial clock (From SYSCON CPU: IC1001)78 SYS_IN Out Serial bus data output (To SYSCON CPU: IC1001)74 SYS_OUT In Serial bus data input (From SYSCON CPU: IC1001)76 - - Not used73 VSS - GND77 TXD Out RS232C output59 RXD In RS232C input75 OSD_CLK Out Serial clock (To OSD: IC1002)58 OSD_DATA Out Serial bus data (To OSD: IC1002)60 - - Not used57 MIC_SCL Out Serial clock for MIC43 VDDH Power supply (REG_3V)42 MIC_SDA In Serial data for MIC44 -41 -
- Not used
- Not used
Not used-
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (5/5)
SECTION 3HEAD CLOG WARNING
3-1
3.1 HEAD CLOG WARNING OF DVCThe method and criterion of DVC head clog detection have been changed from this DVC series.Differently from the previous models which detect head clog in the recording mode only, the new systemincorporated in this series detects head clog in both the recording and playback modes based on the newdetection criterion that is much more strict with possible error as compared with the previous system.When the head clog warning is occurred on the DVC with the previous detection system, it is impossible toplay back the data correctly rather than the recording data is deteriorated. On the other hand, the DVCwith the new detection system warns the user about deterioration in recording signal because of headclog.
3.1.1 Structure of Sync Blocks and Error correctionThe structure of sync blocks and error correction of the DVC will be explained first. In the digital magneticrecording and playback system, there is a possibility that random error and burst error caused by signaldropout in tape occur. Generally, the data transmission systems which quality is not so good adopt thepacket data transmission system for the necessity of frequent reproducing (playback) synchronization.Therefore, the DVC records data in the form of sync blocks.One sync block of the AUDIO/VIDEO sector consists of 2 bytes of sync area, 3 bytes of ID code to identifythe attribute of data, and 85 bytes of inner codes. A definite sync pattern is recorded in each sync area. Ifthe definite sync pattern is not detected in playback, the data in the sync block cannot be restored andplayed back. An ID code consists of 3 bytes, namely, 2 bytes of ID and 1 byte of ID parity. The content ofthe ID of the AUDIO/VIDEO sector is 4 bits of a sequence number showing the continuity of frames, 4 bitsof track pair number showing the track number, and 8 bits of sync block number showing the row of syncblocks.Since the 8-bytes inner parity is added to the AUDIO/VIDEO sector, maximum four errors can be correctedby this 8-bytes parity and considerable random errors can be corrected also.Moreover, the 11-bytes outer parity is added to the VIDEO data and 5-bytes outer parity is added to theAUDIO data. Therefore, burst error caused by signal dropout in tape can be corrected by those parities.As mentioned above, the optimum error correction strategy with the inner and outer parities is constructedfor intermingled random errors and burst errors in consideration of the dropout characteristic of the tapemedium to be used.Number of sync blocks in the AUDIO sector is 17 (14 in the data area besides 2 pre-sync blocks and 1post-sync block). Number of sync blocks in the VIDEO sector is 152 (149 in the data area besides 2 pre-sync blocks and 1 post-sync block).
Syn
c A
rea
IDCode
A U D I OA U X
(AAUX)A U D I O D A T A
InnerPari ty
Outer Par i ty
Sync blocknumber 0 1 2 3 4 5 9 81 89
012345
9
678
10111213141516
Byte-posit ion number
Pre-syncblock (2)
Data-syncblock (14)
Post-syncblock (1)
Sync Block length : 90 Byte
5 72 8
Fig. 3-1-1 Structure of sync blocks in audio sector
3-2
Syn
c A
rea
IDCode
VIDEO AUX (VAUX)
VIDEO DATAInnerParity
Outer Parity
Sync b lockn u m b e r 0 1 2 3 4 5 9 81 89
181920
Byte-pos i t ion number
Pre-syncblock (2)
Data-syncb lock(149)
Post -syncblock (1)
Sync Block length : 90 Byte
77 8
17
21
156157
167168
VIDEO AUX (VAUX)
Fig. 3-1-2 Structure of sync blocks in video sector
The length of sync blocks of the sub code is just 12 bytes. The sub code has the fast search function tosearch the target point at a high speed. In the fast search mode, if the tape speed is increased, the anglethat the head scans the track is decreased and the form of signals that can be read by one scanningbecomes like beads on an abacus. If data of signals read by one scanning are not grouped as a syncblock, those data cannot be decoded and played back. Therefore, the length of a sync block is shortenedto secure the reproducibility of data. Since the probability to pick up the outer parity is very low in the fastsearch mode, no outer parity is prepared in the sub code differently from the AUDIO/VIDEO sector. Inorder to secure the reproducibility and reliability of playback data, the same data is not only written twice indifferent parts of a track but also written in a half of a frame (in 5 or 6 tracks). In other words, the samedata is written over and over 10 times or 12 times in the tracks of the first half of a frame. The next data ismultiply written in the second half of the frame in the same manner, namely, written 10 times or 12 timesrepeatedly.
Syn
c A
rea
IDCode
Sub-codeD A T A
Inne
r P
arity
Sync blocknumber 0 1 2 3 4 5
0123
7
456
89
1011
Byte-posit ion number
Data-syncblock
Sync Block length : 12 Byte
6 7 8 9 10 11
Fig. 3-1-3 Structure of sync blocks in subcode sector
3-3
3.1.2 Error Rate of DVCThe error rate of the DVC is shown by the average number of error corrections by the inner parity in theAUDIO/VIDEO sector (A/V inner errors) per 1 second (300 tracks). Error correction is carried out by theECC inside the DV-DSP IC, and the ECC outputs Error Flag SBE (Sync Block Error). The SBE isclassified into 7 levels from 0T pulse to 12T pulse according to number of error connections, and it isoutput for each of 14 sync blocks of the AUDIO sector and 149 sync blocks of the VIDEO sector. Forevaluating the error rate actually, all SBE pulses that were output in 1 second are weighted by a certainmethod and the total of the weighted SBE's is used as the DVC error rate.
0T: Sync fai luer
2T: Error free
4T: 1-error correct ion
6T: 2-error correct ion
8T: 3-error correct ion
10T: 4-error correct ion
12T: Correct ion-disabled
1T=18MHz 1c lock
Weight ingfor SBE
0
0
1
2
3
4
5
Fig. 3-1-4 Particulars of SBE
The error rate jig in its infancy shows the total of weighted data of input SBE's by a frequency counter.However, the error rate of the recent DVC models (GR-DVM5 and after) is output by the TCCS and can beshown on the display of a personal computer by use of the Service Support Software (SSS).
Graph showed a change inthe Error Rate visual lyWhite l ine: CH1Pink l ine: CH2Green l ine: 500 reference
Percentage of sync blockcount ing in Audio/Videosector
Numerical value of ErrorRate
Fig. 3-1-5 Error Rate window in SSS
3-4
3.1.3 Previous method of head clog detectionThe previous head clog detection system (for the models of GR-DVL9800 and before) is based on thecount of sync blocks as the criterion. The count of sync blocks that a head plays back per frame is:
NTSC: ( Audio 17 + Video 152 ) × 5 Track = 845PAL: ( Audio 17 + Video 152 ) × 6 Track = 1014
Strictly explaining, number of sync blocks of the ITI sector and sub code sector must be added to theabove count. However, these additional counts cannot be detected by the system of the third generationmodels (GR-DVX7 and after).If some sync block is not detected, the data in the sync block is treated as an error that is impossible tocorrect. If the status that the count of sync blocks in the AUDIO/VIDEO sector per 1 frame is lower than240 of the threshold level continues in the short-playback mode just after start of recording for a certainperiod (more than 0.5 second), the system judges that the head is clogged. In other words, the systemrecognizes the head clog when the quantity of playback data is one-fourth as little as the normal.Therefore, if the system detects head clog in recording, it recognizes the recording part as impossible forplayback (regards as no-signal recording).The short-playback mode just after restart (resuming) of recording is the status that the tape is rewoundfor 1.5 second (back-space) according to the absolute track number that is memorized as recording issuspended (by pause operation). When recording is resumed (restarted), the tape is transported in theplay mode first and then recording is actually resumed with the point of the memorized track number. Thisperiod is called the short-playback period (mode). Head clog detection is not started at the first start ofrecording but done at every resuming of recording for the second time, third time, and so on.
R E C
REC start
REC stop
R E C
Short PB1.5 sec
Back Space
Track No. Finding
Fig. 3-1-6 Short Play Back
3-5
3.1.4 New method of head clog detectionThe new head clog detection system (for this DVC series and after) performs detection in the normal(usual) playback mode besides the short-playback mode just after resuming of recording as well as theprevious system. The criterion of the new detection system is not the count of sync blocks but number ofA/V inner errors per frame.
1) Detection in normal playbackOnly when sync data recorded on both channels or one channel is read in the normal playback mode(after detection of non-signal part), the new system judges that the head is clogged and warns theuser about it if number of A/V inner errors per frame continuously exceeds the threshold level for 7seconds (for 210 frames: 30 x 7).If errors less than the threshold level are continuously detected for 2 seconds after that, the systemjudges the head as not clogged and cancels the warning indication. If the playback is suspended ordiscontinued in the head clog status, the warning indication remains as it was until the systemdetects no clog, or Eject or Power Off operation is performed.
2) Detection in short playbackIn the period of short-playback just after recording is resumed, the servo controls the track positionaccording to the self-recording just before recording is suspended and the detection system judgesthe head clog and warns the user about it if the status that number of A/V inner errors per frameexceeds the threshold level continues for 6 frames (for about 0.2 second) after the capstan phasewas locked.If recording is suspended (by pause operation) as the head is clogged, the warning indicationremains until the system detects no clog in the short-playback mode or Eject or Power Off operationis performed.
3) Setting of threshold levelThe error threshold level is set by the EEPROM as follows.
5 low-order bits in 8 bits: Threshold level in normal playback (0 ~ 31)3 high-order bits in 8 bits: Coefficient in short-playback (0 ~ 7)
The actual threshold level in the normal playback is 10 times as high as the standard setting value,and that in the short-playback is several times as high as the actual threshold level in the normalplayback because of the short detection time. If this detection level is converted into number of A/Vinner errors per second (the error rate), it approximates to 10,000. In other words, the system judgesthat the head is clogged when number of A/V inner errors per second exceeds 10,000. If thethreshold level of the previous sync block count system is converted into the error rate, itapproximates to 1,000,000. As compared with the sync block count system, the detection capacity ofthe new detection system is improved by 20 dB or so.
3-6
Previous method(GR-DVL9800 and before)
Detection periodDuring Short PBat recording start
Judgment elementThe number of Sink block counts
par 1 frame
Normal PB Short PB
∗Over 1507 sec
∗Over 6000.2 sec
Error rate conversion Rough estimate: 1,000,000
Threshold level andContinuation period
Below 2400.5 sec
Rough estimate: 10,000
New method(GR-DVL300 series)
During Normal PB and Short PBat recording start
The value of A/V inner error par 1 frame
∗∗∗∗Note:The threshold level of new method is decoded by data in EEPROM.EEPROM Address: 3AEh → Data: 8Fh “10001111”Lower 5 bits: Setting of threshold level in normal PB “01111” → 15Value of threshold level in normal PB: 15 × 10 = 150Upper 3 bits: Coefficient of short PB “100” → 4Value of threshold level in short PB: 150 × 4 = 600Above addresses and threshold levels are for GR-DVL300 series, and those may vary in the model.
Table 3-1-1 Difference of the head clog method
4) History of head clog warningWith detection of head clog, the EEPROM counts the data and the history of head clog warnings canbe checked on the display of a personal computer with the SSS (Service Support Software).Other specifications are as follows.• If sync block data is read from neither of two channels for 10 continuous frames, the system
recognizes that no signal is recorded in the part and does not perform clog detection. (The cleaningtape is recognized as a non-recorded tape.)
• Head clog detection in the short-playback mode is not performed at the first start of recording.• Head clog detection is not performed in any mode other than the normal playback mode such as
the FF/REW, Special Playback, Audio-dubbing/Insert modes.• Method to display marks and messages conforms to the specifications of respective models.
SECTION 4DOCTOR SYSTEM
4-1
4.1 WHAT IS DOCTOR PROGRAM?The function and performance of a product (an electric/electronic appliance in this case) generallydepends on the program of the internal microcomputer. If there is some fault in the electrical function andperformance of a product, the program of its microcomputer should be changed (upgraded) at theexpenses of the manufacturer. To prepare for an unexpected trouble, recently manufactured articles storea part of the program data in the EEPROM coupled with the microcomputer so that the program of themicrocomputer can be easily revised. Such the program data written in the EEPROM coupled with themicrocomputer is called the "Doctor Program".If the microcomputer of an article has no need of support of the Doctor Program, no program data iswritten in the EEPROM. Even in such the case, the EEPROM of recent products prepares specificaddresses (several bytes to dozens of bytes) as the area to write the Doctor Program. The area(addresses) differs from model to model. Since the Doctor Program must vary depending on the programof the microcomputer and expected troubles, its matching with the microcomputer (program) is veryimportant.
4.1.1 Matching of Doctor Program with Microcomputer ProgramThe program of the microcomputer can be revised by rewriting the Doctor Program stored in the EEPROMcoupled with the microcomputer. However, if the program of the microcomputer is changed by upgradingor so, the Doctor Program conforming to the previous program stored in the EEPROM is useless. If themicrocomputer that is consistent with the Doctor Program stored in the EEPROM is replaced with a newmicrocomputer of an upgraded one, continuous use of the Doctor Program to cope with a trouble maydevelop an unexpected situation. An example of progress of revisions (upgrading) of the microcomputerprogram and EEPROM Doctor Program is shown below.
Microcomputer A
No DoctorProgram
Microcomputer B
DoctorProgram A
DoctorProgram B
No DoctorProgram
DoctorProgram B
Fig. 4-1-1 Example of progress of revisions
If there is such the change in production of a series of products, matching of the microcomputer andDoctor Program with each other is as follows.
Microcomputer A + No Doctor Program, Doctor Program A, or Doctor Program B = OK,Microcomputer B + No Doctor Program or Doctor Program C = OK,Microcomputer A + Doctor Program C = NG,Microcomputer B + Doctor Program A or Doctor Program B = NG.
If the Doctor Program mismatches the microcomputer program, the product falls into troubles showingvarious symptoms when the Doctor Program is rewritten and it is difficult to specify the cause of thetrouble, for example, the product fails in power supply or shows the picture abnormally depending on thesituation. Such being the case, pay careful attention to matching of the Doctor Program with themicrocomputer program (version).
4-2
4.1.2 Use of Doctor Program for CamcorderDoctor Programs have been widely used for stationary video decks, however, the function of the DoctorProgram is an obstacle to repair of the product, namely, it occasionally brings about secondary troubles ifthe program data stored in the EEPROM mismatches the microcomputer program as mentionedpreviously. Under the circumstances that most of stationary video decks are not backed up by servicesupport system software and there is no means to read and write data stored in the EEPROM's of them,the only way to cope with mismatching between the microcomputer program and Doctor Program is toreplace the EEPROM with a new one conforming to the microcomputer program or to kill the DoctorProgram electrically (to remove the resistor or to add a resistor). Although it is easy to replace theEEPROM, the manufacturer is burdened with severe inventory management of spare parts because it isrequired to have a large stock of differently written EEPROM's to supply them properly to variousmicrocomputer programs.No Doctor Program had been adopted for camcorders until quite recently, however, late camcordermodels such as the GR-DVL9500 series and after adopt the Doctor Program. Fortunately such thecamcorders don't need to replace the EEPROM's with those which proper data are written in, becausedata stored in the EEPROM can be rewritten by means of the service support system software. In such thecase servicemen are required to pay careful attention to matching between the microcomputer programand the EEPROM data including the Doctor Program.
4.1.3 Revision of Service Support System Software for Doctor ProgramTo rewrite camcorder's Doctor Program in the field and to avoid trouble caused by mismatching betweenthe microcomputer program and Doctor Program, the Service Support System Software is reexaminedand revised as follows.
Doctor Load
Fig. 4-1-2 EEPROM Utility window
4-3
1. Specification of Doctor Program areaIf there is a Doctor Program area in the EEPROM data, the area is specified by coloring (gray) the cell onthe EEPROM utility map.
2. Deletion of Data Editing Function in Doctor Program AreaTo avoid trouble caused by data editing in the Doctor Program area, data editing is disabled for thecolored cell (Doctor Program area).
3. Addition of Data Rewriting Function in Doctor Program Area OnlyIf there is a need of rewriting of the Doctor Program in the field, the manufacturer announces it through theMCI or Service Bulletin and supplies an EEPROM initial data file including revised Doctor Program data tothe dealers, service stations and others concerned. For rewriting the Doctor Program data, it is required touse the "Doctor Load" (refer to "Procedure to Rewrite Doctor Program" to be mentioned later) that is thespecial function to renew the Doctor Program area only without disturbing other data such as adjustmentdata, fixed data and so on. In other words, this special function secures the productivity of the camcorder.
4. Deletion of Doctor Program from Initial Data FileEvery service support system software is supplied together with the initial data file. The initial data file tobe used for servicing the model that is designed to be doctored by the Doctor Program from the first stageof the production should contain the Doctor Program. However, the initial data file for service use issupplied without the Doctor Program in order to avoid possible trouble caused by mismatching of theDoctor Program with the microcomputer program as mentioned previously, because the initial data file isprepared based on the initial data at the beginning of the production. Such being the case, the servicesupport system software may not demonstrate full of the original function in doctoring the product with theDoctor Program, however, this demerit is ignored from a viewpoint that doctoring with the Doctor Programis a simple and easy measures against trouble. In the case the microcomputer is replaced with new oneand it is programmed by the backup data, pay heed the Doctor Program whether it matches themicrocomputer program or not, because the aforementioned way of thinking does not apply to backupdata.
4.1.4 Procedure to Rewrite Doctor ProgramThe special function "Doctor Load" is newly added to the service support system software. The "DoctorLoad" function facilitates renewal of data in the Doctor Program area only and deletion of the DoctorProgram.
1. Data Renewal in Doctor Program Area OnlyIn case of necessity of field service to revise the Doctor Program, the manufacturer supplies a data filenecessary for the service. The revision data file is the same format as the initial data file supplied with theservice support system software. If the initial data is rewritten in the EEPROM in the usual manner whenrevising the Doctor Program, it brings about such a trouble as other data, for example adjustment data anddata to be fixed, are also rewritten at the same time. To avoid such a trouble, the new function "DoctorLoad" can be used.
1. Read out the EEPROM data.2. Open the supplied data file (including Doctor Program data) using the "Doctor Load" functionAfter the data file is loaded, data only in the Doctor Program area is read in the map on the EEPROM
utility (data stored in the EEPROM of the camcorder is not yet rewritten at this stage).3. Confirm that the Doctor data is read in the map.4. Write the data in the EEPROM in the usual way.
It is possible that the data only in the Doctor Program is rewritten with this process.
4-4
2. Data Deletion from Doctor Program Area OnlyIf the microcomputer is replaced, it occasionally needs to delete the Doctor Program stored in theEEPROM. Although the service support system software has no data deletion function like the emergencyutility, the Doctor Program can be deleted by the "Doctor Load" function.
1. Read out the EEPROM data.2. Open the initial data file supplied with the service support system software by the "Doctor Load"
function.Since nothing of the Doctor Program is written in the initial data file as mentioned previously, all datain the Doctor Program area are reset to "FEh" respectively as the initial data file is loaded, in otherwords, all data are apparently deleted from the Doctor Program area (data stored in the EEPROM ofthe camcorder is not yet rewritten at this stage).
3. Confirm that the Doctor data are reset to "FEh" in the map.4. Write the data in the EEPROM in the usual way.
It is possible that the data only in the Doctor Program is deleted with this process.
4-5
4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCESThough it explained about the outline of the Doctor Program and the doctor complying with of the servicesupport system software in the preceding clause, it explains here about the present circumstances of theDoctor Program system.
4.2.1 ON/OFF address and Program addressThe Doctor Program system is stored in the EEPROM. The system is divided into two blocks; one is theON/OFF address block and the other is the program address block. Each address varies in the model.Moreover, those blocks may be away.In case of this model, the ON/OFF addresses are (1ACh ~ 1AFh), and program addresses are (2A4h ~2F4h, 77h, DAh ~ DFh). For other models, refer to the “table 4-2-3. Address list of Doctor Program” of thepostscript.
The contents of the ON/OFF address and the program address are as mentioned in the following.For the ON/OFF addresses, write as follows.
To answer to the Doctor system: 1ACh = “12h” / 1ADh = “34h” / 1AEh = “56h” / 1AFh = “78h”Not to answer to the Doctor system: 1ACh to 1AFh = “00h”
For the program addresses, write as follows.To answer to the Doctor system: Programmed dataNot to answer to the Doctor system: "FEh" or any data
It can be considered that there are four kinds of combinations in theory, and those combinations determineON or OFF of the Doctor Program system. As shown in the Table 4-2-1, the combination that turns theDoctor Program system on is the pattern (1) only. The pattern (2) turns the Doctor Program system offbecause "FEh" is written for all the program addresses, in which "FEh" is a cancelable data even when theON/OFF address is in the ON status. The pattern (3) is invalid even when an optional data is written in,because the ON/OFF address is in the OFF status. In practice there are two patterns of (1) and (4).In case of the pattern (1), if “33h” is written for the address 1ADh for example, the Doctor Program systemturns off. When all aforementioned data are written in four addresses properly, and Doctor Programsystem becomes on for the first time.
Programmed Data"Feh"
or any data
1ACh = 12h
1ADh = 34h
1AEh = 56h
1AFh = 78h
(ON)
1ACh = 00h
1ADh = 00h
1AEh = 00h
1AFh = 00h
(OFF)
Program Address
ON/OFF Address
ON…(1) OFF…(2)
OFF…(3) OFF…(4)
Table 4-2-1 Combinations of ON/OFF Address and Program Address
4-6
As mentioning above, it is unacceptable by using the service support system software to edit the doctorarea directly at the time of the repair. However, when writing of the initial data or the backup data is done,the doctor area is also rewritten at the same time. Also, it is possible to turn off or renew the DoctorProgram by using the "Doctor Load" function. Table 4-2-2 shows the combinations that may be probablyprogrammed in practice now.
ON/OFFAddress
ProgramAddress
ON/OFFAddress
ProgramAddress
ON Correct ON Correct Yes → Yes ∗1
ON Incorrect ON Correct No → Yes ∗2
OFF “ FEh ” Change ON Correct Yes → Yes ∗3
ON Correct OFF “ FEh ” Yes → Yes ∗4
ON Incorrect OFF “ FEh ” No → Yes ∗5
OFF “ FEh ” OFF “ FEh ” Yes → Yes ∗6
Writing DataYes: Normal No: Locked
Original Data
Table 4-2-2 Changing situations of Doctor Program
The following explains each pattern from ∗1 to ∗6.∗1: For the camcorder that Doctor Program System has been turned on, but it is replaced with another
Doctor Program System for improvement of the performance.∗2: For the camcorder that has been locked because the data of the Doctor Program was broken for
some reason, the same Doctor Program is written again to release the set from the locked status.∗3: For the camcorder that Doctor Program System has been turned off, the Doctor Program is written
for improving the performance.∗4: For the camcorder that Doctor Program System has been turned on, the microcomputer is replaced
with an upgraded one.∗5: It is required to release the set temporarily from the same locked status as the case ∗2.∗6: For usual EEPROM data writing, which does not affect the Doctor Program System.
Under the locked condition such as ∗2 or ∗5, if the camera system fails in communication such as itcompletely dead, the camera system cannot be recovered by rewriting the data of the EEPROM. In suchthe case, it needs to replace the EEPROM with a new one and to write original data in it or to adjust allitems after writing the initial data in the new EEPROM. However, the communication may be recovered byturning on in the deck mode after disconnecting the DC power supply once and connecting it again if thedeck system does not affected by the trouble. If the communication is recovered by the above means, turnoff the Doctor Program System using the “Doctor Load” function.Unless there occurs a trouble, don't use the “Doctor Load” function. Usual editing of the EEPROM andrewriting the initial data don't bring on any trouble.
4-7
4.2.2 Writing function of EEPROM dataThe writing function of the previous service support system software (before complying with the doctorsystem) was the method which data are written in one after another as the turn of the address. If theON/OFF address is younger than the Program address, the data renewal process becomes the following.A problem occurs when it tries to write the data that the Doctor Program system is on in this method.
Rewriting of ON/OFF address data first↓
Rewriting of program address data next
The Doctor system becomes on the moment "78h" is written at the end of the ON/OFF address. There isactually no problem at this moment if all program addresses are "FEh" that means cancellation. But afterthat, the Doctor Program area begins to be written. The camera system becomes locked condition themoment data were written in the first address. The Doctor Program handles the whole of the programaddresses as a lump. The locked condition happens because the program is destroyed by different data'sthere being written.
So, the present service support system that is complying with the doctor system is programmed by thefollowing process to prevent the camera from such the trouble as mentioned above. This process does notbring on such the trouble, because the Doctor Program System is turned on at the last stage of theprocess.
Memorizing the ON/OFF address data from the EEPROM↓
Writing "00h" in all the ON/OFF addresses↓
Rewriting the data of the program addresses↓
Writing the memorized data in the ON/OFF addresses
4.2.3 Upgrade of the service support systemAt present, though the initial data attached to the service support system should turn off all the DoctorPrograms in consideration of the safety, that is not necessarily the best way. To make the initial data withthe Doctor Program, it is indispensable that the congeniality decision with the microcomputer’s version onthe camera can be done easily.So, the function which congeniality is judged automatically now is being developed. The microcomputer’sversion is read at the time of writing, then it is checked whether the Doctor Program corresponds to themicrocomputer or not. For the purpose of this, the microcomputer’s version information corresponded withthe Doctor Program is included into the initial data file.Also, it is possible to make the backup data containing the microcomputer’s version information. This isconvenient when data are returned after replacement of the circuit board.If this is realized, the trouble that relates to Doctor Program will be dissolved. As for Upgrade, it will be ableto be released soon.
4-8
4.2.4 Address list of the doctor program area
Address Data
3ACh 12h
3ADh 34h
3AEh 56h
3AFh 78h
1C4h 12h
1C5h 34h
1C6h 56h
1C7h 78h
1C4h 12h
1C5h 34h
1C6h 56h
1C7h 78h
6F0h 12h
6F1h 34h
6F2h 56h
6F3h 78h
1ACh 12h
1ADh 34h
1AEh 56h
1AFh 78h
Doctor ProgramAddress
Models
GR-DVL7GR-DVL9500UGR-DVL9500EG/DVL9500EKGR-DVL9600EG/DVL9600EKGR-DVL9600EA/DVL9600A
3B0h to 3CFh
Doctor ON/OFF
GR-DVX7/DVM50U/DVM70UGR-DVX4EG/DVX7EG/DVX4EK/DVX7EKGR-DVX40A/DVX70A/DVX40SH/DVX70SHGR-DVX4EA/DVX7EAVMD8
1A0h to 1C3h
GR-DVA1/DVF1/DVF11U/DVF21U/DVF31UGR-DVL40EG/DVL40EK/DVL30EG/DVL30EKGR-DVL20EG/DVL20EKGR-DVL25A/DVL20EA/DVL28ED/DVL33SHGR-DVL45A/DVL40EA/DVL48ED/DVL38SHVMD2/VMD3
290h to 2F4h
GR-DVL700GR-DVL9800UGR-DVL9800EG/DVL9800EKGR-DVL9700EG/DVL9700EKVMD10/VMD20
600h to 61Bh
GR-DVA10/DVF10 seriesGR-DVL300U/DVL300UM seriesGR-DVL300KR/DVL805KR seriesGR-DVL300EG/DVL300EK seriesGR-DVL300A/DVL300A-S seriesGR-DVL300EA/DVL300ED seriesCC9370
77hDAh to DFh
2A4h to 2D6h
Table 4-2-3 Address list of the doctor program area
VICTOR COMPANY OF JAPAN, LIMITED
Printed in Japan2000-09 (TM1)