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A 12b-control ultra-low-power low-noise SC-VGA for medical ultrasound probes

Peng Wang1, Thomas M. Halvorsrd2, Trond Ytterdal1

1Department of Electronics and Telecommunication, Norwegian University of Science and Technology, Trondheim, Norway2

GE Vingmed Ultrasound AS, Horten, NorwayE-mail: pengw@iet.ntnu.no

Published inThe Journal of Engineering; Received on 22nd August 2013; Accepted on 29th September 2013

Abstract:This Letter presents a 12b-control ultra-low-power low-noise two-stage single-ended to differential switched-capacitor variable gain

amplier (SC-VGA) for 26-MHz second harmonic cardiac imaging ultrasound probes in 0.18m complementary metal oxide semiconductor.

The proposed SC-VGA consists of inverters and capacitor (CAP) arrays. By adopting inverters instead of operational trans-conductance ampli-

ers (OTAs) in traditional SC-ampliers, both the power and noise are signicantly improved. Each stage has a 6b binary-weighted CAP array,

and in total the 12b CAP arrays achieve the dB-in-linear gain range from 21 to 21 dB. The CAP array is divided between the upper 3b andlower 3b by a CAP to decrease the capacitance spread. The total power consumption is 150 A at 1 V supply voltage, and the input referred

noise is 6.5 nV/HZ at 4 MHz. The second harmonic distortion (HD2) has the mean value 77 dB at the 460 mV peak-to-peak output swingfor 50 samples of Monte Carlo mismatch simulation with a 30 MHz sampling frequency.

1 Introduction

Since ultrasound arose past century ultrasound imaging for medical

and non-destructive applications has made remarkable progress. In

the past few years, digital imaging system further enhances the

image quality. Although the digital signal processing could

improve the imaging capability, the analogue front-end is indis-

pensable for the receive chain and limits the performance of ultra-

sound probes. The new generations of three-dimensional (3D)/4D

medical ultrasound probes contain thousands of receive channels

in a probe. To achieve the high sensitivity while under regulatory

limits, the power consumption and noise are the top challenges

for analogue front-end design. A high dynamic range is required

in the receive chain because of the reected echo strengths which

are from different depths with 1 dB/MHz/cm attenuation, hence a

large gain-range VGA as the rst stage of front-end becomes one

of the most important parts in an ultrasound probe. This work

aims at the VGA design for 26-MHz second harmonic cardiac

ultrasound probes. Hence, HD2 becomes another important require-

ment for the VGA. Continuous-time (CT) VGAs were used in early

generations of CT ultrasound systems to avoid glitches in the image

[1]. In recent years, SC techniques become attractive in beam-

formers [2], which demand a discrete-time VGA to make a good

interface.

Most VGAs adopt a resistive feedback loop to tune the gain or

adjust the input trans-conductance either by source degeneration

feedback or current steering. These techniques have severaldrawbacks including the low gain accuracy, high power and

poor noise for the latter since their effective input trans-

conductance varies [1]. VGAs in electrocardiogram systems

exploit tuneable integration time to achieve the dB-in-linear

characteristics [3], but require a relatively long period for a

large tuning range. Switched-capacitor variable gain ampliers

(SC-VGAs) achieve a tightly controlled gain by a capacitor

(CAP) ratio and good noise performance for discrete-time circuits

[4], but the trans-conductance ampliers (OTAs) in traditional

SC-VGAs are very power-hungry [5]. This Letter proposes an

ultra-low-power low-noise SC-VGA based on inverters and

CAP arrays, which has a power consumption 150A at 1 V

power supply, 6.5 nV/Hz

input referred noise at the 4 MHz

centre frequency and 77 dB HD2 at a 30 MHz sampling fre-quency. The area is 245m 134m which enables the integra-

tion of thousands of VGAs into a single probe.

2 Proposed SC-VGA

Fig.1illustrates the proposed SC-VGA architecture based on inver-

ters and CAP arrays. The SC-VGA has two stages. First stage

adopts a larger sampling CAP than the second stage to limitkT/C

noise, while providing a gain range from 9.5 to 9.5 dB. Thesecond stage converts the single-ended input to pseudo-differential

outputs with a gain range from 12 to 12 dB. Compared with theOTA-based SC-VGA, common mode feedback is not required for

the proposed inverter-based SC-VGA. Each stage has a 6b binary-

weighted gain control, and in total the two-stage SC-VGA has a 12b

gain control from 21 to 21 dB. There are three different clockphases. Clocks 1 and 2 are two non-overlapped clocks, and2 is an advanced version of2 to accommodate bottom plate

sampling. For the rst stage, during 1 the inverter is reset, and

the input signal is sampled onto CS1, during2(2) the sampled

signal is transferred from CS1 to Cf1. The gain of rst stage is

decided by the CAP ratio CS1/Cf1 [6]. For the second stage,

during 2(2) the input signal is sampled onto CS2 between

nodes A and B (Fig.1), anotherCS2 is connected to Vcm. During1, two CS2 CAPs are in the inverter feedback loop, while the

bottom plates are connected together to cancel the DC offset and

leftoating performing the single-ended to differential conversion

on the VGA outputs and the gain expression is CS2/Cf2 [7]. The

gain of the proposed SC-VGA is decided by the CAP ratio

CSx/Cfx

x=1, 2, the sampling CAP and the feedback CAP are

formed by the binary-weighted CAP array as shown in Fig. 2a[8].

Fig. 1 Proposed SC-VGA

J Eng 2013

doi: 10.1049/joe.2013.0088

This is an open access article published by the IET under the Creative Commons

Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/

licenses/by-nc-nd/3.0/)

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The sampling CAPCa + Cand the feedback CAPCa Care setto the input and the feedback, respectively. To reduce the capaci-

tance spread for a binary-weighted 6b array (1:64), the array is

divided between the upper 3b and lower 3b arrays. Therefore the

required resolution is achieved without overly huge CAPs, and

the smaller spread in CAP values makes it easier to attain a better

monotonicity in gain control. According to the approximate algo-

rithm e2x

1+

x/1

x

which shows a good match for 0.7

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[4] Fujimoto Y., Akada H., Ogawa H., Iizuka K., Miyamoto M.: Aswitched-capacitor variable gain amplier for CCD image sensor inter-face system. IEEE European Solid-State Circuit Conf., 2002

[5] Fan M., Ren J., Guo Y., ET AL.: Low-voltage low-power operationalamplier for SC circuits,Electron. Lett., 2009,45, (25), pp. 12741276

[6] Chae Y., Han G.: Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator, IEEE J. Solid-State Circuits, 2009,44, (2), pp. 458472

[7] Nagari A., Nicollini G.: A 2.7 V 350 uW 11-b algorithmic

analog-to-digital converter with single-ended multiplexed

inputs. Proc. Design, Automation and Test in Europe Conf.

Exhibition, 2004

[8] Nakamura K., Decker S., Kelly D., ET AL.: A CMOS analog front-end

chip-set for mega pixel camcorders. IEEE Int. Solid-State Circuit

Conf., 2000

J Eng 2013

doi: 10.1049/joe.2013.0088

This is an open access article published by the IET under the Creative Commons

Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/

licenses/by-nc-nd/3.0/)

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