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A 1.8V Single-Inductor Dual-Output Switching Converter for Power Reduction Techniques

Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui and Philip K.T. Mok

Integrated Power Electronics Laboratory Department of Electrical and Electronic Engineering

The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong SAR, China

Tel: (852) 2358-8535 Fax: (852) 2358-1485 Email: eemds@ee.ust.hk

Abstract

A 1.8V integrated single-inductor dual-output boost converter is presented. This converter adopts a time- multiplexing control in providing two independent supply voltages using only one lpH off-chip inductor. The topology could easily be extended to give multiple outputs. The converter is fabricated with a standard 0.5pm CMOS n-well process. At an oscillator frequency of 1 MHz, the conversion efficiency reaches 88% at a total output power of 350mW.

multiplexing (TM) control, a single controller is shared by all the outputs. Synchronous rectification, in the sense that the transistor in replacing the diode is switched off when the inductor current tends to go negative, is employed, thus eliminating diode drops and enhancing efficiency. All power switches are fabricated on-chip and with only one inductor for two outputs, off-chip components are minimized. Other features include modified current sensing technique and ringing suppression technique, to be discussed in due course.

II. SIMO Converter Architecture and Control Strategy I. Introduction

For a digital signal processor, high speed computation requires a high supply voltage v d d for fast switching. Since power consumption is proportional to the square of V,, it is advisable to lower v d d when the computation speed could be reduced. Supply voltage scheduling using multiple or variable supply voltage schemes [I-51 are thus desirable in optimizing the power and speed of switching systems. A critical issue in implementing such a power management system is to generate multiple power supply voltages efficiently. Conventional solutions may use several independent converters or employ a transformer with multiple secondary windings to deliver energy into the various outputs [6,7]. The first method is not preferred because it requires too many components (controllers and power devices). The second method may suffer serious problems arise from cross regulation.

A multiple-output converter with multiple inductors is reported in [5] recently. Because existing monolithic magnetic technology cannot fabricate inductors of suitable values and quality for efficient power transmission, inductors remain as off-chip components. As the number of outputs increases, the number of inductors increases accordingly, which is not preferable for portable applications. Furthermore, the topology in [5] limits to step-down conversion and only voltages lower than the power supply could be generated. If no high supply voltage is available, the system may not fulfill optimization tasks [3], because part of the system may have high speed requirements. Moreover, to work at low voltages, sophisticated analog circuits are needed, which are not easy to design. Hence, a boost converter is more favorable to power high-speed processor cores with a very low supply voltage.

In this work, we introduce a single-inductor multiple-output (SJMO) boost converter topology. By employing time

Fig. 1 shows the power stage of the proposed single- inductor dual-output (SIDO) boost converter. The two outputs Vo, and Vob share the inductor L and the switch SI. Fig. 2 shows the timing of the converter. It works with two complementary phases $a and 4. During Qa = 1, Sb is opened and no current flows into Vob, while SI is closed first. The inductor current IL increases until DlaT expires (determined by the output of an error amplifier), where T is the switching

L r"""ipo p

Fig. 1 Power stage of the SIDO converter

. . . . . . . . . : :wit : : : : :

: H n . . . S. ;-n= . . .

. . . . . . . . . . . . . . . . . .

Fig. 2 Timing diagram of the SIDO converter

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period of the converter. During D2,T, SI is opened and Sa is closed to divert the inductor current into the output Voa. A zero current detector senses the inductor current, and when it goes zero, the converter enters D3,T, and Sa is opened again. The inductor current stays zero until &, = 1. Here, DIa, DZa and D3a satisfy the requirements that

During &, = 1, the controller multiplexes the inductor current into the output Vob in similar fashion as discussed above, and the two outputs are regulated by the controller alternately.

The presence of D3,T and D3bT puts the converter into DCM (discontinuous conduction mode), essentially isolating the control of the two outputs such that load variation in one output does not affect the other. Therefore, the problem of cross regulation is alleviated. Another advantage of DCM control is simple compensation of the system because there is only one LHP pole in the transfer function of the loop gain of each of the output [8].

With similar time multiplexing control, the converter can easily be extended to have N outputs as shown in Fig. 3, if N non-overlapping phases are assigned to the corresponding outputs accordingly.

A switching converter with a similar topology was reported in [9] while the proposed converter was being fabricated. However, synchronous rectification is not employed, and power diodes are added in series with SI and Sz to prevent the inductor

fVK S . F N T l 1

P T T T * * * * Fig. 3 Topology of SIMO converter with N outputs

current from going negative. Besides almost doubling the number of power devices, addition of the diodes lowers the efficiency significantly and deems unacceptable for low voltage applications. Moreover, according to the timing diagrams in [9], the converter works at the boundary of CCM (continuous conduction mode) and DCM. To maintain this condition, a load change at one output would increase or decrease the switching period, thus affecting the other output. Hence, serious cross regulation sets in and the design of the controller becomes very complicated, and no such working controller has been reported so far.

Table 1 summarizes and compares the features of the representative designs on N-output converters:

TABLE 1: Comparison of multiple-output converters

N converters Ref. [5] Ref. [9] Thi work inductors N N 1 1 power devices 2N 2N 2N+1 N+1 control loops N 1 1 *

*No control loop is discussed in [9].

111. Controller and Functional Blocks

A. Controller

Fig. 4 shows the block diagram of the single-inductor dual- output boost converter. The two output voltages are scaled and fed to their respective error amplifiers.

During $a = 1 , the switch SI is closed and the output voltage of the error amplifier EA, is sampled by the PWM generator to determine the duty ratio DIa for the output VOa. During = 1, the switch S2 is on and switch SI is off. In similar fashion, the duty ratio Dlb for Vob is determined. Note that many of the functional blocks in the control loop are time-shared that reduces the complexity of the controller.

B. Synchronous Rectification

For a switching converter, one of the switches is usually replaced by a diode, to save control circuitry and to block

Cumnt Sensor A

Scaler

PWM Generator - V*

Over Current Delector

Scaler

Current Sensor B

Fig. 4 Block Diagram of SIMO Converter

2001 Symposium on VLSl Circuits Digest of Technical Papers 138

reverse current automatically. Now, imagine the switches Sa and Sb of Fig.1 are replaced by diodes with the anodes connected to the inductor. Without using switches, the inductor current cannot differentiate between V,, and V,b and will charge up both outputs at the same time and gives v,, = Vob in the steady state. This is the reason why a transistor is added in series with each of the diode in [9]. In order to achieve a high efficiency, synchronous rectification is adopted in this work.

For implementation, free wheeling diodes are replaced by transistors M,, and Mpb with low on-resistance. Two current sensors A and B sense the currents flowing into the outputs V,, and V,, respectively. Consider the case for $, = 1. Because the converter works in DCM, the inductor current tends to go negative at the end of D,T. The bi-directional switch M, cannot block reverse current as a diode does, and when current sensor A detects a zero inductor current, the power transistor Mp is then turned off to prevent the current from flowing back to the source. Similar action applies to switch Mpb.

The present design uses PMOS power transistors to replace the diodes. For a boost converter, the two output voltages are both larger than the supply voltage. The substrate of the switches and the supply voltage of the dead-time control buffer should be connected to the highest voltage of the system so that the switches can be fully turned on and off.

C. Over Current Detector

The over current detector is used to sense the inductor current and help to prevent a large current from damaging power devices. Existing techniques include using current transformer or a sensing resistor R,,,, in series with a power device. If the current is large, the large IzRsense loss degrades the efficiency. Fig. 5 introduces a CMOS current sensing circuit using transistor scaling.

The transistors MI and M2 constitute a current mirror in sinking equal currents into two identical NMOS transistor M3 and h4+ If the transistors are well matched, the voltages at the sources of M3 and M4 are equal, forcing the source voltages of MS, Mg and M7 to be equal. M7 and M6 work as two switches controlled by complementary control signals V,,, and V,,,. respectively. The node X is connected to the drain of the NMOS power transistor M, in Fig. 4. Once M, is turned on

T vdd

(with V,,, = 1 at the same time), M7 is also turned on with Vd, 2 0. In this case, Ms and M, have the same DC voltage biasing. Therefore, the current through MS is proportional to that of M, according to the scale ratio a = (W/L)s/(W/L),. M5 is designed to be much smaller than M,, and CL << 1. The power loss by the sensing resistor R,,,,, is scaled down by a times. When M, is shut off (and V,,,. =l), M6 is switched on in draining the current to ground to keep the current mirror active.

D. Ringing Suppression

Since the converter works in DCM, during the time intervals when all power transistors are off, the inductor and the filtering capacitor then form an oscillatory circuit. Very often, large ringing occurs at node X (see Fig. 4), causing large switching noise and electromagnetic interference (EMI). The present design incorporates a ringing suppression circuit that is similar to that discussed in [lo] by shorting the inductor when all power transistors are off. The voltages at node X with and without ringing are shown in Fig. 6.

I . I . ‘0- h I*

iJ34 h .to-

Fig. 6 Voltage at node X without / with ring suppression

IV. Experimental Results

The SIDO boost converter has been fabricated with a standard 0.5pm CMOS n-well process. Fig. 7 shows the chip photo of the converter. Table 2 summarizes the performance of the converter. Fig. 8 shows the inductor current of the converter in the steady state. This current waveform correlates well with the simulated waveform. Fig. 9 shows the voltage at node X of the converter, and demonstrates that

Fig. 5 Schematic of current detector Fig. 7 Chip photo of the converter

2 .

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ringing due to DCM has been effectively suppressed. The two output voltages, 3V and 3.6V, are shown in Fig. 10 with reference to the inductor current. Fig.11 shows the efficiency of the converter w.r.t. to load changes. With an inductor resistance of 125mC2 and capacitor ESRs of 100mC2, the converter could achieve high efficiency over a wide range. The filtering capacitors of the two outputs are 40pF and 33pF respectively.

TABLE 2 Performance of the SIDO converter

supply voltage inductor die area

oscillator frequency output voltages

peak-to-peak output ripple maximum glitch at outputs

1.8V 1 pH

2.4mm2 lMHz

3.0V 3.6V 90mV 40mV 200mV lOOmV

l r l 1.00 w

Fig. 9 Voltage at node X

Fig. 10 The two outputs with reference to the inductor current

Efficiency (%) 100 1 1

70 IJ 0 100 200 300 400 500

Ouput power (mW)

Fig. 11 Efficiency of the SIDO converter

V. Conclusion

A single-inductor dual-output boost converter with novel topology and TM control is presented. Compared to the existing designs, the converter needs one small inductor, one control loop and fewer power devices. This topology would find applications in portable instrument and system-on-chips (SOCs). The multiple-output feature makes it very attractive in realizing power reduction techniques in embedded systems.

References

[I] J-M Chang and M. Pedram, “Energy minimization using multiple supply voltages,” IEEE Trans. VU1 Systems, Vol. 5 , pp. 43-3, Dec. 1997.

[2] K. Us& et al., “Automated low-power technique exploiting multiple supply voltages applied to a media processor,” IEEE J. Solid-state Circuits, Vol. 33, pp. 463472, March 1998.

[3] T. Kuroda et al., “Variable Supply-Voltage Scheme for Low-Power High-speed CMOS Digital Design,” in IEEE J. Solid-state Circuits, Vol. 33, NO. 3, pp. 454-462, March 1998.

[4] V. Gutnik and A. P. Chandrakasan, “An efficient controller for variable supply-voltage low power processing,” IEEE VU1 Symposium on Circuits, pp. 158-159, June 1996.

[5] A. P. Dancy, R. Amirtharajah and A. P. Chandrakasan, “High- efficiency multiple-output dc-dc conversion for low-voltage systems,” IEEE Trans. V U 1 Systems, Vol. 8, pp.252-263, June 2000.

[6] G. Levin, “A new secondary side post regulator (SSPR) PWh4 controller for multiple output power supplies, IEEE Applied Power Electronics Cont, pp.736-742, 1995.

[7] A.F. Rozman, “Multiple output converter having a single transformer winding and independent output regulation,” US Patent 6,058,026, May 2000.

[8] R. D. Middlebrook and S. Cuk, “A general unified approach to modeling dc-to-dc converters in discontinuous conduction mode,” IEEE Power Electronic Specialist Con$, pp. 36-57, 1977.

[9] T. Li, “Single inductor multiple output boost regulator,” US Patent 6,075,295, June 13,2000.

[IO] S-H Jung, N-S Jung, 3-T Hwang and G-H Cho, “An integrated CMOS DC-DC converter for battery-operated systems,” IEEE Power Electronics Specialists Con$, pp.43-47, 1999.

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