jan m. rabaey anantha chandrakasan borivoje · pdf file · 2015-08-11© digital...
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© Digital Integrated Circuits2ndSequential Circuits
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic
November 2002
© Digital Integrated Circuits2ndSequential Circuits
Sequential LogicSequential Logic
2 storage mechanisms• positive feedback• charge-based
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
© Digital Integrated Circuits2ndSequential Circuits
Naming ConventionsNaming Conventions
In our text:a latch is level sensitivea register is edge-triggered
There are many different naming conventions
For instance, many books call edge-triggered elements flip-flopsThis leads to confusion however
© Digital Integrated Circuits2ndSequential Circuits
Latch versus RegisterLatch versus RegisterLatchstores data when clock is low
D
Clk
Q D
Clk
Q
Registerstores data when clock rises
Clk Clk
D D
Q Q
© Digital Integrated Circuits2ndSequential Circuits
LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
© Digital Integrated Circuits2ndSequential Circuits
LatchLatch--Based DesignBased Design
• N latch is transparentwhen φ = 0
• P latch is transparent when φ = 1
NLatch Logic
Logic
PLatch
φ
© Digital Integrated Circuits2ndSequential Circuits
Timing DefinitionsTiming Definitions
t
CLK
t
D
tc 2 q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
© Digital Integrated Circuits2ndSequential Circuits
Characterizing TimingCharacterizing Timing
Clk
D Q
tC 2 Q
Clk
D Q
tC 2 Q
tD 2 Q
Register Latch
© Digital Integrated Circuits2ndSequential Circuits
Maximum Clock FrequencyMaximum Clock Frequency
FF’s
LOGIC
tp,comb
φ
tclk-Q + tp,comb + tsetup = T
Also:tcdreg + tcdlogic > thold
tcd: contamination delay = minimum delay
© Digital Integrated Circuits2ndSequential Circuits
Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2
Vo2 = Vi 1
Vo1 = Vi 2
Vi1
A
C
B
Vo2
Vi1 = Vo2
Vo1 Vi2
Vi2 = Vo1
© Digital Integrated Circuits2ndSequential Circuits
MetaMeta--StabilityStability
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
© Digital Integrated Circuits2ndSequential Circuits
Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
© Digital Integrated Circuits2ndSequential Circuits
MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=
© Digital Integrated Circuits2ndSequential Circuits
MuxMux--Based LatchBased Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
© Digital Integrated Circuits2ndSequential Circuits
MasterMaster--Slave (EdgeSlave (Edge--Triggered) Triggered) RegisterRegister
1
0D
CLK
QM
Master
0
1
CLK
Q
Slave
QM
Q
D
CLK
Two opposite latches trigger on edgeAlso called master-slave latch pair
© Digital Integrated Circuits2ndSequential Circuits
MasterMaster--Slave RegisterSlave Register
QM
Q
D
CLK
T2I2
T1I1
I3 T4I5
T3I4
I6
Multiplexer-based latch pair
© Digital Integrated Circuits2ndSequential Circuits
ClkClk--Q DelayQ Delay
D
Q
CLK
2 0.5
0.5
1.5
2.5
tc 2 q(lh)
0.5 1 1.5 2 2.50time, nsec
Vol
ts
tc 2 q(hl)
© Digital Integrated Circuits2ndSequential Circuits
Setup TimeSetup Time
D
Q
QM
CLK
I2 2 T2
2 0.5
Vol
ts
0.0
0.2 0.4time (nsec)
(a) Tsetup 5 0.21 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
DQ
QM
CLK
I2 2 T2
2 0.5V
olts
0.0
0.2 0.4time (nsec)
(b) Tsetup 5 0.20 nsec
0.6 0.8 10
0.5
1.0
1.5
2.0
2.5
3.0
© Digital Integrated Circuits2ndSequential Circuits
Reduced Clock Load Reduced Clock Load MasterMaster--Slave RegisterSlave Register
D QT1 I 1
CLK
CLK
T2
CLK
CLKI2
I 3
I4
© Digital Integrated Circuits2ndSequential Circuits
Avoiding Clock OverlapAvoiding Clock OverlapCLK
CLK
AB
(a) Schematic diagram
X
D
Q
(b) Overlapping clock pairs
CLK
CLK
CLK
CLK
© Digital Integrated Circuits2ndSequential Circuits
Overpowering the Feedback Loop Overpowering the Feedback Loop ──CrossCross--Coupled PairsCoupled Pairs
Forbidden State
S
S
R
Q
QRS Q
Q00 Q
101 0
010 1011 0R Q
NOR-based set-reset
© Digital Integrated Circuits2ndSequential Circuits
CrossCross--Coupled NANDCoupled NAND
S
QR
Q
M1
M2
M3
M4
Q
M5S
M6CLK
M7 R
M8 CLK
VDD
Q
Cross-coupled NANDsAdded clock
This is not used in datapaths any more,but is a basic building memory cell
© Digital Integrated Circuits2ndSequential Circuits
Sizing IssuesSizing Issues
Output voltage dependenceon transistor width
Transient response
4.03.53.0W/L5 and 6
(a)
2.52.00.0
0.5
1.0
1.5
2.0
Q (V
olts
)
time (ns)
(b)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
1
2
W = 1 mμ
3
Volts
Q S
W = 0.9 mμW = 0.8 mμ
W = 0.7 mμW = 0.6 mμ
W = 0.5 mμ
© Digital Integrated Circuits2ndSequential Circuits
Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic (charge-based)
CLK
CLK
CLK
D
Q
Static
© Digital Integrated Circuits2ndSequential Circuits
Making a Dynamic Latch PseudoMaking a Dynamic Latch Pseudo--StaticStatic
D
CLK
CLK
D
© Digital Integrated Circuits2ndSequential Circuits
More Precise Setup TimeMore Precise Setup Time
tD 2 C
t
t
t
tC 2 Q1.05tC 2 Q
tSu
tH
Clk
D
Q
(b)
(a)
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
TSetup-1
TClk-Q
Time
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
ClockDataTSetup-1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)
© Digital Integrated Circuits2ndSequential Circuits
Timet=0
ClockDataTSetup-1
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)
Clk-Q Delay
TSetup-1
TClk-Q
Time
© Digital Integrated Circuits2ndSequential Circuits
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
0
Clk-Q Delay
THold-1
TClk-Q
Time
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
0
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
DataClockTHold-1
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case
0
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
ClockTHold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case
0
© Digital Integrated Circuits2ndSequential Circuits
Clk-Q Delay
THold-1
TClk-Q
Time
D
CN
Q M
CP
D1 SM
Inv1
Inv2TG1
Timet=0
Clock
THold-1
Data
Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case
0
⇒
© Digital Integrated Circuits2ndSequential Circuits
Other Latches/Registers: COther Latches/Registers: C22MOSMOS
M1
D Q
M3CLK
M4
M2
CLK
VDD
CL1
X
CL2
Master Stage
M5
M7CLK
CLK M8
M6
VDD
Slave Stage
“Keepers” can be added to make circuit pseudo-static
Transistor orderimportant
© Digital Integrated Circuits2ndSequential Circuits
Insensitive to ClockInsensitive to Clock--OverlapOverlap
M1
D Q
M4
M2
0 0
VDD
X
M5
M8
M6
VDD
(a) (0-0) overlap
M3
M1
D Q
M2
1
VDD
X
M71
M5
M6
VDD
(b) (1-1) overlap
© Digital Integrated Circuits2ndSequential Circuits
PipeliningPipeliningRE
GRE
G
REGlog
a
CLK
CLK
CLK
Out
b
REG
REG
REGlog
a
CLK
CLK
CLK
REG
CLK
REG
CLK
Out
b
Reference Pipelined
© Digital Integrated Circuits2ndSequential Circuits
Other Latches/Registers: TSPCOther Latches/Registers: TSPC
CLKIn
VDD
CLK
VDD
In
Out
CLK
VDD
CLK
VDD
Out
Negative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
© Digital Integrated Circuits2ndSequential Circuits
Including Logic in TSPCIncluding Logic in TSPC
CLKIn CLK
VDDVDD
QPUN
PDN
CLK
VDD
Q
CLK
VDD
In1
In1 In2
In2
Example: logic inside the latch AND latch
© Digital Integrated Circuits2ndSequential Circuits
TSPC RegisterTSPC Register
CLK
CLK
D
VDD
M3
M2
M1
CLK
Y
VDD
Q
Q
M9
M8
M7
CLK
X
VDD
M6
M5
M4
© Digital Integrated Circuits2ndSequential Circuits
PulsePulse--Triggered LatchesTriggered LatchesAn Alternative ApproachAn Alternative Approach
Master-Slave Latches
D
Clk
Q D
Clk
Q
Clk
DataD
Clk
Q
Clk
Data
Pulse-Triggered Latch
L1 L2 L
Ways to design an edge-triggered sequential cell:
© Digital Integrated Circuits2ndSequential Circuits
Pulsed LatchesPulsed Latches
CLKGD
VDD
M3
M2
M1
CLKG
VDD
M6
Q
M5
M4
CLK
CLKG
VDD
XMP
MN
(a) register (b) glitch generation
CLK
CLKG
(c) glitch clock
© Digital Integrated Circuits2ndSequential Circuits
Pulsed LatchesPulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
P1
M3
M2D
CLK
M1
P3
M6
Qx
M5
M4
P2
CLKD
© Digital Integrated Circuits2ndSequential Circuits
Hybrid LatchHybrid Latch--FF TimingFF Timing
20.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.20.0 0.4
QD
time (ns)
Volts
0.6 0.8 1.0
CLKDCLK
© Digital Integrated Circuits2ndSequential Circuits
LatchLatch--Based PipelineBased Pipeline
F G
CLK
CLK
In Out
C1 C2
CLK
C3
CLK
CLK
Compute F compute G
© Digital Integrated Circuits2ndSequential Circuits
NonNon--BistableBistable Sequential CircuitsSequential Circuits──Schmitt TriggerSchmitt Trigger
In Out
Vin
Vout VOH
VOL
VM– VM+
•VTC with hysteresis
•Restores signal slopes
© Digital Integrated Circuits2ndSequential Circuits
Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger
Vin
t0
VM−
VM+
t
Vout
t0 + tp t
© Digital Integrated Circuits2ndSequential Circuits
CMOS Schmitt TriggerCMOS Schmitt Trigger
Moves switching thresholdof the first inverter
Vin
M2
M1
VDD
X Vout
M4
M3
© Digital Integrated Circuits2ndSequential Circuits
Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC
2.5
VM2
VM1
Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.m
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
2.5
k = 2k = 3
k = 4
k = 1
Vin (V)
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
© Digital Integrated Circuits2ndSequential Circuits
CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)
VDD
VDD
OutIn
M1
M5
M2
X
M3
M4
M6
© Digital Integrated Circuits2ndSequential Circuits
MultivibratorMultivibrator CircuitsCircuits
Bistable Multivibrator
Monostable Multivibrator
Astable Multivibrator
flip-flop, Schmitt Trigger
one-shot
oscillator
S
R
T
© Digital Integrated Circuits2ndSequential Circuits
TransitionTransition--Triggered Triggered MonostableMonostable
DELAY
td
In
Outtd
© Digital Integrated Circuits2ndSequential Circuits
MonostableMonostable Trigger (RCTrigger (RC--based)based)VDD
InOutA B
C
R
In
B
Out t
VM
t2t1
(a) Trigger circuit.
(b) Waveforms.
© Digital Integrated Circuits2ndSequential Circuits
AstableAstable MultivibratorsMultivibrators (Oscillators)(Oscillators)
0 1 2 N-1
Ring Oscillator
simulated response of 5-stage oscillator
0.0
0.0
0.5
1.0
1.5
2.0
2.5V1 V3 V5
3.0
20.50.5
time (ns)
Vol
ts
1.0 1.5
© Digital Integrated Circuits2ndSequential Circuits
Relaxation OscillatorRelaxation Oscillator
Out2
CR
Out1
Int
I1 I2
T = 2 (log3) RC
© Digital Integrated Circuits2ndSequential Circuits
Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)
In
VDD
M3
M1
M2
M4
M5
VDD
M6
Vcontr Current starved inverter
Iref Iref
Schmitt Triggerrestores signal slopes
0.5 1.5 2.5Vcontr (V)
0.0
2
4
6
t pH
L (n
sec)
propagation delay as a functionof control voltage