J. HolmaCERN TE/ABT, Geneva, Switzerland

Acknowledgement M.J. BarnesCERN

February 6, 2014 CLIC WS, CERN, 2014 1

Present Status of Inductive Adder Development for the CLIC DR Kicker Systems

Overview Background

CLIC Layout with Damping Ring (DR) kickers Specifications for CLIC DR Extraction Kicker System Challenges and Issues

Inductive Adder Design Schematic Contributors to the Droop of the Output Waveform Compensation of Droop and Ripple

Status of the Prototyping Specifications for the First Prototype Inductive Adder HV Measurements on the First Prototype Adder Passive Droop Compensation at 1 kV

1.2 kV Pulse with < ±0.2 % Droop and Ripple

Summary and Future Work

February 6, 2014 2CLIC WS, CERN, 2014

Ideal current for 1 GHz option:

DR: Damping Ring;PDR: Pre-Damping Ring.

PDR & DR Kickers ( ): One injection and extraction system per ring and per beam (8 systems); Damping rings reduce beam emittance; hence kickers must be high stability (low ripple); Low beam coupling impedance and good field homogeneity are required (talk by C. Belver-Aguilar).

CLIC General Layout

February 6, 2014 3CLIC WS, CERN, 2014

ExtractionKicker

InjectionKicker

DampingRing(DR)

Damping ring kickers

Drawing of the CLIC DR extraction kicker

(Courtesy of C. Belver-Aguilar)

Specifications for the CLIC DR Extraction Kicker Systems

February 6, 2014 4CLIC WS, CERN, 2014

Schematic of a kicker system

CLIC DR (1 GHz | 2 GHz)

Pulse voltage (kV) (per Stripline) ±12.5

Stripline pulse current [50 Ω load] (A) ±250

Repetition rate (Hz) 50

Pulse flat-top duration (ns) ~160 | ~900

Flat-top reproducibility ±1x10-4 (±0.01 %)

Flat-top stability [inc. droop], (Inj.)per Kicker SYSTEM (Ext.)

±2x10-3 (±0.2 %)±2x10-4 (±0.02 %)

Field rise time (ns) 1000

Field fall time (ns) 1000

Beam energy (GeV) 2.86

Total kick deflection angle (mrad) 1.5 (0.09 deg)

Aperture (mm) 20

Effective length (m) 1.7

Field inhomogeneity (%) [3.5mm radius] [1mm radius]

±0.1 (Inj.)±0.01(Ext.)

ExtractionKicker

InjectionKicker

DampingRing(DR)

Damping ring kickers

CLIC DR kicker pulse definition

NOTE: For rise/fall times, 100 ns desired! Close to 0 V required between

pulses!

Challenges and Issues

±0.02 % (± 2.5 V) requirement for the flat-top stability of ±12.5 kV, 160 to ~900 ns pulse is an extremely demanding specification!

An order of magnitude better than in any existing kicker systems! Compensation of droop and ripple of the output voltage is required.

Adequate impedance matching to minimize duration of settling time: Impedance (and field homogeneity) of the stripline kicker has been optimized: unfortunately the

impedance cannot be 50 Ω for both power-off (even) and power-on (odd) operation modes! Odd-mode impedance of the striplines is ~41 Ω (see talk by C. Belver-Aguilar), which causes

settling time to be ~100 ns. Therefore the pulse flat-top length is at least ~260 ns (2 GHz option)Suitable high precision measurements of the pulse in the laboratory:

better precision than ±2.5 V in 12.5 kV required!

February 6, 2014 5CLIC WS, CERN, 2014

Schematic of a kicker system

ExtractionKicker

InjectionKicker

DampingRing(DR)

CLIC DR kicker pulse definition

Inductive Adder

February 6, 2014 6

Many primary “layers”, each with solid-state switches

The output voltage is the sum of the voltages of the primary constant voltage layers

+ Control electronics referenced to ground

+ No electronics referenced to high voltage despite the high voltage output of the adder

+ The output voltage can be modulated during the pulse with an analogue modulation layer

+ Modularity: the same design can potentially be used for kickers with different specifications (CLIC PDR & DR kicker modulators)

+ Redundancy and machine safety: if one switch or layer fails, the adder still gives full voltage or a significant portion of the required output pulse

+ Possibility to generate positive or negative output pulses with the same adder: the polarity of the pulse can be changed by grounding the other end of the output of the adder

Schematic of an inductive adder

A prototype inductive adder

CLIC WS, CERN, 2014

Contributors to the Droop of the Output Waveform of an Inductive Adder

The droop of the output pulse of an inductive adder is caused by:

The voltage droop of the storage capacitor (Cs) as it [slightly] supplies charge during the pulse

The resistive losses in the primary switch and in the primary circuit (Rsw)

Only the voltage droop of the capacitors can be compensated by adding more capacitance per layer!The only methods to effectively decrease the droop, caused by a combination of resistive losses and magnetizing inductance of the transformer core, is to apply either passive or active analogue modulation (or both) for the output pulse. These methods are necessary to reach very low droop (<< 1 %).

February 6, 2014 7

Capacitor voltage Vcap and voltage of a layer Vlayer during a pulse. Cs = 24 uF, Rsw = 0.34 Ω and Rload/N = 10 Ω.

CLIC WS, CERN, 2014

Simplified model of a layer of an inductive adder during the pulse

Simplified schematic of a constant voltage layer of an

inductive adder

-305

-300

-295

-290

-285

-280

1.0E-07 2.0E-07 3.0E-07 4.0E-07 5.0E-07 6.0E-07 7.0E-07

Axi

s Ti

tle

Time/s

Vcap

Vlayer

Vcap

Vlayer

SwitchLm

Compensation of Droop and Ripple

February 6, 2014 8CLIC WS, CERN, 2014

In analogue modulation layer, there is no storage capacitor but there is resistor Ra

Resistor Ra is effectively in series with the load Load voltage:

VMax is the sum of the voltages over the layers

except the analogue modulation layer: VLoad ≤ VMax! Resistor Ra is in parallel with magnetizing

inductance Lm

Compensation modes: PASSIVE MODE: During the pulse, current

through Lm increases, which causes current through Ra to decrease. Therefore, voltage over Ra decreases, which causes VLoad to increase. This voltage change is reverse in comparison with voltage droop caused by storage capacictors in other layers.

ACTIVE MODE: A linear RF power transistor provides a shunt path for the current through resistor Ra. Therefore, the voltage over Ra can be controlled by controlling the current through the RF power transistor.

LoadLoad Max

Load a

RV V

R R

No capacitor hereRF PowerTransistor

VMax

LmRa

VMax

VRa

VLoad

CLIC WS, CERN, 2014 9February 6, 2014

Compensation of Droop and Ripple

Simulated droop compensation with passive analogue modulation

Simulated droop and ripple compensation with active analogue modulation

Passive analogue modulation – partial droop compensation Active analogue modulation – partial droop and ripple compensation For the CLIC DR kicker modulator, both PASSIVE and ACTIVE modulation methods

will be applied!

±0.02 %

-1025

-1020

-1015

-1010

-1005

-1000

-995

-990

-985

-980

1.0E-07 2.0E-07 3.0E-07 4.0E-07 5.0E-07 6.0E-07 7.0E-07

Vol

tage

/V

Time/s

Vload - w/o AM

Vload - AM 1

Vload - AM 2

Droop < 0.1 %

Droop ~ 0.5 %

Droop > 1.5 %

CLIC WS, CERN, 2014 10February 6, 2014

The Prototype Inductive Adder The purpose of the prototype inductive adder is:

To verify experimentally design steps for the high precision inductive adder To test both passive and active analogue modulation To approach the required ±0.02 % flat-top stability for the output pulse, as specified

for the CLIC DR extraction kicker modulator

Desing Parameter Prototype Inductive Adder

CLIC DR Extraction

Kicker Modulator

Output Voltage (kV) 3.5 12.5

Output Current [50 Ω load] (A) 70 (250) 250

Voltage per layer 700 700

Number of layers 5 20

Pulse flat-top duration (ns) *350 (900) 160 – 900

Pulse rise time [0.1-99.9 %] (ns) 100 < 1000

Pulse fall time [0.1-99.9 %] (ns) 100 < 1000

Flat-top stability (for 160 ns) ±0.02 % ±0.02 %

The prototype inductive adder with two half-layers inserted* limited by transformer cores, design value 900 ns

CLIC WS, CERN, 2014 11February 6, 2014

Measurements on the Prototype Inductive Adder

The prototype inductive adder with the measurement setup

Oscilloscope

Prototypeinductive adder

Signal generators

DC powersupplies

Trigger inputs

CLIC WS, CERN, 2014 12February 6, 2014

Measurements on the Prototype Inductive Adder

The prototype inductive adder with a current transformer and a load

In initial measurements, only one branch per half-layer PCB was powered! 2 branches per layer.

CLIC WS, CERN, 2014 13February 6, 2014

Measurements: Output up to 1.4 kV – No Modulation

1.0E-07 2.0E-07 3.0E-07 4.0E-07 5.0E-07 6.0E-07 7.0E-07-1,440

-1,430

-1,420

-1,410

-1,400

-1,390

-1,380

-1,370

-1,360

Vload, simulatedVload, measured

Time/s

Vlo

ad/V

Vload 1.4 kV

Flat-top ~300 ns

Setup for the measurement: The prototype adder with 5 layers 1 branch powered per half-layer

PCB, 2 branches per layer Capacitors (24 µF/layer) charged

initially to 302 V 50 Ω, 18 kV load by Diconex No modulation applied.

Output pulse parameters Output voltage: 1.4 kV Droop: ~1.5 % for 300 ns flat-top

(~0.8 % for 160 ns) Ripple: ±0.36 % (maximum) Small backswing (~4 V).

Comparison with simulations Simulated waveform from a PSpice

model, based on the design of the prototype inductive adder

The measured droop is very close to the predicted value (~1.5 %).

Conclusion: The overall electrical design of the

prototype inductive adder is correct.

±0.2 %

160 ns

Measurements: Droop Compensation with 1 kV

February 6, 2014 14CLIC WS, CERN, 2014

Setup for the measurement: The prototype adder with 4 constant voltage

layers and a passive analogue modulation layer 1 branch powered per half-layer PCB, 2

branches per layer Capacitors (24 µF/layer) charged initially to 270

V (w/o modulation) or 285 V (with modulation).Output pulse parameters

Without modulation: Vload = 1.023 kV, ΔUload = 15 V (1.5 %).

With modulation:Vload = 1.002 kV, ΔUload = 10 V (1.0 %).

The passive analogue modulation layer effectively reduced the droop with 1 kV output voltage from 1.5 % (w/o modulation) to 1.0 % (with modulation).

Comparison with the CLIC DR kicker parameters

1.0 % of droop in 350 ns corresponds to 0.46 % (±0.23 %) in 160 ns (flat-top length for CLIC DR extraction kicker)

The droop can be decreased further by optimizing the passive analogue modulation layer, adding more capacitance and switches on the layers, and applying active analogue modulation.

350 ns

Connection of Ra on the passive analogue modulation layer.

10 V

15 V

Flat-top ~350 ns

Measurements: 1.2 kV pulse with < ±0.2 % droop and ripple

February 6, 2014 15CLIC WS, CERN, 2014

Zoom of 160 ns flat-top

Vload 1.2 kV160 ns

Vripple+droop 3.8 V, ±0.16 %

Setup for the measurement: 4 constant voltage layers and a passive analogue modulation layer 1 branch powered per half-layer PCB, 2 branches per layer Capacitors (24 µF/layer) initially charged to 350 V (Ra = 7.9 Ω)

Notes: • Tektronix scope used (DPO 5034) has a nominal vertical resolution of 8 bits (< ±0.4%) – can be

improved with averaging• Picoscope 4227 (100 MHz, 2 Channel, 12-bit USB Oscilloscope) purchased and to be tested in

the near future.

160 ns

Measurements: 2.5 kV Output Pulse

February 6, 2014 16CLIC WS, CERN, 2014

80 ns

260 ns

Vload 2.5 kV

100 ns

Setup for the measurement: The prototype adder with 4 constant voltage layers and a passive analogue modulation layer 1 branch powered per half-layer PCB, 2 branches per layer Capacitors (24 µF/layer) charged initially to 700 V (Ra = 4.0 Ω, droop ±1.5 %)

80 ns

Summary The first 5-layer prototype inductive adder is

currently being tested at CERN The initial high voltage measurements have verified

that the prototype adder performs as expected The final goal is to reach the stability requirement

for the CLIC DR extraction kicker modulator Another 5-layer inductive adder will be assembled

in February 2014. The prototype adders will be used to test both

passive and active analogue modulation methods Two prototype adders allow bipolar output pulses

and measurements of pulses with oppostive polarity with a single current transformer: the sensitivity of the measurements of the pulse flat-top can be improved.

The design of the full-scale 12.5 kV, 250 A, CLIC DR kicker prototype inductive adder will be based on the design of the two 5-layer prototype inductive adders.

February 6, 2014 17CLIC WS, CERN, 2014

Questions & Comments?

February 6, 2014 18CLIC WS, CERN, 2014

References and Bibliography1. Holma J., Barnes M.J.: ”Initial Measurements on a Prototype Inductive Adder for the CLIC

Kicker Systems”, Proc. of PPC’13, San Francisco, CA, USA, June 16-21, 2013.

2. Holma J., Barnes M.J., Ovaska S.J.: ”Modelling of Parasitic Inductances of a High Precision Inductive Adder for CLIC”, Proc. of IPAC’13, Shanghai, China, May 12-17, 2013.

3. Holma J., Barnes M.J.: “Sensitivity Analysis for the CLIC Damping Ring Inductive Adder”, Proc. of Int. Power Modulators and High Voltage Conference, San Diego, CA, USA, Jun. 3-7, 2012.

4. Holma J., Barnes M.J.: “Evaluation of Components for the High Precision Inductive Adder for the CLIC Damping Rings”, Proc. of IPAC 2012, New Orleans, USA, May 20-26, 2012.

5. Holma J., Barnes M.J.: “Pulse Power Modulator Development for the CLIC Damping Ring Kickers”, CLIC-Note-938, CERN, Geneva, Switzerland, April 27, 2012.

6. Holma J., “Present Status of Development of DR Extraction Kicker System”, International Workshop on Future Linear Colliders, Granada, Spain, 26-30 Sept., 2011.

7. Holma J., Barnes M.J.: “Preliminary design of an inductive adder for CLIC damping rings”, Proc. of IPAC 2011, San Sebastián, Spain, 4-9 Sept., 2011.

8. Holma J., Barnes M.J., Ovaska S.: “Preliminary design of the pulse generator for the CLIC damping ring extraction system”, Proc. of 18th IEEE International Pulsed Power Conference, Chicago, Illinois, USA, 19-23 Jun, 2011.

February 6, 2014 19CLIC WS, CERN, 2014

Spare Slides

February 6, 2014 CLIC WS, CERN, 2014 20

Ideas for High Precision Measurements of the Output Pulses

• Se

±0.02 % requirement for the flat-top stability of ±12.5 kV, 160 to ~900 ns pulse for DR extraction kicker is an extremely demanding specification : An order of magnitude better than in any existing systems! Active compensation of droop and ripple will be studied further with the prototype

Adequate impedance matching to minimize duration of settling timeSuitable high precision measurements of the pulse in the laboratory

Droop and ripple measurement: Pulse from an inductive adder and output of a high precision DC source with an opposite polarity are summed to compare pulse with an ”ideal” flat-top

Reproducibility and stability: Pulses from two inductive adders are fed through a single current transformer with opposite sense, which ideally sums to zero field if the pulses are identical

The kicker system will finally be tested in an accelerator facility

February 6, 2014 21CLIC WS, CERN, 2014

Schematic of kicker system with an inductive adder

Measurements on the First Prototype Inductive Adder (cont’d)

Polarity change of the load voltage by grouding other end of the stack The polarity of the pulse capacitors remain the same; the only difference is that the positions of the load

connector and short-circuit are swapped For a stripline kicker, positive and negative pulses are needed simultaneously, therefore two identical

inductive adders will be built.

February 6, 2014 22

VTrigger

VLoad

VSwitch(D-S)VSwitch(D-S)

VLoad

VTrigger

Output = TOP of the stack Negative load voltage

CLIC WS, CERN, 2014

Output = BOTTOM of the stack Positive load voltage

3D-Modelling of the Inductive Adder

The output impedance of the inductive adder has to be very well matched to the kicker magnet and the load, in order to generate the required flat-top pulses with minimum rise and fall times.

New methodology has been developed to estimate the parasitic circuit elements of the inductive adder structure in order to design the adder to have the desired electrical behaviour: FastHenry code has been used to predict the

primary leakage inductance of the inductive adder. The simulations have been verified by measurements of the prototype inductive adder.

These studies are valuable for gaining experience in designing pulse modulators with very high performance and allows to finish the design without several iteration steps.

February 6, 2014 23

A single branch under impedance measurement

The FastHenry model of a single branch

Cc

Lks

Lkpsl

Cross-section of a single branch

CLIC WS, CERN, 2014

Future Work re Inductive Adders Dump kicker modulator for CLIC damping rings

The CLIC DR extraction kicker inductive adder (12.5 kV; 20 layers) would have 8-10 extra layers which can be switched on to abort the beam (17.5 kV pulse)

Pulse generator (~12 kV, 1 kHz) for breakdown tests of CLIC RF cavities

Combiner ring extraction kicker modulator for CLIC Specifications (CR 1): 10 kV [50 Ω], pulse duration up to

450 ns, burst-rate up to 688 kHz for 140 µs (average repetition rate ~5 kHz)

An active (fast) reset circuit may be a solution to keep the transformer core sizes reasonable

February 6, 2014 24

Schematic of DR extraction kicker inductive adder with extra layers for dump kicker

GateDrive

Circuit

Extra Layers for Dump Kicker

DR Extraction Kicker Inductive Adder

SemiconductorSwitch (array)

Trigger

VLoad

Capacitor Bank 700 V+ _

1 : 1Transformer

GateDrive

Circuit

Trigger

Capacitor Bank 700 V+ _

20 Layers

8...10 Layers

CLIC WS, CERN, 2014