IEEE Solid-State Circuits Society Quarterly Newsletter

Volume 10Number 1

January 2005

Solid-State Circuits Society Newsletter 1

ISSCC Enters the Nanoelectronic Integrated-Circuit Era

ISSCC 2005 in San Francisco, Cali-fornia, 6–10 February, the fore-most global forum for new devel-

opments in the integrated-circuitindustry, will feature the theme“Entering the nanoelectronic integrat-ed-circuit era.” With the appearanceof integrated circuits having transistordimensions less than 100 nm, inte-grated circuit technology is movingfrom the microelectronic era into thenanoelectronic era. Three Plenary Ses-sion speakers will launch the three-day conference with their commentsand views on the challenges ahead.

Daeje Chin, Korea’s Minister ofInformation and Communications,will address the registrants on“Nanoelectronics for the ubiquitousinformation society.” Chin holdsthat the economic risk to developprocess technology for manufactur-ing nanodevice parameters willrequire the government to play akey role. Tight collaboration amongsemiconductor manufacturers, sys-tem infrastructure providers, andservice industries will be essential.

Hugo De Man, a senior researchFellow at IMEC and a professor atKatholieke Universiteit Leuven, Bel-gium, will talk about “Ambientintelligence: gigascale dreams andnanoscale realities.” The future willrequire two-orders-of-magnitude-lower power dissipation thantoday’s processors, at one-twentieththe cost. Breakthroughs will have tobe achieved in nanoscale-devicequantum physics, in parameter-variation control at the atomic level,and in low-power software at thetop of the product-developmentchain. De Man will address thephysical realities of devices andinterconnects at the nanoscale level,such as gate and source-drain leak-age, and transistor-parameter vari-ability. “More-than-Moore” improve-ments in transistor density will berequired, such as MEMS structuresand new materials and devices forsensors and wireless sensor net-works.

Sunlin Chou, Senior Vice Presi-dent and General Manager, Tech-nology and Manufacturing Group,Intel, Hillsboro, Oregon, will speak

on “Innovation and integration inthe nanoelectronics era.” With tran-sistors and circuit elements alreadyat nanoscale dimensions, Chouasserts that innovation will acceler-ate through skillful integration ofnew materials, processes, anddevice structures. Hardware andsoftware are already evolving solu-tions via multitasking, parallel pro-cessing, mobility, and wireless con-nectivity. Likewise efficient use ofpower in nanoelectronics will callfor holistic solutions involving sys-tems, circuits, processes, devices,and packaging. Chou concludes thatinnovation and integration of nano-technology will extend Moore’s Lawbeyond the next decade.

During the three central days ofthe conference, 233 technical paperswill be presented in thirty-one ses-sions. Papers covering wireless topicscontinue to lead the technical cover-age of ISSCC at 18%, with analog andwireline topics running right behindat 16% each. The other five topics arelisted in the order of technical cover-age at the conference. What followsare selected highlights of the eightmajor topics of the conference.

Registration for tutorials, forums,and short courses fill up quickly.Please see the offerings online andregister at www.isscc.org/isscc.

Wireless CommunicationsIn Session 5, Atheros and Broadcomwill present the most integratedsolutions to date on CMOS WiFi-on-a-chip. With many architectures to

Continued on page 2

A JSSC Classic Paper:Matching Properties of MOS Transistors . . . . . . . . . . . . . . . . . . . .6

A JSSC Classic Paper:Sigma-Delta Converters . . . . . . . . . .8

SSCS e-News More Often in 2005;Less Paper . . . . . . . . . . . . . . . . . . . . . .9

SSCS Elects Five AdCom Members . . .10

Santa Clara Valley Chapter isOutstanding . . . . . . . . . . . . . . . . . .11

Congratulations New Senior Members .11

Listen to Gordon Moore Talk aboutMoore’s Law . . . . . . . . . . . . . . . . . .12

Call for Fellow Nominations . . . . . . .12

IEEE Virtual Museum Praised byScientificAmerican.com . . . . . . . . . .12

SSCS Tops 50 Chapters . . . . . . . . . . .13

Chapter News . . . . . . . . . . . . . . . . . .14

2003-2004 Membership Report . . . . .16

Kawamoto Chairs Steering Committeeof JDT . . . . . . . . . . . . . . . . . . . . .17

Books of Interest to SSCS . . . . . . . . . .17

SSCS Events Calendar . . . . . . . . . . . .20

IN

SSCS Elects Five AdCom Members page 10

January 2005 • Volume 10 – Number 12

achieve a CMOS WLAN system, Ath-eros utilizes a sliding-IF super-het-erodyne structure, which eliminatesone of the on-chip phase-lockedloops required in traditional super-heterodyne radios. The BroadcomSOC has an antenna as its input anddigital bits (to the host processor) asits output.

Due to the radically different sig-naling technique of WiFi from ultrawide band (UWB), developers facethe challenge that no fully-integrat-ed UWB transceivers exist today.Session 11 contributors will presentconcept circuits. One example ofencouraging performance will bepresented by developers from theCalifornia Institute of Technology,who solved propagation challengesat 24 GHz by applying radar tech-nology or a phased array multiple-antenna system on both the receiv-

er and the transmitter. The beam-forming function of the chip canalso be used for ranging and sens-ing applications, effectively makingit the world’s first radar-on-a-chip.

During Session 17, Berkana Wire-less will showcase, for the first time,the technology of a fully-integratedquad-band GSM transceiver inmature low-cost 0.18-µm CMOS.This design has the best sensitivi-ty/linearity and power dissipationtradeoff on the market today forCMOS transceivers, showing that weare one step closer to low-cost sin-gle-chip cell phones.

New applications for silicon-based IC technologies that are in theprocess of being defined in fre-quency bands well above 10 GHzwill be presented in Session 29.Developers from the University ofToronto, Delft University of Tech-

Continued from page 1

nology, and IBM will describe thefirst SiGe power amplifier to delivermore than 100 mW at 26 GHz, fivetimes higher than prior art. Theamplifier has 20-dB gain and a goodefficiency (more than 12.5%). Toachieve this, metal layers in thetechnology (that are normally usedfor connecting transistors) arestacked to form transformers.

Developers from Broadband willpresent a noise-cancellation tech-nique in active RF-CMOS mixers.MOS transistors have much higherflicker noise than BJT transistors.The novel technique steers away theflicker-noise current at brief intervalswithin the signal waveform. Thisresults in a dramatic improvement(ten times) in noise performance fora direct-conversion mixer, with nopenalty in power consumption, chiparea, gain, or linearity.

Wireline Communications In Session 3, two of the backplanesthat will be presented double the bitrate from existing 3-Gb/s (XAUI) to6-Gb/s backplanes. The increasingclock rates of processing cores thataccompany the continuing advancesin silicon technology drive the needfor higher-speed electrical intercon-nects. In separate papers, IBM andTexas Instruments each will presentbackplanes that employ feed-for-ward equalization and decision-feedback equalization. This combi-nation optimally compensates forbandwidth losses and providesimproved immunity to intersymbolinterference (ISI) and crosstalk.

In Session 8 Seoul National Uni-versity will describe judicious use ofcircuit techniques to enable a 40-Gb/s transmitter out of 0.13-µmCMOS. The single-chip 40-Gb/stransmitter runs an onboard 20-GHzPLL, a 16:1 MUX, and a PRBS gen-erator, achieving power consump-tion of just 2.8 W.

Session 12 will address the opti-cal communications benefits fromlow-power and low-voltage laserdrivers and high-speed and low-power burst mode receivers. Ana-log Devices developers will pre-sent a 10-Gb/s laser driver with

President:Stephen H. LewisUniversity of CaliforniaDavis, CAlewis@ecc.uc.davis.eduFax: +1 530 752 8428

Vice President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, AL

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Charles G. SodiniMassachusetts Institute of TechnologyCambridge, MA

Other Representatives:Representative to Sensors Council

Darin YoungRepresentative from CAS to SSCS

Georges GielenRepresentative to CAS from SSCS

Ian Galton

Newsletter Editor:Lewis TermanIBM T. J. Watson Research Center terman@us.ibm.comFax: +1 914 766 2814

Elected AdCom Members at LargeTerms to 31 Dec. 05:Anantha ChandrakasanJohn CorcoranWanda GassTeresa MengJan Sevenhans

Terms to 31 Dec. 06:Brian AcklandGary BaldwinTom LeeJan RabaeyJan Vander Spiegel

Terms to 31 Dec. 07:Bill BidermanDavid JohnsTerri FiezTakayasu SakuraiMehmet Soyuer

Chairs of Standing Committees:Awards David HodgesChapters Jan Van der SpeigelEducation CK Ken YangMeetings Anantha ChandrakasanMembership Teresa MengNominations Charles G. SodiniPublications Bernhard Boser

For detailed contact information, see the Society Web page: www.sscs.org

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the March 2005 issue of the e-News must be received by 1 February 2005 at the SSCS Executive Office.

Anne O’Neill, Executive Director Tel: +1 732 981 3400IEEE SSCS Fax: +1 732 981 3401445 Hoes Lane Email: a.oneill@ieee.orgPiscataway, NJ 08854

IEEE Solid-State Circuits Society AdCom

Solid-State Circuits Society Newsletter 3

impedance-matched electrical out-put, delivering all of the signalpower to the laser diode andenabling the use of cheaper pack-aging for the laser.

During Session 18, high-speedinterconnects and techniques toovercome the non-idealities of thetransmission channels will beaddressed. Borrowing from wire-less-circuit architectures based onmodulation techniques forenhanced broadband performanceprovides advantages. Developersfrom SST Communications andUCLA will describe a technique thatmodulates the transmitted data sig-nal to create two independent high-speed channels. This circuit, real-ized in 0.18-µm CMOS, achieves anaggregate data rate of up to 3.6-Gb/s per pin, and dissipates 92 mW.

Session 22 will include near-idealmulti-Gb/s clocks that permit high-er data rates over both new andexisting links, and enable greatertransmission distances. IBM andMiromico developers will present amultiple-clock-phase PLL with ded-icated phase detectors that permitsub-ps rms tracking jitter at 10Gb/s. Synopsis will present specialcircuit techniques and address loopdynamics to enable a lower-powersmall-area PLL with 1.3-ps rms jitterat 3.125 GHz.

AnalogA key element in the signal chain,the digital-to-analog converter(DAC), will be the focus of Session 6.A DAC with clock rates up to 22gigasamples per second will be pre-sented by Nortel Networks and Insti-tut fuer Mikroelektronik—that is overtwice as fast as any 6-b design previ-ously published. Another direct syn-thesis of multicarrier signals at high-er IF and an important step towards‘software radio’ will be presented byPhilips and Technical UniversityEindhoven. Using a minimum-com-plexity circuit-design approach andconventional CMOS architecture, theDAC performs 500 MS/s.

Session 9 will feature majordevelopments in the design andrealization of A/D converters.

Developers from Oregon State Uni-versity and Asahi Kasei Microsys-tems used a switched-RC integratortechnique to enable the operationof the ∆!M at 0.6 V. This is accom-plished without any clockboosting,bootstrapping, or switched-opamptechniques. A feed-forward topolo-gy to reduce the dynamic range atthe integrator output node alsoenables the low-voltage operationand 1-mW power consumption.

Session 15 will focus on ADCswith speeds ranging from 1 MS/s to200 MS/s, and resolution rangesfrom 16-b to 8-b, enabled bydynamic voltage management. TheUniversity of Toronto and TexasInstruments will present a 90-nmdigital CMOS pipelined 10-b ADCthat operates from a 1.2-V supply,achieving a peak SNDR of 52.6 dB,12MS/s, while consuming 3.3 mWof power.

Session 27 will focus on filtersand continuous-time ∆! convert-ers. CT noise-shaping can yieldvaluable savings in power, and canalso provide useful attenuation ofinterference before the first sam-pling function. The University ofToronto uses an improved complexnoise shaper to attain a single-sidedbandwidth of 23 MHz. The 72.5-dBdynamic range and 45-dB imagerejection for only 42.5 mW permitsdirect digitization in a low-IF WLANreceiver with minimal additionalanalog functions. Columbia Univer-sity will show that useful self-tuningfilters can be realized at extremelylow voltages without resorting tospecial device thresholds. Employ-ing a new transconductor designwith body bias tuning, the 135-kHzfilter achieves a DR of 57 dB withonly a 0.5-V supply.

Digital In Session 10, all eight papers willdescribe microprocessors containingmultiple processor cores of varioustypes rather than higher frequen-cies. New approaches to dynamicvoltage and frequency scaling toreduce power consumption will bediscussed in this session.

Implementation of a next-genera-

tion Itanium® processor will bedescribed by Hewlett-Packard andIntel. It is comprised of two dual-threaded cores integrated on thesame die with a 26.5-MB cache in90 nm. In addition to performanceimprovements, this design reducessusceptibility to soft errors andimproves power efficiency throughlow-power techniques and activepower management.

The first-generation multicoreSOC CELL processor, to bedescribed by IBM, Sony, and Toshi-ba, combines eight streamingprocessors on a chip providing ahigh-performance platform for mul-timedia and streaming workloads.These processors are designed withfeatures specifically targeted for cer-tain applications, saving power andarea by this narrower applicationfocus. Implemented in a 90-nm SOIprocess, the chip incorporatesextensive power- and thermal-man-agement techniques.

The processor that will bedescribed by Sun Microsystems alsofollows the dual-core approach toimproving performance throughparallelism. This fourth-generationSPARC® processor combines twoenhanced third-generation coreswith expanded caches and an on-chip 2-MB L2 cache. Fabricated in a90-nm technology, it operates at 1.8GHz from a 1.1-V supply.

Another approach, which will bedescribed by IBM (BlueGene/L),uses low-cost, small, power-efficientprocessors in a massively parallelfashion. This complex SOC ASICincludes two processor cores,embedded DRAM, SRAM, and cus-tom logic, achieving a high-power/cost-performance trade-off,suited to its role as a building blockof IBM’s BlueGene/L supercomputer.

For on-chip interconnection theUniversity of Twente and Philipswill propose a differential-signalingscheme as an alternative to classicrepeater-based wiring in Session 20.

Developers from Rambus andStanford University will address thetransfer of data on and off chip atthe high intrinsic speed ofadvanced processors. They will pre-

sent an I/O interface with a totaldata rate of more than 0.5terabits/second (that is, 500 billionbits per second)! Each pin operatesat a data rate of 6.4 Gb/s, consum-ing an energy of only 20 pJ for everytransferred bit. To achieve an accu-rate timing relationship between theI/O pins, the presenters willdescribe the on-chip clock-distribu-tion technique that delivers the ref-erence clock across the width of theI/O interface with a clock-trackingarchitecture that allows the use oflow-cost clock sources. These cir-cuits can maintain high analog per-formance even in an SOI CMOSprocess.

Technology Directions Session 4 will feature hybrid interdis-ciplinary technologies that demon-strate exciting and powerful newintegration directions.

The Max Planck Institute willexplain a true breakthrough, a neu-ron-cell-to-semiconductor connec-tion that enables neuroelectroniccommunication, an exchange that isnoninvasive for the cells and non-corrosive for the chips, using purelycapacitive effects across the inter-face. Information is transmitted inelectronic systems by electrons andin neurons by ions. Being able toachieve information exchangebetween these two different chargecarriers is a significant challenge.Such microscopic interfacing isdemonstrated between a siliconchip and snail neurons, with thediameter of the interface junctionestimated to be between 10 and 100microns.

The University of Michigan willdiscuss a miniaturized microsystemfor an atomic clock with the accuratetiming needed for electronic com-munication systems, such as theGlobal-Positioning System (GPS).With MEMS realization of the atom-ic-clock package with a sealedcesium-vapor cell, and integration ofother components, the fabricateddevice is smaller than a sugar cube,and consumes only 30 mW ofpower. The result is 700 times small-er than the present art.

Developers from IMEC, ASM,IMSE-CNM, Philips, and Bosch willdiscuss a MEMS gyroscope inte-grated on top of a CMOS wafer.The combination performs bothdirectional sensing and informationprocessing. This implies that theMEMS must be made at sufficientlylow temperatures (below 400ºC),so that the underlying CMOS is notdegraded. Integration of sensingand processing makes this theworld’s first single-chip miniature-gyroscope solution having excel-lent performance.

Session 14 will look at low-powerwireless and advanced integration.CSEM, Xemics, and Texas Instru-ments will present an ultra-low-power demonstration of sensor inte-gration using a radio electronicinterface. This type of solution canbe used for distributed sensingapplications because of the ultra-low-power integrated-sensor node.

Developers from Keio Universityand the University of Tokyo willpresent 1-terabit/s wireless commu-nication among chips in a package,especially useful for three-dimen-sional integration schemes. Thetransmit power-control schemeeliminates interference and opti-mizes power dissipation.

Session 21 will look at the 60-GHz frequency band, once theexclusive domain of III-V-com-pound semiconductors, such asGaAs and InP. However, aggressivescaling of CMOS technology is mak-ing possible the fabrication of high-data-rate wireless communicationsfor home, office, or automotive anti-collision warning systems. Re-searchers at National Taiwan Uni-versity offer, for the first time, twoessential building blocks (a VCOand broadband amplifier) for creat-ing a robust 60-GHz radio in con-ventional CMOS technology. TheVCO is operational at a much high-er frequency (to 114 GHz). UCLAwill present a low-noise amplifierand a mixer for frequency transla-tion directly to DC, each for use in a60-GHz receiver.

Among the presentations onadvanced array structures in Session

32 will be organic transistors inte-grated into a flexible scanner anddisplay. Researchers from the Uni-versity of Tokyo will describe a newcircuit concept called ‘double word-line and bit-line structure’ that dra-matically reduces the delay of thecircuit by a factor of five, and thepower by a factor of seven. In orderto realize the new structure, two lay-ers of organic transistors are stackedin three dimensions, for the firsttime, together with organic pho-todetectors, using laser drilling. Theresulting faster circuit has enabled asheet-type scanner made with flexi-ble plastic sheets. This portable,ultra-lightweight and flexible scan-ner is made possible by organic-transistor technology. A prototypeof the sheet-type scanner is less thanone millimeter thick, with an area ofeight square centimeters, with 64 x64 resolution. If four million pixelswere to be implemented in a futuredesign, the time for a single scan isestimated to be less than one minuteusing these 3-D organic circuits.

Signal Processing National Taiwan University willreport in Session 7, the first imple-mentation of a high-definition single-chip H.264 video encoder. This stan-dard has features that will enable thepossible presentation of high-defini-tion digital-video disc (HD-DVD) anddigital-video broadcasting on hand-held terminals (DVB-H), a consider-able improvement on MPEG-2 andMPEG-4. The encoder contains amain controller and five engines forinteger motion estimation (IME), frac-tional motion estimation (FME), intra-prediction (IP), entropy coding (EC),and deblocking (DB). The core sizeof the chip is 31.72 square millime-ters using 0.18-micron CMOS tech-nology. It contains 923-K logic gatesand 35-KB SRAM. Power dissipationis 581 mW for D1 video (YUV420,720x480, 30 fps), and is 785 mW forHDTV 720p video.

Two designs that will be present-ed in Session 24 are among thefastest and lowest-power UWBtransceivers reported to date. Whileone transceiver pursues an aggres-

January 2005 • Volume 10 – Number 14

sive data rate, the other focuses onultra-low power consumption.

The first solution from NationalChiao Tung University implements ahigh-data-rate 480-Mb/s UWB base-band transceiver based on codedmulticarrier techniques. This designconsumes a total power of 575 mW,providing an energy efficiency of 1.2nJ/bit. The second design fromNational Taiwan University imple-ments a 62.5-Mb/s UWB transceiver,which consumes only 6.7 mW, andoccupies an area of under 3 squaremillimeters in 0.18-micron CMOStechnology. This corresponds toan impressive energy efficiency of0.1 nJ/bit!

Two recent innovations in WLANbaseband transceivers that improvethe reliability of wireless channelsand increase the coverage area ofexisting WLANs will be presented inSession 24.

Atheros will describe its multi-antenna solution, which utilizesadvanced signal-processing tech-niques to greatly increase the relia-bility and range of conventionalWLAN channels. Atheros will alsodescribe its advanced packet-man-agement functions, which facilitatevideo transmission. In the enterprisearena, the wide range of data ratesused within the same channelresults in low-rate clients, severelylimiting the performance of high-rate clients, yielding low overall net-work performance.

Engim will describe a widebandWLAN solution that is capable of oper-ating on three adjacent channels con-currently. This wideband multichannelapproach allows low-rate clients to begrouped on a slow channel, whilehigh-rate clients can operate unimped-ed on a fast channel, yielding muchbetter overall network performance.Engim will also discuss its real-timespectral-monitoring facilities that pro-vide advanced network-managementcapabilities to detect interferers androgue clients, allowing for improvedperformance and security.

Imagers, MEMS, and Displays In Session 13, Delft University ofTechnology will present a low-cost

CMOS temperature sensor thatachieves accuracy of ±0.1°C overthe temperature range of –55°C to125°C. This 4.5 mm2 chip offers afivefold improvement over formerart using microwatts of power,which makes it ideal for low-costwireless-sensor networks. The Uni-versities of Michigan and Utah,along with Analog Devices, will pre-sent a CMOS micro-sensor that candetect less than 1 ppb of lead con-centration, fabricated by using a fewthin-film post processing steps.

In Session 19, Sanyo Electric willpresent the smallest pixel yet, 1.56-µm x 1.56-µm pixels with 7-V oper-ation. The smaller pixels in this CCDimager improve the image-resolu-tion-to-cost tradeoff. This design sig-nificantly reduces smear to –75 dBby using a 9-phase vertical-transfertechnique. MIT Lincoln Laboratorieswill demonstrate a one-megapixelimage sensor with processingbehind every pixel by advance-ments in fabrication processing;wafer bonding with small 2-µm x 2-µm x 7.5-µm 3D vias.

In Session 30, Sandia NationalLabs and the University of Michiganwill describe how they haveimproved the monitoring of analoginformation systems that feed ahuge amount of data while only asmall portion of transferred data car-ries relevant information. Throughspike detection that recognizes rele-vant events only, they reduce datafor real-time processing by eliminat-ing 92% of the bottlenecks.

MemoryTwo papers that will be presented inSession 2 exhibit the highest-densityflash memories ever reported: 8 Gbfabricated in advanced 70-nm (Toshi-ba and SanDisk) and 63-nm (Sam-sung) technologies, using a multi-level approach and NAND structure.Write performance is dramaticallyimproved to reach a level compara-ble with single-bit-per-cell memories.

Intel will present the fastest syn-chronous-read frequency and pro-gramming throughput ever reportedwith a 512-Mb flash memory in90-nm technology. It is targeted at

communications and multimediaapplications that demand both fastcode execution and fast nonvolatiledata storage. The memory is capableof a 166-MHz continuous-burstmode for fast code execution. Con-current 166-MHz read operation and1.5-MB/s programming operation isoffered for memory subsystems thatrequire simultaneous read and writeoperations.

In Session 25, Matsushita ElectricIndustrial will present the fastestrandom-cycle embedded DRAM.The 400-MHz 1.5-V dual-port inter-leaved DRAM has been developedwith only two key additions to a0.15-µm CMOS logic process: sense-signal-loss-compensating technolo-gy, based on an intensely-detailednoise-element analysis, and astriped-trench capacitor (STC) cellthat is fabricated by adding onlyone mask.

Samsung will present the firstcommercially-viable 2-Gb DRAM. Bythe creative use of a third level ofmetal (typically not found inDRAMs), and an unconventionalbank arrangement, Samsung memo-ry developers have been able tomodify the chip-aspect ratio to fit theJEDEC industry-standard packaging.

In Session 26, Samsung will intro-duce the world’s largest SRAM at256 Mb. Based on their 0.16-µm2

stacked single-crystal-silicon thin-film-transistor SRAM cell, introducedat the 2004 VLSI Symposium, the256-Mb chip has an area of just 61.1mm2. The novel design approachuses the stacked single-crystal-sili-con thin-film transistor as the localcolumn-select transistor in a hierar-chical bitline architecture, to virtual-ly eliminate the usual area penaltyassociated with this approach. Anarray efficiency of over 70% isachieved, while maintaining thepower and speed benefits of theshort hierarchical bitlines. The chipis ideally suited for mobile applica-tions, opening this low-power mar-ket to the benefits of very-high-den-sity, high-bandwidth static memory.

Hewlett Packard and Intel willpresent a three-times increase in theItanium L3 cache size. The 24-MB

Solid-State Circuits Society Newsletter 5

L3 cache is the largest embeddedmemory ever reported. Thanks toimprovements in array design, anda reduced array of operating volt-age, the L3 cache consumes only4.2 W, with cache latency reducedfrom eight cycles to five. A shiftfrom the traditional synchronous-SRAM design approach to an asyn-

chronous design also eliminatesclocking power in the memoryarrays.

Details Online Forums and Short Courses arescheduled for the first and last daysof the conference. To register, orfor a more detailed view of all the

presentations in the Advance Pro-gram, go to www.isscc.org/isscc.Articles from the ISSCC 2005 Digestwill be available in IEEE Xplore™by summer.

Anne O’NeillSSCS Executive Directora.oneill@ieee.org

January 2005 • Volume 10 – Number 16

BackgroundAround the year 1980 a major pro-ject in Philips Research Laboratoriesaimed at digitizing the televisionsystem. An essential part of thisproject was a video-field store,which had a 2.4-Mbit size. It was aridiculously small memory fromtoday’s perspective. However, in anera when people were strugglingwith expensive 16-kbit DRAMs,realizing a cheap video-field storeof this size was a real breakthrough.

In the design phase of thismemory a significant area reduc-tion could be achieved by rotat-ing one of the sense amp transis-tors by 90º. The potential hazardwas in spending too much onguarding headroom for theunknown amount of mismatchthis rotation would introduce. Soa small test circuit was designedin a 2-µm NMOS enhancement-depletion process to find out theconsequences of this rotation.

In that same period matching ofIC components was already animportant subject: the introductionof the CD audio format requireddigital-to-analog converters withresolutions of 14 to 16 bits. Match-ing was related to analog, and ana-log was equivalent to bipolar tech-

nology, so everybody knew formany years that the lithographicalprecision of the emitter caused themismatch.

The first NMOS measurements(1982–83), however, did not meetthose emitter lithography assump-tions and showed many moreeffects that pointed in other direc-tions. In addition to the lack of adecent model, setting up an accu-rate automated test system was amajor struggle. The third test set-upfinally showed sufficient accuracyand repeatability of the measure-ments to start a large-scale charac-terization. With correct data, theobservation of the relationship withthe inverse square of the area wasnot too difficult. From there thetheoretical search for the underly-ing charge-related mechanismscould start.

Publishing the ResultsWe gained more and more confi-dence in the theoretical basis wewere building up because we hadaccess to the early process genera-tions of a large company. Also, wehad a test set-up that would runthroughout the weekend whenthere were fewer noise sources,which provided results of great sen-

sitivity. The simple model providedthe means to analyze yield, andconsequently many other effectscame to the surface. In 1986 Laksh-mikumar published his measure-ments, which fit well with theresults from the correspondingPhilips technology. (Kadabar R.Lak-shmikumar, Robert A. Hadaway,and Miles A. Copeland published“Characterization and modeling ofmismatch in MOS transistors forprecision analog design” in theDecember 1986 JSSC, another often-cited JSSC classic article.) This wasanother indication that the often-heard statement, “mismatch was aproduction-plant-specific issue,”needed revision.

In some four-to-five years manyhundred thousands of devices onwafers in various process genera-tions were measured. This allowedrefining the model and confirmingthe oxide thickness scaling. Designswith yield problems were analyzedand predictions of redesign mea-surements turned out to be valuable.

The first conference publicationof the matching work was in ESS-CIRC 1988, followed by the submis-sion of the paper to the Journal ofSolid-State Circuits. However, themanuscript almost did not get

A JSSC Classic Paper:Matching Properties of MOS Transistors

Published in the October1989 JSSC, “Matching prop-erties of MOS transistors”

by Marcel J.M. Pelgrom, Aad C.J.Duinmaijer, and Anton P.G. Wel-

bers of Phillips Research Labora-tories, Eindhoven, Netherlands, isa classic article. It has been citedmore than 150 times accordingthe Journal Citation Report, 2003

Science Edition. The conceptswere presented first in the fallmeeting of ESSCIRC one yearbefore they were published in theJSSC.

accepted. Both reviewers were pret-ty critical. The first one said that the“paper might be better off by justpresenting experimental data with-out many equations,” while the sec-ond stated that “the analysis of mis-match in the Fourier transformdomain contributes new insight …its neglect of the underlying physi-cal mechanisms leaves several ques-tions unanswered.” Publication as acorrespondence item was recom-mended. With one reviewer in favorof the theory and the other in favorof the experimental data, the associ-ate editor at the time, Charles Sodi-ni, allowed a full paper. So, do notdespair if you receive a (very) criti-cal review; you still might end uphigh on this list.

Follow-upIt still took some five years beforethe paper started appearing in ref-erence lists. In the mid-1990s tech-nology had reached a point whereit became commercially attractiveto integrate analog functions on aCMOS chip (system-on-chip). Thistrend made the matching problemmore visible to industry. The one-parameter mathematical description(AVT) allowed easy communicationon the matching propertiesbetween designers and technolo-gists; foundries started quoting theAVT matching coefficient in theirprocess descriptions. AVT is the mis-match constant equal to the stan-dard deviation between the thresh-old voltages of a pair of transistors,each sized 1 square micron. Othertransistor dimensions are easilyderived by dividing AVT by thesquare root of their area.

Moreover, designers realized thatthe right balance between (analog)yield and electrical performancewould give them a competitiveedge. The paper predicted thematching behavior in future processgenerations by linking the matchingcoefficient to the gate-oxide thick-ness. This prediction has turned out

to be largely valid, even for today’sprocesses.

The characterization groups, real-izing that this phenomenon was alasting design constraint, now startedmeasuring matching characteristics.So, once started as a designer’s prob-lem, matching became a technolo-gist’s concern. Process people real-ized the value of monitoring the mis-match behavior, as it often served asan early warning indicator for yieldproblems. In advanced processes theconsequences of certain technologi-cal steps on matching performanceare well understood, and thereforematching plays a role in the entiretechnology architecture.

Many researchers from academiaand industry have been studyingmismatch over the last ten years.Valuable papers have been writtenon subthreshold extension of themodel, as well as application of theidea to bipolar mismatch. Manytechnology artifacts influencingmatching were identified and pub-lished in IEDM and ICMTS. Peoplehave tried to refine the model; how-ever, improving the significance ofany statistical prediction is very dif-ficult. On one hand, the modelalready covers all area-relatedmechanisms. On the other hand, itrequires measuring many ten thou-sands of devices to determine thesecond digit of the standard devia-tion with sufficient relevance.

Still there remains some truth inthe second reviewer’s remark; someof the basic physical mechanismshave not yet been thoroughly ana-lyzed. The fundamentals behind themismatch issues in the current factorare still hidden and, perhaps, willreveal new insights.

OutlookAs dimensions shrink, the granulari-ty of the silicon device will play amore and more dominant role. In a0.25-µm process the behavior of theminimum-size device was deter-mined by some 1200 doping atoms,

at the 65-nm node there are only80–100 atoms that play a role. Theinfluence of the uncertainty increas-es to a level such that even standarddigital CMOS circuit designers haveto take mismatch into account.Where in the analog world mis-match can be circumvented bychoosing optimum architectures andelaborate calibration schemes, thereseems to be little room for improve-ment in standard digital cells. Apotential improvement in matchingmay come from new device struc-ture where dual gates control thecurrent flow. However, also in thesestructures some granularity effects,caused by working with devicesmeasuring a limited number latticedistances, will appear.

It seems inevitable that we arenow entering an era where statisticaldesign is the rule not the exception.The 1989 paper was perhaps anoticeable step in that direction. Yetwe will see many more papersexploring the statistical behavior ofthe devices and their interactionwith technology. The ways to pre-dict these effects in simulations arestill in their infancy and, on a systemlevel, only the first steps have beentaken to deal with these problems.

And the video memories? Theywere produced and designed intothe first digital televisions. Thesememories allowed television systemdesigners to explore, implement,and test video-field-related process-ing. The original plan for digitizingtelevision materialized many yearslater in a completely different form.That is the thrilling side of research;it will never deliver what youexpect, but what it ultimately deliv-ers is beyond your expectation!

Marcel PelgromScientist, PhilipsResearch Lab, Eindhovenmarcel .pelgrom@philips.com

Solid-State Circuits Society Newsletter 7

January 2005 • Volume 10 – Number 18

Published in the December 1988JSSC, ““The Design of Sigma-Delta Modulation Analog-to-

Digital Converters,” by Bernhard E.

Boser and Bruce A. Wooley, is a clas-sic article. It has been cited more than100 times according the Journal Cita-tion Report, 2003 Science Edition.

For more classic, often-citedarticles from the Journal of Solid-State Circuits see the Web sitesscs.org/jssc/top-cites.htm.

A JSSC Classic Paper:

Sigma-Delta Converters

Bernhard Boser comments:When I arrived at Stanford University in fall of 1984,Bruce Wooley just had joined the faculty. He intro-duced me to the topic of oversampled A/D conver-sion by handing me the draft of a now-famous paperon the topic by James Candy (“A use of double inte-gration ...”). I must have read the paper at least tentimes and still did not understand the thing. So Iwrote a little program to check out the ideas and, lowand behold, this thing WAS a converter. But how didit work?

It took me many months (more precisely, years) toanswer this question. On the path there I met manyengineers who flat-out stated that getting 16-bit accu-racy out of what seemed to be just a 1-bit converterwas plain impossible. I even found a doctoral thesisgiving a ‘proof’ that higher-order modulators couldnot work!

In good engineering tradition I proved the skepticswrong not with a piece of computer code but with anactually working silicon example. In designing that partI was faced with another set of questions: Only a 1-bitADC (that is, a simple comparator) is needed, but whatabout its accuracy? Are the offset, hysteresis, and noisespecifications at the 16-bit or 1-bit level? What about therequirements for the other components? By now wellresearched, these questions were most confusing in themid-1980s.

When I got my sigma-delta modulator working I sawan opportunity to help the community by presentingmy experiences and conclusions in writing so that oth-ers would not have to take my arduous (and reward-ing!) path. I hope I succeeded in helping some readersgrasp the concept of sigma-delta modulation a littlemore quickly than I did. Of course, the results present-ed in my article have long been exceeded, refined andextended.

I blush when I think that my paper also contains atleast one inaccuracy when it states overly modestgain requirements for the amplifiers. Fortunately,engineers never stand still and much has been writ-ten on the topic since. Still, it is rewarding to see thatauthors still cite (and read?) my publication. It is a bighonor to appear on the Journal’s list of most-citedpapers.

Bruce Wooley comments:The invention of the transistor in the mid-20th century wasfollowed by the rapid growth of interest in digitizing infor-mation for communications, storage and signal processing.In particular, attention began to focus on the use of digitaltransmission and switching in the voice telephone net-work. Analog-to-digital conversion thus became anincreasingly important function in the communicationsinfrastructure in both Europe and North America.

Prior to the emergence of large-scale MOS integrated cir-cuits, A/D converters for applications in communicationswere typically expensive, rack-mounted systems that wereshared among multiple channels in order to amortize theircost. However, the emergence of MOS VLSI technology andthe ability to integrate thousands of digital gates on a siliconchip motivated efforts to find a means of exploiting thiscapability to reduce the cost of digitizing analog signals.

Oversampling approaches to digitizing analog signals,which combine sampling at well above the Nyquist ratewith feedback and digital filtering, offer a means ofexchanging resolution in time for that in amplitude. Thus,they are an effective approach for exploiting the compo-nent density and speed of scaled VLSI technology toavoid the need for complex, precision analog circuits.

Oversampling modulation for analog-to-digital conver-sion first appeared in the form of delta modulation, whichwas introduced at about the same time as the inventionof the transistor. Ten years later an approach referred toas sigma-delta, or equivalently delta-sigma, modulationwas introduced. As opposed to delta-modulators, whichencode the rate of change of a signal, sigma-delta modu-lators digitize the signal itself while shaping the resultingquantization noise in frequency so as to push most of itsenergy outside the signal band where it can be removedby digital filtering. Consequently, they are an especiallyrobust means of digitizing signals that require only a verylimited amount of analog circuitry.

Bernhard’s research focused on devising architecturesand circuit implementations best suited to implementingprecision A/D converters in scaled digital VLSI technolo-gies. As described in the JSSC paper, his work focused onthe design and realization of second-order sigma-deltamodulators, which avoid the large spurious noise tonesinherent in first-order architectures, as well as the stabili-ty concerns associated higher-order loops. He established

The ImpactNoise-shaping modulators now play a dominant role inthe realization of A/D converters, not only for voice tele-

phony, but also in a broad range of digital audio sys-tems. Moreover, they are beginning to make inroads intoapplications with higher bandwidths.

The papers resulting from Bernhard’s work continue toserve as a foundational reference for insight into the sim-ulation and design of noise-shaping oversampled A/Dconverters at both the architectural and circuit levels. Hiswork clearly established the critical circuit requirementsfor designing such modulators, and it pointed the way tothe effective modeling of such systems at the behaviorallevel. The second-order modulator design he proposedand demonstrated has subsequently served as the keybuilding block for the realization of higher-order, cascad-ed sigma-delta modulators that have been used to digitizeboth low-pass and bandpass signals with bandwidths ofseveral megahertz and center frequencies as high as 20MHz. Moreover, the software he developed remains avaluable tool for assessing the behavior of mixed-signalsystems in which feedback plays an important role.

Solid-State Circuits Society Newsletter 9

behavioral models for each of the functional buildingblocks in a second-order modulator that included theimpairments associated with practical circuit realizations.Extensive simulations were then used to establish the cir-cuit design criteria for each of these blocks, and an exper-imental modulator was integrated to verify the validity ofthese criteria.

Because the performance of oversampling modula-tors can only be assessed by examining long data traces,they cannot be efficiently simulated at the circuit level.As an alternative, Bernhard developed an event-drivenfunctional simulator for mixed digital and analog sam-pled-data systems (MIDAS) to accomplish this task. Thissimulator was a critical component of Bernhard’sresearch and is still in widespread use today.

Beginning January 2005, SSCS e-News alerts willcome in alternate months, six times a yearinstead of quarterly. In contrast, the print

newsletter (for those who still receive the postalmailed version) will come less frequently, once everyfour months, or three times a year. Those receivingthe e-News alerts will be given twice as much newson the Society’s Web site as those dependent on theprint version. The news site online will feature a newlook and feel as well.

The print version will come January, May, and Sep-tember, and will be timed to include information aboutmajor upcoming SSCS conferences (the ISSCC in Febru-ary, the VLSI Symposium on Circuits in June and theCICC in October). Additional coverage in the expandede-News postings will include more information aboutIEEE elections, IEEE Fellows, books of interest to mem-bers, technology highlights, reminders about nomina-tion deadlines, and deadlines for best rates for advanceregistration for conferences.

E-News alerts to the bimonthly SSCS Newsletter areavailable free to SSCS members. If you aren’t receivingthe e-News alerts yet it’s because your email address isnot in the IEEE member database. Or you may haveopted out of receiving the e-News alerts.

1. To update your member record onlinewww.ieee.org/emembership.manage.xml

2.To request e-News delivery or opt out, use the online form at sscs.org/e-enews

E-News Serves Members’ InterestsThe move to email alerts of the SSCS Newsletter postedonline is serving our members well since its launch inJanuary 2003. Analysis of the hits to the Society elec-tronic news for April and July 2004 shows that on theday that an email notice is mailed, there is a four- tofivefold increase in hits to the e-News site. There weretwice as many visits and twice as many unique visitorsduring the issue month of April compared to July, per-haps because of summer vacations. But each visitoraveraged more page views per visit in July, and spentlonger at the site.

Articles that named people were the most frequentlyread articles, for example, “Ultra-wideband wirelssschip wins student design contest,” “ JSSC Best Paperawarded to Shrivanik Su and Wooley,” and “Nagarajnamed new editor-in-chief for JSSC.” Cover stories onthe VLSI Circuits Symposium and CICC were next mostread along with the table of contents of each issue.“Congratulations to new Senior Members” was amongthe top 10 articles for both issues and in April even hadmore hits than the 2004 class of IEEE Fellows. Olderarticles continue to be read: the January and April 2003articles on the Gilbert cell, and the October 2003 reviewof the business bestseller Good to Great: Why SomeCompanies Make the Leap and Others Don’t.

Newsletter coverage for 2005 will include more com-mentary on JSSC classics and coverage of books ofinterest.

SSCS e-News More Often in 2005; Less Paper

January 2005 • Volume 10 – Number 110

Three new members will jointhe IEEE SSCS AdministrativeCommittee when it meets 6

February 2005, and two incumbentswill return. The SSCS membershipelected new members Bill Bider-man, Terri Fiez and Mehmet Soyuerlast fall. David Johns and TakayasuSakurai will return to serve three-year terms.

“Our congratulations go out tothese leaders in their field,” saidCharlie Sodini, SSCS Past-Presidentand Nominating Committee Chair,“and our gratitude for the willing-ness to serve of all the candidates.SSCS bylaws specify that we mustprovide our members a choice andwith so many talented leaders, thechoice is a difficult one.”

The AdCom is responsible foroverseeing conferences, publica-tions, and other potential technicalactivities within the Society’s field ofinterest. Each AdCom memberserves a three-year term. Terms arestaggered so there are always someexperienced members and somenew members. The NominatingCommittee puts together a ballot ofcandidates each summer. A membercan petition to be included on theballot. See details online atsscs.org/nomelec.htm.

William R. Bidermann (M’89)received his BSand MS degrees inelectrical engin-eering and com-puter science fromthe MassachusettsInstitute of Tech-nology in 1978.Currently he is

Vice President of Sensor Develop-ment at Pixim Inc., a Silicon Valleystartup delivering high dynamic-range CMOS image sensors to thesecurity market. He managed theAdvanced Development Group atDEC, which produced a self-con-tained liquid-nitrogen-cooled com-puter system and the groundbreak-

ing Alpha microprocessor. Over thepast 20 years, Mr. Bidermann con-tributed to the first µVAX micro-processors, managed the firstSPARC V9 implementation at HaLComputers, and led the develop-ment of a novel media-processor atChromatic Research. He began hiscareer at HP Labs, where hedesigned dynamic RAMs and EEP-ROM devices.

Mr. Bidermann currently serveson the Executive Committee of theSymposia on VLSI Circuits and Tech-nology (Treasurer) and has previ-ously served as the General Chair(‘99–‘00), Program Chair (‘97–‘98)and as a Program Committee mem-ber since 1993. He twice has been amember of the ISSCC Program Com-mittee and has edited several specialeditions of the IEEE Journal of Solid-State Circuits.

David A. Johns received his BASc,MASc, and PhDdegrees from theUniversity of Toron-to, Canada, in1980, 1983 and1989, respective-ly. In 1988 hejoined the Uni-versity of Toronto

where he is currently a full profes-sor. Dr. Johns has ongoing researchprograms in analog integrated cir-cuits with particular emphasis ondigital communications, oversam-pling, signal processing, PLLs,ADCs, DACs, and adaptive filter-ing. His research work has result-ed in more than 40 publicationsas well as the 1999 IEEE Darling-ton Award. Coauthor of the Ana-log Integrated Circuit Design(Wiley, 1997) textbook, Dr. Johnshas given numerous industrialShort Courses. In addition to hisacademic experience, he has fouryears of semiconductor industrialexperience during 1980, 1983–85,and 1995, and is cofounder ofSnowbush, a microelectronics

company. He served as an associ-ate editor for IEEE Transactionson Circuits and Systems Part IIfrom 1993 to 1995 and for Part Ifrom 1995 to 1997. Dr. Johns is anIEEE Fellow and is already serv-ing on the SSCS AdCom.

Terri S. Fiez received her BS andMS in electricalengineering in1984 and 1985,r e s p e c t i v e l y ,from the Univer-sity of Idaho,Moscow. In 1990,she received aPhD in electrical

and computer engineering fromOregon State University, Corvallis.From 1985 to 1987 and in 1988she worked at Hewlett-PackardCorporation in Boise and Corval-lis, respectively. In 1990 Dr. Fiezjoined Washington State Universi-ty as an assistant professor whereshe became an associate professorin 1996. In the fall of 1999 Profes-sor Fiez joined the Department ofElectrical and Computer Engineer-ing at Oregon State University asa professor and department head.

She became Director of theSchool of Electrical Engineeringand Computer Science in 2003.She has been involved in a varietyof IEEE activities including serv-ing on the committees for theIEEE International Solid-State Cir-cuits Conference, IEEE CustomIntegrated Circuits Conference,ISCAS, and as a guest editor of theJournal of Solid-State Circuits. Dr.Fiez previously was awarded theNSF Young Investigator Awardand the Solid-State Circuit Predoc-toral Fellowship. Her researchinterests are in the design of high-performance analog signal-pro-cessing building blocks, simula-tion and modeling of substratecoupling effects in mixed-signalICs, and innovative engineeringeducation approaches.

SSCS Elects Five AdCom Members

Solid-State Circuits Society Newsletter 11

Takayasu Sakurai (S’77–M’78–S M ’ 0 1 – F ’ 0 3 )received his PhDin electrical engi-neering from theUniversity ofTokyo in 1981. In1981 he joinedToshiba Corpora-tion, where he

designed CMOS DRAM, SRAM, RISCprocessors, DSPs, and SOC solu-tions. He has worked extensively oninterconnect delay and capacitancemodeling known as the Sakuraimodel and the alpha power-lawMOS model. From 1988 through1990, he was a visiting researcher atthe University of California, Berke-ley, where he conducted research inthe field of VLSI CAD. Since 1996,he has been a professor at the Uni-versity of Tokyo, working on low-power high-speed VLSI, memorydesign, interconnects, ubiquitouselectronics, organic ICs and large-area electronics. He has publishedmore than 350 technical publica-tions including 70 invited papersand several books, and has filed

more than 100 patents. He served asa conference chair for the Sympo-sium on VLSI Circuits and ICICDT,as a vice chair for ASPDAC and as aprogram committee member forISSCC, CICC, DAC, ICCAD, FPGAworkshop, ISLPED, TAU and otherinternational conferences. He was aPlenary Speaker for the 2003 ISSCC.He is also an IEEE Fellow, an elect-ed AdCom member of the IEEESolid-State Circuits Society and anIEEE CAS Distinguished Lecturer.

Mehmet Soyuer received a PhD inelectrical engineer-ing from the Uni-versity of Califor-nia, Berkeley, in1988, subsequentlyjoining IBM at theThomas J. WatsonResearch Center asa research staff

member. His work has involvedhigh-frequency mixed-signal inte-grated circuit designs, in particular,monolithic phase-locked-loop de-signs for clock and data recovery,clock multiplication and frequency

synthesis using silicon and SiGetechnologies. He managed theMixed-Signal Communications Inte-grated-Circuit Design group from1997 to 2000, and since then hasbeen the senior manager of theCommunication Circuits and SystemsDepartment at the Thomas J. WatsonResearch Center, Yorktown Heights,New York.

Dr. Soyuer has authored numer-ous papers in the areas of analog,mixed-signal, RF, microwave andnonlinear electronic circuit design,and he is an inventor and co-inven-tor of eight U.S. patents. Since 1997he has been a technical programcommittee member of the Interna-tional Solid-State Circuits Conference(ISSCC). He was an associate editorof the IEEE Journal of Solid-State Cir-cuits from 1998 through 2000, andwas one of the guest editors for theDecember 2003 special ISSCC issue.Dr. Soyuer also chaired the Analog,MEMS and Mixed-Signal ElectronicsCommittee of the International Sym-posium on Low-Power Electronicsand Design (ISLPED) in 2001. He isa Senior Member of the IEEE.

The Santa Clara Valley Chap-ter, the first SSCS chapter,will receive the Outstanding

Chapter Award next February atthe ISSCC. Jan Van der Spiegel, theSSCS Chapters Coordinator, notedthat the SCV Chapter had been“consistently active” since its incep-tion in 1997 with an “impressive

list of monthly speakers.” Thechapter has organized Short Cours-es and has reached out to localmembers and students, as reportedin the SSC Newsletter, July 2004.

The SCV Chapter is the largestSSCS chapter, with 1600 members.In a survey conducted last year,the chapter found it has at least 77

senior IEEE members, and 24 IEEELife Members. Twenty-three IEEEFellows belong to the chapter, sixof whom are IEEE Life Fellows;there are many prestigious mem-bers of the Solid-State CircuitsSociety in Santa Clara Valley.

Congratulations on a job welldone!

Santa Clara Valley Chapter Is Outstanding

Congratulations New Senior MembersJean-Luc AutranEric N. CartagenaRamon G. CarvajalHenry ChangWard J. HelmsVikram B. KrishnamurthyTad A, Kwasniewski

Stefan W. LachowiczYuyun LiaoPradeep MaitraDragon MaksimovicGlenn H. MartinMasayuki MiyamotoArthur S. Morris

Nawej MwezAnil SahaDouglas W. StoutDennis M. SylvesterMarek SyrzyckiBrian K. SwannGraham E. Town

Chua-Chin WangTin Tin WeeStephen T. WilliamsFeng YingHoi-Jun YooBenyong Zhang

January 2005 • Volume 10 – Number 112

Call for Fellow Nominations

Nominations are beingaccepted for the 2006 classof IEEE Fellows. For the

second year, nominations, refer-ences and endorsements may besubmitted electronically. The dead-line, 1 March 2005, is two weeksearlier this year.

At its June 2003 meeting, the IEEEBoard of Directors approved

changes to the process for nominat-ing and electing IEEE members toFellow grade. The change estab-lished a new nomination category forindividual contributions, with thegoal of increasing nominations formembers in industry and encourag-ing nominations of application engi-neers or engineering practitionerswho have made contributions of

unusual distinction to the profession.The board also established a Fel-

low Nomination Resource Center tohelp nominators locate the requirednumber of references to support anomination.

To nominate an IEEE seniormember or to learn more aboutthe Fellow program, visitwww.ieee.org/fellows.

The IEEE Virtual Museum isamong five Web sites chosenby ScientificAmerican.com for

its Science & Technology WebAwards 2004 in the Engineering &Technology category.

According to ScientificAmeri-can.com, the 50 sites chosenoverall represent the “best sitesfrom the rest” and are “worthy ofhigh praise.” In reference to theIEEE Virtual Museum, Scientifi-

cAmerican.com told readers,“Start digging—you’ll be just asgrateful as the Institute expectsyou to be!”

For more information, visitwww.ieee-virtual-museum.org/.

IEEE Virtual Museum Praised by ScientificAmerican.com

The 40th anniversary of Moore’sLaw is approaching in 2005.Penned in 1965 in Electronics

magazine, Moore’s initial predictionthat the number of transistors on anintegrated circuit would double annu-ally has been referenced and dis-cussed often in the industry and inthe financial press. It was CarverMead at Cal Tech who called it a law,as if it were a fundamental principalof science or economics. And thebehavior of the industry has pro-gressed accordingly. Often IC firmsused it to set design goals in theirgeneral drive for process and productimprovement.

Now the Solid-State Circuits Soci-ety makes available online GordonMoore’s Plenary Session presenta-tion on his exponential descriptor ofthe IC industry. In February 2003Gordon Moore spoke at the 50thanniversary of the InternationalSolid-State Circuits Conference(ISSCC). The online presentation

includes a sound track and the coloroverheads of graphs and devicesover the years.

Download Specifications (requiresMicrosoft Office Animation Runtime):

• Sample of four slides, 7 minutesruntime, 5M download size

• The complete presentation, 35minutes runtime, 40M down-load size

The Web site, sscs.org/History/MooresLaw.htm, provides a sampleintroductory download to test onyour system.

The Web site also provides thetranscript of the full soundtrackand links to Moore’s article andvisuals as originally published inthe ISSCC 2003 Digest and Supple-ment. Other articles on Moore’sLaw in IEEE publications are fea-tured on the site. Readers areencouraged to suggest otherpapers on the future of IC growthand let us know why they thinktheir suggested article should be

referenced on the site. Write toa.oneill@ieee.org.

Anne O’NeillSSCS Executive Directora.oneill@ieee.org

Listen to Gordon Moore Talk about Moore’s Law

Excerpts from Moore’s PresentationThe number of transistors shippedper year has grown 81

2 orders ofmagnitude over the last 35 years.Three hundred million-fold, main-taining an average growth of about80% per year, now that’s a growthindustry! Truly phenomenal growth.

To illustrate this number—you’regetting up near 1018—I’ve usedraindrops falling on California. NealWilson, the Harvard biology experton ants, estimated that the numberof ants in the world is 1016 to 1017.So for years I used that. Now eachant has to carry 10100 transistors ifit’s going to take care of its load!

With the addition of five newchapters that were formedduring the last half of 2004,

the Solid-State Circuits Society hasexceeded its goal of 50 chapters, aswas envisioned at its founding in1997. The prediction of our chapterchair coordinator, Jan Van derSpeigel, was realized in July of 2004.

SSCS would like to extend a warmwelcome to the five new chaptersthat helped put us at the top. Two ofthe new chapters are singularlyfocused on the SSCS field of interest:the Tucson Chapter, chaired byJoseph Wu, and the Vancouver Chap-ter, chaired by Resve Saleh. The Cen-tral North Carolina Chapter shares thefields of interest of SSCS and ElectronDevices (EDS) and is chaired by TonyIvanov. Two new joint SSCS/Circuitsand Systems Society (CAS) chaptersare the Southern Alberta Chapter,chaired by Caitlin Davis, and theCanada Atlantic Chapter, chaired byMarc Murphy. (Chapters devoted tothe technical interests of more thanone society are described as joint.)

More than half of all SSCS chap-ters are singularly focused on theSSCS technical interests. Thirty per-cent of SSCS chapters are joint chap-ters with only one other societytechnical interest. Nine chapters arejoint with only EDS, seven chaptersare joint with only CAS, and one

joint with SPS. The remaining nineare joint with multiple societies.

The Society has chapters in nineregions worldwide. There are cur-rently thirteen chapters in regions 1–6(U.S.), seven in region 7 (Canada),twenty-two in region 8 (Europe andAfrica), and ten in region 10 (Asia andAustralia). The Society’s goal is tocontinue chapter formation.

Van der Speigel commented on theachieving the goal, “It is very excitingto see the strong interest in SSCS chap-ters. The healthy growth of the SSCSchapters is a good indicator of theinvolvement of the members in SSCSrelated activities worldwide. I would

like to take the opportunity to thankall the chapter officers for their effortsin offering educational and profession-al activities to their members.”

To see if there is an SSCS chapternear you, visit our online roster atsscs.org/Chapters/chptrchairs.htm.For tips, instructions and petitionforms to start a chapter in yourcity check out this URL: sscs.org/chapter.htm#startchapter.

Chapter chairs meet annually overlunch during the February ISSCC inSan Francisco to discuss best prac-tices. If you are interested in startinga chapter, contact Jan Van derSpeigel at jan@seas.upen.edu.

Solid-State Circuits Society Newsletter 13

SSCS Tops 50 Chapters

Denver ChapterDuring the past half year, the SSCSDenver Chapter hosted several tech-nical seminars and a social event. InMay 2004 Michael Rubin of AgilentTechnologies presented “IC designsolutions in a foundry environ-ment,” an important topic especiallygiven the concentration of fablessdesign houses in northern Colorado.Due to summer tapeout pressuresencountered by the chapter officers,chapter activities resumed in Sep-tember with a BBQ social at a localclubhouse. The following month,Ken Richardson of LSI Logic pre-sented an informative tutorial on“Measurement, modeling, and simu-lation of high-speed transmissionlines.” This was a particularly applic-able seminar since many local com-panies in Fort Collins have activeR&D efforts in developing high-speed serial data interfaces.

Our year ended with a seminaron the globalization of engineeringand high-tech jobs, a topic thatattracted participation from overone hundred people—the largestattendance since the chapter’sinception two years ago! Dr. DonMorris, recently retired from AgilentTechnologies, gave a thoroughlyinsightful presentation on the con-troversial topic. He drew upon clas-sical economic thought and provid-ed powerful historical examples of

high technology and internationaltrade dating back many centuries inorder to motivate the conclusionthat the outsourcing of commodi-tized engineering activity to lower-cost geographies is merely aninevitable and natural economicevolution driven by the “cold, deadhand of Adam Smith.” Alluding tohis experiences managing a designlab he created in Singapore, Dr.Morris also explained that the high-tech sector in Singapore was indeep fear of job outsourcing toeven lower-cost geographies. Thekey to surviving through such eco-nomic trends is to embrace out-sourcing whenever and whereverpossible in order to enjoy costadvantages sooner than competi-tors, but continue to innovate new

products, hence creating new activ-ities to replace outsourced ones. Ona personal level, this requires con-tinual development of new skillsthat enable such innovations so asto maintain marketability.

The 2005 annual elections werealso held in November with Dr.Alvin Loke elected as Chapter Chair,Dr. Don McGrath as Vice Chair, TinTin Wee as Secretary/Web master,and Bob Barnes as Treasurer.

We look forward to growing par-ticipation in upcoming seminars.Please visit our Web site atewh.ieee.org/r5/denver/sscs/ formore information (including pastpresentation slides) about our chap-ter events.

Alvin LokeDenver Chapter Vice Chairalvin.loke@ieee.org

Tin Tin WeeDenver Chapter Secretary/Web mastertintin.wee@ieee.org

ED/SSC Varna ChapterThe Technical University of Varna,Bulgaria, held a three-week summerschool on CAD in electronics, fund-ed primarily by the joint IEEE Solid-State Circuits and Electron DevicesChapter. There were lectures andpractical training by faculty from theTechnical Universities of both Varnaand Sofia. The main topic was ana-log IC design, simulation, and layout

January 2005 • Volume 10 – Number 114

Chapter News

The new Atlantic (Canada) Chapter: Section Chair Ken Mah, Chapter Chair MarcMurphy, and Guest Speaker Farhad Shafai. The Atanatic Chapter, joint SSCS andCAS is online at www.ieee.org/cas_ckts

Hans Stork spoke in July to the San Diego Chapter on the Realities of System-on-Chip Integration.

using Pspice and Cadence softwareproducts. Of the sixteen in atten-dance, half were IEEE members.

In the fall of 2003 the Varna Chap-ter cosponsored two technical meet-ings. As a part of the ConferenceET2003 (Electronic Engineering2003) in Sozopol, whose primarysponsor was the TU of Sofia, morethan 100 papers were presented inthe sessions. As part of the anniver-sary conference of the TechnicalUniversity of Gabrovo, there wereover 90 papers presented in the ses-sions on electrical engineering, com-puter science and engineering, elec-tronics, and communications.

Jordan Kolev SSCS Bulgaria Chapter Chairikolev@ieeel.bg

Kansai ChapterThe Kansai Chapter held a technicalseminar on 25 October in Kyoto,focusing on interconnects in termsof signal integrity in nanometer-scale designs. Two excellent speak-ers attracted an audience fromacross Japan, including 34 profes-sionals and 12 students.

Toshiki Kanamoto from RenesasTechnology Corporation provided atutorial lecture on “Interconnectmodeling technology for SoCdesign,” introducing the basics oftiming analysis, interconnect model-ing and extraction technologies. Healso provided insights into the prac-tical consideration of inductive par-asitics in SoC design with the latestEDA tools.

Dr. Nishath Verghese fromCadence Design Systems dealt thor-

oughly with delay calculation forgate models that accurately account-ed for long wires, crosstalk, groundbounce, temperature inversion, aswell as process variability. The inter-play of crosstalk and timing wascovered in his presentation, “Accu-rate crosstalk and timing analysis ofnanometer-scale digital ICs.”

Both talks were well organized,providing a good reference forexperienced designers as well asmotivating students towards innov-ative thesis work in the VLSI designfield. Questions from the audienceand answers by the lectures werevery detailed and helped furtherunderstanding of the topics, whichcharacterized the success of theseminar.

Makoto NagataKansai Chapter Secretarymnagata@ieee.org

Solid-State Circuits Society Newsletter 15

Kansai Chapter at 25 October 2004 seminar (left to right) : Junji Ishikawa (Trea-surer ), Hironori Yamauchi (Chapter Vice Chair), Masao Nakaya (Chapter Chair),Toshiki Kanamoto (Invited lecturer), Nishath Verghese (Invited lecturer), HidetoshiOnodera (Former Chair of Kansai Chapter) and Makoto Nagata (Secretary).

Solid-State Circuits is online: Find us at www.sscs.org

! International Solid-State Circuits Conference (from 1955)

! Custom Integrated Circuits Conference (from 1988)

! Symposium on VLSI Circuits (from 1988)

! European Solid-State Circuits Conference (from 2003)

Society Member Annual Subscription: $75 Product number 037-751

www.ieee.org/membership/manage.xml

IEEE Solid-StateCircuits Conference Digital Library

January 2005 • Volume 10 – Number 116

The SSCS membership dropped 7.8% from May 2003to May 2004. Other IEEE societies experienced sim-ilar attrition (see the table below). The Communi-

cations Society enjoyed an increase in membership fromFebruary 2004 to May 2004 due to more than 10,000 newstudent members.

In July 2004 the IEEE performed an All-Society ResearchProject (ASRP). The goals of ASRP were threefold:

• Gather data from individuals who maintained theirIEEE membership but dropped their society mem-bership in one or more IEEE societies.

• Identify the reasons for the declining membership.• Identify potential improvements in products and

services.For SSCS, 1077 current IEEE members who dropped

their SSCS membership were invited to participate, anda total of 281 former Society members completed sur-veys for a 26% response rate. The demography of the“population” who dropped SSCS membership is sum-marized in the following table.

Of the “population,” 52% were with private industry, 18%were full-time students, and another 18% were with educa-tional institutions. The high percentage of dropped mem-berships in private companies reflected the spending cuts

within the semiconductor industry in the past few years.When asked to give their reasons for dropping SSCS

membership, four major factors were quoted to haveinfluenced their decisions:

• My employer/university has access to IEEE publica-tions and I feel I no longer need my personal IEEESSCS membership (31%)

• I do not have time to read IEEE SSCS publications (30%)• My career/position has changed and IEEE SSCS is

no longer relevant (28%)• IEEE SSCS membership dues are too expensive (23%)When asked if they would choose to rejoin SSCS in

the next year, 52% said unlikely, 31% undecided, andonly 17% said likely. Since 56% of them also quoted thatthe reason they joined SSCS in the first place was toobtain SSCS publications, the availability of IEEE publi-cations online would have a continual effect on ourmembership enrollment.

When asked why they were dissatisfied with the SSCSmembership specifically, the high cost of membershipfees and the JSSC publication charges were ranked dis-tinctly the top issues. Changed job functions and narrowfocus of the Society publications on analog design weretwo other major factors.

When asked what the SSCS could do to regain theirpatronage, over 50% wanted a reduced membership feeand access to online publications at no extra cost. A moreinteresting suggestion was to create an SSCS Magazine,similar to the Communications Magazine, which can servethe circuit-design professionals at large. For example, thearticles in the magazine can be devoted to a broader cov-erage of various circuit design disciplines, explanations ofcurrent and breaking technologies, and tutorials on designtechniques, rather than the detailed research papers, ascurrently published in JSSC. Providing more local activitiesfor networking and job-related opportunities and helpingyoung engineers realize their career goals were also men-tioned as lacking in our Society services.

Finally, a survey on IEEE publications indicated thatJSSC was voted the most “useful” among all IEEE publica-tions (59.8% “extremely useful”), and that ISSCC was alsovoted the most useful among all IEEE-sponsored confer-ence proceedings. In general, the majority of our mem-bers feel well served due to our high-quality publicationsand conferences. However, we may have a challengingtask ahead to reach out to more engineers, especially theyounger ones. We will need to provide a broader base ofknowledge and services to accommodate the shift infocuses of the semiconductor industry over time.

Teresa MengSSCS AdCom Membership Chairthm@stanford.edu

2003–2004 Membership Report

H i r o h i s aKawamoto is thechair of the firststeering commit-tee organized tolaunch the newIEEE/OSA Journalof Display Tech-nology (JDT) in

2005. Kawamoto, an IEEE Fellow, isa visiting professor at Nara Instituteof Science and Technology, Takaya-ma, Nara, Japan. He received his BSdegree in electronics from KyotoUniversity, Japan, in 1961 and his MSand PhD degrees in electrical engi-neering and computer sciences fromthe University of California, Berke-ley, in 1966 and 1970, respectively.

From 1961 to 1968 he was withthe Matsushita Electronic Corpora-tion, Osaka, Japan. In 1970 hetaught as an acting assistant profes-sor at the Department of ElectricalEngineering and Computer Sciencesof the University of California,Berkeley. From 1970 to 1980 heworked for the RCA David SarnoffResearch Center, Princeton, NewJersey. In 1980 he founded the SonyConsumer Electronics Laboratoriesin Paramus, New Jersey, where heserved as general manger until 1985.During the same time he foundedthe Princeton Community JapaneseLanguage School, Princeton, New

Jersey, and served as the chair of itsBoard of Trustees until 1985.

From 1985 to 2001 he was withthe Sharp Corporation, Japan, wherehe participated in the founding ofSharp Laboratories of Europe atOxford, U.K., and Sharp Laborato-ries of America at Camus, Washing-ton. His last assignment at Sharpwas as vice president and divisiongeneral manager of the TechnicalInformation Center.

Since July 2001, he has been asenior business advisor with SiliconImage Inc., Sunnyvale, California,stationed in Nara Gakuen-Mae,Japan. From 1994 to 2000 he actedas a delegate from Japan to theCommittee of Action of Internation-al Electro-Technical Commission,Geneva, Switzerland.

Dr. Kawamoto was elevated toIEEE Fellow in 1992 for contribu-tions to materials, device, and sys-tems technologies for the use invideo systems. Dr. Kawamoto hasalso received the IEEE CentennialMedal and Third Millennium Medal.

Call for Papers and SubscribersThe JDT will cover display systemsand engineering, materials and com-ponents, optical design, lightingtechnologies, display drivers andinterfaces, display packaging, manu-facturing technology, reliability and

testing, and applications. Manu-scripts can be submitted electroni-cally for peer review thoroughIEEE’s Manuscript Centralhttp://www.i-leos.org/. Sponsoredby seven IEEE societies includingSSCS, the peer review process forJDT is managed through the staff ofthe Laser and Electro-optics Society(LEOS). New authors should createan account. Authors who have pre-viously submitted manuscripts toLEOS publications could simplyselect the IEEE/OSA Journal of Dis-play Technology and log on. Forquestions, contact Linda Matarazzo,Manager, IEEE LEOS EditorialOffice, l.matarazzo@ieee.org (phone+1 732 562 3910; fax +1 732 9811138).

The inaugural issue of the JDT isscheduled for September 2005. Themid-year introduction in 2005 will befollowed by quarterly publication in2006. The member prices for theintroductory year will be $13 foronline, $14 for print, and $17 forboth in 2005, reflecting just twoissues printed in the launch year. In2006, when four issues will be print-ed, subscription rates will be adjust-ed. Subscriptions are available at anytime by choosing to “Add Services”to your membership record:http://services1.ieee.org/membersvc/addservices/intro.htm.

Solid-State Circuits Society Newsletter 17

Hirohisa Kawamoto Named Steering Committee Chairof IEEE/OSA Journal of Display Technology

Books of Interest to SSCS

This selection of technical bookscovers topics that may be ofinterest to our readers. The

descriptions are provided by the pub-lishers.

Electronic Physical Design by Barry M. Lunt, PhD, BrighamYoung University, published byPrentice Hall, 2004, $91.00, ISBN: 0-13-094387-8.

Electronic Physical Design is auseful reference for both the theory

and practice of electronic physicaldesign for courses in areas such aselectronic manufacturing processes,electronic physical design, circuitboard design, and electronic proto-typing. This text addresses thechoices to be made at the IC level,the IC package level, and the circuitboard level. It then discusses thechoices among the many types ofresistors, capacitors, connectors, andtransistor packages. Finally, this textaddresses the concepts involved in

building high-quality products,including robust design, heat vibra-tion, shock, dust, and humidity.

Fundamentals of Electric Circuits(Third Printing) with CD-ROM(Second Edition)by Charles Alexander, Cleveland StateUniversity, and Matthew Sadiku,Prairie View A&M University, pub-lished by McGraw-Hill, 2004, price tobe announced, ISBN: 0-07-304835-6.

Fundamentals of Electric Circuits

January 2005 • Volume 10 – Number 118

is intended for use in the introduc-tory circuit analysis or circuit theorycourses taught in electrical engi-neering or electrical engineeringtechnology departments. The mainobjective of this book is to presentcircuit analysis in a clear, easy-to-understand manner, with manypractical applications. Each chapteropens with either historical sketch-es or career information on a sub-discipline of electrical engineering.This is followed by an introductionthat includes chapter objectives.Each chapter closes with a summa-ry of the key points and formulas.

The authors present principles inan appealing and lucid step-by-stepmanner, carefully explaining eachstep. Important formulas are high-lighted to help students sort outwhat is essential and what is not.Many pedagogical aids reinforcethe concepts learned in the text sothat students become comfortablewith the various methods of analy-sis presented in the text.

Formal Verificationby Douglas Perry and Harry Foster,to be published by McGraw-HillProfessional, 2005, $89.95, ISBN: 0-07-144372-X.

Formal verification is a powerfulnew digital design method. In thiscutting-edge tutorial, two of thefield’s best-known authors team upto show designers how to efficient-ly apply formal verification, alongwith hardware description lan-guages like Verilog and VHDL, tomore efficiently solve real-worlddesign problems.

An Introduction to Radio-Fre-quency Engineeringby Christopher Coleman, publishedby Cambridge University Press, May2004, £40.00, ISBN 0-52-183481-3.

This book provides an excellentintroduction to radio-frequency engi-neering, using a straightforward andeasily understood approach com-bined with numerous examples,illustrations, and homework prob-lems. The author focuses on mini-mizing the mathematics needed tograsp the subject while providing a

solid theoretical foundation for thestudent. Emphasis is also placed onthe practical aspects of radio engi-neering. The book provides a broadcoverage of RF systems, circuitdesign, antennas, propagation, anddigital techniques. Written for upper-level undergraduate courses, it alsoprovides an excellent introduction tothe subject for graduate students,researchers and practicing engineers.

Introduction to SemiconductorDevices for Computing andTelecommunications Applicationsby Kevin Brennan, published by Cam-bridge University Press, December2004, £40.00, ISBN: 0-52-183150-4.

From semiconductor fundamentals tostate-of-the-art semiconductor devicesused in the telecommunications andcomputing industries, this book pro-vides a solid grounding in the mostimportant devices used in the hottestareas of electronic engineering today.The book includes coverage of futureapproaches to computing hardware andRF power amplifiers, and explains howemerging trends and system demandsof computing and telecommunicationssystems influence the choice, design,and operation of semiconductordevices. The book begins with a discus-sion of the fundamental properties ofsemiconductors. Next, state-of-the-artfield-effect devices are described, includ-ing MODFETs and MOSFETs. Short-channel effects and the challenges facedby continuing miniaturization areaddressed. The rest of the book discuss-es the structure, behavior, and operatingrequirements of semiconductor devicesused in lightwave and wireless telecom-munications systems. This is an excel-lent senior/graduate text, and a valuablereference for engineers and researchersin the field.

Low-Voltage, Low-Power VLSISubsystemsby Kiat-Seng Yeo and Kaushik Roy,to be published by McGraw-HillProfessional, 2005, $130.00, ISBN:0-07-143786-X.

There is no better way to learnthe latest techniques in VLSI designthan Low-Voltage, Low-Power VLSI.An invaluable reference and practi-

cal guide to the latest in optimizedVLSI subsystem design, written byleaders in cutting-edge chip design,this focused tutorial offers immedi-ate access to state-of-the-art, proventechniques in CMOS, BiCMOS, andother in-demand applications. Todesigners already hard at work inthe $200-billion-per-year-and-grow-ing electronics marketplace, and tostudents who want to join this fast-track industry, Kiat-Seng Yeo andKaushik Roy offer

• New approaches to the chal-lenges of silicon-level design forlow-power circuitry pacing elec-tronics

• Low-power solutions forSRAMs, DRAMs and signalprocessors

• Expert performance compar-isons and contrasts of low-power options

• Reduced-complexity designsolutions

• Optimization and implementa-tion techniques indispensablein modern VLSI subsystemdesign

• Useful charts, illustrations, andapplied algorithms

• Clear presentations of complextopics

• Real-life examples clarifyingkey concepts

Mobile Wireless Communicationsby Mischa Schwartz, published byCambridge University Press, Decem-ber 2004, £40.00, ISBN: 0-52-184347-2.

Wireless communication hasbecome a ubiquitous part of mod-ern life, from global cellular tele-phone systems to local and evenpersonal-area networks. This bookprovides a tutorial introduction todigital mobile wireless networks,illustrating theoretical underpin-nings with a wide range of real-world examples. The book beginswith a review of propagation phe-nomena, and goes on to examinechannel allocation, modulationtechniques, multiple accessschemes, and coding techniques.GSM and IS-95 systems arereviewed and 2.5G and 3G packet-

switched systems are discussed indetail. Performance analysis andaccessing and scheduling tech-niques are covered, and the bookcloses with a chapter on wirelessLANs and personal-area networks.Many worked examples and home-work exercises are provided and asolutions manual is available forinstructors. The book is an ideal textfor electrical engineering and com-puter science students taking cours-es in wireless communications. Italso is a valuable reference for prac-ticing engineers.

PSpice for Basic Circuit Analysis(First Edition)by Joseph G. Tront, Virginia Poly-tech Institute & State University,published by McGraw-Hill, 2004,price to be announced, ISBN: 0-07-298509-7.

PSpice for Basic Circuit Analysisintroduces readers to the fundamen-tal uses of PSpice in support of basiccircuit analysis. This book isdesigned so that the reader mayadvance rapidly to solving a varietyof circuit analyses. Although thefundamental capabilities of PSpiceare covered in this book, the princi-ples can easily extend to analyze thecomplex electrical and electronicnetworks used in modern integratedcircuit design today.

RapidIO—The Embedded SystemInterconnectby Sam Fuller, published by JohnWiley & Sons, January 2005,$135.00, ISBN: 0-470-09291-2.

RapidIO was developed specifical-ly to achieve high-performance, low-cost, reliable and scalable system con-nectivity in embedded, networkingand communications devices. Writtenby one of the founders of the RapidIOTrade Association, this is the first com-prehensive reference on this intercon-nect technology. It covers logical layerprotocols, network, link and physicallayer technologies, packet and symbolformats, register file definitions, andsystem software application program-ming interfaces. The book:

• Discusses the usage of RapidIO

in embedded systems such asenterprise storage and wirelessinfrastructure

• Illustrates newly defined tech-nologies such as the RapidFab-ric dataplane extensions

• Describes case studies ofRapidIO usage in real systemarchitectures

• Evaluates the programmingmodels associated with RapidIO

• Reviews related mechanical stan-dards such as the VME SwitchedSerial Extensions and the PICMGAdvanced TelecommunicationsArchitecture (ATCA) standards

RF Power for Industrial Applications by Louis E. Frenzel, Jr., published byPrentice Hall, 2004, $95, ISBN: 0-13-096577-4.

Written for two- to four-semester-hour courses in RF power in theelectronics/computer technologydepartments, RF Power for Industri-al Applications also can be used forindustry courses in RF power. Thistext, the only one of its kind on themarket, focuses on RF power for usein industrial applications, wheresemiconductor manufacturingequipment generates a plasma forprocessing wafers. The emphasis ison equipment and circuits related toRF power in manufacturing equip-ment tools such as etchers andchemical vapor deposition, amongothers. This is a useful book thatprovides a base upon which a stu-dent can pursue more equipment-specific knowledge.

Silicon Germanium: Technology,Modeling, and Designby Raminderpal Singh, Modest M.Oprysko, and David Harame, pub-lished by Wiley-IEEE Press, 2004,$99.95, ISBN: 0-471-44653-X.

Written for RF/analog and mixed-signal designers, CAD designers,semiconductor students, and foundryprocess engineers worldwide, SiliconGermanium provides detailedinsight into the modeling and designautomation requirements for leading-edge RF/analog and mixed-signalproducts, and illustrates in-depth

applications that can be implement-ed using IBM’s advanced SiGeprocess technologies and design kits. The book:

• Discusses IBM’s design automa-tion and signal integrity knowl-edge and implementationmethodologies

• Highlights details of highly inte-grated SiGe BiCMOS System-On-a-Chip (SOC) design

Tech Mining: Exploiting NewTechnologies for CompetitiveAdvantageby Alan L. Porter, Georgia Instituteof Technology, Atlanta, and Scott W.Cunningham, published by JohnWiley & Sons, November 2004,$69.95, ISBN: 0-471-47567-X.

Tech Mining incorporates thepremise that the information, thetools to exploit it, and the need forresulting knowledge is available andprovides the comprehension neededto enable technology managers toutilize new capabilities. By using thelessons presented in the book, man-agers can identify and access themost valuable technology informa-tion resources; search, retrieve, andclean the information on topics ofinterest; and lower the costs andenhance the benefits of competitivetechnological intelligence operations.

WCDMA for UMTS: Radio Accessfor Third-Generation MobileCommunications (Third Edition)by Harri Holma and Antti Toskala,both of Nokia, Finland, publishedby John Wiley & Sons, September2004, $105.00, ISBN 0-470-87096-6.

Regarded as “the book” on the airinterface of 3G cellular systems,WCDMA for UMTS has been fullyrevised and updated. Now detailingthe key features of 3GPP Release 6,this book remains the leadingresource in this constantly progress-ing area. By providing a deepunderstanding of the WCDMA airinterface, the practical approach willcontinue to appeal to operators, net-work and terminal manufacturers,service providers, university stu-dents, and frequency regulators.

Solid-State Circuits Society Newsletter 19

January 2005 • Volume 10 – Number 120

445 Hoes Lane Piscataway, NJ 08854

SSCS SPONSORED MEETINGS2005 ISSCC International Solid-State Circuits Conferencewww.isscc.org6–10 February 2005 San Francisco Marriott Hotel, SanFrancisco, CA, USAPaper deadline: passedContact: Courtesy Associates,ISSCC@courtesyassoc.com

2005 Symposium on VLSI Circuitswww.vlsisymposium.org16–18 June 2005Kyoto, JapanPaper deadline: 7 January 2005 Contact: Phyllis Mahoney,vlsi@vlsisymposium.orgor Business Center for Academic Soci-eties, Japan,vlsisymp@bcasj.or.jp

2005 CICC Custom Integrated Cir-cuits Conferencewww.ieee-cicc.org18–21 October 2005San Jose, CA, USAPaper deadline: awaitingContact: Ms. Melissa Widerkehr,cicc@his.com

2005 A-SSCC Asia Solid-State Cir-cuits Conference (the first meeting)a-sscc.org/1–3 November 2005TaiwanPaper deadline: 31 May 2005Contact: org@a-sscc.ee.ntu.edu.tw

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP VLSI-TSA International Symposiumon VLSI Technologyvlsitsa.itri.org.tw25–27 April 2005Hsinchu, TaiwanPaper deadline: passed

2005 International Conference onVLSI Design www.isical.ac.in/~vlsi2005 3–7 June 2005Taj Bengal, Kolkata, IndiaPaper deadline: passed

2005 Radio Frequency IntegratedCircuits Symposium www.rfic2005.org12–14 June 2005Long Beach, CA, USAPaper deadline: 3 January 2005

2005 Design Automation Conferencewww.dac.com13–17 June 2005Anaheim, CA, USAPaper deadline: passed

2005 Symposium on VLSI Technology www.vlsisymposium.org14–16 June 2005 Kyoto, JapanPaper deadline: 7 January 2005

2005 European Solid-State CircuitsConferencewww.esscirc2005.org/12–16 September 2005Grenoble, FrancePaper deadline: 9 April 2005

2005 International Conference onComputer-Aided Design www.iccad.org6–10 November 2005San Jose, CA, USA Paper deadline: 20 April 2005

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER (ISSN 1098-4232) is publishedquarterly by the Solid-State Circuits Society of The Institute of Electrical and Electronics Engi-neers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 permember per year (included in society fee) for each member of the Solid-State Circuits Soci-ety. This newsletter is printed in the U.S.A. Periodicals postage paid at New York, NY andat additional mailing offices. Postmaster: Send address changes to IEEE Solid-State CircuitsSociety Newsletter, IEEE, 445 Hoes Lane, Piscataway, NJ 08854. ©2005 IEEE. Permission tocopy without fee all or part of any material without a copyright notice is granted providedthat the copies are not made or distributed for direct commercial advantage and the title ofpublication and its date appear on each copy. To copy material with a copyright noticerequires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man-ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.