introduction to vhdl programming
TRANSCRIPT
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Dr. Y. NARASIMHA MURTHY Ph.D.,
Sri Saibaba National College (Autonomous)
ANANTAPUR-515001-A.P
INTRODUCTION TO VHDL
&BEHAVIOURAL MODELLING
(During the TWO day workshop on VHDL Technology
at Loyola Academy , Alwal ,Hyderabad On 7-02-2013)
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HDL ? ??
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PROLOGUE
In early years the digital circuits were designedmanually using the techniques such as Booleanexpressions , circuit schematics , Karnaughmaps etc .Most of the people used schematicbased soft wares like p spice , h spice etc.
With the increasing device densities the choiceof this traditional methods has become
limited. Because it is a known fact that theschematics with more than 600 gates areincomprehensible.
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Contd..
So , it is unimaginable to think how manyman-years would be required to design the
modern chips which contains millions of
transistors .
It is a must for IC designers to go for some
EDA tool.
So, the electronic design Automation (EDA)tool made the multimillion IC design simple
and possible.
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Contd..
With the increasing use of computer based
design methodologies ,the IC design hasmigrated to EDA tools.
One such outcome of these EDA tools is the
HDL (Hardware Description Language).
This HDL resembles a general programming
language like C, but is specifically oriented
to describing hardware structures andbehaviors. The most common use of a HDL is
to provide an alternative to schematics
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Is HDL so indispensable???
O.K. Lets discuss it .
For illustration , let us design ,a 16 x 16multiplier with schematic capture andusing the HDL.
The multiplier is a complex arrangementof adders and registers . In the presentcase we have two 16 bit inputs and one
32-bit product output .So , a total of 64I/O s. Approximately the circuit requires6000 equivalent gates.
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Contd..
So , in the schematic implementation ,all the
required gates have to be loaded, positionedon the page , interconnected and I/O buffersshould be added . This will take at least 3
days of hard time . But the HDL implementation ,which also
need 6000 gates, requires 8-lines of text andcan be done happily in 3 minutes . This filewill have all the information required todefine the 16 x 16 multiplier.
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Simple Code Entity MULT is
port (A,B: in std _ logic(15 down to 0);
Y:out std_logic (31 down to 0);
end MULT;architecture Behav of MULT is
begin
Y
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Contd..
So, the HDL implementation has All the 6000 gates
Only 1 text file
3 minutes to write
Completely vendor independent ..
Do you accept the importance of the using a
HDL in digital circuit design ??
( source : Xilix Website)
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Types of HDLs
There are two standard HDL s that aresupported by IEEE.
One is VHDL and the other is
Verilog
HDL whichoriginated in 1983at Gateway Design Automation
Both Verilog and VHDL simulators gainedthe acceptance of the designers soon tosimulate large digital circuits quickly.
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WHAT IS VHDL ??....
Is it
VERY
HARD
DIFFICULT
LANGUAGE??????.....
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Contd..
I think most of the students at the first instance
feel like this
But , is it true ???
No !! Not at All
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VHDL is an acronym of
V : Very High Speed IntegratedCircuit
H : Hardware
D : DescriptionL: Language
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Contd
A Language developed to describe thecomplex digital circuits.
It is a C like language that supports wide
range of description styles(Structuraldescription, data flow description ,
behavioral description and mixed
description )
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FLASH BACK
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Genesis of VHDL During 1980s ,the rapid advances in
integrated circuit technology provokedthe idea of developing a standard design
procedure for digital circuits .
The VHSIC Program launched in 1980,was an initiative of the Defense
Department of US to push the state of the
art in VLSI technology, and VHDL wasproposed as a versatile hardware
description language
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Contd
Woods Hole Workshop Held in June 1981 in
Massachusetts.
In July 1983, a team of Intermetrics , IBM and
Texas Instruments were awarded a contract todevelop VHDL
In August 1985, the final version of the language
under government contract was released: VHDL
Version 7.2
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Contd In December 1987, VHDL became IEEE
Standard 1076-1987 and in 1988 anANSI standard
In September 1993, VHDL was re
standardized to clarify and enhance thelanguage (IEEE Standard 1076-1993)
VHDL has been accepted as a DraftInternational Standard by the IEC(International Engineering Consortium)
VHDL 1993, 1997, 2000, 2002
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DESIGN FLOW
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VHDL -TERMS
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SPECIALITIES
VHDL allows the designer to work atvarious level of abstraction:
behavioural; RTL;
boolean equations and
gates.
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Contd..
Allows for various design methodologies : top-down, bottom-up, delay of detail.
very flexible in its approach to describing
hardware.
Provides technology independence
VHDL is independent of any technologyor process (ASIC,FPGA)
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VHDL PORTABILITY
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Format
VHDL is a free format language . No formatting
conventions, such as spacing or indentationimposed by VHDL compilers. Space and carriagereturn treated the same way.
Example:if (a=b) thenor
if (a=b) then
or
if (a =
b) then
are all equivalent
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Contd
Because VHDL is a standard, VHDL
design descriptions are device
independent, allowing the designer to
easily benchmark design performance in
multiple device architectures. The same
code used for designing with
programmable logic can be used by an
ASIC vendor to produce an ASIC when
production volumes warrant a
conversion.
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Contd VHDL is a well suited language for designing
with programmable logic, and it is gaining inpopularity. Designing with larger capacityCPLDs (complex programmable logicdevices)and FPGAs (field programmable gatearrays) of 600 gates to 20K gates.
VHDL delivers portability of code betweensynthesis and simulation tools, device
independent design, and easy ASIC migration.VHDL is an open, standard language, not aproprietary language.
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VHDL PROGRAMMING
Let us now understand the basics ofwriting a VHDL program for a digital
circuit. For this let us consider the
Fundamental sections of a basic VHDLcode.
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Fundamental sections of a basic VHDL code.
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Contd..
Every piece of VHDL code is composed of
at least three fundamental sections LIBRARY declarations: Contains a list of
all libraries to be used in the design.
ENTITY: Specifies the I/O pins of thecircuit.
ARCHITECTURE: Contains the VHDL
code which describes how the circuitshould behave (function).
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A VHDL code for the full adderFull-adder Schematic
Simulation results from the VHDL design
Example code - VHDL
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LIBRARY
A LIBRARY is acollection of commonly
used pieces of code.
Placing such pieces inside
a library allows them to bereused or shared by other
designs.
The typical structure of a
library is shown aside.
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Library Declarations
To declare a LIBRARY (that is, to make it
visible to the design) two lines of code are
needed, one containing the name of the
library, and the other a use clause.
The syntax is as follows
LIBRARY library_name ;
USElibrary_name.package_name.package_parts ;
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Contd..
At least three packages, from three
different libraries, are usually needed in a
design :
ieee.std_logic_1164(from the ieee library), standard (from the std library) , and
work (work library)
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Library Declarations
LIBRARY ieee; --A semi-colon (;) indicates the end of a
statement or a declaration
USE ieee.std_logic_1164.all ;
LIBRARY std ; - a double dash (--) indicates a
comment. USE std . Standard . all ;
LIBRARY work ;
USE work. all;
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Contd..
The std_logic_1164 package of the ieee
library specifies a multi-level logic
system; std is a resource library (data
types, text i/o, etc.) for the VHDL designenvironment; and the work library is
where we save our design (the .vhd file,
plus all files created by the compiler,simulator, etc.).
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STD_LOGIC typeValue Meaning
U UninitializedX Forcing (Strong driven) Unknown
0 Forcing (Strong driven) 0
1 Forcing (Strong driven) 1
Z High Impedance
W Weak (Weakly driven) Unknown
LWeak (Weakly driven) 0.
Models a pull down.
HWeak (Weakly driven) 1.
Models a pull up.
- Don't Care
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ENTITY
An ENTITY is a list with specifications of
all input and output pins (PORTS) of thecircuit with the following syntax.
ENTITY entity_name IS
PORT (
port_ name : signal_mode signal_type ;
port_ name : signal_mode signal_type ;
... );
END entity_name ;
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Contd.. The mode of the signal can be IN, OUT,
INOUT, or BUFFER . IN and OUT are truly unidirectional pins,
while INOUT is bidirectional.
BUFFER, on the other hand, is employedwhen the output signal must be used
(read) internally.
The name of the entity can be basicallyany name, except VHDL reserved words
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Example Entity
ENTITY nand_ gate ISPORT (a, b : IN BIT;
x : OUT BIT);
END nand_gate;
RC C R
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ARCHITECTURE
The ARCHITECTURE denotes the
description of how the circuit should behaveor function . The syntax is as below.
ARCHITECTURE architecture_name OF
entity_name IS [declarations]BEGIN
(code)
END architecture_name ;
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Contd..
So, an architecture has two parts : a
declarative part (optional), where signals
and constants (among others) are
declared, and the code part (from BEGINdown).
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Example -Architecture
ARCHITECTURE my arch OF nand_ gate IS
BEGINx
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Contd..
It is a known fact that the VHDL
representation is a text file describing adigital system, the digital system can be
represented in different levels of
abstractions such as a behavioral model
or a structural model or a mixed model.
These levels of abstraction help the
designer to develop any complex digital
system efficiently.
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Contd..
Behavioral level describes the system, the
way it behaves and describes the
relationship between the input and output
signals. The description can be a Register
Transfer Level (RTL) or Algorithmic (set
of instruction) or simple Booleanequations.
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Contd..
RTL typically represents data flow withinthe systems like data flow between
registers. RTL is mostly used for design
of combinational logics.
In the algorithmic level , specific
instruction set of statements define the
sequence of operations in the system.
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Contd..
Algorithmic level is mostly used for
design of sequential logics. The Structural
level describes the digital system as gates
or as component blocks interconnected to
perform the desired operations. Structural
level is primarily the graphical
representation of the digital system and soit is closer to the actual physical
representation of the system.
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Concurrent versus Sequential
VHDL code is inherently concurrent
(parallel). Only statements placed inside a
PROCESS, FUNCTION, or
PROCEDURE are sequential.
Though within these blocks the execution
is sequential, the block, as a whole, is
concurrent with any other (external)statements. Concurrent code is also called
data flow code.
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Concurrent code
In concurrent code the following can beused :
Operators
The WHEN statement (WHEN/ELSE orWITH/SELECT/WHEN)
The GENERATE statement
The BLOCK statement.
O t
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Operators
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Multiplexer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN
STD_LOGIC;
y : OUT STD_LOGIC);
END mux; ARCHITECTURE pure_logic OF mux IS
BEGIN
y
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WHEN (Simple and Selected) LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux; ARCHITECTURE mux1 OF mux IS
BEGIN
y
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Alternative LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN INTEGER RANGE 0 TO 3;
y: OUT STD_LOGIC);
END mux; ARCHITECTURE mux1 OF mux IS
BEGIN
y
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Tri-state Buffer LIBRARY ieee;
USE ieee.std_logic_1164.all; ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END tri_state;
ARCHITECTURE tri_state OF tri_state IS
BEGIN
output 'Z'); END tri_state;
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Sequential Code
PROCESSES,FUNCTIONS, and PROCEDURES are
the only sections of code that are executed
sequentially.
One important aspect of sequential code is that
it is not limited to sequential logic. With it wecan build sequential circuits as well as
combinational circuits.
Sequential code is also called behavioral code.
S ti l St t t
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Sequential Statements
PROCESS
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PROCESS
A PROCESS is a sequential section of VHDL
code. It is characterized by the presence of IF,WAIT, CASE, or LOOP, and by a sensitivity
list (except when WAIT is used).
A PROCESS must be installed in the main
code, and is executed every time a signal in the
sensitivity list changes (or the condition relatedto WAIT is fulfilled).
S t
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Syntax
PROCESS (sensitivity list)
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)
END PROCESS [label];
D-type flip-flop
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D-type flip-flop LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
q
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DFF- ALTERNATIVE
LIBRARY ieee;
USE
ieee.std_logic_1164.all;
ENTITY dff IS
PORT (d, clk, rst: INSTD_LOGIC;
q: OUT STD_LOGIC);
END dff; ARCHITECTURE dff
OF dff IS
BEGIN
PROCESSBEGIN
WAIT ON rst, clk;
IF (rst='1') THEN
q
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CASE
CASE is another statement intendedexclusively for sequential code.
CASE identifier IS
WHEN value => assignments ; WHEN value => assignments ;
...
END CASE;
E l
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Example
CASE control IS
WHEN "00" => x
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VHDL- CODE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
STD_LOGIC
ENTITY dff IS
PORT (d, clk, rst: IN BIT; q: OUT BIT);
END dff;
ARCHITECTURE dff3 OF
dff IS
BEGIN
WHEN '1' => q
IF (clk'EVENT ANDclk='1') THEN
q NULL;
END CASE;
END PROCESS;
END dff3;
PROCESS (clk, rst)
BEGIN
CASE rst IS
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Conclusions Design entry is more efficient at the behavioral
level than at the register transfer level for a
number of reasons. The behavioral model
flows from the original algorithm
specification; thus, model generation is a lesscomplex and faster process than RTL model
generation. In addition, changes in the
algorithm are also easier to incorporate in abehavioral model.
Contd
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Contd.. The Behavioral VHDL module describes
features of the language that describe thebehavior of components in response to signals.
Behavioral descriptions of hardware utilize
software engineering practices and constructsto achieve a functional model. Timing
information is not necessary in a behavioral
description, although such information may be
included easily.
REFERENCES
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REFERENCES
During the preparation of this lecture Ihave collected the information from many
books and resources. The following is the
list books and resources ,which inspired
me and helped me to overcome myignorance to some extent .
1. Circuit Design with VHDL- Volnei A. Pedroni,
the finest resource which no learner can hardlymiss.
Contd
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Contd
2.Fundamentals of Digital Logic with VHDLdesignStephen Brown. Most elaboratelywritten book.
3.Digital Design with VHDLBenjamin
Abramov 4.VHDL TutorialPeter J.Ashenden.
5.www.xilinx.com
6. Principles of Modern Digital Design -Parag K. Lala.
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A Big.
THANQ FOR
YOUR
PATIENCE