introduction to vhdl

V.D. Maheta EC 529 1

VHDLDr. Vrajesh. D. Maheta

Department of Electronics & CommunicationG. H. Patel College of Engineering &

Technology

[email protected]


Introduction to VHDL

Hardware Description Language (HDL)High-level language to model, simulate, and synthesize digital circuits and systems.

History1980: US Department of Defense Very High Speed Integrated Circuit program (VHSIC)1987: Institute of Electrical and Electronics Engineers approvesIEEE Standard 1076 (VHDL’87) 1993: VHDL language was revised and updated

Verilog is the other major HDLSyntax similar to C language

VHDL is mostly used for FPGA design

Many tools accept both Verilog and VHDL


VHDL strengths and limitations

Strengths:Power and Flexibility: supports design libraries and the creation of reusable components. It can be used for design and simulation.

Device-Independent Design: design can be created without being familiar with a device’s architecture. Also the use of multiple styles of design description is allowed.

Benchmarking Capabilities: different device architecture and synthesis tools can be used, then evaluate the results and choose the device that is the best.

Quick Time-to-Market and Low Cost: Programmable logic eliminates the expenses and facilitates quick design iterations.


VDHL strengths and limitations

Limitations:Does not always produce optimal (or even synthesizable) implementation

Inefficient code can result in unneeded, repetitive, or sub-optimal logic.


Architecture of Digital Systems

A system is defined by its behaviour

relates inputs to outputscombinational

• function table (truth table)

• mathematical expressions

sequential• algorithmic rules

Inputs Outputsdigital

system


Design Units

Design units in VHDL:Entity Declaration

Architecture Body

Configuration Declaration

Package Declaration

Package Body


VHDL Entities and Architecture

Every VHDL design description has one Entity/Architecture pair.

Entitydescribes circuit as it appears from outside

Architecturedescribes function (contents)of entitycan be numerous alternative arch’s

ENTITY

alternative architecture #1

alternative architecture #2

etc..


VHDL Entities and Architecture

Package

Entity

Architecture(structural)ArchitectureArchitecture

Concurrentstatement

Concurrentstatement Architectureprocess

Sequentialstatement

Generic Ports


Terminology

Dataflow modelingDescribes the functionality of a component/system as a set of concurrent signal assignment statements

Behavioral modelingDescribes the functionality of a component/system as a set of sequential statements

Structural modelingA component is described by the interconnection of lower level components/primitives

Synthesis:Translating the HDL code into a circuit, which is then optimized

Register Transfer Level (RTL):Type of behavioral model used for instance for synthesis


Entity Declaration

Provides complete interface for circuitdefines I/O for connection and verification

syntax:entity identifier is

port ( port_interface_list );end identifier ;

BLACK_BOXrstd[7:0]clk

q[7:0]

co

-- eight bit comparator

entity compare isport (A, B : in bit_vector ( 7 downto 0 );

EQ : out bit );end compare;

List of inputs and outputs

Entity name

Port types

A[7:0]B[7:0]

EQcompare

Mode


Architecture declaration

Describes how circuit is implementedDescribes the internal operation of a moduleEvery entity must have at least one architecturesyntax:architecture identifier of entity_name is[Architecture –item-declarations]begin[statements];end identifier ;--eight bit comparator

architecture compare1 of compare isbegin

EQ ⇐ ‘1’ when ( A = B ) else ‘0’;end compare1;

A[7:0]

B[7:0]EQcompare1

Entityname

Declaration name

Functionaldescription

Assignmentoperator


Basic VHDL Language Elements-Ports

Used to define inputs and outputs of an entityThe means by which information is fed into and out of the circuitEach port defined by:

Name: specifies name of the portsDirection (mode): specifies whether information flows into or out from the entity through the portData type: specifies the kind of information that can be communicated

PORTS

PORTS

ENTITY


Port Modes

Describes direction of data transferPort in : data flows only into circuitPort out : data flows only out of circuitPort buffer : for internal feedback or driver NOT bidirectionalPort inout : bidirectional signal, allows internal feedback

In

In

In

Out

Buffer

Inout


Data Objects

They hold values of a specific type

They belong to one of four classes:Constants

Signals

Variables

Files


Constants

Hold a single value of a given type.Value cannot be changed during the course of simulationExample:

constant RISE_TIME:TIME:=10ns;constant BUS_WIDTH:INTEGER:=8;constant NO_OF_INPUTS: INTEGER --Deferred constant

Package my_pack isconstant NO_OF_INPUTS: INTEGER;end my_pack; Package body my_pack isconstant NO_OF_INPUTS: INTEGER:= 3; -- complete constant

declaration

end my_pack;


Variables

It can hold a single value of a given type

Different values can be assigned to the variable at different times using a variable assignment statement.

Variables can be declared and used only within a PROCESS, i.e. they cannot be used to communicate information between processes

Can be of any valid SIGNAL type

Examples: variable CTRL_STATUS: BIT_VECTOR(10 downto 0); variable SUM: INTEGER range O to 100 := 10; variable FOUND, DONE: BOOLEAN;


Signals

Holds a list of values, which include the current value of the signal and a set of possible future values that are to appear on the signal.

Future values can be assigned to a signal using a signal assignment.

Examples:signal CLOCK: BIT;signal DATA_BUS: BIT_VECTOR(0 to 7);signal GATE_DELAY: TIME := 10ns;


Initialization

At time zero in simulation all signals are given their initial value depending on which data type they are declared as.

Unless specified otherwise, all signals are given datatype’left (data type’s first value in the type declaration) value.

type bit is (‘0’, ‘1’); -- bit’left =‘0’type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); -- std_logic’left =‘U’

Default initial value can be changed by defining a particular value in the entity or signal declaration in the architecture

Several signals can be initialized to the same value in one line.Signal a, b: std_logic_vector (2 downto 0):= “001”;


VHDL Data Types

VHDL is a strongly typed language (you cannot assign a signal ofone type to the signal of another type)Different types can not be mixed without type conversion

bit - a signal of type bit that can only take values of '0' or '1'bit_vector - a grouping of bits (each can be '0' or '1')

SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending rangeSIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range

a <= "0111"; -- double quotes used for vectorsb <= "0101";

This means that: a(0) = '0' b(0) = '1'a(1) = '1' b(1) = '0'a(2) = '1' b(2) = '1'a(3) = '1' b(3) = '0‘


VHDL Data Types

A type is a name that has associated with it a set of values and a set of operations.


Sub types

It is a type with a constraint. The constraint specifies the subset of values for the type.

The set of operations belonging to a subtype is the same as thatassociated with its base type.

Subtypes are useful for range checking and for imposing additional constraints on types. Examples: subtype MY_INTEGER is INTEGER range 48 to 156 ;

type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ; subtype MIDDLE is DIGIT range '3' to '7' ;

subtype NUMBER is DIGIT;


Enumerated type

Defines a type that has a set of user-defined values consisting of identifiers and character literals. Order in which values appear in declaration defines their ordering

The values are called enumeration literals.Examples: Type MVL is ('U','0','1','Z’); type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL, DIV); subtype ARITH_OP is MICRO_OP range ADD to DIV; Some object declarations using these types aresignal CONTROL_A: MVL; signal CLOCK: MVL range '0' to '1'; -- Implicit subtype declaration.

variable IC: MICRO_OP := STORE; -- STORE is the initial value for IC.

variable ALU: ARITH_OP;


Predefined enumeration types

CHARACTER: 191 characters of the ISO 8-bit coded character setExamples: 'A', '_', '" (the single quote character itself), '3' (the character literal 3)

BIT: It has the literals '0' and 1‘.

BOOLEAN: It has the literals FALSE and TRUE.

SEVERITY_LEVEL: It has the values NOTE, WARNING, ERROR, and FAILURE.


IEEE Data Type

Make VHDL an effective platform and simulator independent.Std_ulogic – type which is declared in the ieee packageStd_logic is a resolved subtype of std_ulogic

Subtype std_logic is resolved std_ulogic;

Both assume exactly same values‘U’ – Uninitialized‘X’ – Forcing unknown‘0’ – Forcing 0‘1’ – Forcing 1‘Z’ – High impedance‘W’ – Weak unknown‘L’ – Weak 0‘H’ – Weak 1‘-’ – Don’t care


Resolved value

entity ex isport (a,b,e1,e2: in std_logic;dbus: out std_logic);end ex;Architecture rtl of ex isbegindbus<= a when e1=‘1’ else ‘Z’;dbus<= b when e2=‘1’ else ‘Z’;end rtl;

H

-

H

L

W

Z

1

0

X

U

-LWZ10XU


Integer type

It defines a type whose set of values fall within a specified integer range.

Examples: type INDEX is range 0 to 15; type WORD_LENGTH is range 31 downto 0; subtype DATA_WORD is WORD_LENGTH range 15 downto 0; type MY_WORD is range 4 to 6;

Some object declarations using these types are

constant MUX_ADDRESS: INDEX := 5; signal DATA_BUS: DATA_WORD;

Integer literals56349, 6E2, 0, 98_71_28


Real/Floating point type

It has a set of values in a given range of real numbers. Examples:type REAL_DATA is range 0.0 to 31.9;

An example of an object declaration is variable LENGTH: REAL_DATA range 0.0 to 15.9; variable LI, L2, L3: REAL_DATA range 0.0 to 15.9;

ORtype REAL_DATA is range 0.0 to 31.9;Subtype RD16 is REAL_DATA range 0.0 to 15.9;

variable LENGTH: RD16;

Floating point literals:16.26, 0.0, 0.002, 3_1.4_2, 62.3E-2,5.0E+2


Integer and floating point literals-base other than 10

Base can be any value between 2 and 16.

Such literals are called based literals.

Syntax:base # based-value # --form1

base # based-value # E exponent -- form 2

Examples:(i) 2#101_101_000# --represents (101101000)2 = (360) in decimal

(ii)16#FA# --represents (FA)16= (11111010)2 = (250) in decimal

(iii)16#E#E1 --represents (E)16* (16^1) = 14* 16= (224) in decimal

(iv) 2#110.01 # --represents (110.01)2 = (6.25) in decimal


Physical type

It contains values that represent measurement of some physical quantity, like time, length, voltage, and current.

Values of this type are expressed as integer multiples of a baseunit.

Predefined physical type is TIME; predefined physical subtype isdelay_length

Example:type CURRENT is range 0 to 1E9 units nA; -- (base unit) nano-ampere uA = 1000 nA; -- micro-ampere mA = 1000 μA; --milli-ampere Amp = 1000 mA; -- ampere end units;

subtype FILTER_CURRENT is CURRENT range 10 μA to 5 mA;


Composite type: Array type

It represents collection of values all belonging to a single type Examples:type ADDRESS_WORD is array (0 to 63) of BIT; type DATA_WORD is array (7 downto 0) of MVL; type ROM is array (0 to 125) of DATA_WORD; type DECODE_MATRIX is array (POSITIVE range 15 downto 1, NATURAL range 3 downto 0) of MVL;

Examples of object declarations using these types are variable ROM_ADDR: ROM; signal ADDRESS_BUS: ADDRESS_WORD;variable DECODER: DECODE_MATRIX;

--POSITIVE and NATURAL are predefined subtypes: subtype NATURAL is INTEGER range 0 to INTEGER'HIGH; subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;

type std_ulogic_vector is array (natural range < >) of std_ulogic;type std_logic_vector is array (natural range < >) of std_logic;


STRING and BIT_VECTOR

STRING: It is an array of charactersExample: variable MESSAGE: STRING(1 to 17) := "Hello, VHDL world";

BIT_VECTOR: It is an array of bits. Example:signal RX_BUS: BIT_VECTOR(0 to 5) := O"37";

A value representing a one-dimensional array of characters is called a string literal.

A string literal that represents a sequence of bits can also be represented as a bit string literal.

X”FFO" -- X for hexadecimal. B"00_0011_1101” --B for binary. O"327" -- O for octal.


Array Aggregate

It is a set of comma separated elements enclosed within parenthesis.

Example:variable OP_CODES : BIT_VECTOR(1 to 5); OP_CODES := ('0', '1', '0', '0', '1'); OP_CODES := (2=>'1', 5=>'1', others=>'0');

OP_CODES := (others=>'0'); -- All values set to '0'.

Others can be used to provide an initial value for an array object in its declaration

signal x: std_logic_vector(0 to 15) := (others=> ‘0’);constant y: std_logic_vector(2 downto 0):= “001”;


Record type

It represents a collection of values that may belong to same or different types. Example:

type PIN_TYPE is range 0 to 10; type MODULE is record SIZE: INTEGER range 20 to 200; CRITICAL_DLY: TIME; NO_INPUTS: PIN_TYPE: NO_OUTPUTS: PIN_TYPE; end record;

Values can be assigned to a record type object using aggregates.variable NAND_COMP: MODULE; NAND_COMP := (50, 20 ns, 3,2); NAND_COMP.NO_INPUTS := 2:


VHDL Operators

Logical: for BIT and BOOLEAN or 1-D array of BIT and BOOLEAN AND, NANDOR, NORXOR, XNORNOT

Relational: Result is always of type BOOLEAN= (equal to)/= (not equal to)< (less than)<= (less than or equal to)> (greater than)>= (greater than or equal to)


VHDL Operators

Shift:sll (shift left logical): fills the vacated bits with left-operand-type’left.

• “10010101” sll 2 is “01010100”srl (shift right logical): fills the vacated bits with left-operand-type’left.

• “10010101” srl 2 is “00100101”sla (shift left arithmetic): fills the vacated bits with the right most bit of the left operand

• “10010101” sla 2 is “01010111”sra (shift right arithmetic): fills the vacated bits with the left most bit of the left operand

• “10010101” sra 2 is “11100101”rol (rotate left): vacated bits to be filled with the displaced bits

• “10010101” rol 2 is “01010110”ror (rotate right): vacated bits to be filled with the displaced bits

• “10010101” ror 2 is “01100101”


VHDL Operators

Adding:+ (Addition)- (subtraction)& (Concatenation) : operand can be either 1-D array type or an elemental type; result is always an array type e.g. 'C' & 'A' & 'T' results in the value "CAT".Multiplying:* (Multiplication)/ (Division)mod (modulus): Result has the sign of its second operand

A mod B = A – B * N --For some integer N e.g. 7 mod (-4) --has value -1

rem (remainder): Result has the sign of its first operandA rem B = A - ( A / B ) * B e.g. (-7) rem 4 --has value -3


VHDL Operators

Miscellaneous: abs (Absolute): for any numeric type.

** (Exponential): for left operand to be of integer or floating point type and for the right operand to be of integer type only.


Semantics: Sequential & Concurrent Statements

There are two types of statementsSequential

• Statements within a process • Evaluated sequentially during simulation

Concurrent• Statements outside of a process• Processes are evaluated concurrently


Concurrent Statements

Concurrent statements include:Boolean equationsx <= (a AND (NOT sel1)) OR (b AND sel1);g <= NOT (y AND sel2);

conditional assignments (when/else, with/select)y <= d WHEN (sel1 = '1') ELSE c;h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE

'1';

Instantiationinst: nand2 PORT MAP (h, g, f);


Sequential statements: The Process

A VHDL construct used for grouping sequential statementsStatements are processed sequentially during simulationCan be either active or inactiveA Process typically has a SENSITIVITY LISTSyntax:[ process-label: ] process [ ( sensitivity-list ) ] [process-item-declarations] begin sequential-statements; these are -> variable-assignment-statement signal-assignment-statement wait-statement if-statement case-statement loop-statement null-statement exit-statement next-statement assertion-statement procedure-call-statement return-statement. end process [ process-label];


Variable Assignment Statement

The variable assignment statement is used to assign values to the variables, e.g. c := a AND b;The value assigned to a variable is available immediately

Example: signal A, Z: INTEGER; . . . PZ: process (A) --PZ is a label for the process. variable V1, V2: INTEGER; begin V1 := A - V2; --statement 1 Z <= - V1; --statement 2 V2 := Z+V1 * 2; -- statement 3 end process PZ;


Signal Assignment Statement

The signal assignment statement is used to assign values to the signals, e.g. c <= a AND b;

If it appears outside of a process - concurrent signal assignment statement. If it appears within a process - sequential signal assignment statement The value of the expression is computed and value is scheduled to be assigned to the signal after the specified delay.


Delta Delay

It is a infinitesimally small delay. Example:

signal A, Z: INTEGER; A <= in_1; --statement 1; Z <= A - 2; --statement 2;

ZAin_1

T+2ΔT+ΔT

Example: Variable A, Z: INTEGER; A := in_1; --statement 1; Z := A - 2; --statement 2;

ZAin_1

T+2ΔT+ΔT

An event always occurs at a real simulation time plus an integral multiple of delta delays.


Wait statement

It provides an alternate way to suspend the execution of a processThere are three basic forms of the wait statement. (i) Wait on: It causes the process to suspend and waits for an event to occur on signals wait on sensitivity-list; -- e.g. wait on A, B, C is identical to process

(a, b, c) if former is placed at the end of process.(ii) Wait until: It causes the process to suspend until the specified condition becomes truewait until boolean-expression; -- e.g. wait until (A=B);

wait until clk = ‘1’;(iii) Wait for: It causes the process to suspend for specified timewait for time-expression ; --e.g. wait for 10ns;

They may also be combined in a single wait statement.wait on sensitivity-list until boolean-expression for time-expression; e.g. wait on CLOCK for 20ns;

wait until (SUM > 100) for 50 ms;


Wait for-statement

Example 1:processbegin

wait for 10 ns;sum1<= sum1+1;sum2<=sum1+1;

end process;

30+Δ30

20+Δ20

10+Δ100

sum2sum1Time

Example 2:processbegin

wait for 10 ns;sum1:= sum1+1;sum2:=sum1+1;

end process;

30+Δ30

20+Δ20

10+Δ100

sum2sum1Time

Once the process has started it takes the time delta t for it to be moved back to waiting state.


Wait for 0 ns

Wait for 0 ns; --wait for one delta delaye.g.

20+Δ

zyxa

20+2Δ2010+2Δ10+Δ10

Processbeginwait on a;x<= a;z<=x;end process;

Processbeginwait on a;x<= a;wait for 0 ns; y<=x;end process;


If statement

It selects a sequence of statements for execution based on the value of a condition. Syntax: if boolean-expression then sequential-statements [ elsif boolean-expression then -- elsif clause; if stmt can have 0 or

sequential-statements ] -- more elsif clauses. [ else -- else clause. sequential-statements ] end if;

e.g.if sel = ‘1’ then

c<=b;else

c<=a;end if;


Case statement

The case statement selects one of the branches for execution based on the value of the expression. Syntax:case expression is when choices => sequential-statements -- branch #1 when choices => sequential-statements -- branch #2 -- Can have any number of branches. [ when others => sequential-statements ] -- last branch end case; e.g. case sel iswhen ‘0’ => c <= a;when ‘1’ => c <=b; end case;

Entity ex isPort ( a: in integer range 0 to 30;

q: out integer range 0 to 6);end ex;

-- process (a)begincase a isWhen 0 to 17 => q<=2;when others => q<=0;end case;end process;


Null & loop statement

Null: It does not cause any action to take place and execution continues with the next statement. “ do nothing”Loop: It is used to iterate through a set of sequential statements. Syntax:[ loop-label : ] iteration-scheme loop

sequential-statements end loop [ loop-label ] ;

(i) for iteration scheme: for identifier in range loope.g. FACTORIAL := 1;

for NUMBER in 2 to N loop FACTORIAL := FACTORIAL * NUMBER; end loop;


Loop statement

(ii) while iteration scheme: while boolean-expression loope.g. J:=0;SUM:=10;

while J < 20 loopSUM := SUM * 2; J:=J+3; end loop;

(iii) without any specific iteration scheme: loop is exited by an exit statement, a next statement, or a return statement.

e.g. SUM:=1;J:=0; L2: loop -- This loop also has a label. J:=J+21; SUM := SUM* 10; exit when SUM > 100; end loop L2;


Exit statement

It causes execution to jump out of the innermost loop or the loop whose label is specified. Syntax:exit [ loop-label] [ when condition ]:

e.g. SUM := 1; J := 0; L3: loop J:=J+21; SUM := SUM* 10; if (SUM > 100) then exit L3; -- "exit;" also would have been sufficient. end if; end loop L3;


Next statement

It results in skipping the remaining statements in the current iteration of the specified loop and execution resumes with the first statement in the next iteration of this loop.

Syntax:next [loop-label] [when condition ]; e.g. for J in 10 downto 5 loop

if (SUM < TOTAL_SUM) then SUM := SUM +2;

elsif (SUM = TOTAL_SUM) then next;

else null;

end if; K:=K+1;

end loop;


Assertion statement

It is useful in modeling constraints of an entity. Syntax:assert boolean-expression [ report string-expression ] [ severity expression ]; If the value of the boolean expression is false, the report message is printed along with the severity level. The expression in the severity clause must generate a value of type SEVERITY_LEVEL The default severity level is ERROR if the severity clause is not specifiede.g. assert (DATA <= 255)

report "Data out of range.'; assert (CLK = '0') or (CLK = '1'); --CLK is of type ('X', '0', 'I ', 'Z')

-- Assertion violation


Report Statement

It can be used to display a message.Syntax:

report string-expression[severity expression];

The expression in the severity clause must be of the predefined type SEVERTTY_LEVEL.The default severity level is NOTE if the severity clause is notspecified.

e.g. if x = ‘Z’ thenreport “ signal x has a high impedance value.”;end if;


Delay models- Inertial delay model

It models the delays often found in switching circuits. It represents the time for which an input value must be stable for a specified pulse rejection limit duration before the value is allowed to propagate to the output.The value appears at the output after the specified inertial delay. If no pulse rejection limit is specified, the default limit is the inertial delay itself. pulse rejection limit can not be negative or greater than the value of the inertial delay.It is the default delay modele.g. Z <= reject 4 ns inertial A after 10 ns;


Delay models- Transport delay model

It models the delays in hardware that do not exhibit any inertial delay. Any changes on an input is transported to the output, no matter how small, after the specified delay.Routing delays can be modeled using transport delay.e.g. Z <= transport A after 10 ns;


Signal Assignment in Processes: Incorrect Solution

ARCHITECTURE archmux2ltch OF mux2ltch ISSIGNAL c: std_logic;

BEGINmux: PROCESS (a,b,s,en)BEGIN

IF s = '0' THEN c <= a; ELSE c <= b;END IF;x <= (x AND (NOT en)) OR (c AND en);

END PROCESS mux; -- c is updated here!END archmux2ltch;

x

s

a

b

en

c

Desired Circuit


Signal Assignment in Processes: correct Solution

ARCHITECTURE archmux2ltch OF mux2ltch ISSIGNAL c: std_logic;

BEGINmux: PROCESS (a, b, s)BEGIN

IF s = '0' THEN c <= a;ELSE c <= b;END IF;

END PROCESS mux; -- c is updated here!x <= (x AND (NOT en)) OR (c AND en);

END archmux2ltch;


Latches and flip-flops

-- LatchProcess (en,din)begin

if enable =‘1’ thenq<= din;end if;end process;

-- flip-flopProcessbegin

wait until clk=‘1’If en=‘1’ then q<= din;end if;end process;

-- flip-flopProcessbegin

wait until clk=‘1’q<= din;end process;

en

qq0

qbd

clk

1d

clk

S

All logic caused by a signal assignment in a clocked processwill end up on the “left” of the flip-flops

All the signals assigned inside the processresulting in a flip-flop.


Flip-flops with synchronous & asynchronous reset

Process (clk,reset)beginif reset=‘1’ thenq<=‘0’;elsif clk’event and clk=‘1’ thenq<=din;end if;end process;

Process (clk)beginif clk’event and clk=‘1’ thenif reset=‘1’ thenq<=‘0’;elseq<=din;end if;end if;end process;


Data flow Modeling

It specifies the functionality of the entity without explicitly specifying its structure.

This functionality shows the flow of information through the entity.

example: entity OR2 is port (A, B: in BIT; Z: out BIT); end OR2; architecture OR2 of OR2 is begin Z <= A or B after 9 ns; end OR2;


Conditional Signal Assignment Statement

It selects different values for the target signal based on the specified, possibly different, conditions Syntax: Target - signal <= [ waveform-elements when condition else ] [ waveform-elements when condition else ] . . . waveform-elements;

Example: Z <= IN0 when S0 = '0' and S1 = '0' else IN1 when S0 = '1' and S1 = '0' else IN2 when S0 = '0' and S1 = '1' else IN3;


Equivalent process statement

process begin if S0 = '0' and S1 = '0' then Z<= IN0; elsif S0='1'and S1='0' then Z<= IN1; elsif S0='0' and S1 = '1' then Z<= IN2; else Z<= IN3; end if; wait on IN0, IN1, IN2, IN3, S0, S1; end process;


Selected Signal Assignment

It selects different values for a target signal based on the value of a select expression Syntax:with expression select —This is the select expression. target-signal <= waveform-elements when choices,

waveform-elements when choices, …waveform-elements when choices ;

Example: with s select Z <= IN0 when “00”,

IN1 when “01”,IN2 when “10”,IN3 when others;

process begin case s is when “00” => Z <= IN0; when “01” => Z <=IN1; when “10” => Z <= IN2; when others => Z <= IN3; end case; wait on s, IN0, IN1, IN2, IN3; end process;


Unaffected statement

It causes no change to the driver for the target signal.Example:with s select Z <= IN0 when “00”,

IN1 when “01”,IN2 when “10”,IN3 when “11”,unaffected when others;

process begin case s is when “00” => Z <= IN0; when “01” => Z <=IN1; when “10” => Z <= IN2; when “11” => Z <= IN3;when others => null; end case; wait on s, IN0, IN1, IN2, IN3; end process;


Concurrent Assertion Statement

If Assertion Statement appears within a process, it is a sequential assertion statement and is executed sequentially with respect tothe other statements in the processIf it appears outside of a process, it is a concurrent assertionstatement. Syntax: assert boolean-expression [ report string-expression ] [ severity expression ]; Example:entity SR is port (S, R: in BIT; Q, NOTQ: out BIT); end SR; architecture SR_ASSERT of SR is begin assert (not(S = '0' and R = '0')) report "Not valid inputs: R and S are both low" severity ERROR; -- Rest of model for SR flip-flop here. end SR_ASSERT;


Structural Modeling

An entity is modeled as a set of components connected by signals, that is, as a netlist. entity mux is port (d0,d1,sel: in std_logic; q: out std_logic); end mux; architecture STRUCT_mux of mux is component AND2 -- component declarationport (X, Y: in std_logic; Z: out std_logic); end component; component OR2 port (A, B: in std_logic; Z: out std_logic); end component; component INV port (A: in std_logic; Z: out std_logic); end component; signal i1, i2, sel_n: std_logic; begin U1: INV port map (sel,sel_n); U2 : AND2 port map (d0,sel,i1); U3 : AND2 port map (sel_n,d1,i2); U3 : OR2 port map (i1,i2,q); end STRUCT_mux;

-- component specification

for U1: INV use entity work.INV(rtl);

for U2,U3: AND2 use entitywork.AND2(rtl);

for U4: OR2 use entity work.OR2(rtl);


Component Declaration

It declares the name and the interface of a component. Syntax:component component-name port (list-of-interface-ports ) ; end component; Example:component AND2 port (X, Y: in std_logic; Z: out std_logic); end component;

It may also appear in a package declaration.

package COMP_LIST is component AND2 port (X, Y: in BIT: Z: out BIT): end component; end COMP_LIST; library DES_LIB; use DES_LIB.COMP_LIST.all;architecture STRUCT of GATING is signal S1, S2: BIT; -- No need for specifying component declarations begin


Component Specification

It is used to choose which library the component is to be compiled in and which architecture is to be simulatedSyntax:For [label]: [component_name] use entity[library].[entity_name]([architecture_name]);

Example:for U1: INV use entity work.INV(rtl);


Component Instantiation

It defines a subcomponent of the entity in which it appearsIt associates the signals in the entity with the ports of that subcomponent.

Syntax: component-label: component-name port map (association-list);

The association-list associates signals in the entity, called actuals, with the ports of a component, called locals.

There are two ways to perform the association of locals with actuals: (i) positional association, (ii) named association.


Positional Association

Each actual in the component instantiation is mapped by positionwith each port in the component declaration.Example:component OR2 –component declarationport (A, B: in std_logic; Z: out std_logic); end component;U3 : OR2 port map (i1,i2,q); –component instantiationIf output port in a component instantiation is not connected, the keyword open can be used to signify that the port is not connected.U3 : OR2 port map (i1,i2, open);An input port may be left open only if its declaration specifies an initial value.

Signal gnd: std_logic;Begingnd<=‘0’;U2: AND2 port map (gnd, sel,i1); end;


Named Association

Each actual in the component instantiation is mapped by name with each port in the component declaration.The ordering of the associations is not important since the mapping between the actuals and locals are explicitly specified. Example:U1: OR2 port map (B=>i2, Z=>q, A=>i1); Rules:

(i) The types of the local and the actual being associated must be the same.

(ii) The modes of the ports must conform to the rule that if the local is readable, so must the actual and if the local is writable, so must the actual.


Half Adder

library ieee;use ieee.std_logic_1164.all;entity halfadder_struct is

port(a,b : in bit;sum, carry : out bit);

end entity;architecture arch of halfadder_struct iscomponent xor_2

port(m,n : in bit;o : out bit);

end component;component and_2

port(x,y : in bit;z : out bit);

end component;beginX2: xor_2 port map (a,b,sum);Y1: and_2 port map (a,b,carry);end arch;

XOR_2 :library ieee;use ieee.std_logic_1164.all;entity xor_2 is

port(m,n : in bit;o : out bit);

end entity; architecture arch_xor2 of xor_2 isbegino <= m xor n;end arch_xor2;

AND_2:library ieee;use ieee.std_logic_1164.all;entity and_2 is

port(x,y : in bit;z : out bit);

end entity; architecture arch_and2 of and_2 isbeginz <= x and y;end arch_and2;

introduction to vhdl

Documents

maheta ec

port port

architecture syntax

entity identifier

outside architecture

devices architecture

comparatormode entity

different device architecture