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Spring 2015 :: CSE 502 – Computer Architecture Introduction Instructor: Nima Honarmand

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Page 1: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Introduction

Instructor: Nima Honarmand

Page 2: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

CSE 502 - CompArch• Computer Architecture is

… the science and art of selecting (or designing)and interconnecting hardware and softwarecomponents to create computers …

• Computer Architecture is an umbrella term– Architecture: software-visible interface

– Micro-architecture: internal organization of components

• This course is mostly about micro-architecture– What’s inside the processor (CPU)

– What implications this has on software

Page 3: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

CSE 502 - CompArch• This course is roughly like CSE 506

– In CSE 506, you learn what’s inside an OS

– In CSE 502, you learn what’s inside a CPU

• This is a project-intensive course– Learn why things are the way they are, first hand

– We will “build” emulators of CPU components

Page 4: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Why Study CompArch?• You need one more qualifier/graduation requirementBad answer!

• You want to learn what’s inside a processor– Cause you’re curios (and there is no computer w/o a processor)– To write better/faster application code– To write system software (OS, compiler, etc.)

• You want to become a computer architect• Computer architecture is cool and intellectually fascinating

– BTW, what is the most complex man-made device?– Hint: there are billions of individually designed and verified

transistors in a modern processor chip

More like it!

Page 5: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Why Study CompArch?

24,129

Page 6: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Why Study CompArch?Sources of performance improvement:

• Improvements in semi-conductor technology– Faster transistors

– More transistors

• Improvements in computer architecture– Computer architects work to turn the additional

resources into speed/power savings/functionality!

In this class, we will study some of the cool techniques invented by computer architects to make this possible!

Page 7: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Moore’s Law• 1st Moore’s Law (1965)

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase.”

• 2nd Moore’s Law (1975)“The new slope might approximate a doubling every two years, rather than every year”

• Nowadays, Moore’s law is a general term for any exponential change in technology (with different slopes)

– E.g., transistor size, transistor speed, processor performance, etc.

Page 8: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Course Topics• Instruction Decode

• Pipelining

• Processor Front-end

• Execution Core

• Memory Hierarchy

• Multi-[socket(SMP,DSM)|thread(SMT,CMT)|core(CMP)]

• Vector Processing and GPUs

Page 9: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Hardware Design Process

Conceptual Design Behavioral Implementation Evaluation

Structural ImplementationLayoutManufacturingPackaging

Page 10: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

GradingWhat? Points

1 Quiz 0

1-2 Homeworks 10

Course Project Up to 110

Midterm 15

Final 25

Participation 10

• 95 pts: Guaranteed A-

• 100 pts: Guaranteed A

Course Project Points

5-Stage pipeline + direct-mapped $ 40

5-Stage pipeline + set-associative $ 50

Above + super-scalar pipeline 60

Above + out-of-order execution 80

Above + branch prediction and speculative execution

90

SMT on top of any of the above 10 extra

Successful synthesis to FPGA on top of any of the above

10 extra

Page 11: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Course Project• Goal: design a super-scalar, out-of-order SPARCv8

processor

• We’ll use SystemVerilog HDL for implementation– Don’t panic! We’ll cover the necessary background

– Hopefully, will help you think and design like a HW designer

• I’ll provide a cross-compiler and a simulation environment

– You’ll design and implement the processor

– See course webpage for details

Page 12: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Logistics (1/3)• Project milestones

– There are no official project milestones– If you need milestones, send me a milestone schedule

• I will deduct 5 points for each milestone you miss

• Books– Recommended for reference, not required

• Does not mean you shouldn’t get them• Do not pirate books

– Modern Processor Design: Fundamentals of Superscalar Processors

– Computer Architecture: A Quantitative Approach (H&P)– Computer Organization and Embedded Systems

Page 13: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Logistics (2/3)• Working in groups: only permitted on the project

– Groups may be up to 4 people• Should let me know of your groups by Feb 19• Group members will grade each other at then end

– Smaller groups gain 10% extra on the project per fewer person• Group of 1: 30% extra• Group of 2: 20% extra• Group of 3: 10% extra

• Attendance– Optional but affects your participation grade– No laptop, tablet, or phone use in class

• Don’t test me - I will deduct grade points

Page 14: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Logistics (3/3)• Blackboard

– Grades will be posted there, nothing else

• Course forum and newsgroup– Subscription Is required

– http://piazza.com/stonybrook/spring2015/cse502/home

• Quiz– Completion is required

– If you missed the 1st class, come to office hours for it

Page 15: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

Academic Integrity Policy• You may...

– Discuss assignment, design, techniques

• You may not…– Share code

– Use any code not distributed as part of project handouts• Exceptions are possible, but must receive explicit permission

Page 16: Introduction - Stony Brook · •Goal: design a super-scalar, out-of-order SPARCv8 processor •We’ll use SystemVerilog HDL for implementation –Don’t panic! We’ll cover the

Spring 2015 :: CSE 502 – Computer Architecture

QUIZ


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SystemVerilog in Simulation

SystemVerilog Testbench

IEEE Standard for SystemVerilog— Unified Hardware Design ...skoczen/hdl/ieee_std/ieee1800-2005.pdf · tem design communities with a well-defined and official IEEE unified hardware

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What, If Anything, In SystemVerilog Will Help Me With FPGA ... · What, if anything, in SystemVerilog will help me with FPGA-based designs – Stuart Sutherland, Sutherland HDL, Inc

System Verilog Assertions - Telecom Paris€¦ · System Verilog Assertions Industrial standard (IEEE 1800-2012) Embedded in SystemVerilog HDL Superset of LTL Sequences and regular

SystemVerilog from Zero to One · • Verilog HDLにはタイミングに関して曖昧な機能が多々あり、SystemVerilogは それらを解決しています。 • 例えば、Verilog

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A Brief Introduction to SystemVerilogcompas.cs.stonybrook.edu/.../slides/03-systemverilog.pdf•SystemVerilog is a superset of another HDL: Verilog –Familiarity with Verilog (or

Getting Ready For SystemVerilog - Sutherland HDL...Getting Ready for SystemVerilog Stuart Sutherland copyright 2004, Sutherland HDL, Inc., Getting Ready for SystemVerilog Seminar 5

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SystemVerilog 3.1a Language Reference Manualcourses.eees.dei.unibo.it/.../2016/02/SystemVerilog... · SystemVerilog 3.1a Language Reference Manual Accellera’s Extensions to Verilog®

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HDL Compiler for SystemVerilog User Guide · HDL Compiler™ for SystemVerilog User Guide Version F-2011.09-SP4, March 2012

Sutherland...Stuart Sutherland, Sutherland HDL, Inc. 5 March 11 - 12, 2002 L H D Sutherland SystemVerilog is an Evolution! SystemVerilog evolves Verilog, rather than replacing …

SystemVerilog for RTL - diversis-education.de · Digital Design & Verification Services SystemVerilog for RTL Seite 1 SystemVerilog for RTL This document describes how to use SystemVerilog

Modeling FIFO Communication Channels Using SystemVerilog ...€¦ · Modeling FIFO Communication Channels Using SystemVerilog Interfaces Stuart Sutherland Sutherland HDL, Inc. [email protected]

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