getting ready for systemverilog - sutherland hdl 3 getting ready for systemverilog stuart sutherland...

6/7/2004 1

Getting Ready for SystemVerilogStuart Sutherland

copyright 2004, Sutherland HDL, Inc., www.sutherland-hdl.com

© 2004, Sutherland HDL, Inc. 1

Getting Ready forSystemVerilog at DAC

Stuart SutherlandSutherland HDL, Inc.

Training engineersto be HDL wizards

www.sutherland-hdl.com

2Getting Ready for SystemVerilog Seminar

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© 2004, Sutherland HDL, Inc.

About the Presenter...

Stuart SutherlandVerilog design consultant, specializing in Verilog training

Hardware design engineer with a Computer Science degreeHeavily involved with Verilog since 1988

Member of IEEE 1364 Verilog standards group since 1993Co-chair of Verilog PLI task forceTechnical editor of PLI sections of the IEEE 1364 Verilog Language Reference Manual

Member of the Accellera committee defining SystemVerilogInvolved with the formation of the “Verilog++” committee that started SystemVerilogTechnical editor of SystemVerilog Reference Manual

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This presentation will…

Define what is “SystemVerilog”

Justify the need for SystemVerilog

Provide an overview of the major features in SystemVerilog

Give the status of the SystemVerilog standard

This short tutorial is a general overview of SystemVerilog• Sutherland HDL also offers a full, comprehensive, training workshop on

SystemVerilog, with hands on labs

The primary goal is to show you the many exciting features are in SystemVerilog — It’s a lot!


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Prerequisites

To gain the most benefit from this seminar, you should:Be familiar with the Verilog HDL

SystemVerilog is an extension to the Verilog HDLThis tutorial assumes you already know Verilog

Have a background in hardware engineering

Basic computer architectures (ALUs, State Machines, ...)

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What is SystemVerilog?

SystemVerilog is an extension of the IEEE 1364 Verilog-2001 standard

Adds C and C++ language constructs to VerilogAdds interfaces to VerilogAdds assertions to VerilogAdds many other features to Verilog

SystemVerilog is the next generation of the Verilog standard!Gives Verilog a much higher level of modeling abstractionGives Verilog new capabilities for design verificationExpected to be adopted by the IEEE in the next revision to the 1364 Verilog standard


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Mile High View of SystemVerilog

from C / C++

initialdisableevents wait # @fork–join

$finish $fopen $fclose$display $write $monitor`define ìfdef èlseìnclude `timescale

wire reginteger realtimepacked arrays2D memory

+ = * / %>> <<

modulesparametersfunction/tasksalways @assign

begin–endwhilefor foreverif–elserepeat

Verilog-1995

ANSI C style portsgeneratelocalparamconstant functions

standard file I/O$value$plusargsìfndef èlsif `line@*

(* attributes *)configurationsmemory part selectsvariable part select

multi dimensional arrays signed typesautomatic** (power operator)

Verilog-2001

SystemVerilog

globalsenumtypedefstructuresunionscastingconst

break continuereturn do–while++ -- += -= *= /= >>= <<= >>>= <<<=&= |= ^= %=

intshortintlongint byteshortreal voidalias

interfacesnested hierarchyunrestricted portsautomatic port connectenhanced literalstime values and unitsspecialized procedures

packages2-state modelingpacked arraysarray assignmentsqueuesunique/priority case/ifcompilation unit space

desi

gn

assertionstest program blocksclocking domainsprocess control

mailboxessemaphoresconstrained random valuesdirect C function calls

classesinheritancestrings

dynamic arraysassociative arraysreferences

verif

icat

ion

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Seminar Flow

Overview of SystemVerilogProductivity Enhancements

Make it easier to model with VerilogRTL Enhancements

Make RTL models more accurateData Encapsulation Enhancements

Make it easier to manage lots of design dataAbstract Modeling Enhancements

Model more functionality with fewer lines of codeVerification Enhancements

State-of-the-art verification methodologiesSummary


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Why Enhance Verilog?

Engineers must design more gates in less timethan ever before

Requires designing at a more abstract levelRequires using new verification techniquesRequires system level design/verification languages

But…Hardware is still built with silicon!

System level designs must be implemented in gatesThe logic gates must still meet timing, area, EMF, thermal and other implementation requirementsHDLs, such as Verilog are still part of the design flow!

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Bridging the System Design Canyon

SystemVerilog is the bridgebetween system engineers

and implementation engineers!

How am I going to build thisde-referenced pointer to a

union of disparate data types?

What do you mean you have to add a pipeline to make my brilliant algorithm meet setup times? What is a setup time, anyway?


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SystemVerilog is an Evolution

SystemVerilog evolves Verilog, rather than replacing itGives engineers the best of Verilog and C

This is easy,it’s just like

using Verilog,only more!

int clock; //global variables

module my_system (...);

always @(posedge clock)case(instruction)...ROR: out = rotate(...);

endcase

enum {ADD, SUB, ROR} instruction;

struct {int word1, word2;} packet;

function int rotate (int data_in, n);int temp;for (int i=0; i<n; i++)...

return(temp);endfunction

endmodule

C language features• Structures• Globals• ++ operator• User-defined types• and much more…

Standard Verilog HDL• Familiar• Concurrency• Proven to work

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SystemVerilog Was Developed In Three Major Phases

SystemVerilog 3.0Enhances hardware modeling aspects of the Verilog HDL

Development began in June 2001Ratified as an Accellera standard in June 2002

SystemVerilog 3.1Extends the design verification aspects of the Verilog HDL

Development began in June 2002Ratified as an Accellera standard in May 2003

SystemVerilog 3.1aRefinement plus some additional design verification extensions

Ratified as an Accellera standard in May 2004To be turned over to IEEE in June 2004


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Why Call It SystemVerilog 3.x?

To show that SystemVerilog is an evolution of VerilogVerilog 1.0 is the IEEE 1364-1995 “Verilog-1995” standard

The first generation of a true Verilog languageBased on the original Verilog HDL created by Gateway Design Automation in 1984

Verilog 2.0 is the IEEE 1364-2001 “Verilog-2001” standardThe second generation of the Verilog languageThe first major enhancement to Verilog since its creation

SystemVerilog 3.x is the Accellera extensions to theVerilog-2001 standard

The third generation of the Verilog languageMany significant enhancements…as will be shown

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SystemVerilog Was Developed By Accellera

Accellera is a not-for-profit consortium of:Electronic Design Automation (EDA) design tool vendorsASIC manufacturersSystems companies

Accellera's mission is to:Focus on identifying new EDA standardsAssist in the development of EDA standards and formatsFoster the adoption of new EDA methodologies

Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International


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Who’s on the Accellera SystemVerilog Committee?

Renown industry experts are defining SystemVerilogSimulation algorithm expertsSynthesis compiler expertsVerification expertsVerilog design engineers and consultantsIEEE 1364 Verilog standard working group members

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Why is AccelleraChanging an IEEE Standard?

The IEEE 1364 standards group is the official governing body of the Verilog language

Defined the 1364-1995 “Verilog-1995” standardDefined the 1364-2001 “Verilog-2001” standard

It took the IEEE 5 years to define and ratify Verilog-2001Our design needs are changing much faster

than the IEEE can react!

Accellera is accelerating the IEEE standardization processCan define a de facto standard in months instead of yearsAccellera will donate SystemVerilog to the IEEE to become part of the next IEEE Verilog standard


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Coordination with IEEE

Accellera’s primary goal is to promote EDA standardsSponsor IEEE standards groups (Verilog, VHDL, SDF...)Think tank for new standards

SystemVerilog development was coordinated with IEEE14 members of the IEEE 1364 Verilog Standards Group also participated on Accellera SystemVerilog committees1364 representatives had official “corporate” voting rights on SystemVerilog, the same as other companies1364 standards meetings often include discussion of what is in SystemVerilog

Accellera plans to turn SystemVerilog over to the IEEE 1364 to integrate into the Verilog standard

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What’s the Best Way?

Two good ways to extend Verilog...Start from scratch (re-invent the wheel)

First decide how new constructs will be addedInvent the syntax and semantics for each new constructCommittee members debate and debate and debate...Years later, if consensus is reached, extensions are released to EDA companies to implement

Start with proven technologiesLearn from other companies trials and errorsPick the best features from many sourcesSyntax is not as uniform because of many sourcesMuch faster time-to-market than re-inventing the wheel


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SystemVerilog’s Roots

SystemVerilog is derived from proven technology:SUPERLOG architectural modeling language (Co-design)PSL-Sugar assertions (IBM)ForSpec assertions (Intel)OVL assertion library (Verplex)OpenVERA assertions (Synopsys)OpenVERA hardware verification language (Synopsys)DirectC programming interface (Synopsys)Other donations from several companies (Novas, 0-in, Real Intent,...)

Accellera spent two years integrating these donationsRemoving overlapMaking syntax look like Verilog

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EDA VendorsSupporting SystemVerilog

A few of the companies that have announced SystemVerilog products...


Overview of SystemVerilog

Productivity enhancements

RTL modeling enhancements

Data encapsulation enhancements

Abstract modeling enhancements

Verification enhancements

Summary

What Comes Next...

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What Are “Productivity Enhancements”

Productivity enhancements:Make it easier to model in VerilogEliminate common modeling errorsDo not add significant new functionality

Caveat:The list in this presentation is not complete

Not enough time to cover everythingIntent is to give an idea of what types of enhancements fall into the “productivity” category

The same caveat is true for subsequent categories


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SimulationTime Units and Precision

In Verilog-2001, time units are a simulation commandDeclared with the `timescale compiler directive

Specified outside of any moduleSource files without a `timescale directive are dependent on compilation order and/or product nuances

compilation order`timescale 1ns/1nsmodule A (...);nand #5 (...);

module B (...);nand #5 (...);

`timescale 1ms/1msmodule C (...);nand #5 (...);

File A

File B

File C

module B delaysare in nanoseconds

compilation order

`timescale 1ns/1nsmodule A (...);nand #5 (...);

module B (...);nand #5 (...);


File A

File B

File C

module B delaysare in ?

compilation order`timescale 1ns/1nsmodule A (...);nand #5 (...);


File A

File C

module B delaysare in milliseconds

module B (...);nand #5 (...); File B

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Enhanced Specification ofTime Units and Time Precision

In Verilog, time units are a module propertyDeclared with the `timescale compiler directive

forever #5 clock = ~clock; 5 what?

module my_chip (…);timeunit 1ns;timeprecision 10ps;...

SystemVerilog adds:Time units can be specified as part of the time value

Module time units and precision can be specified with keywords

forever #5ns clock = ~clock;


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Enhanced `define Text Substitution

SystemVerilog enhances the `define text substitution macroA backslash ( \ ) can be used to continue on a new line

`define OUTPUTS {load_r, load_b, load_f, load_pc, inc_pc, set_br, \rslt_oeN, dout_oeN, dmem_rdN, dmem_wrN, halt}

int i;`define print(x) $display(`“ variable x = %d `", x)...`print(i); Substitutes to:

$display(“ variable i = %d ”, i);

The macro can include a quote marks, using `”

int i1;`define printi(x) $display(`“ variable i``x is %d `", i``x)...`printi(1);

Substitutes to:$display(“variable i1 = %d”, i1);

Identifier names can be created from macros, using ``

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Block Names and Statement Labels

Verilog allows a statement group to have a nameIdentifies all statements within the blockCreates a new level of model hierarchy

begin: block1 ... end

begin: block2 ... end: block2

SystemVerilog adds:A name can be specified after the end keyword

Documents which statement group is being ended

shifter: for (i=15; i>0; i--)

Specific statements can be given a “label”Identifies a single statement


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Named End Statements

SystemVerilog also extends to ability to specify an ending name with endmodule, endinterface, endprimitive, endprogram, endtask, endfunction, endclass, endpropertyand endsequence

The ending name must match the name used with the corresponding beginning of the code block

module my_chip (...);...task get_data (...)

...endtask: get_data

endmodule: my_chip

Specifying ending names helps to make large blocks of code more readable, but does not affect functionality in any way

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Enhanced Literal Value Assignments

In Verilog, there is no simple way to fill a vector with all 1’sparameter N = 64;reg [N-1:0] data_bus;data_bus = 64’hFFFFFFFFFFFFFFF; //set all bits of data_bus to 1

reg [N-1:0] data_bus;data_bus = x’1; //set all bits of data_bus to 1

SystemVerilog enhances assignments of a literal valueAll bits of a vector can be filled with a literal 1-bit value

x’0 fills all bits on the left-hand side with 0x’1 fills all bits on the left-hand side with 1x’z fills all bits on the left-hand side with zx’x fills all bits on the left-hand side with x

vector width must be hard coded

could also use operations, such as replicate or invert


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The SystemVerilog logic Data Type

In Verilog, the term “reg” confuses new usersThe name would seem to infer a hardware registerIn reality, reg is a general purpose variable that can represent either combinational logic or sequential logic

SystemVerilog’s 4-state logic type is identical to a reglogic is a more intuitive name for new Verilog users

Historically, logic comes from the Superlog language, where it had different semantic rules than regSystemVerilog made the rules equivalent for backward compatibility with existing Verilog modelsVerilog also has equivalent keywords, (e.g. wire and tri)that historically once had different semantics

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The 2-state bit Data Type

Verilog uses 4-state logicMost hardware can be modeled with 2-state logicSynthesis mostly only considers 2-state values

The SystemVerilog 2-state bit typeModels RTL logic the way synthesis sees the logicAllows easy mixing of 2-state and 4-state in the same designUses the same rules with all SystemVerilog tools

reg mode;

always @(a, b, mode)if (mode)

y = a + b;else

y = a - b;

Synthesis does not take into consideration that mode could have an X or Z value


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SystemVerilog Relaxes Verilog Variable Semantic Rules

Verilog has strict rules on when to use a variable (eg. reg) and when to use a net (e.g. wire)

Context dependentA variable cannot be “driven” by a continuous assignment or an output port

SystemVerilog allows variables to be used in the same places a net can be used:

Limited to a single driver type (procedural, continuous or output of a module/primitive instance)

1-driver limit prevents inadvertent shared variable behavior where wired-logic resolution is needed

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An Example of Using VariablesWith SystemVerilog’s Relaxed Rules

The same data type can be used for the entire modelWith the restriction that signals only have a single driver

Most designs mostly only have a single driver for each signal — the “single driver” restriction on variables

can can catch design errors at compile time!

module compare (output logic lt, eq, gt,input logic [63:0] a, b);

always @(a or b)if (a < b) lt = 1'b1; //procedural assignmentselse lt = 1'b0;

assign gt = (a > b); //continuous assignments

comparator u1 (eq, a, b); //module instance

endmodule


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Module Port Connections

Verilog restricts the data types that can be connected to module ports

Only net types on the receiving sideNets, regs or integers on the driving sideChoosing the correct type frustrates Verilog modelers

SystemVerilog removes all restrictions on port connectionsAny data type on either side of the portReal numbers (floating point) can pass through portsArrays can be passed through portsStructures can be passed through ports

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Module InstancePort Connection Shortcuts

Verilog module instances can use port-name connectionsMust name both the port and the net connected to it

module dff (output q, qb,input clk, d, rst, pre);

...endmodulemodule chip (output [3:0] q,

input [3:0] d, input clk, rst, pre);

dff dff1 (.clk(clk), .rst(rst), .pre(pre), .d(d[0]), .q(q[0]));

can be verbose and redundant

dff dff1 (.clk, .rst, .pre, .d(d[0]), .q(q[0]));

SystemVerilog adds .name and .* shortcuts.name connects a port to a net of the same name

dff dff1 (.*, .q(q[0]), .d(d[0]), .qb());

.* automatically connects all ports and nets with the same name


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For Loop Variables

In Verilog, the variable used to control a for loop must be declared prior to the loop

integer i;initial begin

for (i=0; i<= 255; i++) ...

i must be declared outside the loop

initialbegin

for (int i=0; i<= 255; i++)...

i can be declared within the loop

SystemVerilog allows the declaration of the for loop variable within the for loop itself

Makes the loop variable local to the loopPrevents the possibility of a conflict between multiple for loops

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Enhancements toTasks and Functions

SystemVerilog enhances Verilog tasks and functionsStatic and automatic storage enhancementsDefault directions for formal argumentsDefault data types for formal argumentsPassing arrays and structures as argumentsPassing arguments by namePassing arguments by reference (pointers)Function outputs and inoutsC-like function returnsVoid functionsImplicit statement grouping

The next few pages illustrate a few of

these enhancements...


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Multiple StatementsIn Tasks and Functions

In Verilog:Multiple statements within a task or function must be grouped using begin...end

function int check_errors (input packet sent, received);int error_count;$display("data sent was %0h", sent.data);if (sent !== received)...

return(error_count);endfunction

a begin...end sequence is implied

In SystemVerilog:Statement grouping is not required

Multiple statements execute as if in a begin...end block

There are several more enhancements involving tasks and functions that are not covered in this presentation!

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Enhanced Task/Function Formal Arguments

In Verilog:The directions of all arguments must be declared

function add (input a, b);...

endfunction

In SystemVerilog:There is a default direction of input

function add (a, b);...

endfunction


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Task/Function Arguments:Passing By Name

In Verilog:Values are passed to tasks and functions by position

always @(posedge clock)result = subtractor( stack, data_bus );

function integer subtractor(input integer a, b);subtractor = a - b;

endfunction

How can I know if stack and data_bus are in the right order?

always @(posedge clock)result = subtractor( .b(stack), .a(data_bus) );

function integer subtractor(integer a, b);return(a - b);

endfunction

In SystemVerilog:Values can be passed using the formal argument name

Uses same syntax as named module port connections

.name and .* connections can also be used

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Function Return Values

In Verilog:Functions must have a return valueThe return is assigned to the name of the function

function int mult (int a, b);return(a * b);

endfunctionMore consistent with C style functions

In SystemVerilog:Functions can return a value using a return statement, like C

function [31:0] mult (input [31:0] a, b);mult = a * b;

endfunction


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Task/Function Arguments:Default Input Values

In Verilog:Values must be passed to all task and function inputs

always @(posedge clock)result = incrementor( data_bus, 1 );

function integer incrementor (input integer count, step);incrementor = count + step;

endfunction

always @(posedge clock)result = incrementor( data_bus );

function int incrementor(int count=0, step=1);return(count + step);

endfunction

In SystemVerilog:Task/function formal argument can have a default value

For this call to the function, the second input will use its default value of 1

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Task/Function Arguments:Passing By Reference

In Verilog:Inputs are copied into tasks and functionsOutputs are copied out of tasks

always @(posedge clock)result = subtractor( data_bus, stack );

function integer subtractor(input integer a, b);...

always @(posedge clock)result = subtractor( data_bus, stack );

function int subtractor(int a, ref b);...

In SystemVerilog:Task/function arguments can “reference” the calling arguments

Uses the keyword ref instead of input, output or inoutUsing const ref makes the reference read-only

The function receives a pointer to “stack” in the calling scope(note: the C “&” is not used)

Pass by reference can be used to pass arrays to a task or function, without copying the array


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Static and Automatic StorageIn Tasks and Functions

Verilog-1995 has static tasks and functionsAll storage is allocated once and shared by all calls

Verilog-2001 adds automatic tasks and functionsAll storage is allocated each time the block is enteredCan be called while a previous call is still executing(allows re-entrant tasks and recursive functions)

SystemVerilog adds:Static storage in an automatic task or functionAutomatic storage in a static task or function

typedef struct {...} packet;task automatic check_results (input packet sent, ref packet received);static int error_count = 0;wait (done)

if (sent !== received)error_count++;

Static storage is only initialized one time, and retains its value from one call to the next

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Summary

What Comes Next...


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RTL Enhancement Characteristics

RTL enhancementsMake it easier to model for synthesisRemove model ambiguityReduce pre- and post-simulation mismatchesAllow all tools to generate warnings if model does not match designer’s intent

Just a few of the enhancements in this category will be shown

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Inferring HardwareFrom always Procedures

The always procedure is a general purpose procedureUsed to model combinational logic, latched logic, sequential logicand testbench logicSoftware tools must “infer” (guess ) what type of hardware an engineer intended based on procedure content and context

always @(posedge clock)begin

if (mode) q1 = a + belse q1 = a - b;q2 <= q1 | (q2<< 2);q2++;

end

Is q1 combinational logic or sequential logic?

Does q2 ever increment?


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Combinational Logic Procedures

The always_comb procedure models combinational logicalways_comb

if (!mode)y = a + b;

elsey = a - b;

always_comb is different from a normal always procedureThe sensitivity list is inferred

Includes every variable read by the procedureVariables on the left-hand side of assignments cannot be written to by any other procedureThe procedure is automatically triggered at time zero

Ensures the outputs are consistent with the inputs at time zero

no sensitivity list

Tools can know the designer’s intent, and verify that the code models combinational behavior

contents must follow synthesis requirements for combinational logic

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Latched Logic Procedures

The always_latch procedure models combinational logic with storage

always_latchif (enable) q <= d;

no sensitivity list

Tools can know the intent, and verify the code models latched behavior

always_latch is different from a normal always procedureHas same required rules as always_comb

The sensitivity list is inferred (same rules as always_comb)Variables on the left-hand side of assignments cannot be written to by any other procedureThe procedure is automatically triggered at time zero

Software tools may apply different additional checksE.g. don’t need to check that all LHS variables are updated


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Sequential Logic Procedures

The always_ff procedure models synthesizable sequential logic behavior

always_ff @(posedge clk or negedge reset)if (!reset) q <= 0;else q <= d;

Tools can know the intent, and verify the code models sequential logic behavior

always_ff is different from a normal always procedureThe sensitivity list must specify an edge for each signalNo event controls are permitted within the procedure

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Unique and Priority Decisions

Verilog defines that if—else—if decisions and case statements execute with priority encoding

In simulation, only the first matching branch is executedSynthesis will infer parallel execution based on context

Parallel evaluation after synthesis may causes a mismatch inpre-synthesis and post-synthesis simulation results

SystemVerilog adds unique and priority keywords:Priority-encoded or parallel evaluation can be explicitly defined for both simulation and synthesisSoftware tools can warn if case or if—else decisions do not match the behavior specified


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Reducing Simulationversus Synthesis Ambiguities

In SystemVerilog allows the designer to specify his intentCan eliminate any ambiguity between simulation interpretations and synthesis implementationsSoftware tools can issue warnings if the code might not behave according to the stated intent

always_combbeginnext_state = state; //default for each branch belowunique case(state)red: if (sensor = 1) next_state = green;yellow: if (yellow_downcnt = 0) next_state = red;green: if (green_downcnt = 0) next_state = yellow;

endcaseend

No ambiguities on design intent!

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New Operators

Verilog does not have increment and decrement operators

for (i = 0; i <= 255; i = i + 1)...

for (i = 0; i <= 255; i++)...

Hooray!

SystemVerilog adds:++ and -- increment and decrement operators+=, -=, *=, /=, %=, &=, ^=, |=, <<=, >>=, <<<=, >>>= assignment operators


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An Increment/Decrement“Gotcha”

The ++ and -- operators behave as a blocking assignment!A parallel process may read the value of an incremented/decremented variable before or after the change

Guideline: Never use ++ and -- in logic that occurs on a clock edge!

always_ff @(posedge clock) case (state)

HOLD: if (count == MAX)...

always_ff @(posedge clock) if (reset_n) count <= 0;else count++;

//same as count = count + 1;

Is count sampled before or after it is incremented?

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Enumerated Types

With Verilog, constants must be used to give names to values

The variable traffic_light could be assigned values other than red, green or yellow

reg [2:0] traffic_light;

parameter red = 0;parameter green = 1;parameter yellow = 2;

always @(posedge clock)if (traffic_light == red)

...

enum {red, green, yellow} traffic_light;

always @(posedge clock)if (traffic_light == red)

...

SystemVerilog adds enumerated types, using enum, as in C

Limits the legal values of a variable

Simplifies declaration of named values


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Hardware SpecificEnumerated Types

SystemVerilog’s enumerated types can be abstract, as in CDefault’s to an int data type (2-state logic)Only specify the names of the enumerated valuesFirst name default’s to a value of 0, second name to 1, ...

enum {WAIT, LOAD, READY} states;

enum bit [2:0] {WAIT=3’b001, LOAD=3’b010, READY=3’b100} states;

Optionally, SystemVerilog enumerated types can be defined with hardware implementation characteristics

Can specify a different data typeCan specify a specific vector sizeCan specify specific values for each name

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Special Methods for Enumerated Types

The implementation of enumerated types is not complete without their “methods”

<enum_variable>.first — returns the value of the first member in the enumerated list<enum_variable>.last — returns the value of the last member in the enumerated list<enum_variable>.next(<N>) — returns value of the Nth next value in the enumerated list<enum_variable>.prev(<N>) — returns value of the Nth previous value in the enumerated list<enum_variable>.num — returns the number of elements in the enumerated list<enum_variable>.name — returns the name of the current value in the enumeration variable

enum {CNT0, CNT1, CNT2, CNT3, CNT4, CNT5, CNT6, CNT7} State, NextState;...always @(state) begin: confidence_check

if (synched) next_state = State.next; // increment by 1 stateelse (next_state = State.prev(2); // decrement by 2 states$display("Next state will be %s (%b)", NextState.name, next_state);

end: confidence_check


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Void Functions

In Verilog:Functions must have a return valueWhen a function is called, it is illegal to ignore the return

function [31:0] multiplier (input [31:0] a, b);... // logic for secret multiplier algorithmmult = a * b;

endfunction

product = multiplier(u, v);

In SystemVerilog:Functions can be declared as type void (no return value)Called like a task, but with the restrictions of functions

function void multiplier (int a, b, output longint y);...

endfunction

multiplier(u, v, product);

• Functions have restrictions (no delays, etc.)• Helps ensure subroutines are synthesizable !

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Summary

What Comes Next...


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Data Encapsulation Enhancement Characteristics

Data encapsulation enhancementsBundle several discrete signals or data togetherTransfer whole groups of signals or data at onceAllow operations on a bundle of signals or data


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Interfaces

Verilog connects models using detailed module ports

Connections must be modeled at implementation level

Interconnection details must be duplicated in every module

White Board Verilog Models

SystemVerilog ModelsWhite BoardConnections between

modules are bundled together

Modules use simple ports, an interface bundle

SystemVerilog adds interfaces


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Interfaces Simplify Module Interconnections

module top;bit clk = 0;chip_bus a(clk); //instantiate the interface

RAM mem(a); //connect interface to module instanceCPU cpu(a); //connect interface to module instance

endmodule

RAM

chip_bus

clk

clk clkdata data

address addressrequest request

grant grantready ready

CPUinterface chip_bus (input bit clk);

bit request, grant, ready;bit [47:0] address;bit [63:0] data;

endinterface

module RAM(chip_bus pins); ...

endmodule

module CPU (chip_bus io); ...

endmodule Modules do not duplicate connection detail

Netlists do not duplicate connection detail

Connection details are in in the interface

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Interface Modports

Interface modports define different sets of connectionsinterface chip_bus (input bit clk);bit request, grant, ready;logic [63:0] address, data;modport master (output request, address,

inout data,input clk, grant, ready);

modport slave (input clk, request, address,inout data,output grant, ready);

endinterface

Modports define the port directions from the

module’s point of view

RAM

chip_bus

clk

clk clkdata data

address addressrequest request

grant grantready ready

CPU

module CPU(chip_bus.master io); ...

endmodule module RAM(chip_bus io);...

endmodulemodule top;chip_bus bus(clk); CPU cpu(bus);RAM mem(bus.slave);

endmodule

module definition

module instance

Which modport to use can be specified in either:• The module definition• The module instantiation


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Using Modports to Limit Access

Modules can only see the signals in the modport being usedinterface chip_bus (input bit clk, test_clk);bit request, grant, ready;logic [63:0] address, data;logic [7:0] opcode; modport master (output request, address,

inout data, input clk, grant, ready, opcode);modport slave (input clk, request, address,

inout data, output grant, ready);endinterfacemodule CPU(chip_bus.master io);

always@(posedge io.clk)case (io.opcode)...

endmodule module RAM(chip_bus.slave io);...

endmodulemodule omniscient(chip_bus a);always@(a.test_clk)...

endmodule

RAM cannot access opcode or test_clk

omniscient can access all signals in interface

CPU cannot access test_clk

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Using Tasks and FunctionsIn Interfaces

Tasks and functions can be declared within interfacesCan represent complex bus transactionsModules can be modeled at an abstract level

Can execute transactions without referencing specific signals interface chip_bus (input bit clk);bit request, grant, ready;logic [63:0] address, data;task Read (...);

... endtasktask Write (...);

...endtask

endinterfacemodule RAM(interface io);always@(io.request)io.Read;

... endmodule //interface and module instantiations not shown

An interface task/function is referred to as a communication “method”


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Using Procedures in Interfaces

Interfaces can contain:initial proceduresalways proceduresassign continuous assignments

Procedures can be used to represent:Functionality shared by all modules connected to the interfaceSelf-checking of transactions and protocols

interface chip_bus (input bit clk);bit request, grant, ready;logic [63:0] address, data;always @(posedge clk)if(request)a1: @(posedge clk) assert(grant)

@(posedge clk) assert(ready);

endinterface

Every request must be followed by a grant and then a ready

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Unpacked Arrays(Verilog Style)

An “unpacked array” is an array of signalsThe signal can be any data typeThe array can have any number of dimensions

wire n [0:1023]; a 1-dimensional “unpacked array” of 1024 1-bit nets

real r [0:1023]; a 1-dimensional “unpacked array” of 1024 real variables

int a [0:7][0:7][0:7]; a 3-dimensional “unpacked array” of 32-bit int variables

Unpacked array dimensions come after the array name (as in Verilog)

In Verilog:Only one element within an array can be accessed at a time

SystemVerilog adds:The entire array can be referenced (e.g. my_array = your_array)A “slice” of multiple elements can be referenced


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Initializing and Assigning to Unpacked Arrays

Unpacked arrays can be assigned using a list of values in { }braces for each array dimension (similar to C)int d [0:1][0:3] = { {7,3,0,5},{2,0,1,6} };

The { } braces are the C array initialize tokens, not the Verilog concatenate operator!

Must have a set of braces for each array dimension

d[0][0] is initialized to 7d[0][1] is initialized to 3d[0][2] is initialized to 0d[0][3] is initialized to 5d[1][0] is initialized to 2d[1][1] is initialized to 0d[1][2] is initialized to 1d[1][3] is initialized to 6

int d [0:1][0:3] = { 2{7,3,0,5} }; d[0][0] is initialized to 7d[0][1] is initialized to 3d[0][2] is initialized to 0d[0][3] is initialized to 5d[1][0] is initialized to 7d[1][1] is initialized to 3d[1][2] is initialized to 0d[1][3] is initialized to 5

A replicate operator can be used to fill unpacked arrays

int d [0:1][0:3] = { default:’1 };

A default assignment can be used

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Packed Arrays

In Verilog a “range” before the name declares a “vector” sizewire [0:63] n; a 64-bit “vector” made up of 64 1-bit nets

A dimension before the signal name declares a vector of 1-bit signals

SystemVerilog calls the dimension before the name a “packed array” of 1-bit signals

SystemVerilog adds “multidimensional packed arrays”

A “packed array” is an array of sub fields within a vectorCan only use be 1-bit data types: reg, logic, bit, wire, ...A Verilog “vector” is a 1-dimensional packed array

a 2-dimensional “packed array” of logic variablesreg [3:0][7:0] a;

a[3] a[2] a[1] a[0]

[7:0] [7:0] [7:0] [7:0]a


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Structures

SystemVerilog adds C-like structures to Verilog

Can be used to bundle several variables into one objectCan assign to individual signals within the structureCan assign to the structure as a wholeCan pass structures through ports and to tasks or functions

An array is a collection of elements that are all the same type and size;A structure is a collection of elements that can be different types and sizes

struct {real r0, r1;int i0, i1;bit [15:0] opcode;

} instruction_word;...instruction_word.opcode = 16’hF01E;

The structure declaration is the same as in C

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Unions

A union is a single element that allows the storage of different data types in the same space

Allows same storage space to be referenced different ways

union {struct packed {

bit [15:0] source_address;bit [15:0] destination_address;bit [31:0] data;

} data;

bit [7:0][7:0] bytes;

} data_reg;

data_reg.data = data_in; //assumes data_in is of type data_packetdest_low_byte = data_reg.bytes[4];

63 0

source dest data

two names for the same storage


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User-defined Types

Verilog does not have user-defined data types

SystemVerilog adds user-defined typesUses the typedef keyword, as in C

typedef enum {FALSE, TRUE} boolean;

boolean ready; //variable “ready” can be FALSE or TRUE

typedef struct packed {bit [15:0] source_address;bit [15:0] destination_address;bit [31:0] data;

} data_packet;

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Passing Arrays,Structures and Unions Through Ports

Arrays, structures and unions can be passed through module ports, or as arguments to tasks and functions

typedef struct {real r0, r1;int i0, i1;bit [15:0] opcode;

} instruction;

module ALU (input instruction IW,input bit clock, reset,output int out_i,output real out_r);

always @(posedge clock, posedge reset)if (reset)beginout_i = 0;out_r = 0.0;

endelsecase (IW.opcode)`ADD_INT : out_i = IW.i0 + IW.i1;`ADD_REAL: out_r = IW.r0 + IW.r1;...

Arrays and structures passed through a port follows same basic rules as assigning an array to an array or a structure to a structure

The array, structure or union name must be defined (using typedef)

before it can be used in a port list


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The Compilation UnitName Space ($unit)

SystemVerilog provides a compilation unit name spaceAllows declarations of variables, functions, etc. outside of modulesExternal declarations are visible to all code compiled at same timeExternal names can be directly referenced as $unit.<name>

bit reset; //external reset

typedef struct {int i0, i1;bit [15:0] opcode;

} instruction_t;

module top; //instance of top-level moduleinstruction_t out, in;...register i1 (out, in, clock, reset);

endmodule

module register (output instruction_t q, ...)...always @(posedge clk or posedge $unit.reset)

External variable

External user-defined type

When a name is referenced:• First, follow Verilog search rules• Second, look in $unit

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Packages

SystemVerilog adds packages to the Verilog HDLUsed to contain declarations that are used in many models

Modules can directly reference declarations in a packageModules can import specific declarations from a packageModules can import only what is needed from a package

package definitions;typedef struct {

int i0, i1;bit [15:0] opcode;

} instruction_t;endpackage

module register (output definitions::instruction_t q, ...)...

module top; //instance of top-level moduleimport definitions::*; // import whatever is needed from packageinstruction_t out, in;...

Packages can contain net and variable declarations, task and function definitions, type definitions, class definitions, coverage definitions, operator overload definitions, ...


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Nested Modules

In SystemVerilog modules can be declared within modulesNested modules are only visible to their parent module

Other parts of the design cannot instantiate themProtects hierarchy within Intellectual Property models

module Top;my_stuff i1 (clock);ip_core i2 (clock);

endmodulemodule my_stuff (input bit clock);...

endmodulemodule ip_core (input bit clock);

module sub1();...

endmodulemodule sub2();

...endmodule

endmodule

modules my_stuff and ip_core are in the global name space, and can be instantiated anywhere

modules sub1 and sub2 are local names within ip_core, and can only be instantiated in ip_core

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Summary

What Comes Next...


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Abstract Modeling Enhancement Characteristics

Abstract modeling enhancementsModel more functionality with fewer lines of codeMore like programming than register transfer level codeMight not be synthesizable (today)Important for Behavioral Modeling and Bus Functional Modeling


RTL modeling can be too primitive for large Bus

Functional Models!

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Abstract Data Types

Verilog has hardware-centric data typesIntended to represent real connections in a chip or systemAt the system and RTL level, models only need 2-state logic

Tri-state busses are the only place 4-state logic is needed

SystemVerilog adds several new data typesC-like data types create a bridge between C and Verilog

byte — an 8-bit 2-state integershortint — a 16-bit 2-state integer, similar to a C shortint — a 32-bit 2-state integer, similar to a C intlongint — a 64-bit 2-state integer, similar to a C longlongshortreal — a 32-bit single-precision floating point, the same as a C floatvoid — no value (used for function returns)


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Signed and Unsigned Modifiers

Verilog-1995 had one signed typeThe integer type is a 32-bit signed variable

Verilog-2001 adds signed nets and regsAny vector size can be explicitly declared as signed

reg signed [63:0] data_bus;

int unsigned uint;

SystemVerilog adds new signed typesThe int, shortint, longint and byte are signed

SystemVerilog adds unsigned declarationsAny signed type can be explicitly declared as unsigned

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Constant Declarations

Verilog has parameter, specparam and localparam constantsAssigned a value during elaboration

Can only be declared in static scopes (modules, static tasks or static functions)

SystemVerilog adds const constantsNot assigned its value until after elaboration

Can be declared in an automatic task or functionThe right-hand side can reference values from elsewhere in the hierarchy

task automatic C;const int N = 5;...

endtask

A const is essentially a variable that can only be initialized


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Type Casting

SystemVerilog adds casting operations to the Verilog language

int’(2.0 * 3.0) //cast operation result to int

<type>’(<value>) — cast a value to any data type, including user-defined types

signed’(y) //cast value to a signed value

<sign>’(<value>) — cast a value to signed or unsigned

17’(n - 2) //cast operation result to 17 bits wide

<size>’(<value>) — cast a value to any vector size

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Redefinable Data Types

Verilog-1995/2001 allows “parameterized” vector declarationsmodule register #(parameter size = 16)

(output reg [size-1:0] q,input wire [size-1:0] d,input wire clock, reset);

module bar;...foo #(.VAR_TYPE(int)) u1 (...); //redefines VAR_TYPE to be an int

endmodule

module foo #(parameter type VAR_TYPE = shortint) (input VAR_TYPE i, output logic [7:0] o);

VAR_TYPE j; /* i and j are of type shortint unless redefined */...

endmodule

SystemVerilog also allows data types to be “parameterized”Data types can be changed using parameter definition


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Jump Statements

Verilog uses the disable statement as a go-toCauses a named group of statements to jump to the end

SystemVerilog adds the C language jump statements:break — works like the C breakcontinue — works like the C continuereturn(<value>) — return from a non-void functionreturn — return from a task or void function

task send_packet(...);if (^data == 1’bx) begin

$display(“Error...”);return; //abort task

end...

endtask

function real absolute(input real a);if (a >= 0.0) return(a);else return(-a);

endfunction

The return statement allows terminating a task or function before reaching the end

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New Bottom Testing Loop

Verilog has for, repeat and while loopsThe control value is tested at the beginning of each pass through the loop

Can require extra code outside the loop to execute statements once if the test value is false at the first pass of the loop

SystemVerilog adds a do—while loopThe control is tested at the end of each pass of the loop

Can eliminate the need, in some cases, to have the loop code both inside the loop and outside the loop (to execute once)

dobegin

if (addr < 0) done = 1;else if (addr > 255) OutOfBound = 1;else begin out = mem[addr]; addr -= 8; end

endwhile (addr > -9 || addr <= 255)

must execute loop at least once to set done or OutOfBound flag


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Direct ProgrammingLanguage Interface

Verilog uses the Programming Language Interface (PLI) to allow Verilog code to call C language code

Powerful capabilities such as traversing hierarchy, controlling simulation, modifying delays and synchronizing to simulation timeDifficult to learnToo complex of an interface for many types of applications

SystemVerilog adds a “Direct Programming Interface” (DPI)Verilog code can directly call C functionsC functions can directly call Verilog tasks and functionsNo PLI is needed for these direct function calls

Cannot do everything the PLI can doCan do many things more easily than the PLIIdeal for interfacing to bus-functional models written in C

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Summary

What Comes Next...


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Testing for a Sequence of Events, The Verilog Way

Verilog does not provide an assertion constructVerification checks must be coded with programming statements

0 1 2 3 4 5

reqack

always @(posedge req) begin@(posedge clk) ; // synch to clockfork: watch_for_ack

parameter N = 3;begin: cycle_counter

repeat (N) @(posedge clk);$display("Assertion Failure", $time);disable check_ack;

end // cycle_counterbegin: check_ack

@(posedge ack)$display("Assertion Success", $time);disable cycle_counter;

end // check_ackjoin: watch_for_ack

end

to test for a sequence of events requires several

lines of Verilog code(that can be difficult to

read and maintain)

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SystemVerilog Assertions

SystemVerilog adds assertion syntax and semanticsImmediate assertions test for a condition at the current time

Concurrent assertions test for a sequence of events spread over time

always @(state)assert (reset && (state != RST)) else $fatal);

generate a fatal error if reset is true

and not in the reset state

0 1 2 3 4 5

reqack

sequence req_ack;@(posedge clk) req ##[1:3] $rose(ack);endsequence

assert property (req_ack);an event sequence is described using a declarative statement


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SystemVerilog Assertion Sequences

SystemVerilog can specify very complex event sequences using a simple and concise syntax

Unifies PSL and Verilog syntax to express sequencesAdds Verilog-like simulation timing and assertion controlCan specify:

Advancing one or more clock cycles, using ##Boolean expressions, using special operators

and, intersect, or, first_match, throughout, within, $rose, $fell, $stable

Repetition of sequencesImplication of sequences

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Specifying Sequences

Sequences of one or more events can be specified using ##

a b c z

a ##1 b ##1 c

Simple Sequence

Expression “Goto” Repetitiona c

a ##1 b[*->2] ##1 c

bb… …

a

a ##1 b ##2 c

Sequence with Skipped Clock

b c

Expression Repetitiona

a ##1 b[*3] ##1 c

bb c

Expression Rangec

a ##1 b[*3:4] ##1 c

bcbbb

a b ba b

Expression Non-Consecutive “Counting” Repetition

a c

a ##1 b[*=2] ##1 c

b… … …b

b


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Sequence Operations

Sequences can be combined to create new sequencesSequence “and”

s1 and s2

s1s2

Sequence “intersect”

s1 intersect s2

s1s2

Sequence “or”

s1 or s2

s1s2

Sequence Concatenation

s1 ##1 s2

s1 s2

Sequence Overlap

s1 ##0 s2

s1 s2

First Match

first_match(s1)

s1

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More Sequence Operations

Sequences can also use special system tasks and methods

Sequence Ended

s1 ##1 s2.ended

s1s2

!a ##1 $rose(a) ##1$fell(a) ##1 $stable(a)

aTemporal Functions Sequence “within”

another Sequence

s1 within s2

s2s1

a throughout s1a[*0:$] intersect s1

a

s1

Expression “throughout”a Sequence


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Black Box Verification

Sequences can be defined outside of the design models, and “bound” to the design

An assertion can be bound to a specific instance of a module or interfaceAn assertion can be bound to all instances of a module or interface

Binding assertions enables “black box” verificationThe verification engineer defines assertions outside of the design modelsThe verification engineer does not need to change the model in any way

bind module_name_or_instance_name assertion_statement ;

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Special Test Bench “Program Blocks”

Verilog uses modules to model the test benchModules are intended to model hardwareNo special semantics to avoid race conditions with the design

SystemVerilog adds a special “program block” for testingEvents are executed in a “reactive phase”

Synchronized to hardware events to avoid races

program test (input clk, input [15:0] addr, inout [7:0] data);initial begin

@(negedge clk) data = 8’hC4;address = 16’h0004;

@(posedge clk) verify_results;end task verify_results;

...endtask

endprogram

• No race conditions between program block and design blocks

• In a module, this example could have race conditions with the design, if the design used the same posedge of clock.


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Modules versus Programs

I don’t understand what makes a program block different than a module?

What makes the program block unique is SystemVerilog’s

enhanced event scheduling

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Verilog Event Scheduling

NextTime Slot

PreviousTime Slot

Read-Only

Active

Inactive

NBA

• Verilog event scheduling is designed to represent event propagation for combinational and sequential logic

• Verification engineers have to be careful that verification events do not have races with the hardware model events


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SystemVerilog Enhanced Event Scheduling

NextTime Slot

PreviousTime Slot

Postponed

Verilog2001

SystemVerilog3.1

Active

Inactive

NBA

Reactive

Observe

Preponed

Enhanced event scheduling allows assertions and testbench to work together without races

Sample stable values

Evaluate Assertions

Execute program block

statements

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Cycle-Based Verification Timing

Verilog has no special clock semantics for verificationVerification engineers must define special test clocks to avoid race conditions with the design clock

SystemVerilog adds a special “clocking domain” constructSpecifies a test “input skew” and “output skew”

Ensures verification events are offset from the design clockAllows the test bench to use the same clock(s) as the design, without having race conditions with the design


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Object Oriented Classes

SystemVerilog adds C++ like “classes” to the Verilog languageAllows Object Oriented Programming techniques

Primary intent is for use in verificationCan be used in abstract h/w models

Can contain“properties” (data declarations)“methods” (tasks and functions)

Similar to C++InheritancePublic, local or private encapsulationNew objects created andinitialized using newPolymorphism

class Packet ; bit [3:0] command; bit [39:0] address;bit [4:0] master_id;integer time_requested;integer time_issued;integer status;

task clean(); command = 4’h0;address = 40’h0; master_id = 5’b0;

endtask

task issue_request(int delay);...

endtaskendclass

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Dynamic Arraysand Associative Arrays

Verilog has static arraysThe size of the array is fixed at compile time and cannot change

reg [31:0] mem [0:1024];

integer table [0:255];

logic [31:0] mem [];

int table [];

SystemVerilog adds:Dynamic arrays

The size of the array is left open-endedBuilt-in class methods are used to change the array size during simulation

typedef enum {A, B, C, D} state;

int table [state];

data = table[A];

Associative arraysThe index into the array can be non-sequential valuesBuilt-in class methods are used to access the array


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Strings

Verilog uses hardware vector types to store stringsEach character is stored as its 8-bit ASCII codeNo convenient way to work with the string values

reg [31*8:1] myString;myString = “hello world”;

string myString = “hello world”;

SystemVerilog provides a special built-in string data typeStored as a dynamic array — length changes with size of stringBuilt-in methods are used to work with the string

len(), tolower(), toupper(), compare(), icompare(), substr(),getc(), putc(), atobin(), atooct(), atoi(), atohex(), atoreal(),bintoa(), octtoa(), itoa(), hextoa(), realtoa()

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Enhanced Synchronization:Mailboxes and Semaphores

SystemVerilog includes built-in class definitions to synchronize verification activity

SemaphoresRepresents a bucket with a fixed number of keysBuilt-in class methods used to check keys in and outProcess can check out one or more keys, and return them laterIf not enough keys are available, the process execution stops and waits for keys before continuing (gives mutually exclusive control)

MailboxesRepresents a FIFO to exchange messages between processesBuilt-in methods allow adding a message or retrieving a messageIf no message is available, the process can either wait until a message is added, or continue and check again later


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Constrained Random Values

Verilog $random returns a 32-bit signed random numberNo way to constrain the random values returned

SystemVerilog adds:rand built-in class for creating distributed random numbersrandc built-in class for creating cyclic random numbers

Random values can be constrained

class Bus;randc bit[15:0] addr;rand bit[31:0] data;

// constrain addr to be word alignedconstraint word_align {addr[1:0] == 2’b0;}

endclassThe random address value will always have the lower 2 bits set to 0

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Enhanced Fork-Join Processes

Verilog supports parallel processes using fork–joinAll parallel processes must finish execution before continuing

always @(posedge request)beginforksend_packet_task(1,255,0);send_packet_task(7,128,5);

joinstart_results_checker;

end

Both tasks run in parallel

When should the results checker start?

SystemVerilog adds dynamic parallel processes using fork–join_any and fork–join_none

join_any

fork

join

fork

join_none

fork


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Final Blocks

Verilog has two types of procedural blocksinitial blocks

Execute statements once, beginning at time 0always blocks

Execute statements repeatedly, beginning at time 0

initialbegina = 0;#10 a = 1;...end

always @(a or b)beginsum = a + b;diff = a - b;end

initial...#10000 $finish;

final$display(“total errors detected = %d”, err_count);

SystemVerilog adds final blocksExecutes statements once, beginning when simulation finishesRestricted to statements that execute in zero time

To duplicate final block behavior in Verilog requires

using the Verilog PLI

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Direct ProgrammingLanguage Interface

Verilog uses the Programming Language Interface (PLI) to allow Verilog code to call C language code

Powerful capabilities such as traversing hierarchy, controlling simulation, modifying delays and synchronizing to simulation timeDifficult to learnToo complex of an interface for many types of applications

SystemVerilog adds a “Direct Programming Interface” (DPI)Verilog code can directly call C functionsC functions can directly call Verilog functionsNo PLI is needed for these direct function calls

Cannot do everything the PLI can doCan do many things more easily than the PLIIdeal for interfacing to bus-functional models written in C








Summary

What Comes Next...

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SystemVerilog Is An Extensive Set of Enhancements to Verilog-2001!

from C / C++

initialdisableevents wait # @fork–join

$finish $fopen $fclose$display $write $monitor`define ìfdef èlseìnclude `timescale

wire reginteger realtimepacked arrays2D memory

+ = * / %>> <<

modulesparametersfunction/tasksalways @assign

begin–endwhilefor foreverif–elserepeat

Verilog-1995

ANSI C style portsgeneratelocalparamconstant functions

standard file I/O$value$plusargsìfndef èlsif `line@*

(* attributes *)configurationsmemory part selectsvariable part select

multi dimensional arrays signed typesautomatic** (power operator)

Verilog-2001

SystemVerilog

globalsenumtypedefstructuresunionscastingconst

break continuereturn do–while++ -- += -= *= /= >>= <<= >>>= <<<=&= |= ^= %=

intshortintlongint byteshortreal voidalias

interfacesnested hierarchyunrestricted portsautomatic port connectenhanced literalstime values and unitsspecialized procedures

packages2-state modelingpacked arraysarray assignmentsqueuesunique/priority case/ifcompilation unit space

desi

gn

assertionstest program blocksclocking domainsprocess control

mailboxessemaphoresconstrained random valuesdirect C function calls

classesinheritancestrings

dynamic arraysassociative arraysreferences

verif

icat

ion


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But Wait...There’s More!

There are many more enhancements to Verilog that were not covered in this presentation

Tagged unionsStatic and automatic variablesConst constantsNested modulesCoverageAssertion API, coverage API, extensions to Verilog VPIAnd many more enhancements...

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Backward Compatibility

Backward compatibility was top priority during the development of SystemVerilog

The SystemVerilog committee integrated donations from several languages

Donations were reviewed construct by constructConstructs were modified as needed to integrate with VerilogGoal was for existing Verilog models to run with no changes

Only compatibility issue is new keywordsSystemVerilog adds several new keywords to Verilog

New keywords may conflict with signal names in existing Verilog models

Keyword conflict can be handled by parsers and compilersInvocation options, compiler directives, ...


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When Can I Use SystemVerilog?

SystemVerilog provides a large number of enhancements to the Verilog language

It is not feasible to implement all the enhancements all at onceNeed to prioritize what features to add first

User’s want the same features to work in all their tools

Cannot adopt SystemVerilog until EDA companies coordinate effortsEDA companies made it difficult for users to adopt Verilog-2001!

Much of Verilog-2001 still can’t be used due to lack of common supportEngineers won’t use SystemVerilog without common support

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Do EDA CompaniesHave A Plan?

Several EDA companies have formed a “SystemVerilog Interoperability Forum”

Details are at www.sutherland-hdl.com/sv_interop

Implement a “Common Synthesis Subset”Productivity enhancementsRTL modeling enhancementsData encapsulation enhancements

Implement assertionsImplement high-level language features

Abstract modeling enhancements (for BFMs and such)Implement OO verification capabilities



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Conclusion

SystemVerilog is an evolution of the Verilog-2001 standardNew levels of modeling abstraction to handle large designsBridges the canyon between system design and implementation

Accellera is developing the SystemVerilog standardA working standard can be completed in months instead of years

SystemVerilog adds: Productivity enhancementsRTL modeling enhancementsData encapsulation enhancementsAbstract modeling enhancementsAdvanced verification enhancements

SystemVerilog will become part of the IEEE Verilog standard

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What Are You Going To BuildWith SystemVerilog?

Sutherland HDL offers Advanced SystemVerilog Training2-state modeling techniques with SystemVerilog’s new data typesWorking with structures, unions and compound arraysCorrectly using new procedures and operators, and avoiding “gotchas”Design verification using assertions, classes and program blocksThe power of interfaces

visit www.sutherland-hdl.com for details on all our training workshops

Verilog-1995 Verilog-2001SystemVerilog


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Some Recommended References

SystemVerilog For DesignStuart Sutherland, Peter Flake, Simon Davidmann & Phil Moorby, planned, 2003, Kluwer, ISBN: 1-4020-7530-8

SystemVerilog 3.1a Language Reference Manual2004, published by Accellera, an HDL standards organizationwww.accellera.org

The 1364-2001 Verilog HDL Language Reference Manual2001, published by the IEEEwww.ieee.org

Verilog-2001: A Guide to the New Features in the Verilog Hardware Description Language

Stuart Sutherland, 2001, Kluwer, ISBN: 0-7923-7568-8