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Israel, May 4, 2010 1
Using High Level Synthesis for Early Prototyping
Eitan Ohayon, Eli Ben-Zino and Itai Yarom
Israel Design Center, Intel
Israel, May 4, 2010
Semiconductor Trends
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– PC market share (units) 45.2% 40%– Consumer + cellphones (units) 32.4% 40.5%– New king in town: consumer devices
Israel, May 4, 2010
Is it Consumer Electronic device or Computer?
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Israel, May 4, 2010
The market react much faster
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12 Years
Years
3 Years3 Weeks
Israel, May 4, 2010
What does it means for us?
• The ground rules are changing– The market window is smaller– The market pace is much faster– Software is taking a major role– It’s harder to verify each of the system’s
component separately
• How can we address those challenges?
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Israel, May 4, 2010
The Design Flow (Today)
• Separate design teams• Separate development process• Long dev. process• Hard to inject changes
– hard to react to the market
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Project development 24 months
53% 34%8% 5%
Spec
Detailed Spec
RTL Unit Verification Chip Verification Silicon + SWEmulation + SW Dev
Israel, May 4, 2010
Desired Design Flow
• Synchronized design teams
• Synchronized development process
• Short dev. process
• Fast flow for injecting changes– Easy to react to the market
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Silicon + SWProject development 12 months
?
Israel, May 4, 2010
Synchronized Environment
• Enable communication between the different teams using common model.
• Provides:– Synchronized design teams– Synchronized development
process
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Israel, May 4, 2010
The missing link
• Outcomes:– Long development cycle– Hard to inject changes (need to update 3 models)
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There isn’t automatic flow that connects the HLM to
the rest of chip design flow
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HLS Prospective
• Outcomes:– Short development cycle– Easy to inject changes
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Israel, May 4, 2010
Driving the Change
• One step approach:– We want to replace the RTL synthesis with a
new flow: High Level Synthesis (HLS).• Management respond: No way. Too risky.
• Two steps approach:1. Use HLS for Prototype (FPGA)
2. Use HLS for Product (ASIC)• Management respond: ROI looks
good – go ahead with step 1.
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Israel, May 4, 2010
1st step: HLS for Prototyping• We can use the HLM
for the following:– FPGA (Prototype)– Power estimation – Equivalence Checking
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Silicon + SWProject development 18 months
Emulation + SW DevRTL CodingMASEAS
UNIT VerificationFC Verification
Israel, May 4, 2010
HLS to Prototype: DSP Testcases
• DSP testcases:– Band Pass Filter (BPF)– Single Section – IIR
• Results (BPF):– Timing: x2 faster clock with HLS– Gates count: 12% reduction with HLS– Resources: HLS 2 Multipliers / RTL 12
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BPF
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HLS to Prototype: FSM Testcase
• FSM testcase:– Control logic (with FSM)
• Results (with focus on latency)– Timing: x2 faster clock with HLS– Gates count: 5% addition with HLS
• Note:– HLS is excellent tool for exploration of
implementations alternatives
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Israel, May 4, 2010
Implementations Alternatives
Area Reduction
Latency 1st: Area Reduction
2nd: Latency
Israel, May 4, 2010
HLS Pros & ConsPros:
– Provides good results– Connects to the rest of the flow– Enables to explore architecture
and implementations alternatives– Reduces turn-around time for new feature significantly
Cons:– HLM needs to be ‘synthesis compatible’– New expertise are needed– New mindset (new flow)– The flow ramp-up is not trivial
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2nd Step: HLS for Design • Gaining experience
with HLS for FPGA, it’s much easier to go to HLS for Silicon– HLS provides a fast
lane from the HLM to the different views
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Emulation + SW Dev
Silicon + SWProject development 12 months
RTL CodingMASEAS
UNIT VerificationFC Verification
Israel, May 4, 2010
Summary
• HLM enables synchronized development
• HLS provide the connection to between the HLM to the rest of the flow– HLS tools are mature and provide good results
• We recommend on 2 steps approach for adopting HLS:1.Use HLS for Prototype
2.Use HLS for Product
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Israel, May 4, 2010 19
Using High Level Synthesis for Early Prototyping
Eitan Ohayon, Eli Ben-Zino and Itai Yarom
For more info: [email protected]