intel package data book

Introduction 1

1.1 Overview Of Intel Packaging Technology

As semiconductor devices become significantly more complex, electronics designers are challenged to fully harness their computing power. Transistor count in products is expected to exceed 100 million. With a greater number of functions integrated on a die or chip of silicon, manufacturers and users face new and increasingly challenging electrical interconnect issues. To tap the power of the die efficiently, each level of electrical interconnect from the die to the functional hardware or equipment must also keep pace with these revolutionary devices. Package design has a major impact on device performance and functionality.

Today, submicron feature size at the die level is driving package feature size down to the design-rule level of the early silicon transistors. At the same time, electronic equipment designers are shrinking their products, increasing complexity, setting higher expectations for performance, and focusing strongly on reducing cost. To meet these demands, package technology must deliver higher lead counts, reduced pitch, reduced footprint area, provide overall volume reduction, aid in system partitioning, and be cost effective.

Circuit performance is only as good as the weakest link. Therefore, a significant challenge for packaging is to insure it does not gate device performance. While packaging cannot add to the theoretical performance of the device design, it can have adverse effects if not optimized. Package performance, therefore, is the best compromise of electrical, thermal, and mechanical attributes, as well as the form factor or physical outline, to meet product specific applications, reliability and cost objectives.

The continuing demand for higher performance products is requiring levels of package performance unattainable by the molded plastic and ceramic packages of the past decade. These factors have driven a variety of major innovations in Intel packaging. Intel had in past years introduced organic packaging with copper interconnect for improved electrical characteristics. Intel has recently introduced flip chip between die and package as an interconnect approach to further improve performance and offer very compact packaging. This has resulted in new classes of technology using organic substrates for both surface mount (Organic Land Grid Array - OLGA) and thru-hole (Flip Chip Pin Grid Array - FCPGA). The microPGA (µPGA) was introduced to combine flip chip interconnect with a very small form factor and socketability for compact and portable systems. While these packages differ in form factor, all can provide the required electrical and/or thermal performance needed by our advanced products.

Chip scale packaging for memory applications has also been a focus of packaging innovations, with new CSP form factors including stacked die packaging. Portability is expected to continue as a strong driver of new packaging approaches.

Fit, form, and function tend to be market specific. Certain Intel devices serve more than one market need but may require different package attributes. Therefore, "one size fits all" is not a practical approach to device packaging. Packaging technology is not a single technology, but instead consists of more than 20 industry proven combinations of core technologies or core technology sets that can be categorized by package families.

In support of the growing number of Intel devices and to meet the industry demand for package-specific applications, Intel’s package portfolio has more than doubled during the past ten years.

1999 Packaging Databook 1-1

Introduction

1.2 Purpose Of This Databook

Intel’s Packaging Databook serves as a data reference for engineering design, and a guide to Intel package selection and availability. Each chapter provides a comprehensive and in-depth analysis of Intel packaging technology, from information on IC assembly, performance characteristics, and physical constants, to detailed discussions of surface mount technology and Intel shipping and packing.

Chapter 1 Introduction: An overview of package families, including package attributes, package types, and a package selection guide.

Chapter 2 Package / Module / PC Card Outlines and Dimensions: A detailed view of Intel package outlines and dimensions.

Chapter 3 Alumina & Leaded Molded Technology: Statistical tools used in the manufacturing process. Also included is a comprehensive analysis of Intel’s IC assembly manufacturing technology and process flow.

Chapter 4 Performance Characteristics of IC Packages: Package characteristics and data for electrical, mechanical, and thermal IC package characteristics.

Chapter 5 Physical Constants of IC Package Materials: Physical constants of IC package materials. This chapter provides valuable information on mechanical, electrical, and thermal properties of case materials, lead/leadframes, and soldering material characteristics.

Chapter 6 ESD/EOS: An overview of electrical static discharge and electrical over stress.

Chapter 7 Leaded Surface Mount Technology (SMT): A review of the mass reflow soldering technologies of printed circuit board (PCB) component assembly termed SMT (surface mount technology).

Chapter 8 Moisture Sensitivity/Desiccant Packaging/Handling of PSMCs: Desiccant Packing Methods and Materials. The six levels of Moisture Sensitivity for packages is also examined.

Chapter 9 Board Solder Reflow Process Recommendations - Leaded SMT: A review of Board Solder Reflow Process Information.

Chapter 10 Transport Media and Packing: Various packing and shipping methods used at Intel. Packing media, desiccant pack materials, and shipping data are illustrated.

Chapter 11 International Packaging Specifications: A listing of international packaging specifications and a comprehensive resource library.

Chapter 12 Tape Carrier Package: A profile of the Tape Carrier Package and its uses in areas that require lightweight small footprint integrated circuits.

Chapter 13 Pinned Packaging: An overview of Plastic Pin Grid Array Package technology, and its physical structure, electric modeling and performance.

Chapter 14 Ball Grid Array (BGA) Packaging: A profile of the Intel Ball Grid Array technology detailing its physical structure, electrical modeling, performance, and other aspects of the BGA packaging.

Chapter 15 The Chip Scale Package (CSP): An overview of Chip Scale Packaging, and its physical structure, electrical modeling, and performance.

Chapter 16 Cartridge Packaging: An overview of the Single Edge Contact Cartridge and its physical structure, electrical modeling, and performance.

Glossary: Packaging Databook terminology defined.

1-2 1999 Packaging Databook

Introduction

1.3 Package Types

1.3.1 Ceramic Packages

1.3.2 Leadless Chip Carrier Packages

A5582-02

CPGA(Ceramic Pin Grid Array)

C-DIP(Ceramic Dual In-Line Package)(Side-braze)

Socket Mount

Insertionor Socket Mount

(bottom view)

Ceramic Packages

A5600-02

(Bottom View)

Leadless Chip Carrier Package

LCC(Socket Mount)


Introduction

1.3.3 Glass-Sealed Packages

1.3.4 Modules

A5603-01

Glass-Sealed Packages

CERDIP(Ceramic Dual In-Line Package)(Insertion Mount; UV Window)

240817-2

A5686-01

Modules

SIMM(Single In-Line LeadlessMemory Module)

SIP(Single In-Line LeadedMemory Module)

(Top View)

(Top View)

240817-2


Introduction

1.3.5 Plastic Packages - Surface Mount

A5684-01

Plastic Packages- Surface Mount

Dual Row

Small OutlinePackages

(SOP)

Quad Row

PSOP(Plastic Small Outline Package)(Gull-Wing)

SSOP(Shrink Small Outline Package)(Gull-Wing)

SOJ(Small Outline Package)(J-Lead)

TSOP(Thin Small Outline Package)(Gull-Wing)

PBGA / H-PBGA / HL-PBGA(Plastic Ball Grid Array)

FLATPACK

QFP(Quad Flatpack)

PLCC(Plastic Leaded Chip Carrier)

PQFP(Plastic Quad Flatpack)

MICRO BGA

240813-3

(bottom view)

(bottom view)


Introduction

1.3.6 Plastic Packages - Insertion Mount/Socket Mount

Plastic PackagesInsertion Mount (wave solder or socketed)

Plastic PackagesSocket Mount

P-DIP(Plastic Dual In-Line Package)

SHRINK DIP(Shrink Dual In-Line Package)

Dual Row

Socket MountPPGA(Plastic Pin Grid Array)

µPGA and FC-PGA can be found in Chapter 13 "pinned packages"

(bottom view)


Introduction

1.3.7 PCMCIA PC Card - Type 1 and Type 11

A5586-01240817-6

WPS

Connector

WPS

Connector

Battery

Type I

Type II


Introduction

1.3.8 S.E.C. Cartridge (242 Contact)

1.3.9 S.E.C. Cartridge (330 Contact)

A5734-01001013

(front view)

A6175-01


Introduction

1.4 Package Attributes

Note: For Package Attribute information on Pinned Packages (Chapter 13), BGA (Chapter 14), and Chip Scale Packages (Chapter 15) please consult their individual chapters.

1.4.1 Ceramic Package Attributes

Table 1-1. Ceramic Dual In-Line Package (C-DIP)(Side Brazed)

Lead Count 40

Sq./Rect. R

Pitch (Inches) 0.100

Package Thickness(Inches)

0.154*0.123

Weight (gm)

Max. Footprint(Inches)

2.020

UV Erasable x

Shipping Media:

Tubes x

Comments / Footnotes * EPROM LID

Table 1-2. Leadless Chip Carrier (LCC)

Lead Count 68 68

Sq/Rect. S S

Pitch (Inches) 0.050 0.050

Package Thickness(inches) 0.096 0.130

Weight (gm) 4.67 4.67

Max. Footprint (Inches) 0.960 0.960

UV Erasable x

Shipping Media:

Tubes x x

Comments / Footnotes


Introduction

Table 1-3. Ceramic Pin Grid ArrayLead Count 68 68 68 88 88 132 168 208 240-

280272-320

387

Sq/Rect. S S S* S S S S S S S R

Pitch (Inches) 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100 0.100/0.50

0.100/0.50

0.100/0.50

Package Thickness

(inches)

0.105 0.110 0.125 0.105 0.110 0.110 0.110 0.110 0.110 0.110 0.110*

Weight (gm) 8.69 8.69 8.69 10.43 10.43 16.07 23.3 84

Max. Footprint (Inches)

1.180 1.180 1.180 1.380 1.380 1.480 1.780 1.780 1.980 2.170 2.670

UV Erasable x

Shipping Media:

Trays x x x x x x x x x x x


* With EPROM


Introduction

Table 1-4. CERDIP

Lead Count 20 28 40

Sq/Rect. R R R

Pitch (Inches) 0.100 0.100 0.100

Package Thickness (inches)

0.153 0.167 0.167

Weight (gm) 2.87 8.68 12.03

Max. Footprint (Inches)

0.995 1.485 2.085

UV Erasable x x x

Shipping Media:

Tubes x x x


Inquire as to the availability with UV Window.


Introduction

1.4.2 Plastic Package Attributes

Table 1-5. Plastic Dual In-Line (PDIP)

Lead Count 24 28 32 40 64

Sq/Rect. R R R R R

Pitch (Inches) 0.100 0.100 0.100 0.100 0.100

Package Thickness (inches)

0.152 0.152 0.150 0.160 0.167

Weight (gm) 1.67 1.94 4.815 6.128 12.05


1.260 1.470 1.655 2.070 2.290

Shipping Media:

Tubes x x x x x

Comments /Footnotes

Some pin counts available in: Half lead, Wide body, Wide Body, and Standard Type P

Table 1-6. Plastic (Flatpack)

Lead Count 68

Sq/Rect. S

Pitch (Inches) 0.050

Package Thickness (inches) 0.168

Weight (gm) 5.6

Max. Footprint (Inches) 1.780

UV Erasable

Shipping Media:

Trays x

Comments / Footnotes Through Hole Use Only

Table 1-7. Plastic Quad Flatpack (PQFP)

Lead Count 84 100 132 164 *196

Sq/Rect. S S S S S

Pitch (Inches) 0.025 0.025 0.025 0.025 0.025

Package Thickness (inches) 0.170 0.170 0.170 0.170 0.170

Weight (gm) 2.07 2.8 4.2 6.1 8.55


0.790 0.890 1.090 1.290 1.490

UV Erasable

Shipping Media:

Tubes

Tape & Reel

Trays

xxx

xxx

xxx

xxx

xxx

Desiccant Pack x x x x x

Comments / Footnotes All PQFPs are “Gull Wing” with bumpers*MM-PQFP


Introduction

Table 1-8. Quad Flatpack

Lead Count 44 48 64 80 80 100 100 128 144 160 176 208

Sq/Rect. S S S S R S R S S S S S

Pitch (mm) 0.80 0.80 0.65 0.50 0.80 0.50 0.80 0.80 0.50 0.65 0.50 0.50

Package Thickness (mm)

2.35 2.55 2.55 1.66 3.15 1.66 3.15 3.65 1.5 3.65 1.5 3.56

Weight (gm) 0.42 0.71 0.50 1.65 0.64 1.65 5.1810.85*


0.50 0.61 0.61 0.56 0.72 0.64 0.72 1.27 .881 1.22 1.03 1.220

Shipping Media:

Trays x x x x x x x x x x x x

Desiccant Pack x x x x x x x x x x x x


Gull Wing lead Configuration, non-bumped

* With heat slug

Table 1-9. Plastic Leaded Chip Carrier (PLCC)

Lead Count 28 28 32 44 52 68 84

Sq/Rect. S R R S S S S

Pitch (mm) 0.050 0.050 0.050 0.050 0.050 0.050 0.050


0.152 0.108 0.108 0.148 0.150 0.150 0.150

Weight (gm)

1.15 0.85 1.1 2.31 3.17 4.8 6.2


0.495 See Note See Note 0.695 0.795 0.995 1.195

Shipping Media

Tubes

Tape & Reel

Trays

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

Desiccant Pack

x x x x x x x


All PLCCs are “J” Lead28R--0.39 x 0.5932R--0.48 x 0.59

Table 1-10. Small Outline Package J-Lead (SOJ)

Lead Count 20 24

Sq/Rect. R R

Pitch (mm) 1.27 1.27

Package Thickness (mm) 0.105 0.113

Weight (gm) 0.50 0.62


Shipping Media:

Tape & Reel

Tray

x

x

x

x


Introduction

Package attributes for Plastic Ball Grid Array can be found in Chapter 14. Package attributes for Micro Ball Grid Array can be found in Chapter 15.

Desiccant Pack x x

Comments / Footnotes “J” Configuration

Table 1-11. Plastic Small Outline Package (PSOP)

Lead Count 44

Sq/Rect. R

Pitch (mm) 1.27

Package Thickness (mm) 2.95

Weight (gm) 1.89


Shipping Media

Tubes

Tape & Reel

Trays

x

x

x

Desiccant Pack x

Comments / Footnotes Gull Wing Lead Configuration

Table 1-12. Thin Small Outline Package (TSOP)

Lead Count 32 40 48 56

Sq/Rect. R R R R

Pitch (mm) 0.50 0.50 0.50 0.50

Package Thickness (mm) 0.0392 0.039 0.039 0.039

Weight (gm) 0.37 0.46 0.56 0.63


0.795 0.795 0.795 0.795

Shipping Media:

Tape & Reel

Trays

x

x

x

x

x

x

x

x

Desiccant Pack x x x x

Comments / Footnotes TSOP is “Gull Wing” Configuration

Table 1-13. Shrink Small Outline Package (SSOP)

Lead Count 56

Sq/Rect. R

Pitch (mm) 0.80


Weight (gm) 1.15


Shipping Media:

Tape & Reel

Trays

x

x

Desiccant Pack x

Comments / Footnotes Gull Wing Lead Configuration

Table 1-10. Small Outline Package J-Lead (SOJ)


Introduction

1.4.3 Module Attributes

Table 1-14. Single In-Line Leaded Memory Module (SIP)

Lead Count 30

Sq/Rect. R

Pitch (mm) 2.54


Weight (gm)


Shipping Media:

Tape & Reel x

Comments / Footnotes Insertable Module

Table 1-15. Single In-Line Leadless Memory Module (SIMM)

Lead Count 30 80

Sq/Rect. R R

Pitch (Inches) 0.100 0.050

Package Thickness (inches) 0.20 0.33

Weight (gm) 15.7


Shipping Media

Tubes

Tape & Reel xx

Comments / Footnotes JEDEC Standard Insertable Module


Introduction

1.5 Package/Module/PC Card Selection Guide

Table 1-16. Package / Module / PC Card Selection Guide (Sheet 1 of 2)

Package Type DescriptionAvailable

Lead CountsMarketing Designator Special Notes

Ceramic Dual-In-Line (C-DIP). 0.100” Pitch, Socket or Insertion Mount24, 28, 40, 48 C-DIPs Available with EPROM or Solid Lid32 C-DIP Available with EPROM (lid) Only

161822

24

28324048

CCC

C

CCCC

Ceramic Leadless Chip Carrier (LCC), 0.050”Pitch, Socket or Surface Mount32, 44, and 68 LCCs Available with EPROM orSolid Lid

182028

32

4468

RRR

R

RR

Ceramic Pin Grid Array (CPGA), 0.100” Pitch for 68L - 208L, 0.100/0.50” for 264L- 387L

Socket or Insertion Mount

68L and 88L “Cavity Up” Available with EPROM or Solid Lid

688888

132168

208240-280272-320

387

AAA

AA

AAA

Cavity Down

Cavity DownCavity Down

Cavity DownCavity DownCavity DownCavity Down

Ceramic Quad Flatpack (CQFP), 68L Available in 0.050” Pitch. 164L and 196L Available in 0.025” Pitch, Socket or Surface Mount

68164196

QKK

Flat LeadsFlat LeadsFlat Leads

Ceramic Dual-In-Line Package (CERDIP), 0.100” Pitch

Socket or Insertion Mount

1618202224

242828324042

DDDD

DP

DDPDDDD

.300”

.300”

Plastic Dual-In-Line Package (PDIP); 0.100” Pitch

64L “Shrink DIP” has a 0.070” PitchSocket and Insertion Mount

1618202424

282832404864

PPPP

PD

PPDPPPU

.300”

.300”

Shrink


Introduction

Plastic Flatpack (PFP), 0.050” Pitch Shipped in Carrier with flat Lead, Through-Hole Mount

68 FP

Plastic Leaded Chip Carrier (PLCC), 0.050: PitchSurface or Surface Mount28L is Available in a Square and Rectangular Package Body32L is Available in a Rectangular Package Body Only

20283244

52

6884

NNNN

N

NN

Sq.Sq./Rect.

Rect.Sq.

Sq.

Sq.Sq.

Plastic Quad Flatpack (PQFP), 0.025” Pitch, Surface Mount

Some Packages Available in a Variety of Options: Die UP, Die Down, and Die Down with Heat spreader

84

100132164

196

KD

KD, KU, NGKD, KU, NG

KU

KU

Quad Flatpack (QFP), Variable Lead Pitch Surface Mount

Quad Flatpack (QFP), Surface Mount, Copper Lead Frame

44486480

100128144160176208208

SSS

SB, S

SB,SS

SBS

SBSBSB

Sq./Rect.

Sq./Rect.

Plastic Ball Grid Array (PBGA) 208272324352

FWFWFWGC

Sq.

Plastic Pin Grid Array (PPGA) 296 FV Sq.

Micro Ball Grid Array* (uBGA) 40,

48

G

G

Rect.

Small Outline J-Lead (SOJ), 1.27 mm Pitch Surface Mount

2024

PEPE

Plastic Small Outline Package (PSOP), 1.27 mm Pitch, Surface Mount

44 PA

Shrink Small Outline Package (SSOP), 0.80 mm Pitch, Surface Mount

56 DA

Thin Small Outline Package (TSOP) Pitch, Surface Mount Available in Die Up or Die Down (32, 40 only)

32, 404856

E, RE

E, DD

Single In-Line Leaded Memory Module (SIP), 2.54 mm Pitch, Socket or Insertion Mount

30 GB

Single In-Line Leadless Memory Module (SIMM)0.100” Pitch, Connector Mount

30

80

SM

SM

Single Edge Contact Cartridge (S.E.C.C) 242

330

Cartridge mounts in a slot

connector

Table 1-16. Package / Module / PC Card Selection Guide (Sheet 2 of 2)


Introduction

1.6 Revision Summary

• Added S.E.C.C. (330 Contact) figure & information.

• Revised the introduction

• General review of the chapter


Package / Module / PC Card Outlines and Dimensions 2

A5581-02

Intel Product Identification Codes

NG

Package Type

AIL

Q

T

ABCDDPEFFPFW

FVGGBGCKKAKDKUNNGPPAPDPEQRSSBSMUX

–––––––––

–––––––––––––––––––––

Indicates automotive operating temperature range.Indicates industrial grade.Indicates extended operating temperature range (-40˚C to +85˚C) express product with160 ± 8 hrs. dynamic burn-in.Indicates commercial temperature range (0˚C to +70˚C) express product with 160 ± 8 hrs.dynamic burn-in.Indicates extended temperature range (-40˚C to +85˚C) express product without burn-in.

Ceramic Pin Grid ArrayCeramic Land Grid ArrayCeramic Dual In-Line PackageCerdip Dual In-Line PackageCerdip Dual In-Line Package, 300 MILThin Small Out-Line Package, Die UpThin Small Out-Line Package, Die DownPlastic Flatpack PackagePlastic Ball Grid Array Die Up 1.27 mm Solder Ball PitchPlastic Pin Grid Array, Cavity Down, Staggered PinMicro Ball Grid ArraySingle In-Line Leaded Memory ModuleHL-PBGA-Thermally Enhanced, Plastic Ball Grid ArrayCeramic Pin Grid ArrayCeramic Pin Grid Array, Dual Cavity, Die DownPlastic Quad Flatpack Package, Fine Pitch, Die DownPlastic Quad Flatpack Package, Fine Pitch, Die UpPlastic Leaded Chip CarrierPlastic Quad Flatpack, Fine Pitch, Die Down with Heat Spreader Plastic Dual In-Line PackageSmall Out-Line "Gull-Wing" PackagePlastic Dual In-Line Package, 300 MILSmall Out-Line "J"-Lead PackageCeramic Quad Flatpack PackageCeramic Leadless Chip CarrierQuad Flatpack PackageShrink Quad Flatpack PackageSingle In-Line Leadless Memory ModulePlastic Dual In-Line Package, Shrink DipUnpackaged Devices

8 0 3 8 6 S X 1 6 S X 3 8 7

Up to15 Alphanumeric CharactersFor Device Types

Up to 6 Alphanumeric Charactersto Show Customer-Specific

Requirements

___

_

_


Package / Module / PC Card Outlines and Dimensions

2.1 Ceramic Side Braze Dual In-line Package

2.1.1 Symbol List for Ceramic Side Braze Dual In-Line Family

Letter or Symbol Description of Dimensions

α Angular spacing between minimum and maximum lead positions measured at the gauge plane

A Distance from seating plane to highest point of body (lid)

A1 Distance between seating plane and base plane

A2 Distance from base plane to highest point of body (lid)

A3 Base body thickness

B Width of terminal leads

B1 Width of terminal lead shoulder which locates seating plane (standoff geometry optional)

C Thickness of terminal leads

D Largest overall package dimension of length

D2 A body length dimension, end lead center to end lead center

E Largest overall package width dimension outside of lead

E1 Body width dimensions not including leads

e1 Linear spacing between centerlines of body standoffs (terminal leads)

eA Linear spacing of true minimum lead position center line to center line

eB Linear spacing between true lead position outside of lead to outside of lead

L Distance from seating plane to end of lead

N The total number of potentially usable lead positions

S Distance from true position centerline of No. 1 lead position to the extremity of the body

S1 Distance from outer end lead edge positions to the extremity of the bodyNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P. C. board hole size: 0.0415-0.0430 inch.

Packaging Family Attributes

Category Ceramic Dual-In-Line

Acronym C-DIP or Side Brazed

Lead Configuration Sidebraze

Lead Counts 40

Lead Finish Gold Plate / Solder Coat

Lead Pitch 0.100”

Board Assembly Type Socket and Insertion Mount

NOTES:1. Alloy 42 or Kovar leads. 2. Multilayer Co-Fired Ceramic Body.



2.1.2 40 Lead Ceramic Dual In-Line Package (Side Brazed)

A5438-01

N

EE1Pin #1

Indicator Area

e1B

B1

D2

DS S1

Seating PlaneBase Plane

LA1 A2A3 A

eB

eA

C

1369-02231369-2

Family: Ceramic Side Braze Dual In-Line

SymbolMillimeters Inches

Min Max Notes Min Max Notes

α 0 ° 10 ° 0 ° 10 °

A 3.30 5.51 Solid Lid 0.130 0.217 Solid Lid

A 4.04 6.58 EPROM Lid 0.159 0.259 EPROM Lid

A1 1.02 1.52 0.040 0.060

A2 2.29 3.99 Solid Lid 0.090 0.157 Solid Lid

A2 3.02 4.88 EPROM Lid 0.119 0.190 EPROM Lid

A3 2.03 3.66 0.080 0.144

B 0.38 0.56 0.015 0.022

B1 1.27 Typical 0.050 Typical

C 0.23 0.30 Typical 0.009 0.012 Typical

D 50.29 51.31 1.980 2.020

D2 48.26 Reference 1.900 Reference

E 15.24 15.75 0.600 0.620

E1 14.86 15.37 0.585 0.605

e1 2.29 2.79 0.090 0.110

eA 14.99 Reference 0.590 Reference

eB 15.24 17.15 0.600 0.675

L 3.18 4.06 0.125 0.160

N 40 40

S 0.76 1.78 0.030 0.070

S1 0.13 0.005



2.2 Ceramic Leadless Chip Carrier

2.2.1 Symbol List for Ceramic Leadless Chip Carrier Family


A Thickness of body

A1 Total package height

A2 Distance from top of base to highest point of body lid

B Width of terminal lead pin


D1, E1 A body length dimension, corner cutout to corner cutout or end lead center to end lead center

D2, E2 A body length dimension, end lead center to end lead center

D3, E3 A body length dimension, corner cutout to index corner cutout

D4, E4 Ceramic body fixture

E Largest overall package dimension of width

e Linear spacing

e1 Linear spacing between edges of true lead positions (corner terminal lead pads) lead corner to lead corner

h Depth of major index feature

j Width of minor index feature

L Distance from package edge to end of effective pad


R1 Inner notch radiusNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P. C. board hole size: 0.0415-0.0430 inch.4. Dimensions “B”, “B1”, and “C” are nominal.5. Corner configuration optional.


Category Ceramic Leadless Chip Carrier

Acronym LCC

Lead Configuration N/A

Lead Counts 68

Lead Finish Gold Plate

Lead Pitch 0.050”

Board Assembly Type SocketNOTES: 1. 68L not certified for Surface Mount. Must be socketed.2. Multilayer Co-Fired Ceramic Body.



2.2.2 68 Ceramic Leadless Chip Carrier Variation: Die Down

A5448-01

A

D3

E3

R1

L

e

D

D2

D1

Terminal #1

BE

E1E2

(Index Corner)Seating Plane

Plane 1Plane 2

E4

A1

D4

N

231369-10

Family: Ceramic Leadless Chip Carrier



A 1.37 1.68 0.054 0.066

A1 2.16 2.72 0.085 0.107

B 0.84 0.99 Typical 0.033 0.039 Typical

D 23.88 24.38 0.940 0.960

D1 21.39 21.39 0.842 0.858



D4 16.76 17.27 0.660 0.680

E 23.88 24.38 0.940 0.960

E1 21.39 21.79 0.842 0.858

E2 20.32 Reference 0.800 Reference


E4 16.76 17.27 0.660 0.680

e 1.04 1.50 Typical 0.041 0.059 Typical

L 0.94 0.037

N 68 68

R1 0.25 0.010



2.2.3 68 Ceramic Leadless Chip Carrier Variation: Die Up

A5446-02

A

D3

E3

L

e

D

D2

D1

N

Terminal #1

BEE1

E2

45˚ Chamfer(index corner) Seating Plane

Plane 2Plane 1

E4

A1

R1

231369-11

Family: Ceramic Leadless Chip Carrier



A 1.91 2.41 0.075 0.095

A1 2.92 3.68 W/EPROM 0.115 0.145 W/EPROM

B 0.84 1.12 0.033 0.044

D 23.88 24.38 0.940 0.960

D1 21.39 21.79 0.842 0.858



E 23.88 24.38 0.940 0.960

E1 21.39 21.79 0.842 0.858



E4 14.33 15.14 0.564 0.596

e 1.04 1.50 Typical 0.041 0.059 Typical

L 1.27 0.050

N 68 68

R1 0.25 0.010



2.3 Ceramic Pin Grid Array Package

2.3.1 Symbol List for Square Ceramic Pin Grid Array Family


A Distance from seating plane to highest point of body


A2 Distance from base plane to highest point of body

A3 Distance from seating plane to bottom of body

A4 Heat spreader thickness

B Diameter of terminal lead pin


D1 A body length dimension, outer lead center to outer lead center

D2 Heat spreader length and width

e1 Linear spacing between true lead position centerlines



S1 Other body dimension, outer lead center to edge of bodyNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415 - 0.0430 inch.4. Dimensions “B”, “B1” and “C” are nominal.5. Details of Pin 1 identifier are optional


Category Ceramic Pin Grid Array

Acronym C-PGA or PGA

Lead Configuration Array

Lead Counts 68, 88, 132, 168-208, 240-280, 272-320

Lead Finish Gold Plate, 60 Micro inches of Gold over 100-350 Micro inches of Nickel Plate

Lead Material Alloy 42 or Kovar

Lead Braze Material Copper/Silver Eutectic

Lead Pitch 0.100”

Board Assembly Type Socket and Insertion MountNOTES: 1. Alloy 42 or Kovar Leads.2. Multilayer Co-Fired Ceramic Body.3. Some body sizes have variable pin count.



2.3.2 68 Lead Ceramic Pin Grid Array Package

A5501-01

D

A3

1.020.25

D

D1

Swaged Pin(4 PL)

Base PlaneA2

A1

e1

A

S1

Ref.

45˚ Chamfer(3 PL)

2.291.52

45˚ Chamfer(index corner)

Ref.

01.65Ref.

Pin B2

L

Seating Plane

SeatingPlane

Swaged PinDetail

0B (all pins)

Family: Ceramic Pin Grid Array Package



A 3.56 4.57 0.140 0.180


A1 0.41 EPROM Lid 0.016 EPROM Lid


A2 3.43 4.32 EPROM Lid 0.135 0.170 EPROM Lid

A3 1.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 28.95 29.97 1.140 1.180

D1 25.27 25.53 0.995 1.005

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 68 68

S1 1.27 2.54 0.050 0.100




A5503-01

D

A3

1.020.25

D

D1

Swaged Pin(4 PL)

Base PlaneA2

A1

e1

A

S1

Ref.

45˚ Chamfer(3 PL)

2.291.52


Ref.

01.65Ref.

Pin B2

L

Seating Plane

SeatingPlane

Swaged PinDetail

0B (all pins)




A 3.56 4.57 0.140 0.180



A3 1.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 34.03 35.05 1.340 1.380

D1 30.35 30.61 1.195 1.205

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 88 88

S1 1.27 2.54 0.050 0.100




A5504-01

D

A3

1.020.25

Swaged Pin(4 PL)

Base PlaneA2

A1

e1

A

S1

Ref.

45˚ Chamfer(3 PL)

2.291.52


Ref.

01.65Ref.

Pin C3

L

Seating Plane

SeatingPlane

Swaged PinDetail

0B (all pins)

DD1

231369-16




A 3.56 4.57 0.140 0.180



A3 1.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 36.57 37.59 1.440 1.480

D1 32.89 33.15 1.295 1.305

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 132 132

S1 1.27 2.54 0.050 0.100



2.3.5 1.75” Sq. Ceramic Pin Grid Array Package

A5505-01

D

A3DD1

Swaged Pin(4 PL)

Base PlaneA2

A1

e1

A

S1

2.291.52


Ref.

01.65Ref.

L

Seating Plane

SeatingPlane

Swaged PinDetail

0B (all pins)

Pin C3

Pin D4(optional)




A 3.56 4.57 0.140 0.180



A3 1.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 44.19 45.21 1.740 1.780

D1 40.51 40.77 1.595 1.605

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 168/208 168/208

S1 1.52 2.54 0.060 0.100



2.3.6 1.95” Sq. Ceramic Pin Grid Array Package

A5506-01

D

A3

DD1

Base PlaneA2

A1

e1

A

S1

2.291.52


Ref.

01.65Ref.

L

Seating Plane

SeatingPlane

Swaged PinDetail

0B (all pins)

Swaged Pin(4 PL)

Pin D4

Pin E5(optional)

231369-19




A 3.56 4.57 0.140 0.180

A1 0.64 1.14 Ceramic Lid 0.025 0.045 Ceramic

A2 2.79 3.56 Ceramic Lid 0.110 0.140 Ceramic

A3 1.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 49.27 50.29 1.940 1.980

D1 45.59 45.85 1.795 1.805

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N 240 280 240 280

S1 1.52 2.54 0.060 0.100



2.3.7 1.95” Sq. Ceramic Pin Grid Array Package Variation: Without Stand-Off Pins

A5508-01

D

DD1

Base Plane

A2A1

0B

e1

S1

2.291.52


Ref.

01.65Ref.

L

Seating Plane

Pin E5(optional)

Pin D4

A

231369-86




A 2.51 3.07 0.099 0.121

A1 0.33 0.43 Metal Lid 0.013 0.017 Metal

A2 2.84 3.51 Metal Lid 0.112 0.138 Metal

B 0.43 0.51 0.017 0.020

D 49.53 50.29 1.940 1.980

D1 45.59 45.85 1.795 1.805

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.120 0.130

N 240 280 240 280

S1 1.52 2.54 0.060 0.100



2.3.8 2.16” Sq. Ceramic Pin Grid Array Package Variation: Without Stand-Off Pins

A5510-01

D

DD1

Base Plane

A2

0B

S1

2.291.52


Ref.

01.65Ref.

L

Seating Plane

Pin D4

A

e1

A1

231369-91




A 2.62 2.97 0.103 0.117

A1 0.38 0.43 Metal Lid 0.015 0.017 Metal Lid


B 0.43 0.51 0.017 0.020

D 54.61 55.12 2.150 2.170

D1 50.67 50.93 1.995 2.005

e1 2.29 2.79 0.090 0.110

L 2.54 3.30 0.120 0.130

N 272 320 272 320

S1 1.651 2.16 0.065 0.085



2.3.9 2.16” Sq. Ceramic Pin Grid Array Package Variation: Without Stand-Off Pins, With Heat Spreader

A5511-01

D

DD1

Base Plane

A

0B

S1

2.291.52


Ref.

01.65Ref.

LSeating Plane

Pin D4

A2

e1

A1

D2

A4

231369-92




A 3.59 4.19 Metal Lid 0.141 0.165 Metal Lid


A2 2.62 2.97 0.103 0.117

A4 0.97 1.22 0.038 0.048

B 0.43 0.51 0.017 0.020

D 54.61 55.12 2.150 2.170

D1 50.67 50.93 1.995 2.005

D2 37.85 38.35 1.490 1.510

e1 2.29 2.79 0.090 0.110

L 3.05 3.30 0.120 0.130

N 272 320 272 320

S1 1.651 2.16 0.065 0.085



2.3.10 1.95” Sq. Ceramic Pin Grid Array Package Variation: Without Stand-Off Pins, Staggered 0.100” Pitch With Heat Spreader

A5509-01

D

DD1

Base Plane

A1A2

0B

e1

S1

2.291.52


Ref.

01.40Ref.

LSeating Plane

Pin B2A

D2

A4

231369-93




A 3.59 4.19 Metal Lid 0.141 0.165 Metal Lid


A2 2.62 2.97 0.103 0.117

A4 0.97 1.22 0.038 0.048

B 0.43 0.51 0.017 0.020

D 49.28 49.78 1.940 1.960

D1 45.59 45.85 1.795 1.805

D2 31.50 32.00 1.240 1.260

e1 2.29 2.79 0.090 0.110

L 3.05 3.30 0.120 0.130

N 264 372 264 372

S1 1.52 2.54 0.060 0.100



2.3.11 1.95” Sq. Ceramic Pin Grid Array Package Variation: Without Stand-Off Pins, Staggered 0.100” Pitch

A5512-01

D

D

D1

A1A2

0B

e1

S1

2.291.52


Ref.

01.65Ref.

LSeating Plane

Pin C3A

S1

D1

231369-A0




A 2.62 2.97 0.103 0.117

A1 0.69 0.84 Ceramic Lid 0.027 0.033 Ceramic Lid

A2 3.31 3.81 Ceramic Lid 0.130 0.150 Ceramic Lid

B 0.43 0.51 0.017 0.020

D 49.28 49.78 1.940 1.960

D1 45.59 45.85 1.795 1.805

e1 2.29 2.79 0.090 0.110

L 3.05 3.30 0.120 0.130

N 264 372 264 372

S1 1.52 2.54 0.060 0.100



2.3.12 Ceramic Rectangular Pin Grid Array Package Family


A Distance from seating plane to top of spreader


A2 Distance from base plane to highest point of body

A3 Distance from seating plane to bottom of body

A4 Head spreader thickness

A5 Pin center to lid clearance

B Diameter of terminal pin

D Largest overall package dimension width

D1 Body width dimension, outer lead center to outer lead center

D2 Heat spreader width

E Largest overall package dimension length

E1 Body length dimension, outer lead center to outer lead center

E2 Heat spreader length

e1 Linear spacing between true lead position centerlines

e2 Linear spacing between true lead position centerlines “staggered pitch”

F1 Capacitor clearance area






N Lead count

S1 Other body dimensions, outer lead center to edge of bodyNOTES: 1. Controlling dimensions: Inches.2. Dimensions “e1” (e) is non-cumulative.3. Details of Pin 1 identifier are optional.


Category Ceramic Pin Grid Array

Acronym CPGA, PGA or SPGA

Lead Configuration Array

Lead Counts 387

Lead Material Kovar over Alloy 42

Lead Pitch 0.100” Staggered

Board Assembly Type Socket MountNOTES: 1. Alloy 42 or Kovar leads.2. Multilayer Co-Fired Ceramic Body.




A5513-01

E

DD1

Base Plane

A

0B

S1

2.291.5245˚ Chamfer(index corner)

Ref.

01.40Ref.

LSeating Plane

Lid

A2

e1

A1

A4A5

E1

e2

E2

D2

F1

F2

F3

F4

Spreader

Chip CapacitorClearance Area

A

F5

Pin B2



Min Max Notes Min Max NotesA 3.56 4.19 0.140 0.165A1 — 1.19 Solid Lid — 0.047 Solid LidA2 — 5.46 Solid Lid — 0.215 Solid LidA4 0.97 1.22 0.038 0.048A5 1.07 — 0.042 —B 0.43 0.51 0.017 0.020D 62.23 62.74 2.450 2.470D1 58.29 58.55 2.295 2.305D2 30.48 35.56 1.200 1.400E 67.31 67.82 2.650 2.670E1 63.37 63.63 2.495 2.505E2 56.26 56.77 2.215 2.235e1 2.29 2.79 0.090 0.110e2 1.02 1.52 0.040 0.060F1 — 26.04 — 1.025F2 9.65 0.290 —F3 9.65 — 0.380 —F4 — 4.95 — 0.195F5 — 1.22 — 0.048L 3.05 3.30 0.120 0.130N 387 387S1 1.52 2.54 0.060 0.100



2.4 Cerdip Dual In-line Package

2.4.1 Symbol List for Cerdip Dual In-Line Family







B1 Width of terminal lead shoulder which locate seating plane (standoff geometry optional)












S1 Distance from outer end lead edge positions to the extremity of the body

α Angular spacing between minimum and maximum lead positions measured at the gauge planeNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415 - 0.0430 inch.4. Dimension “B1” is normal.

Package Family Attributes

Category Cerdip

Acronym Cerdip

Lead Configuration Dual-In-Line

Lead Counts 20, 28, 40

Lead Finish Hot Solder Dip

Lead Pitch 0.100”

Board Assembly Type Socket and Surface MountNOTES: 1. Alloy 42 Leads.2. Pressed Ceramic Body.3. UV Window is available for reprogramming.



2.4.2 20 Lead Cerdip Dual In-Line Package

A5522-01

N

e1B

B1

D2

DS S1


LA1 A2A3 A

eB

eA

C

EE1Pin #1

Indicator Area

Family: Cerdip Dual In-Line Package



α 0 ° 10 ° 0 ° 10 °

A 5.08 0.200

A1 0.38 0.015

A2 3.56 4.44 0.140 0.175

A3 3.56 4.44 0.140 0.175

B 0.41 0.51 0.016 0.020



D 24.38 25.27 0.960 0.995


E 7.62 8.13 0.300 0.320

E1 7.11 7.90 0.280 0.311

e1 2.29 2.79 0.090 0.110


eB 8.13 10.16 0.320 0.400

L 3.18 3.81 0.125 0.150

N 20 ½ Leads 20 ½ Leads

S 0.38 1.78 0.015 0.070

S1 0.13 0.005



2.4.3 28 Lead Cerdip Dual In-Line Package (600 MIL)

A5522-01

N

e1B

B1

D2

DS S1


LA1 A2A3 A

eB

eA

C

EE1Pin #1

Indicator Area




α 0 ° 10 ° 0 ° 10 °

A 5.72 0.225

A1 0.38 0.015

A2 3.56 4.95 0.140 0.195

A3 3.56 4.70 0.140 0.185

B 0.41 0.51 0.016 0.020



D 36.58 37.72 1.440 1.485


E 15.24 15.75 0.600 0.620

E1 13.08 15.37 0.515 0.605

e1 2.29 2.79 0.090 0.110


eB 15.75 17.78 0.620 0.700

L 3.18 4.32 0.125 0.170

N 28 28

S 1.40 2.29 0.055 0.090

S1 0.13 0.005



2.4.4 40 Lead Cerdip Dual In-Line Package

A5522-01

N

e1B

B1

D2

DS S1


LA1 A2A3 A

eB

eA

C

EE1Pin #1

Indicator Area




α 0 ° 10 ° 0 ° 10 °

A 5.72 0.225

A1 0.38 0.015

A2 3.56 4.95 0.140 0.195

A3 3.56 4.70 0.140 0.185

B 0.41 0.51 0.016 0.020


C 0.23 0.30 0.009 0.012

D 51.69 52.96 2.035 2.085


E 15.24 15.75 0.600 0.620

E1 13.08 15.37 0.515 0.605

e1 2.29 2.79 0.090 0.110


eB 15.75 17.78 0.620 0.700

L 3.18 4.32 0.125 0.170

N 40 40

S 1.40 2.29 0.055 0.090

S1 0.13 0.005



2.5 Plastic Dual In-line Package

2.5.1 Symbol List for Plastic Dual In-Line Family


α Angular spacing between minimum and maximum lead positions measured at the gauge plane

A Distance from seating plane to highest point of body (lid)





B1 Width of terminal lead shoulder which locates seating plane (standoff geometry optional)












S1 Distance from outer end lead edge positions to the extremity of the bodyNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415 - 0.0430 inch.4. Dimension “B1” is normal.5. Details of Pin 1 identifier are optional.


Category Plastic Dual-In-Line

Acronym PDIP


Lead Counts 24, 28, 32, 40, 64

Lead Finish Solder Coat

Lead Pitch 0.100” (excludes shrink)

Board Assembly Type Socket and Surface MountNOTES: 1. Alloy 42 and Cu Alloy Leads



2.5.2 24 Lead Plastic Dual In-Line Package (600 MIL)

A5534-01

N

e1B

B1

D2

DS S1


LA1

A2

A

EE1Pin #1

Indicator Area

eB

eA

C

Family: Plastic Dual In-Line Package



α 0 ° 10 ° 0 ° 10 °

A 5.08 0.200

A1 0.38 0.015

A2 3.68 4.06 0.145 0.160

B 0.41 0.51 0.016 0.020



D 31.37 32.00 1.235 1.260


E 15.75 0.620

E1 13.59 13.84 0.535 0.545

e1 2.29 2.79 0.090 0.110


eB 15.24 17.78 0.600 0.700

L 3.18 3.68 0.125 0.145

N 24 600 MIL 24 600 MIL

S 1.52 2.03 0.060 0.080

S1 0.74 0.029




A5534-01

N

e1B

B1

D2

DS S1


LA1

A2

A

EE1Pin #1

Indicator Area

eB

eA

C




α 0 ° 10 ° 0 ° 10 °

A 5.08 0.200

A1 0.38 0.015

A2 3.68 4.06 0.145 0.160

B 0.36 0.56 0.014 0.022


C 0.23 0.30 0.009 0.012

D 36.70 37.34 1.445 1.470


E 15.75 0.620

E1 13.59 14.00 0.535 0.551

e1 2.29 2.79 0.090 0.110


eB 15.24 17.78 0.600 0.700

L 3.18 3.68 0.125 0.145

N 28 600 MIL 28 600 MIL

S 1.65 2.16 0.065 0.085

S1 0.86 0.034




A5534-01

N

e1B

B1

D2

DS S1


LA1

A2

A

EE1Pin #1

Indicator Area

eB

eA

C




α 0 ° 15 ° 0 ° 15 °

A 4.83 0.190

A1 0.38 0.015

A2 3.81 Typical 0.150 Typical

B 0.41 0.51 0.016 0.020

B1 1.14 1.40 0.045 0.055

C 0.20 0.30 0.008 0.012

D 41.78 42.04 1.645 1.655


E 15.24 15.88 0.600 0.625

E1 13.46 13.97 0.530 0.550

e1 2.54 Reference 0.100 Reference


eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135

N 32 600 MIL 32 600 MIL

S 1.78 2.03 0.070 0.080

S1 1.14 0.045




A5534-01

N

e1B

B1

D2

DS S1


LA1

A2

A

EE1Pin #1

Indicator Area

eB

eA

C




α 0 ° 10 ° 0 ° 10 °

A 5.08 0.200

A1 0.38 0.015

A2 3.94 4.19 0.155 0.165

B 0.41 0.51 0.016 0.020


C 0.23 0.30 0.009 0.012

D 51.94 52.58 2.045 2.070


E 15.75 0.620

E1 13.59 13.84 0.535 0.545

e1 2.29 2.79 0.090 0.110


eB 15.24 17.78 0.600 0.700

L 3.18 3.68 0.125 0.145

N 40 40

S 1.65 2.16 0.065 0.085

S1 0.99 0.039



2.5.6 40 Lead Plastic Dual In-Line Package (600 MIL)Variation: ½ Lead

A5532-01

N

e1B

B1

D2

DS S1


LA1

A2

A

eB

eA

C

EE1Pin #1

Indicator Area




α 0 ° 10 ° 0 ° 10 °

A 4.55 0.179

A1 0.38 0.015

A2 3.75 3.95 Nom 3.85 0.147 0.155

B 0.35 0.51 0.014 0.020

B1 1.40 1.60 0.055 0.063

C 0.25 0.45 Nom 0.35 0.009 0.018

D 52.30 2.06

D2

E 13.50 13.09 Nom 13.70 0.531 0.547

E1

e1 2.29 2.79 Nom 2.54 0.090 0.110

eA 14.74 15.74 Nom 15.24 0.580 0.619

eB

L 3.00 3.60 Nom 3.30 0.118 0.141

N 40 ½ Lead 40 ½ Lead

S 1.65 2.16 0.065 0.080

S1



2.5.7 64 Lead Plastic Dual In-Line Package (Shrink)

A5533-01

N

e1BB1

D2

D


LA1

A2

A

eB

eA

C

E1

Pin #1Indicator Area




α 0 ° 15 ° 0 ° 15 °

A 5.65 0.22

A1 0.51 0.020

A2 4.15 4.35 0.163 0.171

B 0.35 0.55 0.014 0.022


C 0.20 0.30 0.008 0.012

D 57.80 58.20 2.28 2.29


E

E1 16.80 17.20 0.661 0.677

e1 1.60 1.96 0.063 0.077

eA 19.05 0.750

eB 19.50 21.00 0.767 0.826

L 3.00 3.60 0.118 0.142

N 64 64



2.6 Plastic Flatpack Package

2.6.1 Symbol List for Plastic Flatpack Family






D1 Largest overall package dimension of length excluding leads

D2 A body length dimension, outer lead center to outer lead center

e1 Linear spacing between centerlines of terminal leads

L Lead dimension free lead length


Q Lead plane to top of body plane distance

S Distance from true position centerline of end lead position to the extremity of the body

S1 Linear spacing of true maximum lead position from lead edge to package edgeNOTES: 1. Controlling dimension: millimeter.2. Dimension “e1” (“e”) is non-cumulative.3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415 - 0.0430 inch.



2.6.2 68 Lead Plastic Flatpack Package

A5535-01

D

D2

Seating and Base Plane

e1

L

D

Q

C

D1

N

1.02 (0.04)45˚ Chamfer

(4 PL)

Pin #1Indicator

B

SS1

A

Family: Plastic Flatpack Package



A 4.19 4.34 0.165 0.171

B 0.46 0.56 0.018 0.022 Typical

C 0.18 0.25 0.007 0.010 Typical

D 44.45 45.21 1.750 1.780

D1 24.08 24.26 0.948 0.955

D2 20.22 20.42 0.796 0.804

e1 1.22 1.32 Typical 0.048 0.052 Typical

L 10.16 10.80 0.400 0.425

N 68 68

Q 2.01 2.06 0.079 0.081

S 1.73 2.08 0.068 0.082

S1 1.47 0.058



2.7 Plastic Leaded Chip Carrier Package

2.7.1 Symbol List for Plastic Leaded Chip Carrier Family


A Overall Height: Distance from seating plane to highest point of body

A1 Distance from lead shoulder to seating plane

CP Seating plane coplanarity

D/E Overall package dimension

D1/E1 Plastic body dimension

D2/E2 Footprint

LT Lead thickness

N Total number of potentially usable lead positions

Nd Total number of leads on short side

Ne Total number of leads on long side

TCP Tweezing coplanarityNOTES: RECTANGLE PACKAGE1. All dimensions and tolerances conform to ANSI Y 14.5M-1982.2. Datum plane -H- located at top of mold parting line and coincident with top of lead, where lead exits plastic body.3. Data A-B and -D- to be determined where center leads exit plastic body at datum plane -H-.4. To be determined at seating plane -C-.5. Dimensions D1 and E1 do not include mold protrusion.6. Pin 1 identifier is located within the defined zone.7. These two dimensions determine maximum angle of the lead of certain socket applications. If unit is intended to be

socketed, it is advisable to review these dimensions with the socket supplier.8. Nd denotes the number of leads on the two short sides of the package, one of which contains pin #1. Ne denotes the

number of leads on the two long sides of the package.9. Controlling dimension, inch.10. All dimensions and tolerances include lead trim offset and lead plating finish.11. Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. The datum is estab-

lished by touching the outermost lead on that side and parallel to A-B or -D-.


Category Plastic Leaded Chip Carrier

Acronym PLCC

Lead Configuration Quad

Lead Counts 20, 28, 32, 44, 52, 68, 84

Lead Finish Solder Plate

Lead Pitch 0.050”

Board Assembly Type Socket and Surface MountNOTES: 1. Copper Alloy Leads.2. Novalac Body.3. Bake and desiccant packaging required.



Family: Plastic Lead Chip Carrier-Rectangular (mm)

28 Lead 32 Lead

Symbol Min Max Notes Min Max Notes

A 3.20 3.56 3.20 3.56

A1 1.93 2.29 1.93 2.29

D 9.78 10.0 12.30 12.60

D1 8.81 8.97 11.40 11.50

D2 7.37 8.38 9.91 10.90

E 14.90 15.10 14.90 15.10

E1 13.90 14.00 13.90 14.00

E2 12.40 13.50 12.40 13.50

N 28 32

Nd 5 7

Ne 9 9

CP 0.00 0.10 0.00 0.10

TCP 0.00 0.10 0.00 0.10

LT 0.23 0.38 0.23 0.38

Family: Plastic Lead Chip Carrier-Rectangular (inch)

Symbol28 Lead 32 Lead


A 0.126 0.140 0.126 0.140

A1 0.076 0.090 0.076 0.090

D 0.385 0.394 0.484 0.496

D1 0.347 0.353 0.449 0.453

D2 0.290 0.330 0.390 0.429

E 0.587 0.594 0.587 0.594

E1 0.547 0.551 0.547 0.551

E2 0.488 0.531 0.488 0.531

N 28 32

Nd 5 7

Ne 9 9

CP 0.000 0.004 0.000 0.004

TCP 0.000 0.004 0.000 0.004

LT 0.009 0.015 0.009 0.015



2.7.1.1 Principal Dimensions and Datums

2.7.1.2 Molded Details

A5539-01

A1

D1

3

E1

0.18 (.007) S-BSS A

–C–Seating Plane

Datum Plane2

C

0.18 (.007) S-BSS SDAC

E

–B–3

Ne

–A–3

8

Nd

8

A

–D–

–H–

D

Tweezing Surface

TCP(all four sides)

11

mm (Inch)

A5537-01

BasePlane

0.38 (.015) Min

3 x0.25 (.0101)RNOM

D1

6

3.81 (0.150)Max Typ

.002mm/mm (In/In) D

0.18 (.007) S-BSS A

–C–

Seating Plane

0.74 (.029)0.58 (.023)

x 30˚

1.91 (0.075) Max Typ

5

1.22 (.048)1.07 (.042)

E15

A

.002mm/mm (In/In) A–B

0.18 (.007) S-BSS SDAC

mm (Inch)



2.7.1.3 Terminal Details ND Side

2.7.1.4 Terminal Details NE Side

A5541-01

0.38 (.015) SDS-BSS AC

0.18 (.007) S-BSS SDAC

4

See Detail L

D

D2

A1

CP–C–

–H–

SeatingPlane

1.27 (.050)0.81 (.032)0.66 (.026) N PLCS

See Detail J

4 Sides

A5540-01

0.38 (.015) S-BSS AC 4

LTSee detail J for Measurement Zone

E

E2

A1

CP–C–

–H–

SeatingPlane

1.27 (.050)



2.7.1.5 Standard Package Bottom View

2.7.1.6 Detail J. Terminal Details

2.7.1.7 Detail L. Terminal Detail

A5542-01

1.57 (.062)1.37 (.054)

0.46 (.018)0.36 (.014)

10˚45˚

0.91 (.036)0.71 (.028)

1.09 (.043)0.89 (.035)

mm (Inch)

A5543-02231369-43

0.18 (.007) SDS-BSM AC

Measurement Zone for LT0.64 (.025)Min

SeatingPlane

0.81 (.032)0.66 (.026)

Bottom of Shoulder

–C–

0.64 (.025)Min

Bottom of Plastic Body

0.51 (.020)0.41 (.016)

mm (Inch)

A5544-02231369-44

1.02 (.040)0.76 (.030)

–H–

0.51 (.020)

1.14 (.045)

0.13 (.005) Max

7

1.02 (.040)0.76 (.030)

–H–

0.51 (.020)

1.14 (.045)

0.13 (.005) Max7

RR

mm (Inch)



Family: Plastic Leaded Chip Carrier-Square (mm)



A 4.19 4.57 4.19 4.57

A1 2.29 3.05 2.29 3.05

D 9.78 10.0 17.4 17.7

D1 8.89 9.04 16.5 16.7

D2 7.37 8.38 15.0 16.0

E 9.78 10.0 17.4 17.7

E1 8.89 9.04 16.5 16.7

E2 7.37 8.38 15.0 16.0

N 20 44

CP 0.00 0.10 0.00 0.10

TCP 0.000 0.10 0.000 0.10

LT 0.23 0.38 0.23 0.38

Family: Plastic Leaded Chip Carrier-Square (inch)



A 0.165 0.180 0.165 0.180

A1 0.090 0.120 0.090 0.120

D 0.385 0.395 0.685 0.695

D1 0.350 0.356 0.650 0.656

D2 0.290 0.330 0.590 0.630

E 0.385 0.395 0.685 0.695

E1 0.350 0.356 0.650 0.656

E2 0.290 0.330 0.590 0.630

N 20 44

CP 0.000 0.004 0.000 0.004

TCP 0.000 0.004 0.000 0.004

LT 0.009 0.015 0.009 0.015



Family: Plastic Leaded Chip Carrier-Square (mm)

Symbol52 Lead 68 Lead 84 Lead

Min Max Notes Min Max Notes Min Max Notes

A 4.19 4.57 4.19 4.83 4.19 4.83

A1 2.29 3.05 2.29 3.05 2.29 3.05

D 19.90 20.20 25.00 25.30 30.10 30.40

D1 19.10 19.20 24.10 24.30 29.20 29.40

D2 17.50 18.50 22.60 23.60 27.70 28.70

E 19.90 20.20 25.00 25.30 30.10 30.40

E1 19.10 19.20 24.10 24.30 29.20 29.40

E2 17.50 18.50 22.60 23.60 27.70 28.70

N 52 68 84

CP 0.00 0.10 0.00 0.10 0.00 0.10

TCP 0.00 0.10 0.00 0.10 0.00 0.10

LT 0.23 0.38 0.20 0.36 0.20 0.36

Family: Plastic Leaded Chip Carrier-Square (inches)

Symbol52 Lead 68 Lead 84 Lead

Min Max Notes Min Max Notes Min Max Notes

A 0.165 0.180 0.165 0.190 0.165 0.190

A1 0.090 0.120 0.090 0.120 0.090 0.120

D 0.783 0.795 0.984 0.996 1.185 1.195

D1 0.752 0.756 0.949 0.957 1.150 1.157

D2 0.689 0.728 0.890 0.929 1.091 1.130

E 0.783 0.795 0.984 0.996 1.185 1.195

E1 0.752 0.756 0.949 0.957 1.150 1.157

E2 0.689 0.728 0.890 0.929 1.091 1.130

N 52 68 84

CP 0.000 0.004 0.000 0.004 0.000 0.004

TCP 0.000 0.004 0.000 0.004 0.000 0.004

LT 0.009 0.015 0.008 0.014 0.008 0.014




2.7.1.9 Molded Detail

A5545-01

A1

D1

3

E1

0.18 (.007) SF-GS A–C–Seating Plane

Datum Plane2

0.18 (.007) SD-ES B

E

–G–3

–F–3

3

A

–D–

–H–

D

Tweezing Surface

TCP(all four sides)

11

–E–

–B –

–A–

A5546-01

BasePlane

0.51 (.020) Min

3 x 0.25 (.010 )R NOM

D1

6

3.81 (0.150)Max Typ

.002mm/mm (In/In) A

0.18 (.007) SF-GS

S

–C–

Seating Plane

1.22 (.048)1.07 (.042)

1.91 (0.075) Max Typ

51.22 (.048)1.07 (.042)

2 PLCS

E1

5

A

.002mm/mm (In/In)

0.18 (.007) -BS SD-ES B

–A–

–B–



2.7.1.10 Terminal Details

2.7.1.11 Standard Package Bottom View (Tooling Option I.)

A5547-01

0.38 (.015) SD-E

0.18 (.007) SS AB

4

See Detail L

D

D2

A1

CP–C–

–H–Seating

Plane

1.27 (.050)0.81 (.032)0.66 (.026) N PLCS

See Detail J

4 Sides

0.38 (.015) SF-G 4E2

LT

4

See Detail J ForMeasurement Zone

mm (Inch)

231369-47

A5548-01

1.57 (.062)1.37 (.054)

0.46 (.018)0.36 (.014)

10˚45˚

0.91 (.036)0.71 (.028)

1.09 (.043)0.89 (.035)

mm (Inch)

231369-48



2.7.1.12 Standard Package Bottom View (Tooling Option II.)

2.7.1.13 Detail J. Terminal Detail

A5551-02

0.51 (.020)0.25 (.010)

5˚45˚

0.89 (.035)0.64 (.025)

0.66 (.026)0.41 (.016)

5˚ Typ

0.71 (.028)0.46 (.018)

mm (Inch)

(Typ)

231369-49

A5552-02

Bottom of Plastic Body

0.18(0.007) SM F–G

Bottom of Shoulder

0.51 (.020)0.41 (.016)

0.81(.032)0.66(.026)

1.52 (0.060) Min

–C–Seating Plane

0.64 (0.025) Min

Measurement Zone For LT

SD–E

mm (Inch)

231369-50



2.7.1.14 Detail L. Terminal Details

A5553-01

1.14 (.045)0.64 (.025)

–H–

1.51 (.020)

1.65 (.065)

0.25 (.010) Max

–H–

0.51 (.020)

1.65 (.065)

0.25 (.010) Max

R

8

Detail L

mm (Inch)

8

231369-51

NOTES: SQUARE PACKAGE1. All dimensions and tolerances conform to ANSI Y 14.5M-1982.2. Datum plane -H- located at top of mold parting line and coincident with top of lead, where lead exits plastic body.3. Data D-E and F-G to be determined where center leads exit plastic body at datum plane -H-.4. To be determined at seating plane -C-.5. Dimensions D1 and E1 do not include mold protrusion. 6. Pin 1 identifier is located within one of the two defined zones.7. Locations to datum -A- and -B- to be determined at plane -H-.8. These two dimensions determine maximum angle of the lead of certain socket applications. If unit is intended to be

socketed, it is advisable to review these dimensions with the socket supplier.9. Controlling dimension, inch.10. All dimensions and tolerances include lead trim offset and lead plating finish.11. Tweezing surface planarity is defined as the furthest any lead on a side may be from the datum. The datum is estab-

lished by touching the outermost lead on that side and parallel to D-E or F-G.



2.8 Plastic Quad Flatpack Package

2.8.1 Symbol List for Plastic Quad Flatpack Family

Symbol Description

A Package height

A1 Standoff

D, E Terminal dimension

D1, E1 Package body

D1, E1 Foot print

D2, E2 Bumper distance

D2, E2 Foot radius location

L1 Foot length

N LeadcountNOTES: 1. All dimensions and tolerances conform to ANSI Y 14.5M-1982.2. Datum plane -H- located at top of mold parting line and coincident with top of lead, where lead exits plastic body.3. Data A-B and -D- to be determined where center leads exit plastic body at datum plane -H-.4. Controlling dimension, inch.5. Dimensions D1, D2, E1 and E2 are measured at the mold parting line. D1 and E1 do not include an allowable mold pro-

trusion of 0.25 mm (0.010 in) per side. D2 and E2 do not include a total allowable mold protrusion of 0.25 mm (0.010 in) at maximum package size.

6. Pin 1 identifier is located within one of the two zones indicated.7. Measured at datum plane -H-.8. Measured at seating plane datum -C-.


Category Plastic Quad Flatpack

Acronym PQFP

Lead Configuration Gull-Wing

Lead Counts 84, 100, 132, 164, 196


Lead Pitch 0.025”

Board Assembly Type Surface or Socket Mount



Plastic Quad Flatpack (PQFP) 0.025 Inch (0.635mm) Pitch

Symbol Description Min Max Min Max Min Max Min Max Min Max

A Package Height 0.160 0.180 0.160 0.180 0.160 0.180 0.160 0.180 0.160 0.180

A1 Standoff 0.020 0.040 0.020 0.040 0.020 0.040 0.020 0.040 0.020 0.040

D,E Terminal Dimension

0.770 0.790 0.870 0.890 1.070 1.090 1.270 1.290 1.470 1.490

D1, E1 Package Body 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2, E2 Bumper Distance 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3, E3 Lead Dimension 0.500 REF 0.600 REF 0.800 REF 1.000 REF 1.200 REF

D4, E4 Foot Radius Location

0.723.

0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437

L1 Foot Length 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

N Leadcount 84 100 132 164 196

Controlling Dimensions in Inches

Plastic Quad Flatpack (PQFP) 0.025 Inch (0.635mm) Pitch

Symbol Description Min Max Min Max Min Max Min Max Min Max

A Package Height 4.06 4.57 4.06 4.57 4.06 4.57 4.06 4.57 4.06 4.57

A1 Standoff 0.51 1.02 0.51 1.02 0.51 1.02 0.51 1.02 0.51 1.02

D,E Terminal Dimension

19.56 20.07 22.01 22.61 27.18 27.69 32.26 32.77 37.34 37.85

D1, E1 Package Body 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37

D2, E2 Bumper Distance 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

D3, E3 Lead Dimension 12.70 REF 15.24 REF 20.32 REF 25.40 REF 30.48 REF

D4, E4 Foot Radius Location

18.36 18.71 20.90 21.25 25.89 26.33 31.06 31.41 36.14 36.49

L1 Foot Length 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76 0.51 0.76

N Leadcount 84 100 132 164 196

Controlling Dimensions in mm




2.8.1.2 Molded Details

A5554-01

Base Plane

A1

0.20 (.008) SAM S–BC

3–B–

3–A–

–H–2

A

0.10 (.004)–C– Seating Plane

–D– 3

D1

D2

DSD

E2 E E1

0.20 (.008) SAM S–BC SD

A5555-01

6

D1

D2

E2 E1

See Detail M

3.81 (.150) Max. Typ

S.002 MM/MM (IN/IN) A–B

1.91 (.075) Max. Typ

0.25 (.010) SAM S–BC SD

S.002 MM/MM (IN/IN) A–B0.25 (.010) SAM S–BC SD

.002 MM/MM (IN/IN) D0.25 (.010) SAM S–BC SD

S.002 MM/MM (IN/IN)0.25 (.010) SAM S–BC SD

D




2.8.1.4 Typical Lead

2.8.1.5 Detail M

See Detail J

0.635 (0.025)

D / E

D3 / E3

See Detail L

A5557-01

D4 / E4

A5556-01

0.20 (.008) SDS-BSM AC

2

L1

0.20 (.008)0.14 (.005)

–H–

8 Deg.0 Deg.

D4 / E4

0.41 (.016)0.20 (.008)

0.31 (.012)0.20 (.008)

A1 –C–

8

Detail J Detail L

0.13 (.005) SDS-BSM AC 7

A5558-01

E2

1.32 (.052)1.22 (.048)

1.32 (.052)1.22 (.048) 0.90 (.035) Min.

2.03 (.080)1.93 (.076)0.90 (.035) Min.

2.03 (.080)1.93 (.076)

D2



2.9 Quad Flatpack Package

2.9.1 Symbol List for Quad Flatpack Family


A Overall Height

A1 Standoff

AAA Lead True Position

b Lead Width

c Lead Thickness

D Terminal Dimension

D1 Body Package

E Terminal Dimension

E1 Body Package

e1 Lead Pitch

L1 Foot Length

N Leadcount

T Lead Angle

Y CoplanarityNOTE: RECTANGLE PACKAGE1. Not all packages are available with all products. Contact local Intel Representative for further package information.


Category Quad Flatpack

Acronym QFP, SQFP, TQFP

Lead Configuration Quad

Lead Counts QFP 44, 48, 64, 80, 100, 160 - SQFP 80, 100, 128, 208 - TQFP 100, 144, 176


Lead Pitch 0. 5, 0.65, 0.8 mm

Board Assembly Type Surface or Socket MountNOTES: 1. QFP - Alloy 42/copper on some lead frames. SQFP / TQFP copper lead frames only.2. Novalac Body.3. Not all packages are available with all products. Contact local Intel Representative for further package information.



2.9.1.1 Principal Dimensions and Data for QFP (Square)/TQFP/SQFP Packages


A6044-01

C

A

D2*

D1

D

E1 E

B

B CP A

C

bS

A6045-01

A

A

YL1

A1

e1

T



Quad Flatpack (Square Packages)

Symbol Description Min Nom Max Min Nom Max

N Lead Count 44 48

A Overall Height 2.35 2.55

A1 Stand Off 0.05 0.05 0.25

b Lead Width 0.20 0.30 .040 0.25 0.30 0.40

c Lead Thickness 0.10 0.15 0.20 0.11 0.15 0.20

D Terminal Dimension 12.0 12.4 12.8 15.1 15.3 15.5

D1 Package Body 10.0 11.9 12.0 12.1

E Terminal Dimension 12.0 12.4 12.8 15.1 15.3 15.5

E1 Package Body 10.0 11.9 12.0 12.1

e1 Lead Pitch 0.65 0.80 0.95 0.70 0.80 0.90

L1 Foot Length 0.38 0.58 0.78 0.65 0.85 1.05

T Lead Angle 0.0° 10.0° 0.0° 7.0°

Y Coplanarity 0.10 0.10

Quad Flatpack (Square Packages) (Continued)

Symbol Description Min Nom Max Min Max Min Max

N Lead Count 64 128 160

A Overall Height 2.55 3.23 3.75 4.00

A1 Stand Off 0.05 0.05 0.30 0.05 0.30

b Lead Width 0.20 0.30 0.40 0.25 0.45 0.20 0.45

c Lead Thickness 0.10 0.15 0.20 0.150 0.188 0.150 0.188

D Terminal Dimension 14.9 15.3 15.7 31.6 32.4 30.2 31.0

D1 Package Body 12.0 27.9 28.1 27.9 28.1

E Terminal Dimension 14.9 15.3 15.7 31.6 32.4 30.2 31.0

E1 Package Body 12.0 27.9 28.1 27.9 28.1

e1 Lead Pitch 0.53 0.65 0.77 0.70 0.90 0.55 0.75

L1 Foot Length 0.65 0.85 1.05 0.60 1.0 0.60 1.0

T Lead Angle 0.0° 10.0° 0° 10° 0° 10°

Y Coplanarity 0.10 0.1 0.1



Shrink Quad Flatpack

Symbol Description Min Nom Max Min Nom Max Min Nom Max Min Max

A Overall Height 1.7 1.7 3.15 3.75

A1 Stand Off 0.00 0.00 0.05 0.40 0.05 0.30

b Lead Width 0.14 0.20 0.26 0.14 0.20 0.26 0.14 0.22 0.28 0.14 0.26

c Lead Thickness 0.117 0.127 0.177 0.117 0.127 0.177 0.10 0.15 0.20 0.150 0.188

D Terminal Dimension 13.70 14.00 14.30 15.70 16.00 16.30 17.5 17.9 18.3 30.2 31.0

D1 Package Body 12.0 14.00 14.0 27.9 28.1

E Terminal Dimension 13.70 14.00 14.30 15.70 16.00 16.30 23.5 23.9 24.3 30.2 31.0

E1 Package Body 12.0 14.00 20.0 27.9 28.1

e1 Lead Pitch 0.40 0.50 0.60 0.40 0.50 0.60 0.40 0.50 0.60 0.40 0.60

L1 Foot Length 0.35 0.50 0.70 0.30 0.50 0.70 0.60 0.80 1.00 0.30 0.70

N Lead Count 80 100 128 208

T Lead Angle 0.0° 10.0° 0.0° 10.0° 0.0° 10.0° 0.0° 10.0°

Y Coplanarity 0.10 0.10 0.10 0.08

D2/E2 Heatspreader 21

Thin Quad Flatpack

Symbol Description Min Max Min Max Min MaxA Overall Height 1.7 1.3 1.7 1.3 1.7A1 Stand Off 0.05 0.20 0.05 0.20 0.50b Lead Width 0.16 0.28 0.16 0.28 0.16 0.28c Lead Thickness 0.117 0.127 0.122 0.160 0.122 0.160D Terminal Dimension 15.70 16.30 21.6 22.4 25.6 26.4D1 Package Body 13.9 14.1 19.9 20.1 23.9 24.1E Terminal Dimension 15.7 16.30 21.6 22.4 25.6 26.4E1 Package Body 13.9 14.1 19.9 20.1 23.9 24.1e1 Lead Pitch 0.40 0.60 0.40 0.60 0.40 0.60L1 Foot Length 0.30 0.70 0.40 0.80 0.40 0.80N Lead Count 100 144 176P Leads True Position 0.08 0.08 0.08T Lead Angle 0.0° 10.0° 0.0° 10.0° 0.0° 1.0°Y Coplanarity 0.10 0.08 0.08



Figure 2-1. Principle Dimensions and Data for QFP (Rectangular) Packages

A5549-01

D1

E1

Sea

ting

Pla

ne

E

D

A1

C

A

SeatingPlane

See Detail A L1

Detail A

Y T

be1

e1

Quad Flatpack (Rectangular Packages)

Symbol Description Min Nom Max Min Nom Max

N Lead Count 80 100

A Overall Height 3.15 3.15

A1 Stand Off 0.05 0.40 0.05 0.40

B Lead Width 0.25 0.35 0.45 0.20 0.30 0.40

C Lead Thickness 0.10 0.15 0.20 0.10 0.15 0.20

D Terminal Dimension 17.5 17.9 18.3 17.5 17.9 18.3

D1 Package Body 14.0 14.0

E Terminal Dimension 23.5 23.9 24.3 23.5 23.9 24.3

E1 Package Body 20.0 20.0

e1 Lead Pitch 0.65 0.80 0.95 0.53 0.65 0.77

L1 Foot Length 0.60 0.80 1.00 0.60 0.80 1.00

T Lead Angle 0.0° 10.0° 0.0° 10.0°

Y Coplanarity 0.10 0.10



2.10 Small Out-line J-lead Package (SOJ)

2.10.1 Symbol List for Small Out-Line J-Lead Family


A Overall Height

A2 Distance from Base Plane to Highest Point of Body (Lid)

B Width of Terminal Leads

B1 Width of Terminal Lead Shoulder Which Locate Seating Plane (Standoff Geometry Optional)

D Largest Overall Package Dimension of Length

E Largest Over Package Width Dimension Outside of Leads

E1 Body Width Dimension Not Including Leads

e1 Linear Spacing Between Center Line of Body Terminal Leads (Standoffs)

eA Linear Spacing of True Minimum Lead Position Center Line to Center Line

N Total Number of Potentially Usable Lead Positions


Category Small Outline J-Lead

Acronym SOJ


Lead Counts 20, 24


Lead Pitch 0.050”

Board Assembly Type Surface MountNOTES: 1. Alloy 42 Leads.2. Novalac body.



2.10.2 20 Lead Small Out-Line Package (SOJ) Variation: J-Lead

A5563-01

D

A2

A

A

B B1

E1 E

e1

eA

231369-61

A2

Family: Small Out-Line J-Lead Package



A 3.04 3.61 0.120 0.142

A2 2.36 3.00 0.093 0.118

B 0.38 0.51 0.015 0.020

B1 0.58 0.84 0.023 0.033

D 17.02 17.27 0.67 0.680

E 8.31 8.64 0.327 0.340

E1 7.49 7.75 0.295 0.305

e1 1.27 Typical 0.050 Typical

eA 6.60 6.99 0.260 0.275

eB 7.62 10.16 0.300 0.400

N 20 20



2.10.3 24 Lead Small Out-Line Package (SOJ) Variation: J-Lead

A5564-01

D

A2

E

A

B

E1

e1eA

Pin 1

Seating Plane

231369-62

Family: Small Out-Line J-Lead Package



A 3.35 3.61 0.132 0.142

A1

A2 2.74 3.00 0.180 0.118

A3

B 0.38 0.51 0.015 0.020

D 15.75 16.18 0.620 0.637

D2

E 8.38 8.64 0.330 0.340

E1 7.49 7.75 0.295 0.305


eA 6.60 6.99 0.260 0.275

eB

L

N 24 24



2.10.4 Plastic Small Out-Line Package/Shrink Small Outline Package (PSOP/SSOP)


A Overall Height

A1 Standoff

A2 Package Body Thickness

A3 Lead Height

b Width of Terminal Leads

c Thickness of Terminal Leads

D1 Plastic Body Length

E Package Body Width

e Lead Pitch


L Lead Tip Length


Y Seating Plane Coplanarity

Z Lead to Package Offset

Ø Lead Tip Angle


Category Plastic Small Outline Package/Shrink Small Outline Package

Acronym PSOP/SSOP

Lead Counts 44/48 & 56


Lead Pitch 1.27 mm/0.8 mm

Board Assembly Type Surface Mount

Standard Registration JEDEC and EIAJNOTES: 1. Copper Alloy 194.2. Novalac body.3. Profile Tolerance zones for D1 and E do not include mold protrusion. (Allowable mold protrusion on D1 is 0.25 mm per

side and on E is 0.15 mm per side.)4. Lead Plating Thickness is 0.007 mm - 0.015 mm (Not part of b or c dimensions).



2.10.5 44 Lead Plastic Small Out-Line Package (PSOP)

A5565-01

A1

A

b

DE

e See Detail A

A2

0

LDetail A

Y

D1

44 23

1 22

A

C

[231369-80]

Family: Small Out-Line Package


Min Nom Max Notes Min Nom Max Notes

A 2.95 0.116

A1 0.050 0.020

A2 2.20 2.30 2.40 0.087 0.091 0.094

b 0.35 0.40 0.50 0.014 0.016 0.020

c 0.13 0.150 0.20 0.005 0.006 0.008

D1 28.00 28.20 28.40 3 1.102 1.110 1.118 3

E 13.10 13.30 13.50 3 0.516 0.524 0.531 3

e 1.27 0.050

D 15.75 16.00 16.25 0.620 0.630 0.640

L 0.75 0.80 0.85 0.030 0.031 0.033

Y 0.10 0.004

Ø 8° 8°



2.10.6 48-Lead Shrink Small Outline Package (SSOP)

A8069-01

D

E

B

4-7˚±1˚

4-7˚±1˚

A1E1

5.505.502.

00

A2

0.25

0

A

0.5x

45˚

0.85

±0.

125

1.20

0.381

0.381

b

L

R

c1c

0.623

(Application Laser Mark)Surface Roughness: Top 3-5µm

Bottom 5.5 ~ 9.5µm(RZ)

e

4.R0.2

4.R0.2

Bottom E-Pin(Cavity#) Mark

Bottom E-Pin(Japan) Mark

C DA-B S SM0.12

Detail B

Detail A

48L Small Outline Package

SymbolMillimeters

Min Nom Max

A 2.44 2.59 2.74

A1 0.20 0.30 0.40

A2 2.24 2.29 2.34

b 0.22 0.30

b1 0.22 0.25 0.28

c 0.18 0.25

c1 0.18 0.20 0.22

D 15.80 15.85 15.90

E 7.45 7.50 7.55

E1 10.16 10.285 10.41

L 0.70 0.80 0.90

e 0.635 BSC

R 0.10 0.20 0.30

θ1 0 5 8

θ2 0 3 6



2.10.7 56-Lead Shrink Small Outline Package (SSOP)

A5566-01

A1A

b

DE

e

e

See Detail A

A2A3 0

LDetail A

D1

Y

[231369-99]

56L Small Outline Package



Package height A 1.80 1.90 0.070 0.075

Standoff A1 0.47 0.018

Package body thickness A2 1.18 1.28 1.38 0.046 0.050 0.054

Lead width b 0.25 0.30 0.40 0.010 0.012 0.016

Lead thickness c 0.13 0.15 0.20 0.005 0.006 0.008

Plastic body length D1 23.40 23.70 24.00 3 0.921 0.933 0.945 3

Package body width E 13.10 13.30 13.50 3 0.516 0.524 0.531 3

Lead pitch e 0.80 0.0315

Terminal dimension D 15.70 16.00 16.30 0.618 0.630 0.642

Lead count N 56 56

Lead tip length L 0.750 0.80 0.85 0.030 0.315 0.033

Seating plane coplanarity Y 0.10 0.004

Lead height A3 1.30 1.40 1.50 0.051 0.055 0.059

Lead tip angle Ø 5° 5°



2.11 Thin Small Out-line Package (TSOP)Note: For more SOP package information refer to SOP package guide Order #296514.

2.11.1 Symbol List for Thin Small Out-Line Package Family


A Overall Height

A1 Standoff


A3 Lead Height

b Width of Terminal Leads

c Thickness of Terminal Leads


D1 Plastic Body Length


e Lead Pitch

L Lead Foot Length


Y Seating Plane Coplanarity

Z Lead to Package Offset

Ø Lead Tip Angle


Category Thin Small Out-Line Package

Acronym TSOP

Lead Configuration Dual-In-Line, Type I

Lead Counts 32, 40, 48, 56


Lead Pitch 0.5 mm

Board Assembly Type Surface MountNOTES: 1. Alloy 42 Leads.2. Novalac body.3. Offered in Reverse Pin-Out for special circuit layout, (32L, 40L only).4. Profile Tolerance zones for D1 and E do not include mold protrusion. (Allowable mold protrusion on D1 is 0.25 mm per

side and on E is 0.15 mm per side.)5. Lead plating thickness is 0.007 mm - 0.015 mm (Not part of b or c dimensions).



2.11.2 32-Lead Thin Small Out-Line Package (TSOP)

A5567-02

A

A2

L

Detail A

Y

D

See Note 2

E

D1

0

C

b

Detail B

See Detail A

See Note 1,3 and 4

e

See Detail B

A1

Z

Pin 1

A2

SeatingPlane

Family: Thin Small Out-Line Package


Min Nom Max Notes Min Nom Max NotesA 1.200 0.047A1 0.050 0.002A2 0.965 0.995 1.025 0.038 0.039 0.040B 0.150 0.200 0.300 0.006 0.008 0.012C 0.115 0.125 0.135 0.004 0.0049 0.0053D 19.800 20.000 20.200 0.780 0.787 0.795D1 18.200 18.400 18.600 4 0.717 0.724 0.732 4E 7.800 8.000 8.200 4 0.307 0.315 0.323 4e 0.500 0.0197L 0.500 0.600 0.700 0.020 0.024 0.028N 32 32Ø 0° 3° 5° 0° 3° 5°Y 0.100 0.004Z 0.150 0.250 0.350 0.006 0.010 0.014

NOTES: 1. One dimple on package denotes Pin 1.2. If two dimples, then the larger dimple denotes Pin 1.3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Package/Tray orientation: Package pin 1 will always be orientated towards the chamfer tray side (Dimension Z) as per

JEDEC standard JEP-95, CS-008.



2.11.3 40-Lead Thin Small Out-line Package (TSOP)

A5570-02

A

0

L

Detail A

Y

D

C

Z

Pin 1

E

D1

b

Detail B

e

A1

SeatingPlane

A2See Note 2See Note 1,3 and 4

See Detail A

See Detail B




A 1.200 0.047

A1 0.050 0.002

A2 0.965 0.995 1.025 0.038 0.039 0.040

b 0.150 0.200 0.300 0.006 0.008 0.012

c 0.115 0.125 0.135 0.0045 0.0049 0.0053

D 19.800 20.00 20.200 0.780 0.787 0.795

D1 18.200 18.400 18.600 4 0.717 0.724 0.732 4

E 9.800 10.000 10.200 4 0.386 0.394 0.402 4

e 0.500 0.0197

L 0.500 0.600 0.700 0.020 0.024 0.028

N 40 40

Ø 0° 3° 5° 0° 3° 5°

Y 0.100 0.004

Z 0.150 0.250 0.350 0.006 0.010 0.014NOTES: 1. One dimple on package denotes Pin 1.2. If two dimples, then the larger dimple denotes Pin 1.3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.4. Package/Tray orientation: Package pin 1 will always be orientated towards the chamfer tray side (Dimension Z) as per

JEDEC standard JEP-95, CS-008




A5568-02

A

0L

Detail A

Y

D

C

Z

Pin 1

E

D1

b

Detail B

See Detail A

e

See Detail B

A1

A2

SeatingPlane

See Notes 1, 2, 3 and 4




A 1.200 0.047

A1 0.050 0.002

A2 0.950 1.000 1.050 0.037 0.039 0.041

b 0.150 0.200 0.300 0.006 0.008 0.012

c 0.100 0.150 0.200 0.004 0.006 0.008

D 19.800 20.000 20.200 0.780 0.787 0.795

D1 18.200 18.400 18.600 4 0.717 0.724 0.732 4

E 11.800 12.000 12.200 4 0.465 0.472 0.480 4

e 0.500 0.0197

L 0.500 0.600 0.700 0.020 0.024 0.028

N 48 48

Ø 0° 3° 5° 0° 3° 5°

Y 0.100 0.004

Z 0.150 0.250 0.350 0.006 0.010 0.014NOTES: 1. One dimple on package denotes Pin 1.2. If two dimples, then the larger dimple denotes Pin 1.3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.4. Package/Tray orientation: Package pin 1 will always be orientated towards the chamfer tray side (Dimension Z) as per





A5569-02

A

0

L

Detail A

Y

D

C

Z

Pin 1

E

D1

b

Detail B

See Detail A

e

See Detail B

A1

SeatingPlane

A2See Note 2See Notes 1, 3 and 4



Min Nom Max Notes Min Nom Max NotesA 1.200 0.047A1 0.050 0.002A2 0.965 0.995 1.025 0.038 0.039 0.040b 0.150 0.200 0.300 0.006 0.008 0.012c 0.115 0.125 0.135 0.0045 0.0049 0.0053D 19.800 20.00 20.200 0.780 0.787 0.795D1 18.200 18.400 18.600 4 0.717 0.724 0.732 4E 13.800 14.000 14.200 4 0.543 0.551 0.559 4e 0.500 0.0197L 0.500 0.600 0.700 0.020 0.024 0.028N 40 40Ø 0° 3° 5° 0° 3° 5°Y 0.100 0.004Z 0.150 0.250 0.350 0.006 0.010 0.014

NOTES: 1. One dimple on package denotes Pin 1.2. If two dimples, then the larger dimple denotes Pin 1.3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.4. Package/Tray orientation: Package pin 1 will always be orientated towards the chamfer tray side (Dimension Z) as per




2.12 Pinned Packages

2.12.1 Plastic Pin Grid Array (PPGA)For package drawings and dimensions of the PPGA package please refer to Chapter 13.

2.12.2 Micro Pin Grid Array (µPGA)For package drawings and dimensions of the µPGA package please refer to Chapter 13.

2.12.3 Flip Chip PGA (FC-PGA)For package drawings and dimensions of the FC-PGA package please refer to Chapter 13.

2.13 Ball Grid Array Packages

2.13.1 Plastic Ball Grid Array (PBGA)For package drawings and dimensions of the PBGA package please refer to Chapter 14.

2.13.2 Organic Land Grid Array (OLGA)For package drawings and dimensions of the OLGA package please refer to Chapter 14.

2.14 Chip Scale Packages (CSP)

2.14.1 Micro Ball Grid Array (µBGA)For package drawings and dimensions of the OLGA package please refer to Chapter 15.

2.14.2 Easy BGAFor package drawings and dimensions of the Easy BGA package please refer to Chapter 15.

2.14.3 Intel® Stacked CSPFor package drawings and dimensions of the Easy BGA package please refer to Chapter 15.

2.14.4 Molded Matrix Array Package (MMAP)For package drawings and dimensions of the Easy BGA package please refer to Chapter 15.



2.15 Cartridge Packaging

2.15.1 Single Edge Contact Cartridge (S.E.C.C.)For package drawings and dimensions of the S.E.C.C. package please refer to Chapter 16.

2.15.2 Single Edge Processor Package (S.E.P.P.)For package drawings and dimensions of the S.E.P.P. package please refer to Chapter 16.

2.15.3 Mobile Mini-CartridgeFor package drawings and dimensions of the Mobile Mini-Cartridge package please refer to Chapter 16.

2.16 Single In-line Leaded Memory Module Package (SIP)

2.16.1 Symbol List for Single In-Line Leaded Memory Module Family


A2 Overall Height

B Width of Terminal Leads

C Thickness of Terminal Leads


E Largest Overall Package Width Dimension Outside of Leads

e1 Linear Spacing between Centerline of body Terminal Leads (Standoffs)

L Distance from Seating Plane to End of Lead


Category Single In-Line Leaded Package

Acronym SIP

Lead Configuration Single Row

Lead Counts 30

Lead Finish Tin/Nickel

Lead Pitch 2.5mm




2.16.2 30-Lead Single In-line Leaded Memory Package (SIP)

A5571-02

A2

E

Be1SeatingPlane

D

L

Family: Small In-Line Leaded Memory Module (SIP)



A2 16.43 16.59 0.647 0.653

B 0.557 0.559 0.018 0.022

C 0.229 0.279 0.009 0.011

D 78.61 78.87 3.095 3.105

E 5.08 0.200

e1 2.54 0.110

L 3.18 Typical 0.125 Typical

N 30 30



2.17 Single In-line Leadless Memory Module (SIMM)

2.17.1 Symbol List for Single In-Line Leadless Memory Module Family


B Width of Terminal Pads

C Thickness of Terminal Pads


E Largest Overall Package Width Dimension Outside of Pads

e1 Linear Spacing between Centerline of body Terminal Pads(Standoffs)



Category Single In-Line Leadless Memory Module

Acronym SIMM

Lead Configuration Single Row

Lead Counts 30, 80

Lead Finish Solder Coat

Lead Pitch 0.100”




2.17.2 30 Pad Single In-Line Leadless Memory Module (SIMM)

A5572-01

e1

D

20.4

5 M

ax

6.35

± 0

.13

10.1

6 ±

0.1

3

0 3.18 ± 0.05

3.38Top View

C

ESide View

B

231369-68

Family: Single In-Line Leadless Memory Module



B 1.78 Typical 0.070 Typical

C 1.19 1.40 0.047 0.055

D 88.77 89.03 3.495 3.505

E 5.08 0.200


N 30 30



2.17.3 80 Pad Single In-Line Leadless Memory Module (SIMM)

A5573-01

e1

D

Front View

E

1 80

B

Back View

1 80

0.7"

0.05" ± 0.004/-0.003

1 Mbit32-lead PLCC(550 x 450 MILS)

Side View

231369-69

Family: Single In-Line Leadless Memory Module



B 1.04 Typical 0.041 Typical

C 1.19 1.37 0.047 0.054

D 117.98 118.24 4.645 4.655

E 8.38 0.33

e1 1.27 Typical 0.050

N 80 80 Typical



2.17.4 PCMCIA PC Card Type I and Type II

2.17.4.1 Type I

2.17.4.2 Type II

A5574-01231369-76

WPS

Connector

A5575-01231369-77

WPS

Connector

Battery



2.17.5 Type I PCMCIA Card Package Dimensions

A5576-01

2.130 (54.10)2.122 (53.90)

3 .378 (85.80)3.362 (85.40)

231369-78

Connector

0.041 (1.04)0.037 (0.94)

0.065 (1.65)0.061 (1.55)

0.041 (1.04)0.037 (0.94)

0.041 (1.04)0.037 (0.94)

#34

#68

#1

#35

0.067 (1.70)0.063 (1.60)

2X

Inch (mm)



2.17.6 Type II PCMCIA Card Package Dimensions

A5577-01231369-82

2.130 (54.10)2.122 (53.90)

3 .378 (85.80)3.362 (85.40)

Connector

0.041 (1.04)0.037 (0.94)

0.065 (1.65)0.061 (1.55)

0.041 (1.04)0.037 (0.94)

0.041 (1.04)0.037 (0.94)

#34

#68

#1

#35

0.067 (1.70)0.063 (1.60)

2X

Substrate Area

Interconnect Area

Protect

Battery

mm (Inch)



2.17.7 PCMCIA Card Physical Dimensions

2.17.8 Host Connector Pin Configuration for Both Type I and Type II

Length WidthInterconnect

Area (1)Substrate

Area (1)

Type I 3.370 ± 0.008(8.56 ± 0.20)

2.126 ± 0.004(54.0 ± 0.10)

0.65 ± 0.002(1.65 ± 0.06)

0.65 ± 0.002(1.65 ± 0.06)

Type II ± 0.008(85.6 ± 0.20)

2.126 ± 0.004(54.0 ± 0.10)

.065 ± 0.002(1.65 ± 0.06)

0.098MAX(2.5)

NOTES: 1. Interconnect area and substrate area thickness are specified from the IC memory card center line to either the top or

bottom surface.2. Millimeters are in parentheses ( ); otherwise inches.

Pin Type Pin Length (L) Pin #

Detect (3.6)0.134 (3.4)

36, 67

General (4.35)0.163 (4.15)

AllOther Pins

Power (5.1)0.193 (4.9)

1, 17, 34,35, 51, 68

NOTES: 1. Millimeters are in parentheses ( ); otherwise inches.



2.17.9 Host Connector Pin Configuration for Both Type I and Type II

2.17.10 PCMCIA Card Connection Socket for Type I and Type II

A5578-01

Engagement Area

231369-83

0.02 (0.5) Max

0.098 (2.50) Min

0.024 (0.60)0.016 (0.40)

L

15˚10˚

0.018 (0.46)0.016 (0.42)

110˚

0.018 (0.46)

Inch (mm)

A5579-01

Pin Insertion

231369-84

0.037 (0.94) Min

mm (Inch)



2.17.11 PCMCIA Card Connector for Type I and Type II

2.18 Revision Summary• General review of chapter

• Removed packages no longer being used by Intel

A5580-01231369-85

0.142 (3.60)0.136 (3.45)

0.049 (1.25)0.045 (1.15)

0.057 (1.45)0.053 (1.35)

0.037 (0.95)0.033 (0.85)

#1

#35

#34

#68

2.138 (54.30)2.132 (54.15)

0.037 (0.95)0.033 (0.85)

0.054 (1.37)0.046 (1.17)

Pin Layout2 row - 68 pin

0.054 (1.37)0.046 (1.17)

1.65 (41.9) Ref

mm (Inch)


e

s but,

t one ) are

t of

ve ess. ocess. er charge to

s, both

ing

Alumina & Leaded Molded Technology 3

3.1 Introduction

The packaging technologies used to manufacture or assemble three basic types of component packages are summarized in this chapter.

The package families, described in Chapter 1, provide the functional specialization and diversity required by device and product applications. Material and construction attributes of individual family members are provided by the following package technologies: (1) fired ceramic, (2) pressed ceramic, and (3) molded plastic. Intel’s packaging technology using organic substrates will bdiscussed in chapters 13, 14, and 15. Cartridge packaging assembly will be discussed in Chapter 16.

Each of the three package families described in this chapter have some similar process stepthe packaging materials and the form factors are uniquely different.

The assembly core technology process steps (die attach, wire bond, lid seal, finish) are moscommonly used in the industry today. However, several form factor modifications, driven on hand by the advent of “Surface Mount Technology” (Quad Flat Pack packages and Ball GridArray) and on the other hand by area array package socketing requirements (Pin Grid Arraynow the more commonly used form factors for microprocessors.

This chapter will review in detail those core packaging technologies that are common to mosthe standard IC package family types, i.e. DIPs, QFPs & Ceramic PGAs.

3.2 Die Preparation

Intel's die preparation consists of wafer mount and wafer saw process. Intel protects the actisurface of wafers from handling-induced defects by using a contactless wafer mounting procThe wafer is mounted to a mylar tape to ensure the die is in place during and after sawing prThe mounted wafer is sawn into singulated die followed by high pressure deionized (DI) watwash. The wafer wash process is properly characterized to ensure no silicon dust and staticbuild-up which will induce passivation damage. Intel uses 100% wafer saw through process prevent die chipping.

3.3 Die Attach

For these packages Intel uses two categories of die attach adhesive materials: (1) adhesiveorganic and inorganic; and (2) hard solders (gold-silicon eutectic). The choice of die attach material depends on the specific applications and its compatibility with the particular packagtechnologies to ensure the highest levels of reliability performance. Table 3-1 and Table 3-2 summarize the die attach materials used by package technology.


Alumina & Leaded Molded Technology

Figure 3-1 through Figure 3-4 are schematic cross-sections through each of the different die attach systems currently in use at Intel, for example, gold/silicon eutectic, silver-filled glass, and silver filled organic adhesives, epoxy, and cyanate ester. The components of each system are identified.

Figure 3-1. Gold-Silicon Eutectic

Table 3-1. Die Attach Materials by Package Technology

Package Technology Die Attach Material Type

Pressed Alumina Ceramic(CERDIP)

Silver-Filled Glass Inorganic Adhesive

Laminated Alumina Ceramic(PGA, CQFP, Side-Braze)

Gold-Silicon EutecticSilver-Filled Cyanate Ester

Hard SolderOrganic Adhesive

Molded Plastic Silver-Filled Epoxy Organic Adhesive

Table 3-2. Die Attach Material Summary

Au-Si Silver-Filled Glass

Silver-Filled Epoxy/Cyanate Ester

Wafer Backside Metallization for Die Attach

Required Not Required Not Required

Wafer Backside Metallization for Ohmic Contact

Not Required Required Required

Thermal Dissipation Good Good Fair

Electrical Conductivity Good Good Fair

Lead Frame Compatibility N/A N/A Good

Substrate Metallization Compatibility(a) Gold(b) Silver(c) A12O3

GoodGoodN/A

PoorGoodGood

GoodGoodN/A

Silicon

A5588-01240818-5

Gold/Silicon Eutectic Alloy

Reaction Zone(Metallurgical Bond)

Silver or Gold Thick-Film Metalization

Al203



Figure 3-2. Silver-Filled Glass

Figure 3-3. Silver-Filled Cyanate Ester

Figure 3-4. Silver-Filled Adhesive

Silicon

A5589-01

240818-6

Silver-Filled Glass

Al203

Silicon

A5590-01240818-35

Silver-Filled Cyanate Ester

Al203

Silicon

A5591-01240818-7

Polymide, Epoxy orCyanate Ester Ag-Filled Adhesive

Silver

Nickel

Copper



3.3.1 Purpose of Each Component

Wafer metallization provides an ohmic contact to the silicon die for the purpose of substrate biasing for those die attach media that do not readily form an ohmic junction. It provides a readily wettable surface for gold/silicon hard soldering and prevents premature oxidation (or aging) of the wafer backside during storage by acting as a diffusion barrier, thus ensuring that die attach integrity remains uncompromised.

Like the wafer backside, substrate metallization provides a readily wetted surface for hard soldering. Metallizations used in hermetic package technologies, both gold and silver, are readily wetted by the liquid solder at die attach temperatures and actually react with the solder to provide a high-integrity metallurgical bond to the substrate. Both substrate metallizations resist oxidation, which can impede wetting, and are electrically conductive for those devices that require electrical contact.

Plastic packages use a plated silver metallization to adhere to organic adhesives, which are electrically conductive. Silver-filled glass does not require a metallization, though it will adhere readily to silver.

Die attach media serve several purposes other than the obvious one of attaching the silicon to the substrate. They also provide a means of making an electrical connection to the die backside for those devices requiring it, as well as a path for the conduction of heat from the die to the ambient. For these reasons, the die attach media used at Intel exhibit good thermal and electrical conductivity.

The incoming quality of die attach materials is monitored through a series of specifications unique to each of the die attach media. Tests are performed to measure those specific characteristics necessary to ensure that materials meet the requirements of die attach applications.

3.3.2 Die Attach Process Consideration

From a process design standpoint, it is necessary to understand the limitations of each die attach process. Every die attach technology used at Intel has its own limitations and merits. The materials and process must be carefully characterized to ensure good package compatibility, reliability and manufacturability.

3.3.2.1 Au-Si Eutectic

There are three key considerations to the Au-Si Eutectic process. Foremost is the effect of processing temperature on die reliability and performance. It is necessary to design the silicon fabrication processes so that the device can withstand the Au-Si process temperatures during die attach. Next is the need to have good die backside metallization for high reliability performance. All wafers used in this process use a gold wafer backside metallization. The third consideration is the need for an excellent process control.

3.3.2.2 Silver-filled Glass (SFG)

SFG, like Au-Si eutectic, is limited to those devices which can withstand SFG processing temperature and time. The silicon fabrication processes should be designed to withstand the die attach process. Because of the organic content (solvent and resin binder) of the SFG paste, its removal is necessary for good adhesion. The larger the die, the longer is the drying/processing time for organic content removal.



There are also limits to the bond line thickness, both thin and thick, that constrain the process. In addition, it is imperative to maintain a nearly void-free die attachment. SFG is limited to (1) non-gold wafer backsides and substrates due to poor adherence to gold, and (2) inert or oxidizing processing ambients.

Like Au-Si eutectic, SFG requires close process control. Once processed, the SFG material is stable to extremely high temperatures.

3.3.2.3 Silver-filled Epoxy/Cyanate Ester

There are two significant considerations for epoxy and cyanate ester adhesives: the first is the upper temperature that the material can tolerate before decomposition of the polymer occurs, which is approximately 200° C for epoxy and 380° C for cyanate ester. The second is the optimum bond line thickness control, again a die stress-related concern. As with the other paste technologies, it is important to maintain a nearly void-free die attachment through control of the dispensed paste volume and pattern, coupled with a good curing temperature profile.

3.3.3 Processes

3.3.3.1 Au-Si

Figure 3-5 is a representation of the gold-silicon phase diagram. In this process, a pure gold preform is placed into a preheated ceramic package under a heated inert gas. The die is placed onto the preform and allowed to reach the preset die attach temperature.

Figure 3-5. Gold-Silicon Phase Diagram

A5592-01240818-8A

Atomic Percentage Silicon

10

L

0 10 20 30 40 50 60 70 80 90 100

Weight Percentage Silicon

1600

oC

1064.43˚

2.85

(Au)

1414˚

(Si)

363˚

J.C. Chonston

80706010 90 95 97 99

2800 oF

2400 oF

2000 oF

1600 oF

1000 oF

200 oF

1400

1200

1000

800

600

400

200

0

600 oF

200 oF



As the temperature is raised, silicon from the die begins to diffuse through the diffusion barrier on the die backside, and at 363 ° C it forms eutectic composition liquid. Once liquid formation occurs, the reactions proceed rapidly by liquid phase diffusion. As the temperature increases beyond the eutectic temperature, more silicon is dissolved from the die backside until the equilibrium volume of silicon is reached. The liquid also begins to dissolve the gold or silver substrate. The amount of gold or silver that dissolves depends on the temperature and the time of die attach.

Once the liquid is evenly distributed across the silicon backside to ensure intimate contact with all areas, the package and die are cooled. During cooling, silicon begins to precipitate from the saturated gold-silicon liquid. These precipitates grow epitaxially from the silicon die backside. Analysis using a transmission electron microscope has confirmed that the epitaxial region is continuous with the bulk silicon crystal structure. When the package again reaches the eutectic temperature, the solder solidifies with a characteristic eutectic-type microstructure. There is no solid solubility of silicon in gold or vice versa, as evidenced by the phase diagram for the system. The joint obtained upon cooling is metuallurgically continuous from the substrate to the die.

3.3.3.2 Silver-filled Glass

Silver-filled glass is a suspension of silver and low-softening temperature glass particles in an organic vehicle. In this process, the paste is automatically applied to the ceramic via a paste dispense system. After the paste is applied, the die is positioned within the dispensed pattern. Because of the high organic content of the paste, the SFG is carefully dried in a continuous furnace to remove the solvent (the presence of solvent will lead to poor adhesion to die). This leaves behind a resin that binds the silver and glass particles until subsequent processing can soften the glass. After drying, the material is carefully heated to remove the binder; the heating rate is determined by die size.

At higher temperatures, the glass begins to soften, and the silver particles begin to sinter together into a cohesive mass. Considerable shrinkage accompanies the reactions at higher temperatures, and care must be taken to ensure that the minimum bond line thickness requirements are maintained after shrinkage. At the highest temperature, the glass wets the silver particles, silicon surface, and ceramic substrate, creating a strong chemical bond between the silicon and the ceramic. Once the material has reached the maximum density, the package is cooled and readied for subsequent assembly operations.

3.3.3.3 Silver-filled Epoxy/Cyanate Ester

Silver-filled epoxy/cyanate ester used by Intel is a solventless system, which eliminates the processing issues associated with drying. Because of the chemical structure of these adhesives, water vapor evolution during process is also not a concern. As with the other paste technologies (polyimide and SFG), the paste is automatically dispensed and the die is positioned with automated equipment, with care taken to ensure a void-free die attach. After placement, the package is heated to the epoxy resin cure temperature to polymerize the epoxy/cyanate ester and create the final chemical bond between the silicon and lead frame or substrate.

3.3.3.4 Backside Requirements and Controls

The wafer backside process can affect the integrity of the joint created during die attach. From gold-silicon eutectic work, it has been determined that a metallized surface is required for highly reliable joining. The quality of the metallization modulates the wetting of the liquid to the silicon and enhances the quality of the braze joint. Surface roughness plays a significant role in eutectic die attach; smooth surfaces wet more readily and more quickly than rougher ones.



tip die zzle oid.

To prevent premature oxidation of the metallization, a diffusion barrier is necessary. The barrier is required to adhere to both silicon and gold, yet not interfere with the integrity of the final joint. The barrier kinetics also must allow rapid diffusion of silicon at the die attach temperatures. Because of this, it is necessary to control the thickness of the barrier metal. The gold thickness must also be controlled to prevent oxidation of the barrier metal.

3.3.3.5 Ohmic Contact

Some MOS devices require an ohmic contact to the die backside. To achieve an ohmic contact, a metallization is required for all paste technologies, as the silver will not form a low-resistance ohmic contact at any of the die attach times or temperatures. An ohmic contact can be achieved with gold-silicon eutectic die attach without the use of a metallization, as the gold readily diffuses at the die attach temperature, creating a low-resistance contact. A wafer backside metallization is necessary for the creation of a highly reliable eutectic joint.

3.3.4 Performance and Engineering Characteristics

3.3.4.1 Die Size Limitations

• Au-Si. Larger dies can be attached with this technique. Dies as large as 1.8 x 1.8 cm (0.7 x 0.7 in.) have been successfully attached by this technique.

• Silver-Filled Glass. Within Intel it has been demonstrated that dies as large as 1.0 x 1.0 cm (0.4 x 0.4 in.) can be successfully attached by this technique.

• Silver-Filled Epoxy/Cyanate Ester. Because there are no limitations on solvent or water vapor evolution for this type of paste, there are no known die size limitations. Dies as large as 1.3 x 1.3 cm (0.6 x 0.6 in.) have been successfully attached using this die attach material.

3.3.4.2 Joint Strengths

Table 3-3 summarizes the die attach joint strengths for each die attach material used at Intel today. As shown, measured strengths easily exceed the military specification for die attach strength as determined by tensile testing.

Typical failure modes related to the die attach process are die cracking and cohesive failure at die attach interface. Intel’s die attach process is characterized to prevent these failures. A roundejector die attach pick up process is used to avoid die backside damage. Intel’s die attach noand dispensing setup is designed for optimum adhesive coverage with minimum die attach v

Table 3-3. Typical Tensile Bond Strengths of Various Die Attach Media

Die Attach MediaTensile Strength

(kg/cm2)Tensile Strength

(psi)

Au-Si 500 >7000

Silver-Filled Glass 100 1400

Silver-Filled Epoxy 140 2000

Silver-Filled Cyanate Ester 140 2000



3.3.4.3 Backside Metallization Controls

Control of the wafer backside metallization process is essential for high-integrity gold-silicon eutectic bonds. As mentioned, it is important to control the thickness of both the barrier metal and the gold. It is also necessary to control the deposition conditions to minimize the oxygen content of the barrier metal. Failure to do so can result in a poorly wettable surface that does not allow rapid, uniform silicon diffusion at the Au-Si die attach temperatures.

3.4 Wire Bonding

Wire bonding is an assembly step that connects the input/output of the device to the package terminals. The thermosonic gold wire bonding and ultrasonic aluminum or gold wedge wire bonding are two common bonding techniques used. At this assembly process stage, the majority of the final cost is already in the device. Thus, it is critical that the highest yield of wire bonding is achieved. The utilization of either wedge or ultrasonic bonding basely dependence of wire pad pitch capability. The former capability will be able to support finer pad pitch up to 65um.

To a achieve a high-quality wire bond, bonding parameters, piecepart material property and bond pad metallization integrity must be well understood and controlled.

Intel works closely with wafer fab process development teams and wire and lead frame/ceramic package vendors to obtain required characteristics for wire, leadframe/package and bond pad metallization.

Critical parameters for wires are diameter, tensile strength, elongation, chemical composition and surface contamination.

Key bond pad characteristics include surface hardness, roughness, cleanliness (freedom from glass residues, oxide and silicon dust), and metallization integrity. The consistency of piecepart materials properties is essential for a high yield and reliable bond process.

3.4.1 Bond Quality Monitors

Intel uses a variety of techniques for measuring the quality and reliability of bonds. The most frequently used techniques are:

• Visual inspection

• Bond pull

• Bond shear test

• Bond etching

• Electrical testing

• Baking test

• Thermal cycling stress

• Surface analysis

3.4.1.1 Visual Inspection

Visual inspection is used to monitor bond quality. Problems that could occur are smashed bonds, small bonds, breaking wires, off-pad and cratering.



3.4.1.2 Bond Pull

The bond-pull test is a primary method used for optimizing the bonding window and monitoring the bond quality. The pull test is influenced by package configuration and wire length. Test results include bond strength and mode of failure.

3.4.1.3 Shear Strength

Intel optimizes bond adhesion strength of gold ball bonds by using the shear strength test. The failure mode and bond strength are used to measure the ball bond quality and reliability.

3.4.1.4 Bond Etching

Bond etching measures the condition of layers under the bond pads after bonding. With this technique, the ball (wire) and pad metallization is removed, and the underlayer materials are examined for defects.

3.4.1.5 Electrical Testing

Electrical testing measures the quality of the bond. A non-sticking bond will result in an electrical open, while two adjacent bonds in contact will result in an electrical short.

3.4.1.6 Bake Test

Bake test measures the degree of intermetallic compound formation of gold-aluminum (Au/Al). Over diffusion of aluminum atoms into gold can lead to Kirkendail voiding at the gold and aluminum interface resulting in bond lifting. Bake test will be done normally followed by electrical test and/or bond pull.

3.4.1.7 Thermal Cycling Stress

Thermal cycling measures reliability of wire bond integrity through accelerated and extreme environment condition. Thermal cycling accelerates bond pad fracture, bond lifting, and metal lifting due to bonding process deficiency or package configuration. Thermal stress will be done normally followed by electrical test and/or bond pull.

3.4.1.8 Surface Analysis

Surface analysis techniques such as energy-dispersive X-ray analysis (EDX), wave-length dispersive X-ray analysis (WDX), Auger, and scanning electron microscopy (SEM) are some failure analysis tools Intel uses to identify the (1) presence of contamination, (2) extent of intermetallic compound formation, bond metalization surfaces and (3) bond irregularities.

3.5 Plastic Molding Process

The technology advancement of molding compound, transfer molding, and package design have made it possible for Intel to manufacture highly reliable plastic component packages.



rial

die

f the g

wder rough llowing s the the

3.5.1 Molding Compound

Molding compound is a composite material, with each component providing a set of properties critical to the overall performance of the system.

The composite matrix material used in Intel packages is an epoxy cresol novolac polymer. This crosslinked material is dimensionally stable, ionically clean, and resistant to assembly process and field-use temperatures. The composite’s largest component by weight is silica filler, added toprovide control of thermal expansion coefficient, thermal conductivity and enhance the matetoughness. The molding compound was also designed for moisture resistance and manufacturability. Intel optimizes the silica filler size and shape to give better flow property, tool wear resistance and moisture resistance property.

The molding compound consists of elastomeric toughening fillers, flame retardants, couplingagents to improve adhesion between matrix and filler, and release agents to allow removal oproduct from the mold. Figure 3-6 is a scanning electron micrograph showing the epoxy moldincompound structure.

Figure 3-6. Cross Section View of Epoxy Molding Compound

3.5.2 Molding Process

Intel suppliers provide partially reacted epoxy molding compound in the form of pelletized popreforms. The epoxy is processed in a transfer molding press which drives the compound ththe heated mold. The molding compound viscosity decreases as it contacts a heated mold, ait to flow easily around the bonding wires and to fill the package cavity. Viscosity increases acuring reaction takes place, until the molding compound is hard enough to be removed from

A5687-01240818-32

Epoxy Matrix(Dark Background) Silica Fillers

Toughening Particles



mold. A schematic plot of molding compound viscosity as a function of time is shown in Figure 3-7, where T2 is greater than T1. Figure 3-8 outlines the primary steps in the transfer molding process.

Figure 3-7. Molding Compound Viscosity—Time Behavior (Schematic)

Figure 3-8. Encapsulation Process Flow

Molding process parameters such as cure temperature, compound transfer rate, and cure time are controlled to ensure quality and reliability of a molded package. Of equal importance are the designs of the mold runner and gate systems, the path through which the molding compounds enter the package cavity. Potential defects seen if encapsulation process is not optimized such as

A5593-01240818-33

Time

Vis

cosi

ty

T1

T2

T2 T1>Note:

A5594-01240818-34

Pre-heated Molding Compund Pellets

Loaded into Mold Die

Die Attached and Wire Bonded Lead Frames Loaded

into Mold Press

Molding Clamp Pressure Applied

MoldingCompound

Transfer

Molding CompoundHardens During Cure

Molding Clamp Pressure Released and Parts Ejected

Parts DegatedRunners Removed



to the that

cal

incomplete encap fill, encap void and wire sweep. Intel uses design of experiments (DOE) methodologies that include these variables throughout the development and optimization of the molding process.

3.5.3 Packaging Reliability Considerations

The molded plastic is a composite system composed of:

• A copper alloy lead frame

• Silver-filled polymeric die attach adhesive

• Silicon chip

• Gold bonding wires

• Epoxy molding compound

Each of these components has a unique set of physical properties, and mismatches of these properties, such as the coefficient of thermal expansion, elastical modulus will present a challenge to maintain the mechanical integrity of the bulk materials and the interfaces between them.

Because of different rates of expansion and contraction, stresses concentrate at the interfaces between materials during the temperature cycle as seen in accelerated reliability testing and circuit board mounting. When these stresses exceed the interfacial strength between materials, package delamination or cracking can occur. The presence of absorbed moisture in the molding compound exacerbates this phenomenon during surface mount process.

Precautions are taken to prevent failure of the encapsulant during processing, testing, and application ambient. From the material perspective, the supplier of the molding compound synthesizes the polymer to exhibit minimum moisture absorption. In addition, coupling agents are used to maximize adhesion between the epoxy matrix and silica filler to limit moisture ingression. Optimization of other material properties, such as flexural strength, modulus, and toughness, ensures that the material can perform under severe moisture and temperature-cycling conditions without the occurrence of delamination or cracking, which can lead to the ingress of corrosion-causing contaminants. The molding compound contains elastomeric toughening agents that curtail the growth of cracks should they occur. These “low-stress” materials also provide protection fragile chip surface by preventing cracking and shear deformation of the thin-film structures make up the circuitry.

Careful package and process designs also ensure integrity of the molded package. Packageengineers employ design features that enhance component robustness by creating mechaniinterlocks between molding compound and lead frame. Assembly process engineers designmaterial flows that maximize adhesion and limit exposure to moisture during manufacturing,shipping, and board mounting.

3.6 Lead Finish

Intel provides three basic lead finishes:

• Gold Plate

• Solder Coat

• Solder Plate



Each type of lead finish offers advantages for specific applications and for internal processing.

3.6.1 Gold Plate

Gold-plated finish is recommended for socket applications only. Package types which use gold plated leads include the ceramic laminate family, including pin grid arrays (PGAs), side-braze dual in-line packages (DIPs), and both leaded and leadless chip carriers.

Previously, gold was considered a universally superior lead finish because of its solderability and electrical and nonoxidizing properties. Over the past several years, however, it has been determined that soldering gold-plated component leads directly into a PC board has disadvantages. Excess gold in the solder joints can result in the formation of a brittle alloy, causing the joints to fail over time in high-vibration or board-flexing environments.

For example, in military applications requiring leadless chip carrier mounting, such considerations become critical. Currently, military requirements demand a solder coated part, replacing gold in direct soldering used for both leadless and leaded components. Gold plating remains the lead finish of choice for socketed units.

3.6.2 Solder Coat

Solder coat components offer the distinct advantages of a low melting point (183° C) and resistance to aging.

The composition of solder coat is the eutectic alloy of 63% tin and 37% lead. Intel normally applies the coating in the following sequence: (1) cleaning the leads, (2) applying a flux, (3) dipping the leads into molten solder, and (4) finishing with a hot water rinse. Great care is taken to minimize any thermal shock to the package and die during solder coat processing and cleaning of the unit after coating. Controlling the temperature profile is important to minimize the thermal stress build-up in the package.

Intel provides solder coat lead finish mostly on plastic and ceramic DIPs for commercial products. The customer can use this lead finish in a variety of PC board assembly processes, including wave soldering, infrared, and vapor phase.

3.6.3 Solder Plate

Intel uses tin-lead alloy plating for plastic quad fine-pitch, quad flatpack, and PLCC packages.

The solder uses co-deposited elements from an alloy composition of 85% tin and 15% lead. As shown in Figure 3-9, the plating on the packages with copper lead frames, with a minimum thickness of 200 microinches, provides full coverage of the copper without exposing any formed intermetallics to the air. At the same time, solder plate produces a very solderable finish with a melting point of approximately 215° C. Like tin-plated leads, those plated with tin-lead alloy can be directly soldered using infrared, vapor phase or socket form.



Figure 3-9. Solder Plating on a Lead Frame

3.6.4 Lead Finish Process Flow

The following sections illustrate the process flow for each type of Intel lead finish.

3.6.4.1 Gold

Packages with gold lead finish are purchased from the package vendor as raw piece parts.

3.6.4.2 Solder Plate

Figure 3-10. Process Flow for Tin and Solder Plating

A5595-02

Plating Region

A5596-0124081810

Package Assembly

Fixturing

Pretreatment

Rinse

Plate

Rinse

Dry

Quality Assurance

Process Step

Mfg. Quality Gate



3.6.4.3 Solder Coat

Figure 3-11. Process Flow for Solder Coat

3.6.5 Process Controls

The plating process is controlled by monitoring a combination of several input and output parameters such as:

• Physical arrangements and condition of the plating anodes and fixtures, as well as distance to the part to be plated.

• Chemical analysis and control of solutions in pre-treatment, plating and rinsing baths.

• Plating parameters such as temperatures, rinse flows, voltage, current density and process times.

• Output quality such as solder thickness, composition, solderability and appearance quality.

The solder coat process is controlled and monitored for:

• Physical height of the solder and condition of fixtures.

• Chemical analysis and control of solutions in pre-treatment, solder bath and rinsing bath.

• Process parameters such as conveyor speed, flux density, preheat temperature, solder temperature and package temperature profile.

• Output quality such as solder thickness, composition, solderability and appearance quality.

A5597-0124081811

Package Assembly

Fixturing

Pretreatment

Rinse

Dry

Fluxing

Preheat

Solder Coat

Cool

Rinse

Dry

Quality Assurance

Process Step

Mfg. Quality Gate



3.6.5.1 Lead Forming

Lead forming is a twofold assembly operation that bends and trims plated or solder-dipped leads to meet specified dimensional accuracy. Leads can be formed into three standard configurations: gull-wing and J-lead for surface mount packages, and straight form for through-hole mounting. During the forming process, extreme care is taken to avoid excessive abrasion to the solder, exposed base metal, scratches and solder flakes. Lead forming tool maintenance is critical to ensure good lead quality.

Figure 3-12. Formation of Gull-Wing Leads

A5598-01

240818-21240818-28

240818-12 240818-13Gull-Wing Forming

Lead Cutting/Bending

ClampShoulders Clamp

Shoulders

Gull Wingis formed

45 Degree

Bend

Cut 3 Tie Bars



Figure 3-13. Formation of Gull-Wing Leads (continued)

A5599-01

240818-30

240818-14 240818-15

SpankingLead Length Cutting

Lead Tip BurrsFrom Cutting

FlattenLead Tips

ClampLeads

240818-31

Cut LeadsTo LengthCut LeadsTo Length



Figure 3-14. Deflash, Trim and Form of J-Leads on PLCCs

As part of the lead-forming process, dambars and excess molding compound or flash that has flowed between the leads and out to the dambars are removed simultaneously from the leads. This step electrically isolates the leads. Dambar removal and lead forming processes can either be done on two separate machines or an integrated machine.

Finally, individual units are separated or singulated from the lead frame and carefully transferred into tubes or trays before being sent to the testing process. These transport media such as tubes and trays are designed to protect the leads.

A5601-01

Step 1. Lead Length Cut

Step 2. Lead Tip Bend by 90˚

Step 3. Shoulder Bend by 60˚ and 77˚

Step 5. Final Curl by Calibration Block

Step 4. Shoulder Bend by 90˚



3.7 Hermetic Sealing

3.7.1 Packaging Options

Hermetic sealing of IC packages is used to seal the die from the external environment, specifically from water vapor and contaminants that can shorten the lifetime of a sensitive electronic device.

Three types of hermetic seals are:

• precious metal eutectic alloy reflow (laminated ceramic package family),

• soft solder metal alloy reflow (laminated ceramic package family), and

• low melting-temperature glasses (pressed ceramic package family).

The precious metal eutectic alloy-sealed packages and soft solder metal alloy-sealed packages are of the laminated ceramic type. The precious metal eutectic alloy-sealed packages involve the brazing of a metal lid to a gold-plated thick-film seal ring on the ceramic. The second method uses soft solder metal alloy to fuse a ceramic lid to the seal ring of the ceramic package. The glass-sealed packages utilize glass to create the seal between pressed ceramic pieceparts. Figure 3-15 illustrates the relative hermeticity of various sealing materials. It can be seen from the graph that a metal seal provides the highest level of hermeticity, followed by glass and ceramic seals.

Figure 3-15. Relative Hermeticity of Materials

A5602-01

10 10 10 10 10 10-4 -8 -10 -12 -14 -16

Metals

Glasses

Fluorocarbons

Silicones

Epoxies

Permeability (gm/cm-s-Torr)

MIN H DAY MO YR 10 100

Thi

ckne

ss (

cm)

10 1

10 0

10-1

10-2

10-3

10-4

YR YR



3.7.2 Materials

3.7.2.1 Laminated Ceramic Package Sealing

Two metal-sealed methods are: (1) precious metal eutectic alloy reflow; (2) soft solder metal alloy reflow.

3.7.2.2 Precious Metal Eutectic Alloy ReFlow (Metal Lid)

The precious metal eutectic reflow process utilizes a gold-tin eutectic hard solder to create the hermetic seal. Alloy composition is 80% gold, 20% tin, and has a melting point of 280° C (see Figure 3-16). This solder has excellent wetting characteristics to the seal ring and lid materials, and high resistance to thermal fatigue. Seals created by the Au-Sn alloy can withstand condition C (-65°

C -150° C) thermal cycles.

Figure 3-16. Au-Sn Phase Diagram

A5604-01240818-22

10 20 30 40 50 60 70 80 90

Atomic Percentage Gold

Sn 10 20 30 40 50 60 70 80 90 Au100

200

300

400

500

600

700

800

900

1000

1100C

1064.43

(Au)

49086.2 96.8

418

280309

252217

231,968

03 10

L

(Sn)

Weight Percentage Gold

β δγ300 F

500 F

700 F

800 F

1000 F

1200 F

1400 F

1700 F

˚

˚˚

˚ ˚˚

˚

˚

˚

˚

˚

˚

˚

˚

˚

1900 F

˚



Figure 3-17. Schematic Cross-Section of a Metal Lid Seal Package (Thicknesses Not to Scale)

The gold-tin eutectic seal is made to a seal ring on the surface of the alumina ceramic. The seal ring is composed of a tungsten thick film that is co-fired to the ceramic material and plated with a thin nickel diffusion barrier and gold overplate. The gold overplate prevents oxidation and provides a wettable surface for the solder. Figure 3-17 is a schematic of the seal area.

The lid material is gold-plated Alloy 42 (a nickel-iron alloy with low thermal expansion) to which is attached an 80% gold, 20% tin alloy (eutectic composition) preform. The seal preform is attached by spot welding. The lid material was chosen for its stiffness and because the thermal expansion of Alloy 42 is quite close to that of aluminum oxide ceramic. The stiffness prevents damage during testing, and the low coefficient of thermal expansion (CTE) difference minimizes stress at the seal due to thermal expansion mismatch.

The gold thickness of the plating used in the seal ring area is important to the success of sealing this system. Gold thickness must be controlled to prevent premature nickel diffusion and oxidation at the gold surface, which can create a poorly wetted surface that will result in seal defects. The nickel diffusion barrier prevents the interdiffusion of tungsten and gold that can also result in seal defects.

The seal preform width and thickness are also specified and controlled to ensure that an adequate amount of solder is present to create a continuous seal.

3.7.2.3 Soft Solder Alloy Reflow (Ceramic Lid)

The soft solder alloy reflow method is similar to the precious metal eutectic alloy reflow method with the exception of the lid and sealant material. It involves the fusing of a ceramic lid onto the ceramic package using a five-element lead-based soft solder. In this method the lid and package are of the same material thus minimizing thermal mismatch which can pose a reliability concern to bigger IC packages. Figure 3-18 is a schematic cross-section of a ceramic lid seal package.

The sealing process takes place in a forming gas environment which removes oxides from the sealant surface. Oxides, when present, inhibit solder flow and cause non-wetting which results in a non-hermetic seal. The pattern and solder dimensions are optimized to ensure maximum seal quality and reliability performance.

A5828-012400818-24

Gold PlatingNickel PlatingTungstenCofired Thick Film

AI203 AI203

Gold-Plated Alloy Az LID

Gold-TinSeal Preform

(Spot-Weldedto Lid)

After SealConstruction



hich with the e most stant to

Figure 3-18. Schematic Cross-Section of a Ceramic Lid Seal Package (Not to Scale)

3.7.2.4 Glass-sealed Pressed Ceramic Packages

In glass-sealed packages, a ceramic lid is sealed to the base ceramic with a vitreous (noncrystallizing), lead-based glass having a low melting temperature. The glasses chosen for hermetic sealing are lead-zinc borates that generally seal in the 415-450° C range. Figure 3-20 illustrates the vitreous glass-forming region (region A) in the lead-zinc-borate system from wthese glasses are chosen. The glasses used in the industry have composition in this range, final selection based on obtaining the lowest possible processing temperature. As a result, thcommonly available seal glasses have very similar compositions. The glasses are highly resichemical plating baths (see Table 3-4) and have excellent thermal shock resistance.

A5606-012400818-36

Gold PlatingNickel PlatingTungstenCofired Thick Film

AI203 AI203

Ceramic LidMetallization

Layer

Lead-BasedSolder



Figure 3-19. Lead-Zinc-Borate Phase Diagram

The glasses used for package sealing have high thermal expansions relative to the ceramic. To reduce thermally induced package stresses, it is necessary to reduce the thermal expansion of the glasses by adding low-thermal-expansion fillers. These fillers are chosen to be compatible with the lead glass and do not react during processing.

Table 3-4. Chemical Durability of Glasses Weight Loss (mg/cm2/hr)

Glass Type

Chemical Treatment Intel B C D

50% H2SO4, 95° C, 1 hr. 8.65 2.32 5.89 0.88

50% H2SO4, 25% HNO3, 25° C 28.44 25.44 25.32 18.00

5% HNO3, 25° C, Direct Transfer to 50% H2SO4 at 95° C

323.60 385.60 226.80 250.80

NOTE: Glasses must exhibit chemical durability to withstand the lead-plating baths.

A5607-01240818-25

Zn0

Pb0B 02 3

A

B



the lasses.

d is d and

n

as ing

furnace ealing

Because the glasses have similar compositions, they have similar strengths. Table 3-5 lists the measured bending strengths for several different sealing glasses commonly used. The glass used by Intel can be seen to have bending strengths equivalent to other commonly used glasses. The fracture toughness of Intel’s sealing glass is also found to be quite similar. It is expected thatmechanical performance of Intel’s sealing glass will be equivalent to other commonly used g

Figure 3-20. Schematic Cross-Section of Glass-Sealed Package

3.7.3 Processes

3.7.3.1 Laminated Ceramic Processing

Sealing of metal-sealed packages is accomplished in a continuous belt furnace. The metal licentered and clipped in place to ensure that the seal ring and preform remain properly alignethat sufficient pressure is exerted on the lid to provide good contact. The units are elevated itemperature past the melting temperature of the alloy and allowed to soak at the sealing temperature. The soak period allows the molten metal time to wet all the sealing surfaces sufficiently and to form an integral metallurgical bond with the seal ring and lid plating.

Sealing can be accomplished in either an inert (nitrogen) or reducing atmosphere (forming gN2H2). The seals obtained with either atmosphere are equivalent in performance. The reducatmosphere is used to build additional margin into the sealing process.

The sealing process is controlled by monitoring the seal temperatures with a thermocouple embedded in a package that is passed through a fully loaded furnace. This ensures that the profile obtained is representative of that seen by actual product. Water vapor content of the satmosphere is also controlled to ensure that the final internal-cavity water vapor levels meetindustry requirements.

Table 3-5. Bending Strengths and Fracture Toughness of Several Lead-Based Sealing Glasses

GlassFour Point Bending Strength

(MPa)Fracture Toughness

(MPa )

Intel 20.1 1.0

B 21.4 1.1

C 20.0 0.9

m

A5608-01240818-27

CeramicCap

Cap Glass

LeadFrame

BaseGlass

BaseCeramic

Construction After Seal

AI 02 3



Two ne leak the

a high-tainer nit is m of , as the

3.7.3.2 Pressed Ceramic Processing

Glass-sealed packages are sealed in a continuous dry air atmosphere belt furnace. Caps and bases are held in fixtures during the seal process to provide proper alignment of the top and bottom of the package. No clips are used; the package weight is sufficient to create the seal. Because glass does not have a sharp melting point, it is necessary to hold the units at the seal temperature for sufficient time to allow glass flow and wet the metal lead frame and ceramic, thus creating the final seal. Insufficient time will result in noncontinuous seals or incomplete flow, causing glass depressions between the leads. These depressions in their worst form can create a continuous path to the cavity (non-hermetic), or in less severe cases act as a stress riser and result in package damage during subsequent handling. Sealing is performed in an oxidizing ambient (dry air) to prevent reduction of the lead glass.

As with the metal-sealed packages, the process is controlled by profiling a fully loaded furnace by means of a thermocouple embedded in a CERDIP-type package, to get an accurate representation of the actual sealing conditions. Water vapor content and flow rates of the atmosphere are controlled to ensure that the internal-cavity water vapor requirements are met.

3.7.4 Performance

Intel’s hermetic packages can be tested for hermeticity using two tests: fine and gross leak. tests are required, since neither test can adequately detect the entire range of leak sizes. Fiuses helium and a mass spectrograph to identify fine leaks. Larger leaks do not show up, asgases leak out too quickly for the detectors to identify. The industry-acceptable leak rate for hermetic packages is less than 5 X 10-8 Std. CC atm/min.

Gross leak testing, which identifies larger leaks that fine leak testing cannot detect, employs vapor pressure fluorocarbon liquid as the detection medium. The unit is pressurized in a conof the fluorocarbon to force the liquid into potential leakage paths. After pressurization, the uimmersed in a hot bath, which vaporizes the fluorocarbon trapped in the leak. A steady streabubbles indicates the location of the leak. The gross leak test cannot be used for small leaksliquid will not penetrate leaks smaller than a certain size.


• General review & update of all sections


ding ke the r els

models

r

a

ntire

stics cess. tween e

ges es rid e the

Performance Characteristics of IC Packages 4

4.1 IC Package Electrical Characteristics

As microprocessor speeds have increased and power supply voltages have decreased, the function of the microprocessor package has transitioned from that of a mechanical interconnect which provides protection for the die from the outside environment to that of an electrical interconnect that affects microprocessor performance and which must be properly understood in an electrical context. Inherent in understanding the electrical performance effects of the package is the need for electrical characterization of the package. The package is a complex electrical environment and the characterization of this environment is a multi-faceted task that consists of models constructed from both theoretical calculations and experimental measurements.

In simple terms, a package electrical model translates the physical properties of a package into electrical characteristics that are usually combined into a circuit representation. The typical electrical circuit characteristics that are reported are DC resistance (R), inductance (L), capacitance (C), and characteristic impedance (Z_o) of various structures in the package. A package model consists of two parts, both of which are necessary for fully understanding the electrical performance effects of the package environment on Intel’s microprocessors.

The first is an I/O lead model that describes the signal path from the die to the board. Depenupon the complexity of the model required for simulation purposes, the I/O lead model can taform of a simple lumped circuit model, a distributed lumped circuit model, a single-conductotransmission-line model, or a multiple-conductor transmission-line model. While lumped modcan adequately model simple effects, such as DC resistive voltage drop, more sophisticated like the multiple-conductor transmission-line model include effects such as time delay and crosstalk.

The second part of a package model is a power-distribution network that describes the powescheme of the package. Like the I/O lead model, the sophistication of the power-distribution network can vary from a simple distributed lumped model to a complex circuit network calledPEEC (partial-element equivalent circuit) network. The simpler models can describe gross electrical characteristics of the power-distribution network, such as DC resistive drop for the epackage, whereas the more complex models enable the analysis of the effects of the power-distribution topology.

Experimental characterization of the package can include measurements of trace characteriand power loop parasitics, to name a few of the package aspects that can be characterized.Experimental characterization is usually the final, validation stage of the package-design proCare must be taken in determining the characteristics that are measured. If a comparison bemeasured and modeled data is to be made, then the same assumptions used in obtaining ththeoretical package model must be replicated in the test environment.

The following sections provide an overview of basic package modeling terminology and methodology, an overview of experimental characterization, and modeled data for the packathat Intel uses for its most advanced microprocessors. These products are housed in packagrepresentative of a broad spectrum of package technologies, including CPGA (ceramic pin-garray), PPGA (plastic pin-grid array), H-PBGA (high thermal plastic ball grid array), TCP (tapcarrier package), OLGA (organic land-grid array), and FC-PGA (flip-chip pin-grid array). For


Performance Characteristics of IC Packages

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sake of completeness, package parasitics data for older package technologies are included in the final part of this section. The package types included are multilayer molded (MM-PQFP), ceramic quad flatpack (CQFP), plastic leaded chip carrier (PLCC), quad flatpack (QFP, SQFP, TQFP), and small outline packages (TSOP, PSOP). These packaging technologies are no longer used foleading-edge microprocessors but are still used for other products.

Since the packages used for Intel’s microprocessors are custom designed for each product,parameters given in the following sections may not reflect the actual values for a particular product. The actual parameters can be obtained by contacting a local Intel sales office. For electrical parameters of packages not listed, please contact your local Intel field sales office.

4.1.1 Terminology

4.1.1.1 DC Resistance (R)

The DC resistance (R) is normally the cause of IR voltage drops in the package. Reduction oresistance is particularly important in the power and ground paths. DC resistance is determinthe cross-sectional dimensions (width and thickness), material, and length of the lead. The Dresistance of an I/O lead with cross-sectional area, A, length, L, and resistivity, ρ, can be calculated using:

Equation 4-1.

Ceramic packages have relatively high resistance because of the high resistivity of the tungsalloy metallization used with ceramic technology. Plastic/organic packages have much lowerresistance because the metallization used is either copper or a copper alloy. The resistivity ocopper or copper alloys is approximately a factor of 6-12 lower than that of tungsten alloys.

4.1.1.2 Capacitance (C)

Capacitance (C) is determined by the lead length and cross-sectional dimensions, the spacibetween leads, the spacing between the lead and the power or ground plane, the dielectric cof the surrounding material, and the number of leads involved. The relative dielectric constanthe material used for ceramic packages is in the range of 8–10. The dielectric constant of thmaterial used for plastic packages is in the range of 4–6. There are formulas for the capacitaclassic geometries; however, the capacitance for a particular structure in a package must uscalculated using a software modeling tool. The formula for the capacitance of a parallel platecapacitor can be used to deduce the general relationship between geometry and capacitanccapacitance for this structure, neglecting fringing fields, is:

Equation 4-2.

where A is the area of one of the plates, ε is the permitivity of the material separating the plates,and t is the thickness of the material.

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Capacitances which are important to package electrical performance are “loading” capacitan“lead-to-lead” capacitance, and “decoupling” capacitance. The loading capacitance is the tocapacitance of a lead with respect to all surrounding conductors. The lead-to-lead capacitancmutual capacitance between the two leads. The loading capacitances are the diagonal termso-called “short-circuit” capacitance matrix, and the lead-to-lead capacitances are the off-diaterms. The lead-to-lead capacitance and the mutual inductance determine the extent of electromagnetic coupling between the two leads. Decoupling capacitance is the total capacibetween the power leads and the ground leads. In a ceramic PGA with power/ground planesdecoupling capacitance is due to the capacitance between power and ground planes, as weadded discrete capacitors to the package. In plastic PGA packages, decoupling capacitanceusually provided by adding discrete capacitors to the package. Decoupling capacitance servreservoir which provides part of the energy required when buffers switch. This reduces the Avoltage drop, also called the switching noise or the ground bounce, of the power/ground path

4.1.1.3 Inductance

A simple definition of inductance (L) is the property of a conductor that describes the proportionality between current change and induced voltage. An inductor is any conductor awhich there is a voltage drop when there is a time-varying current present. This aspect of a pis important in determining the extent of the effects of crosstalk and simultaneous switching nThe classical definition of inductance implies that the inductance is that of a current loop, howa loop can be segmented, and partial-self and partial-mutual inductances can be attributed tsegment. This is a useful concept for analyzing package AC noise and is widely used today.example, a pin inductance is a partial-self inductance.

Another useful term is the “open-loop” inductance which is the inductance of a loop with gaptwo ends. We can visualize a segment of a transmission line as an open-loop and the total inductance of that segment as the open-loop inductance. Inductances used in analyzing behsuch as propagation delay and crosstalk of electrical interconnects are, in general, open-looinductances.

When partial inductances are used in package electrical performance analysis, it is essentiaunderstand the current direction in each segment. Wrong assumptions on current directions lead to erroneous results. The term “current return path” is widely used to stress the importaunderstanding the current direction in each segment involved.

The inductance values are determined by the lead length and cross-sectional dimensions, thspacing between leads, the spacing between the power or ground plane, the permeability ofconductor, and the number of leads involved. A general rule of thumb is that the smaller the current loop involved the lower the inductance. This is an important concept to be aware of wdesigning packages and systems, in general. Each signal needs to have a nearby, well-defincontinuous return path. There are few simple formulas for inductance because the inductancdependent upon both the physical geometry of the structure and the current return path. A feclassic problems have been solved in closed form. Software codes that use electromagneticanalysis techniques are usually used to compute the inductance of the complex structures inpackages.

4.1.1.4 Characteristic Impedance (Z_o)

Characteristic impedance (Z_o) is one parameter that is used to describe transmission-line structures, which are any structures consisting of two conductors - a signal conductor (lead) reference conductor, typically a power/ground plane. In package modeling, traces are usualldescribed in terms of transmission-line parameters because this type of description inherentincorporates time delay. A model that consists of lumped circuit components cannot accountthe time delay of the signal through the package.



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The characteristic impedance of a line can be found using:

Equation 4-3.

L and C are per-unit-length values of the inductance and capacitance of the line, so Z_o is independent of line length.

Z_o is an important factor in determining the amount of signal reflection that will occur at the boundary between the die and the package and at the boundary between the package and the board. The amount of reflection and, thus signal distortion, is directly proportional to the amount of mismatch between Z_o’s at these boundaries. As an example, the Z_o of traces in FR-4 boatypically used for motherboards is around 50 ohms, so typical packaging technologies attemmatch this impedance as closely as possible. For example, a typical CPGA package has a 4trace impedance and a typical PPGA package has a 47-ohm impedance.

4.1.1.5 Crosstalk

Crosstalk refers to unwanted signal coupling between lines. It is a complex function of the dand receiver characteristics, trace characteristics, and switching patterns. Some generalitieregarding package design and its relationship to crosstalk can be made. Crosstalk in a packdependent upon the stack-up, just as is characteristic impedance; however, crosstalk is primaffected by the distance between traces and the amount of parallelism between them. The lthe parallel distance between two or more lines, the higher the crosstalk between them. Alscloser the lines are to one another, the higher the crosstalk. The proximity of power/ground pto the traces can help reduce crosstalk. That is, crosstalk is directly proportional to the distabetween the planes above and below the trace. There are no simple formulas for predictingcrosstalk. Models of the traces, with the mutual inductance and capacitance calculated, mugenerated and simulations run using buffer models and models representing the system loacorrectly determine the amount of crosstalk in a package design or system.

4.1.1.6 Simultaneous Switching

A final concern in package and system design is the effect of simultaneous switching of signThere are two items of concern when many signals switch simultenously: noise generated opower/ground planes and timing pushout of signals. The first item, power/ground noise, is ureferred to as "SSN", simultaneous switching noise, and is the noise generated in power/grostructures due to a changing current and inductive elements in the power delivery system. Tsecond item is usually referred to as "SSO (simultaneous switching output) pushout." This idifference in timing between single-bit and multiple-bit switching. System designers must bufor the worst-case switching case upfront in their design to insure a design that is robust enohandle all switching cases. Analyses of SSN and SSO are very complex but critical to the odesign process. The general guideline to mitigate the impact of simultaneous switching is to that all signals have well-defined return paths with low inductance and to insure that the powdelivery network has a low inductance. Models and simulations for simultaneous switching phenomenon are very complex and product dependent and, thus, will not be included in thisdocument. Please contact your Intel field sales office for product-specific models.

Z_o LC----=



4.1.2 Modeling Methodology

The exact format for a package model depends upon the model usage. For analyzing specific critical signals, it is necessary to model only a few I/O signal leads in a small section of the package. For designing a power supply scheme, it is necessary to model the power supply loop for the entire package. A complete package model consists of an I/O signal lead for a typical lead geometry plus power loop models for each isolated power supply in the package. The amount of detail included in the model and the exact format of the model are items that the packaging engineer must determine based upon assessments of the model usage and the system characteristics. The next few sections outline some of the issues that the packaging engineer must consider in creating an appropriate package electrical model.

4.1.2.1 I/O Signal Lead Model

The I/O signal lead model consists of the parasitics for a particular signal path in the package. For a wirebond, pin-grid array (PGA) package, the signal path includes the bondwire, the trace, vias, the pin, and the plating bar. Intel has migrated to flip-chip packaging (OLGA and FC-PGA) for its higher performance products. For these types of packages, the signal path includes the solder bump connection between the die and package, the trace, vias, and the pins or lands. If crosstalk is to be considered, then the cross-coupling parasitics for the nearest leads should also be included in the model. Ordinarily it is useful to analyze the lead both in isolation and in conjunction with the nearest traces on either side of the lead.

The key to providing an accurate I/O signal lead model is to identify the return current paths. For example, in analyzing the I/O signal lead bondwire inductance, the closest current return path is the nearest power or ground bondwire. If the effect of this bondwire is not included in the analysis, then the calculated I/O signal lead bondwire inductance will be higher than it actually is because the mutual effects of nearby wires have not been included. In analyzing the signal trace, it is necessary to identify the nearest current-carrying package planes that provide a current return path. In effect, signal traces are usually modeled as microstripline or stripline structures, where a microstripline structure is defined as a trace with one current-carrying plane in close proximity and a stripline structure is defined as a trace sandwiched between two current-carrying planes.

Unless a highly accurate model for a particular critical signal is required, the I/O signal lead model for a package is usually based upon the typical lead geometry. Crosstalk parameters are usually based upon the worst-case crosstalk scenario, i.e., the minimum trace spacing. Typically, the individual components comprising the signal lead are modeled individually using two and three dimensional solutions obtained using electromagnetic field-solving software. The primary parasitics of interest are the line characteristic impedance (Z_o), the line inductance (L), the line resistance (R), the line capacitance (C), and cross-coupling L and C matrices for crosstalk analysis. SSO models usually include mutual effects between signal lines and include the power distribution network effects. To obtain the level of accuracy and complexity required for SSO modeling, three-dimensional fully coupled models are necessary.

4.1.2.2 Power Loop Models

The power loop model consists of the structures used for power delivery in the package. Typically, all power and ground bondwires, vias, planes, and pins must be included along with mutual effects between structures in close proximity to one another. The format for the power loop model is not as straightforward as for the I/O signal lead model because of the complexity of the system. To accurately model the power loop, the entire package structure must be comprehended. This is an unwieldy task, so the packaging engineer must use approximations and partitioning of the package structure to simplify the model. The amount of complexity that is included depends upon the usage. A simple distributed lumped model may be sufficient for certain analyses; however, a more



complex model is usually required for making power distribution design decisions, such as determining the quantity and location of power and ground pins and bondwires and the quantity and location of decoupling capacitors.

A simple distributed model usually consists of a single resistor/inductor element to represent each major structure in the package. For example, all the power bondwires are considered to be parallel, equivalent resistive/inductive structures, so their parasitics are lumped into one resistor/inductor element. Similarly, all the pins and vias are lumped together, and each plane is represented as a single resistor and inductor. This is a highly simplistic model which assumes equal current flow through each pin. Although this is not a very accurate model, it is quite useful for obtaining an approximation for the total package resistance and inductance. To more accurately model the intricacies of the power distribution in the package, all elements must be represented by circuits that contain both self and mutual inductance and capacitance terms. This type of representation is typically called a PEEC (partial-element equivalent circuit) network and must be generated using software tools that solve electromagnetic field equations. The drawback of this type of model is that it consists of a large, complex circuit with many individual elements. The effects of various elements are not intuitively obvious, so circuit simulations must be run. Since the network is large, much computer memory and simulation time is required for this type of analysis.

4.1.2.3 Trade-Offs Between Accuracy and Complexity

Package modeling is both a science and an art. Ideally, one would like to be able to exactly and entirely model the package; however, this is extremely impractical, if not impossible. Both the amount of computational resources and the complexity of the final package model are prohibitive. On the other hand, using a very convenient approach of modeling the entire package as an R, L, C circuit whose parameter values are determined from closed form formulas is crudely simplistic. Somewhere between these extremes lies the realm in which the packaging engineer realistically must develop electrical models for the package.

Inherent in this development is the decision of how much loss in accuracy is acceptable in order to provide a convenient and usable model. This is a decision that is best made after experimentation to test for convergence of a model and, ideally, after comparison to measured data. In general, a single I/O lead model can be quite accurately constructed using two-dimensional approximations for the trace itself and even for the bondwire. Three-dimensional modeling is usually required for the pin and via. All these structures can be easily created and accurately analyzed using commercial software tools for solving electromagnetic field equations. Because of its complexity, there are more engineering approximations that must be made in constructing a model for the power supply loop. For example, a power plane may have a hundred vias connected to it; however, inputting this complex geometry into a software tool would be a time-consuming task. In addition, analyzing this type of geometry would require large quantities of computer memory and time. The accuracy lost in grouping vias together may be very small, i.e., one via could be used to represent ten vias in close proximity. After some practice and experimentation, one can learn to recognize opportunities for model simplification which will not overly compromise accuracy.

4.1.2.4 Lumped-Element Models versus Transmission-Line Models

One key choice that must be made in creating a package model is whether to represent package structures as lumped circuit elements or as transmission-line elements. The general guideline that is given throughout packaging literature is that a transmission-line model should be used if:



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Equation 4-4.

where is the round-trip delay in the medium in which the signal path lies and is the risetime of the signal. As an example, a typical package trace in a ceramic package is around 1 inch long. Using a dielectric constant of 10 for ceramic, the round-trip delay is:

Equation 4-5.

This is the order of the risetimes for signals in today’s microprocessors. Therefore, using a transmission-line model for traces in a package is an appropriate modeling decision.

Typically, a transmission-line model should be used for the trace and lumped models for the bondwires, pins, and vias. Most of the time delay in the package is due to the trace delay, antransmission-line model for the trace will appropriately account for the time delay. A lumped model cannot account for time delay and should only be used when the delay through a strucnot a significant portion of the overall signal propagation delay. As risetimes decrease and propagation delays through the package become more critical, transmission-line models willnecessary for many structures in the package.

4.1.2.5 Frequency-Dependent Effects

Another choice that must be made in creating a package model is whether or not to include frequency-dependent effects. To briefly summarize the issue, at DC, current is evenly distribacross the cross-section of a conductor. At high-frequencies, the current is confined to the sof the conductor. At frequencies in between DC and high-frequency, the current is confined tarea defined as the skin depth of the conductor. Skin depth is material-, geometry-, and freqdependent and decreases with increasing frequency. Because of the frequency dependenceskin depth, the resistance and inductance of a conductor vary with frequency. The cross-secarea through which current flows in a conductor is also affected by the presence of other conductors. This phenomenon is called the proximity effect.

It is usually adequate to simply model the DC resistance of a conductor in a package and tohigh-frequency, or quasi-static inductance calculations to model the inductance. Because sigrisetimes are decreasing with each new generation of microprocessor, however, the spectracontent of typical signal waveforms is increasing and frequency-dependent effects are becommore critical to accurate package analysis. For this reason, future package models should includboth frequency-dependent resistance and inductance values. These parameters must be causing software tools which accurately perform a full-wave solution to Maxwell’s equations, thequations which describe electromagnetic field interactions.

4.1.2.6 Power-Distribution Design Concepts

There are many applications for a complete and accurate package model. The obvious use analyzing signal distortion and delay through the package environment. A second area whicvery important, but not as obvious, is in designing the power decoupling scheme for a packagpower-distribution design, there are a few general guidelines that should be mentioned. First

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are two types of decoupling: low and high-frequency. Low-frequency decoupling is used on the board to typically control the noise from the power supply entering the board. High-frequency decoupling is used on the package and chip to control simultaneous switching noise.

When decoupling capacitors are placed on the package, they should be placed as close as possible to the die to minimize stray inductance associated with the connection between the capacitor and the die. It is important in using any type of decoupling capacitor to try to minimize the stray resistance and inductance associated with the interconnect and the capacitor itself. This is more important for high-frequency decoupling than low-frequency. In general, low-frequency decoupling schemes require large values of capacitance. Larger inductances are usually associated with larger capacitors. High-frequency capacitance values should be small to reduce the associated stray inductance.

The placement of decoupling capacitors affects the overall effective inductance; therefore, a fairly complex package model that allows analysis of the effects of capacitor placement is usually necessary for power-distribution design. The package model for this use, therefore, should take the form of a complex distributed model, or partial-element equivalent circuit (PEEC) model.

4.1.2.7 Modeling Tools

The theoretical values for package parameters are obtained at Intel by using in-house and commercial two-dimensional and three-dimensional modeling tools. The software calculates the inductance, capacitance, resistance, and characteristic impedance values based upon physical design parameters, such as geometry information and material properties, which are input using a CAD-based graphical interface. The user can usually input this information manually or use interface modules which can convert physical design databases for the package geometry into the appropriate format for the modeling tool.

Most of these tools are based upon numerical solutions of electromagnetic field equations, i.e., Maxwell’s equations. The techniques used vary according to the software vendor. Some of tmost common solution techniques include moment method, finite-element method, finite-difference time-domain technique, and boundary-element method. Although one need not bexpert, using commercially available software tools which use these techniques usually requthat one be somewhat knowledgeable about the basic theory behind the technique becauseadditional user input is usually required to accurately solve for the parasitics. For example, this usually required to specify the meshing scheme used to divide the geometry for numericaanalysis. One should also be aware of the limitations and requirements of the tool and technused for solving for package parasitics or one could inadvertently produce data that is not usaccurate. Some of the issues that should be understood are the limits on the types of geometcan be analyzed, the assumptions concerning return-current paths, the assumptions concernground planes and ground conductors, and the underlying analysis algorithms.

4.1.3 Experimental Characterization Methodology

4.1.3.1 Equipment

The equipment necessary for characterizing the parasitics of a package falls into three categThe first is measurement equipment, which is standard and available from several companiewhich specialize in the design and manufacture of this equipment. A well equipped laboratorshould contain a D.C.-ohmmeter, an impedance analyzer, a network analyzer for frequency-domain characterization, and a time-domain reflectometry (TDR) set-up for time-domain characterization. The second category is test fixtures. These must be specially designed forpackage and structure being characterized. Methods for de-embedding the test fixture from



measurement must be devised. The third category is probes. Most package measurements involve probing very small structures with fixed pitches. Probes and calibration standards for these probes are available from companies which specialize in this area.

The following sections outline some of the basics for measuring I/O signal lead and power loop parasitics. It is impossible to cover the intricacies of measurement technique adequately in such a small space. Measurement methodology is continually evolving, and packaging engineers should remain in close contact with measurement equipment representatives and should keep up with conference proceedings and technical journals so that they are well informed concerning the latest and most accurate techniques. Regardless of the measurement technique, the packaging engineer should take care to model and measure the same scenarios if reliable validation data is to be obtained.

4.1.3.2 I/O Signal Lead Characterization

4.1.3.2.1 DC Resistance

The resistance for a given CPGA package is measured from the tip of the bond finger to the pin braze pad. The lead resistance for plastic packages is measured from tip to tip. Figure 4-1 shows the four-probe setup used to measure resistance values. Two sets of readings are taken by reversing the direction of current to eliminate the contact potential. The average value is considered the resistance of the sample.

Figure 4-1. Four-Probe Set-up

4.1.3.2.2 Capacitance

Loading capacitances are measured using an impedance analyzer. The setup for measuring loading capacitance is shown symbolically in Figure 4-2. In this setup, all leads except the lead of interest are grounded. The capacitance is measured between this lead and ground. Decoupling capacitance is measured between a power lead and a ground lead.

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Figure 4-2. Set-up for Measuring Loading Capacitance

4.1.3.2.3 Inductance

Like capacitances, inductances are measured using an impedance analyzer. The inductance measurement is a rather complicated process which involves sophisticated fixturing and de-embedding techniques. Typically, measuring inductance is quite difficult because the test method and fixture can affect the outcome of the measurement. One method of indirectly extracting the inductance is to measure the characteristic impedance (Z_o) and self-capacitance, which can be more accurately measured, and to determine the inductance using:

Equation 4-6.

4.1.3.2.4 Characteristic Impedance

Characteristic impedance (Z_o) for a signal trace can be measured using time-domain reflectometry (TDR). It is important in performing this measurement to identify the return-current path. If the proper return path is identified and incorporated into the measurement, this technique is highly accurate and can be used to extract the trace inductance.

4.1.3.3 Power Loop Characterization

Power loop characterization typically requires special test fixtures and de-embedding techniques. The standard characterization method is to use an impedance analyzer; however, inductance measurements using this technique are not very accurate. Newer techniques are being developed which involve using a network analyzer to perform frequency-domain characterization. Curve-fitting is used to match an equivalent circuit model to the frequency-domain response. In this way, package parasitics can be extracted. Regardless of the measurement equipment, the methodology usually involves shorting all the power elements together and shorting all the ground elements together using a test fixture designed for the particular package that is being characterized. In this way, the parasitics for the entire power supply loop can be extracted.

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4.1.4 Product Package Models for Intel’s Leading-Edge Microprocessors

The following sections contain data describing the parasitics for the packages for Intel’s mosrecent microprocessors. The I/O signal lead, power loop, and crosstalk models for TCP, CPGPPGA, H-PBGA, OLGA, and FC-PGA packages are given. All values are calculated values upon the final package design and calculated using commercially available software tools. Tvalues given for the I/O signal lead models are given as ranges of values for the bondwires per-unit-length parasitics for the traces. The ranges for trace lengths in the package are alsoThe power loop model is based upon the typical package and microprocessor design. Crossmodels account for coupling between the closest signals on either side of the signal of interetransmission-line models and inductance values are calculated assuming high-frequency conditions, i.e., assuming that current flows on the exterior of the conductor only. Resistancevalues are calculated at DC. Transmission line models are used where necessary, and mutueffects of nearby current-return paths are incorporated into the final parasitic values. For exathe inductance of a bondwire is calculated by considering the particular location of the bondwwith respect to current-return paths. The inductance is not calculated assuming an isolated bondwire. For assistance in constructing models for specific leads in a package, contact youIntel field sales office for information pertaining to the lead of interest.

4.1.4.1 I/O Signal Lead Models

A single I/O lead in a package is modeled as a circuit consisting of representative elements bondwire, the trace, the pin or land, and the plating trace. Bondwires, pins, and lands are moas series resistors and inductors. The signal and plating traces are represented by transmisswith per-unit-length resistance (R), inductance (L), and capacitance (C) or with characteristicimpedance (Z_0). Figure 4-3 illustrates the generic I/O lead model for any multilayer package technology. This circuit can be used to describe a specific package technology by changing parasitic values to match the technology. Table 4-1 lists the typical parasitics for the CPGA, PPGAH-PBGA, OLGA, and FC-PGA packages. The values listed assume that the package is mounthe motherboard using a socket, so the pin/land parasitics include the socket effects as well connecting via parasitics inside the package. For flip-chip packages (OLGA and FC-PGA), tbondwire is replaced by the die bump and connecting via and there are no plating traces. Tvalues given in this section are for typical cases only. For more accurate data for simulationspecific signals on specific products of interest, contact your local Intel field sales office.



Figure 4-3. Package I/O Signal Lead Model for Multilayer Packages

Because the geometry of TCP packages is very different from that of multilayer packages, another circuit representation for the package model must be used. This is shown in Figure 4-4. The model consists of three transmission lines with different parasitics that represent different portions of the signal path through the package. Typical TCP parasitics are given in Table 4-2.

Table 4-1. Summary of Package I/O Lead Electrical Parasitics for Multilayer Packages

Electrical ParameterWirebond Package Type Flip-chip Package Type

CPGA PPGA H-PBGA OLGA FC-PGA

Bondwire/Die bump R (mohms) 126 - 165 136 - 188 114 - 158 2 0.06

Bondwire/Die bumpL (nH) 2.3 - 4.1 2.5 - 4.6 2.1 - 4.1 0.02 0.013

Trace R (mohms/cm) 1200 66 66 590 120

Trace L (nH/cm) 4.32 3.42 3.42 3.07 2.329

Trace C (pF/cm) 2.47 1.53 1.53 1.66 1.707

Trace Z_0 (ohms) 42 47 47 43 38.5

Pin/Land R (mohms) 20 20 0 8 20

Pin/Land L (nH) 4.5 4.5 4.0 0.75 2.9

Plating Trace R (mohms/cm) 1200 66 66 N/A N/A

Plating Trace L (nH/cm) 4.32 3.42 3.42 N/A N/A

Plating Trace C (pF/cm) 2.47 1.53 1.53 N/A N/A

Plating Trace Z_0 (ohms) 42 47 47 N/A N/A

Trace Length Range (mm) 8.83 - 26.25 6.60 - 42.64 4.41 - 22.24 3.0 - 18.0 10.0 - 42.6

Plating Trace Length Range (mm) 1.91 - 10.50 1.91 - 16.46 0.930 - 8.03 N/A N/A

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Figure 4-4. Package I/O Signal Lead Model for TCP Packages

4.1.4.2 Power Loop Models

There are many different methods of representing the power loop parasitics in a package model. As a general rule, the more distributed the model, the more accurate the model. As a comparative tool, however, this type of model is not very useful. To provide a simple model by which the overall power loop parasitics of different packaging technologies can be compared, the model shown in Figure 4-5 is used here. The overall inductance and resistance of the power loop for the core (Vcc and Vss) power supply have been calculated and are given in Table 4-3. As in the previous section, the parasitic values for the multilayer packages include the effects of a socket. This is a highly simplistic model but a good one for comparing the different packaging types. For more accurate data for simulations, contact your local Intel field sales office

Table 4-2. Summary of Package I/O Lead Electrical Parasitics for TCP Packages

Electrical Parameter

Trace Segment

Inner Lead Segment

Fan-Out Lead Segment

Outer Lead Segment

Trace Segment R (mohms/cm) 352 290 144

Trace Segment L (nH/cm) 6.48 - 8.84 6.43 - 8.81 7.56 - 9.77

Trace Segment C (pF/cm) 0.58 - 0.83 0.13 - 0.19 0.12 - 0.16

Trace Segment Z_0 (ohms) 89 - 124 183 - 256 220 - 288

Trace Segment Length Range (mm) 0.90 - 4.0 0.05 - 11.8 0.91 - 3.25

A5682-01

Board

ccpV

Vssp

Outer Lead TraceSegment

Fan-Out Lead TraceSegment

Inner Lead TraceSegment

L, R, C, Z_0 L, R, C, Z_0L, R, C, Z_0



only. l field

Figure 4-5. Package Core Power Loop Model

4.1.4.3 Cross Talk Models

As devices migrate to lower voltage designs and smaller packages, the detrimental effects of crosstalk become more pronounced. Care must be taken in package design to minimize and quantify crosstalk. To simulate the effects of crosstalk, an appropriate model is needed. The model included in this handbook, Figure 4-6, is for coupling between three parallel signal leads located at minimum spacing for the package technology from one another. Figure 4-6 illustrates the numbering convention and placement of the signal leads. Table 4-4 gives the inductive coupling coefficients, and Table 4-5 gives the capacitive coupling coefficients for the CPGA, PPGA, TCP, H-PBGA, OLGA, and FC-PGA packages. Note that the mutual terms have negative signs, which is the convention for the “short-circuit” matrix representation. These values are for typical casesFor more accurate data for simulations for specific signals of interest, contact your local Intesales office.

Table 4-3. Summary of Package Core Power Loop Electrical Characteristics

Electrical ParameterPackage Type

CPGA PPGA TCP H-PBGA OLGA FC-PGA

R_Vcc (mohms) 5.5 2.0 6.0 4.1 0.5 1.2

L_Vcc (pH) 150 150 150 217 15 64.4

R_Vss (mohms) 5.5 2.0 6.0 4.1 0.5 1.2

L_Vss (pH) 150 150 150 198 15 64.4

A5680-01

Die Board

R_Vcc

R_VssL_Vss

L_Vcc



y

ot ions

Figure 4-6. Package Crosstalk Model

4.1.4.4 SSO Models

Models and simulations for simultaneous switching phenomenon are very complex and product dependent and, thus, will not be included in this document. Please contact your Intel field sales office for product-specific models.

4.1.5 Package Models for Mature Package Technologies

To meet the performance requirements of Intel’s microprocessors for future silicon technologgenerations, Intel’s package technologies are evolving toward complex, multilayer plastic structures with copper traces and planes. Some of Intel’s older microprocessor products do nrequire these advanced package technologies. For many embedded microcontroller applicat

Table 4-4. Summary of Package Crosstalk Inductive Coupling Coefficients


Package Type


L11 (nH/cm) 4.26 3.39 5.71 3.39 3.2 2.329

L22 (nH/cm) 4.30 3.42 4.94 3.42 3.15 2.329

L33 (nH/cm) 4.30 3.42 4.94 3.42 3.15 2.329

L12 (nH/cm) 0.79 0.46 2.43 0.46 0.85 0.214

L13 (nH/cm) 0.79 0.46 2.43 0.46 0.85 0.214

L23 (nH/cm) 0.18 0.082 1.33 0.082 0.31 0.055

L31 (nH/cm) 0.79 0.46 2.43 0.46 0.85 0.214

L21 (nH/cm) 0.79 0.46 2.43 0.46 0.85 0.214

L32 (nH/cm) 0.18 0.082 1.33 0.082 0.31 0.055

Table 4-5. Summary of Package Crosstalk Capacitive Coupling Coefficients


Package Type


C11 (pF/cm) 2.80 1.60 1.25 1.60 1.65 1.707

C22 (pF/cm) 2.68 1.56 1.23 1.56 1.75 1.707

C33 (pF/cm) 2.68 1.56 1.23 1.56 1.75 1.707

C12 (pF/cm) -0.49 -0.21 -0.48 -0.21 -0.33 -0.126

C13 (pF/cm) -0.49 -0.21 -0.48 -0.21 -0.33 -0.126

C23 (pF/cm) -0.022 -0.0092 -0.094 -0.0092 -0.001 -0.008

C31 (pF/cm) -0.49 -0.21 -0.48 -0.21 -0.33 -0.126

C21 (pF/cm) -0.49 -0.21 -0.48 -0.21 -0.33 -0.126

C32 (pF/cm) -0.022 -0.0092 -0.094 -0.0092 -0.001 -0.008

A5688-01

2 1 3



tinely ters e are ting a

tel

involving mature silicon technologies, older, more mature package technologies are the appropriate choice. Table 4-6 through Table 4-12 give the package parasitics for some of the older packages. Although they are not used for Intel’s leading-edge microprocessors, they are rouused for other Intel products. As with all the packages discussed in this chapter, the paramegiven in the following sections may not reflect the actual values for a particular product. Thestypical values only. The actual parameters for a particular product can be obtained by contaclocal Intel sales office. For electrical parameters of packages not listed, contact your local Infield sales office.

Table 4-6. Summary of CQFP Electrical Data

Electrical ParameterLead Count

164L 196L

Llead (nH) 3.3 3.3

Rlead (Ω) 0.004 0.004

LTrace(I/O) (nH) 5.0 6.0

RTrace(I/O) (Ω) 0.8 0.9

Cload (pF) 4.0 5.0

LTrace(Vcc/Vss) (nH) 1.5 2.5

RTrace(Vcc/Vss) (nH) 0.2 0.4

Lwire (nH) 3.0 3.0

Rwire (W) 0.08 0.08

C(Vcc Plane to Vss Plane) (pF) 170.0 240.0

Table 4-7. Summary of MM Packages


Lead Count

132 Lead MM 196 Lead MM

Min Max Min Max

I/O

RWire + Lead (mΩ) 81 106 83 115

LWire + Lead (nH) 6.6 8.3 7.6 10.2

CLoad (pF) 0.5 1.3 0.7 2.2

Vss and Vcc

RVss db Wire (mΩ) 34 34 34 34

LVss db Wire (nH) 1.1 1.1 1.1 1.1

LVss Plane (nH) 0.2 0.2 0.3 0.3

CPlane (nF) 0.090 0.090 0.210 0.210

RVcc db Wire (mΩ) 55 55 55 55

LVcc db Wire (nH) 1.9 1.9 1.9 1.9

LVcc Plane (nH) 0.2 0.2 0.3 0.3

RLead to Pin (mΩ) 9 10 10 12

LLead to Pin (mΩ) 3.8 4.2 4.7 5.3

NOTE: db = Down bond



Table 4-8. Summary of PQFP Electrical Data


Lead Count

84 Lead PQFP 100 Lead PQFP 132 Lead PQFP 164 Lead PQFP

Min Max Min Max Min Max Min Max

RWire + Lead (mΩ) 62.9 106.4 64.9 108.8 63.2 112.8 65.8 116.9

LWire + Lead (nH) 5.3 9.8 5.9 10.6 5.4 11.9 6.2 13.2

CLoad (pF) 0.2 0.6 0.3 0.7 0.2 0.9 0.3 1.0

Table 4-9. Summary of PLCC Electrical Data


Lead Count

28 Lead PLCC 32 Lead PLCC 44 Lead PLCC 68 Lead PLCC

Min Max Min Max Min Max Min Max

RWire + Lead (mΩ) 56.7 74.0 56.9 74.3 57.7 75.6 57.7 78.4

LWire + Lead (nH) 4.1 7.1 4.2 7.3 5.0 8.4 5.0 10.3

CLoad (pF) 0.2 0.6 0.2 0.7 0.3 0.8 0.3 1.2

Table 4-10. Summary of QFP Electrical Data


Lead Count

44 Lead PLCC 64 Lead PLCC 80 Lead PLCC

Min Max Min Max Min Max

RWire + Lead (mW) 60.9 102.3 60.9 102.0 61.8 108.6

LWire + Lead (nH) 4.8 8.7 4.8 8.6 5.1 10.8

CLoad (pF) 0.1 0.4 0.1 0.4 0.1 0.6

Table 4-11. Summary of SQFP/TQFP Electrical Data


Lead Count

80 LeadSQFP

100 LeadSQFP

144 LeadTQFP

176 LeadTQFP

208 LeadSQFP

Min Max Min Max Min Max Min Max Min Max

RWire + Lead (mW) 61.5 82.6 61.8 84.6 69.5 98.1 69.5 103.7 69.5 122.6

LWire + Lead (nH) 4.0 6.4 4.1 6.9 5.2 8.7 5.2 9.8 6.3 12.6

CLoad (pF) 0.2 0.4 0.2 0.5 0.3 0.7 0.3 0.8 0.4 1.0



to testing

de two or hermal licon sed to n steps r

nts of a

4.2 IC Package Mechanical Characteristics

A typical electronic package assembly consists of different materials which are attached together in a variety of ways. The coefficient of thermal expansion mismatch between these different materials induces stresses in the attached components during manufacture and in operation. Flexing of a card, or other types of mechanical loads on the card with surface mounted components attached to it causes stresses to be induced in the surface mounted joints. Irrespective of the origin of the stress, when these stresses exceed the strength of the material, a crack initiates at the weakest point. After initiation, the crack propagates until complete failure occurs. Depending on the material and the location at which failure initiates, loss of functionality of the component (electrical or mechanical) can take different periods of time. The manufacturing process typically introduces many small flaws at different regions of the component. Crack initiation usually occurs at these pre-existing flaws at high stress locations in the component. Typical causes of failure of electronic packages are briefly discussed below.

Intel optimizes it’s packages through design, construction, material selection, and processesinsure that mechanical characteristics are acceptable. Packages then go through extensive and qualification.

4.2.1 Stresses generated during a thermal excursion

Structures used in microelectronic assemblies are constructed from materials that have a wirange of thermal expansion properties. This thermal expansion mismatch at an interface of more materials of different CTE’s cause stresses to be developed in the materials during a texcursion. At the device level, oxide passivation layers and metallic interconnect lines on siare good examples of multi-material interfaces. The oxidation and deposition temperatures uconstruct these structures are different from the temperatures at which subsequent fabricatioare carried out, and different from the temperature at which the device will be operated. Thepackaging of fabricated devices introduces similar problems at a different scale. Ceramics oorganics used as chip carriers to provide a stable operating environment for the active elemestructure, introduce stresses due to a CTE mismatch with the silicon.

Table 4-12. Summary of SOP Electrical Data


Lead Count / Package Type

32L TSOP 40L TSOP 56L TSOP 44L PSOP

28F010 28F001BX 28F020 28F008SA 28F016 28F008SA

L (nH) 6.86 - 7.84 5.05 - 5.95 3.62 - 4.28 4.44 - 5.39 6.57 - 11.05

Pin C (pF) 8 - 12

Lead-to-Lead C (pF) 0.80 - 0.94 0.59 - 0.73 0.38 - 0.40 0.45 - 0.50 2.09 - 3.32



layer ive cing ilicon,

sile bend in bution e top of ss f the ress. In tress lance the ie

Figure 4-7. Schematic of Thermal Stresses During Reflow

Consider the simplified case of attaching a silicon die to an organic substrate using a thin layer of eutectic lead tin solder, as depicted in Figure 4-7. The melting temperature of eutectic lead tin is about 183°C. Therefore, at 183°C or higher, the individual materials are the free to expand independently. While cooling the assembly down (at temperatures below 183°C), the soldersolidifies, adhering the silicon and the organic substrate rigidly at the mating surfaces. Relatmotion is thereby prevented between the mating surface of the silicon and the substrate, forthem to contract together. However, the organic substrate which has a larger CTE than the swould want to contract more. Compressive forces are therefore, induced on the die and tenforces on the substrate. These opposing forces constitute a moment forcing the assembly toa convex shape when viewed from the top. This bending has a significant effect on the distriof stresses in the attached layers. Due to the bending, tensile stresses are introduced on ththe die and compressive stresses on the bottom of the substrate. For elastic layers, the stredistribution can easily be calculated. The location along the thickness where the direction ostress changes would depend upon the relative magnitudes to the two components of the stsome cases, there are actually more than one neutral axis along the thickness. The actual sdistribution in the assembly may vary from those calculated from an elastic model due to theviscoelastic nature of the adhesive layer. Further die edge shear stresses are present to baforces on the center regions of the assembly. As a result high stresses occur locally at the dedges.

A6002-01

+

E1, α1, ν1

E2, α2, ν3

E3, α3, ν3

α3 > α1

Stress distributiondue to the force

Stress distributiondue to the moment

Re-distributedstresses

>183o C

<183o C



terial y) are

to the

erials.

In general, there are three primary stresses that exist at the interfaces of the assembly after reflow- normal stresses, shear stresses, and peeling stresses. All these stresses vary along the length of the interface, and their magnitudes depend upon the stiffnesses of the individual components being attached. Normal stresses have a maximum value almost over the entire center regions of the assembly, and drop to zero at the edges. Shear stresses have a maximum magnitude at the edges of the die. Peeling stresses change directions along the length of the die, and have a maximum magnitude close to the edge of the die. There are a number of analytical formulations based on Timoshenko’s theory of bi-metallic thermostats, that predict the stress distribution for a tri-maassembly. Most of these formulations (though some account for limited adhesive non-linearitderived for elastic material behavior. However, these analytical relations are very useful to understand the fundamentals of thermal stresses in a tri-material assembly, and the relative influences of different design parameters and material properties on their stress state.

One set of analytical relations developed by Suhir E. [1], for a tri-material assembly when thethickness or the modulus of the adhesive material is small are of the form:

Equation 4-7.

where:

Fdie, Fsub, Mdie and Msub are the forces and moments acting on the die and the substrate due CTE mismatch between them.

E, G, and v, are the elastic modulus, shear modulus, and the poisson’s ratio of the three mat

α is the CTE mismatch between the die and the substrate (αsub - αdie).

hdie, hsub, and h are thickness of die, substrate and the assembly (hdie + hsol + hsub).

λ is the axial compliance of the assembly.

Equation 4-8.

Here, D is the flexural rigidity of the assembly and k is the interfacial compliance of the assembly

Equation 4-9.

k is a parameter of the assembly stiffness which is a function of the axial and the interfacial compliances.

σdie

Fdie max,

hdie--------------------

6Mdie max,

h2

die

------------------------- ∆α∆Tλhdie--------------- 1 3

hhdie---------

Ddie

D----------+

χ x( )–=+=

σsub

Fsub max,

hsub---------------------

6Msub max,

h2

sub

------------------------- ∆α∆Tλhsub--------------- 1 3

hhsub----------

Dsub

D-----------+

χ x( )–=––=

solτ κ∆α∆T

λ---------------χ’ x( )=

∆

λ 1 diev

–Ediehdie-------------------- 1 sub

v–

Esubhsub--------------------- h

2

4D------- D

Edieh3

die

12 1 v2

die–( )--------------------------------

Esubh3

sub

12 1 v2

sub–( )--------------------------------+=,+ +=



Equation 4-10.

The functions , and characterizes the longitudinal distribution of forces from the center to the edge of the interface(I).

Figure 4-8. Comparison of analytically and numerically calculated stresses along the length of the die.

Figure 4-8 compares the normal stress in the die and the substrate, and the shear stress in the solder joint, obtained using these relations to those obtained numerically using a finite element model. The material properties and the design dimensions used for this comparison are listed in Table 4-13.

κ dieh

die3G-------------- sol

2h

sol3G------------- sub

h

sub3G---------------+ +=

k λk---=

χ x( )1

kx( )coshkl( )cosh

----------------------–= χ’x( ) kx( )sinh

kl( )cosh---------------------=

A6003-01

-60

-50

-40

-30

-20

-10

0

10

20

30

40

0.03

0.33

0.63

0.93

1.23

1.53

1.83

2.13

2.43

2.73

3.03

3.33

3.63

3.92

4.22

4.52

4.82

Distance along the length of the interface (mm)

Str

ess

(MP

a)

Die (FEA)

Sub (FEA)

Solder (FEA)

Die (anal)

Sub (anal)

Solder (anal)

a b

a b



Table 4-13.

Note that for the most part, the results match well.

The following general conclusions can be made from the analytical equations for the stresses in the assembly.

Figure 4-9. Variation of the maximum shear stress and normal stress with increasing die size

• The factors and describes the longitudinal distribution of shear and normal stresses along the length of the interface. The maximum shear stresses occur at the end (at x = l) where the function has the value:

and the maximum normal stress occurs at the center where:

Figure 4-9 shows the variation of these two factors for increasing values of kl. From Figure 4-9, it is evident that increases with kl, for values of kl less than 3.5, and increases with kl for

E (GPa) α (ppm/°C) v Thickness (mm) Half Length (mm)

Die 130 3.2 0.3 0.7 5

Solder 6.2 27 0.3 0.05 5

Substrate 17 16 0.3 1.65 10

A6001-01

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 2 4 6 8 10 12

kl

X'(

max

), X(m

ax) X'(max)

X(max)

χ’ x( ) χ x( )

χ’ x( )

χ’ l( ) χ’ max( ) kl( )sinhkl( )cosh

--------------------- kl( )tanh= = =

χ 0( ) χ max( ) 11

kl( )cosh---------------------–= =



nt in d .

efects wing

pagate

. ture mal ower ature te for itions y as a h.

values of kl less than about 7.5. This indicates that for the die/solder/substrate assembly considered, σdie and σsubstrate increases with increasing die size for kl< 7.5 (ie 2/ < 19.5 mm), and tsolder increases with die size for kl< 3.5 (ie 2/ < 5.5mm). For die sizes greater than 19.5 mm square (and 5.5 mm square for shear stress), the normal stress in the die and the substrate, and the shear stress in the solder layer will remain unchanged. For die and substrates of different thicknesses and properties than that considered here, the size of the die beyond which the stresses will remain unchanged, will be different.

• The coefficient of thermal expansion of the attachment material does not enter into the relations for the stresses in the assembly. This means that the CTE of the solder material does not affect the thermally induced stresses in the assembly, as long as the thickness and/or the modulus of the adhesive are small compared to that of the adherents.

However, the modulus and the melting temperature of the adhesive layer plays an important part in the magnitude and distribution of the stresses. Lower the modulus of the solder, lower will be the amount of stresses transmitted to the attached components. Also, lower melting temperature solders decrease the stresses in the assembly by lowering the temperature differential between reflow and room temperature. However, low melting temperature solders are at high homologous temperatures (T/Tmelting in the absolute scale) during the range of operating temperatures of an electronic package, leading to inelastic strain accumulation in the solder material. This accumulation of inelastic strain in the material could lead to fatigue failure of the material during operation.

Eutectic lead tin solder melts at 183°C, and therefore, is at about 65% (0.65TM)of its melting temperature in the absolute scale, at room temperature. In general, creep becomes significamaterials at homologous temperatures above 0.5TM . Therefore, inelastic strain gets accumulatein the eutectic lead-tin solder after reflow and during subsequent thermal cycles in operation

In addition to these primary failure mechanisms, manufacturing processes induce numerous din a package, which typically becomes the preferred site for failure initiation. For example, saa die from a wafer introduces numerous micro-cracks at the edges of the die, which can produe to the stresses induced in the die during operation.

4.2.2 Temperature Cycles in Operation

A microprocessor package is subjected to numerous heating and cooling cycles in operationWhen the device is powered up, its temperature rises, and when it is shut down, its temperadrops. The magnitude of the maximum temperature on the die surface depends on the thersolution employed, and is usually between 80 to 125°C. In addition to these power on and poff cycles (maxi-cycles), the microprocessor is cycled between different intermediate tempervalues depending upon processor usage (mini-cycles) in any application program. The InstituInterconnecting and Packaging Electronic Circuits [2] lists the typical worst case usage condfor personal computers and consumer electronics as given below. This table is intended onlguideline, and individual companies use different field use conditions based on their researc



Table 4-14. Worst Case Use Environment

To investigate the reliability of a microprocessor package during the intended life of the package, they are subjected to temperature and power cycling tests.

4.2.3 Delamination of bi-material interfaces

As mentioned previously, an electronic package consists of many multi-material interfaces. Mechanical bonding is the primary bonding mechanism at many of these interfaces. Delamination can occur at these interfaces during temperature excursions in manufacture or operation. The primary cause of delamination of interfaces are manufacturing defects compounded by the shear stresses acting at these interfaces due to a CTE mismatch. One of the common interface seen in a package is an organic material (like an epoxy or an encapsulant) bonded to a metallic or a ceramic surface. There are a number of publications in literature that describe mechanisms associated with delamination of an interface from the elements in the package. The key events or process steps leading up to delamination can be incorporated into a reasonably coherent picture on the basis of information presented in these references.

4.2.4 Shock and vibratory loads

The increasing speed requirements of modern day microprocessor packages has resulted in packaging memory components along with the CPU, leading to larger sizes of packages. Cantilevered and lightly restrained structures are regions of concern in shock and vibratory loading environments. The dynamic response of a package can introduce high frequency cyclic stresses in some components of the package leading to the possibility of high cycle fatigue. As an example, consider the stresses that occur when a computer is subjected to vibrations. Repeated flexure of a structure within the package will put the copper lines and solder joints through a fully traversed stress cycle. If the package has a resonant frequency at 10 Hz and an expected service life of 4000 hrs, the circuit lines and solder bumps would have to survive a minimum of 100 million cycles of stress reversals.

The ability of a package to survive these stress-inducing environments is governed by the properties of the materials used in its construction, as well as by its design.

4.2.5 Typical Analysis Methodologies

Finite element analysis along with suitable experiments, is the most common technique used to determine the behavior and the reliability of a package to various stress inducing environments. Due to the complex structure of packages, geometric and analysis simplifications are often utilized in these analyses. To ensure that all relevant interactions are accounted for, and the model accurately captures the behavior of the real structure, model validation experiments are carried out. The experimental results are used to calibrate the model to ensure the validity of the model predictions.

Category Worst case use environment

Tmin °C Tmax °C ∆T °C Dwell (hrs) Cycle/yr Approx. Years in Service

Consumer 0 +60 35 12 365 1-3

Computers +15 +60 20 2 1460 5



ared e in-e be

ed to nd the e size

d to be ture.

good

In recent years, extremely sensitive, full-field optical interference techniques have been extensively used to calibrate and compare numerical predictions to actual behavior. Some of the commonly employed "opto-mechanical tools" that produce high-resolution, full-field contour maps of thermo-mechanical deformation within an electronic package are Moiré Interferometry, Infr(IR) Fizeau Interferometry and Shadow Moiré [3-5]. While Moire interferometry measures thplane deformation, Fizeau interferometry and Shadow moire are used to map the out of plandeformation (warpage) of packages. In addition to model validation, these tools by itself canused to study the effect of design changes on the behavior of the package quickly.

4.2.5.1 Numerical analysis and model validation examples

Figure 4-10 shows a finite element model and the out of plane displacement of a C4 die bonda substrate after assembly. Since there is a CTE mismatch between the silicon, substrate, adie attach materials, the assembly warps after cool-down from the reflow temperature. For thof the assembly modeled, the out of plane displacement on the surface of the die is predicte39.45 microns. Figure 4-11 shows the Fizeau measurement of the die warpage after manufacThe fringe sensitivity of this measurement is 2.65 um/fringe, which gives the total warpage (measured from center to corner) on the die surface to be 39.4 microns. Note that there is acorrelation between the numerical prediction and the experimental measurement, thereby, validating the general behavior of the finite element model.

Figure 4-10. Finite element model and out of plane displacement of a die C4 attached to a substrate

A6007-01



Figure 4-11. Fizeau measurement of die warpage

However, before this model can be used for stress predictions in microscopic regions of the package, this model has to be further validated. Figure 4-12 and Figure 4-13 compare the inplane displacements in the fillet region of the underfill. The fringe constant for the fringe patterns shown in these figures is 0.417 mm/fringe. For comparison purposes, an image analysis software has been used to depict the displacements in a selected region of the fillet as a displacement contour pattern having the same scale as the numerical contour pattern. Note that the results match well. This validated model is now used for stress and life predictions. Typically, the properties of materials used in these packages are not well characterized. Therefore, a number of iterations of model calibration using the experimental results are required before the model can be used for stress predictions.

Figure 4-12. Comparison of model prediction and moire results of horizontal displacement in the fillet region

A6008-01

A6009-01



)

but m a

eel ients

e

Figure 4-13. Comparison of model prediction and moire results of verticle displacement in the fillet region

Besides it’s use as model validation tools, these interferometric techniques are also used to compare materials and design options, due to its relatively short time-to-data. Two epoxy samples proposed to be used as the encapsulant material in PLGA (Plastic Land Grid Arraypackages were compared using Moire interferometry. In PLGA packages, the silicon die is covered with the encapsulated. This epoxy not only covers the active surface of the silicon, also the wire-to-pad interconnects. Therefore, these two epoxy samples were compared frowire bond reliability perspective.

Figure 4-14 compares the Moiré U-field displacement patterns (horizontal fields) of the wire hregion (at the wire to die interface) using the two different encapsulant materials. Fringe gradin any direction would indicate relative motion between the encapsulant and the die in that direction, increasing the likelihood of failure during temperature excursions. V-field images (vertical field) revealed almost no fringe gradients in the wire heel region indicating negligiblrelative motion between the die and the encapsulant in that direction.

Figure 4-14. Comparison of horizontal displacement fields in the wirebond region of PLGA.

Note the higher density of fringes in the right image

A6010-01

A6011-01

Encapsulant Sample A Encapsulant Sample B



eel

ing e gth

re

lding tors ced to

sweep

lead hermal ts from

d

Figure 4-15. Comparison of free expansions of the two encapsulant materials used in the study

However as shown in Figure 4-14, the horizontal displacement of the the encapsulant in wire heel area of the sample using encapsulant B is twice that in the case of the package using sample A. This difference in behavior between encapsulant A and B was confounding since both encapsulants had nearly identical bulk CTE’s in the horizontal direction. The encapsulant material in the harea of both packages were seperated and moire performed. Figure 4-15 shows the horizontal displacement fields obtained from both encapsulant materials. Figure 4-15 indicates that encapsulant B has a much larger CTE at the interface that encapsulant A. This was later determined to be due to a lower filler content at the interface.

4.2.6 Surface Mounted Lead Packages

4.2.6.1 Bond Stresses

In addition to the mechanical and metallurgical stresses developed during the wire-bonding process, encapsulation and environmental stresses subsequent to bonding can contribute todegradation of the interconnection. Reliable first and second bonds can be ensured by bondwithin the process windows for force, power, time, and temperature. Excursions beyond theswindows are minimized through regular process monitors such as bond pulls. Both pull strenand failure mechanism criteria must meet specifications. In particular, no cratering failures aacceptable even if pull strength criteria are met, since craters indicate excessive force duringbonding which could lead to reliability problems in the field.

During encapsulation, wire sweep may occur if wire lengths are too great or if drag during moflow is excessive. Current mold gate designs provide low drag flow patterns, and X-ray moniare used to confirm process stability. Wire diameter and length design rules are strictly enforensure that there is adequate mechanical stability of the bond arch to resist drag forces. Development of new package designs includes analysis and experiment to ensure that wire is minimized.

In plastic packages, delamination at the interface between molding compound and silicon orframe can cause high stresses at the first or second bond location, because the differential texpansions must be accommodated across the bond itself. The delamination generally resultemperature cycling of packages with trapped moisture. To suppress the adverse effects of delamination, selection of materials with enhanced interfacial adhesion and the design of lea

A6012-01

Sample A Sample B



55° C ition of design

-n in FR–

frames that feature additional mold compound locking characteristics have proven to be effective. Finite element models are used to guide and optimize designs. For packages that are particularly moisture-sensitive, shipment of prebaked product in sealed moisture-proof bags with desiccant ensures that delamination is minimized and operation of the assembled part will be reliable.

4.2.6.2 Compliant Leads and Solder Joint Fatigue

With the advent of surface mounted packages, solder joint integrity became an issue of considerable concern. It was found that solder joints on leadless ceramic packages measuring more than 0.5 inch on a side could survive only a few hundred temperature cycles (Condition B, –to +125° C) when the packages were surface mounted to FR–4–type circuit boards. The addcompliant leads to these packages has extended the life considerably and is now used in theof all new surface mounted packages.

As a means of experimentally evaluating the in situ stiffnesses of leads on packages surfacemounted to boards, the straddle board method has proven to be a very useful tool. As showFigure 4-16 and Figure 4-17, the straddle board consists of a slotted, double-sided epoxy-glass4.–4 board that is patterned for corner leads. All other package leads are removed.

Figure 4-16. Lead Stiffness Straddle Board

A5614-01

240819-20



ing on

l cycles ing

shown

Figure 4-17. Straddle Board with Two Packages in Place

Units are mounted on both sides of the board using production-level processes and specifications for each package. The board is mounted vertically in a tensile test set-up such as a materials test system (MTS), and the narrow sides of the slot are cut, separating the two ends of the package. The MTS is fitted with a 200 lb. load cell and a 6 inch displacement actuator. This allows the straddle board to be tested with a 0.020 inch displacement, 0.010 inch in the tensile cycle and 0.010 inch in the compressive cycle. These values were chosen to span the lead displacement experienced during temperature excursions from –65° C to +150° C (MIL–STD–883C T/C [C]).

A total cycle time of five seconds was used with a maximum load range of 0.8-8 lbs., dependthe package type and lead count. As Figure 4-18 shows, leads are loaded in both lateral and transverse directions (i.e. in the plane and normal to the plane of the lead bend). Twenty-fivesamples per lead count per direction were evaluated. Once the board was mounted, three fulwere run, and the force versus deflection curve was recorded. The linear portions of the loadand unloading curves were used to determine the lead stiffness. A typical hysteresis curve isin Figure 4-19.

Figure 4-18. Orientation of Applied Load

A5615-01

240818-21

Force Force

Transverse Mount Lateral Mount

A5616-01240819-62



S 3–D to the

re

the port d

the QFP sult

iated

re is values OP,

n rest, portant along tion in ent

stress high the

level e to

Figure 4-19. Lead Stiffness Determined from Hysterisis

Designing leads with adequate compliance is now recognized as an important element of overall product design, and mechanical modeling has proven to be a useful design tool. Lateral and transverse lead stiffnesses were calculated for PLCC, and PQFP packages using the ANSYelastic beam element option. The calculated stiffness for each type of package was matchedvalue obtained from the straddle board measurements by locating the point on the lead wheagreement was reached. In all cases, the point lay within the solder joint, in agreement with physical expectations.

Of particular interest were the boundary conditions imposed by the solder joint on the foot oflead. In the lateral direction, the solder volume is adequate for the joint to provide built-in supto the lead foot (zero rotation). However, in the transverse direction for the PLCC and cerquapackages, the J-bend lead stiffnesses are large enough to produce inelastic deformations insolder joint. As a result, the joint acts like a pinned support (free rotation). In all cases, the Pgull-wing leads are sufficiently compliant for the solder joint to act as a built-in support. This resuggests that reducing lead stiffness will significantly reduce solder joint stresses and assoccreep and fatigue. Experimental data recently reported in supports this hypothesis.

Because of the contribution of lead stiffness to the level of stress in the solder joint when thethermal mismatch between package and board, a comprehensive list of in situ lead stiffnessis provided in Figure 4-21. All surface mounted packages currently used for Intel products (TSPLCC, PQFP and CQFP) are listed in Table 4-15. For these packages both translational and rotational stiffness components are given. The translational stiffness is defined as the force ipounds created by a displacement in inches applied at the solder joint in the direction of intethe remaining force and rotation components being zero. These stiffness components are imwhen the thermal mismatch creates differential displacements which must be accommodatedthe leads. The rotational stiffness is defined as the moment in inch-pounds created by a rotaradians applied at the solder joint about the axis of interest, all other moments and displacemcomponents being zero. These stiffness components are important when thermally induced differential rotations are imposed at the ends of the leads.

The magnitude of the stiffness components are useful in making comparisons of the level ofor strain induced in the solder joint by various package types; high lead stiffness will generatesolder stresses, etc. Experience to date indicates that in situ translational lead stiffnesses onorder of 100 lb./in. or less produce excellent joint reliability. Even lead stiffnesses above thisare acceptable although they have less margin than the more compliant leads. With referenc

A5617-01

0.010*-0.005*-0.010*

Load

(LS

B)

Dissplacement (IN.)240819-23

4.0

3.0

2.0

1.0

-1.0

-2.0

-3.0

-4.0

0.005*



rtance

.

nt lead r the

ms in

kage d upon

ckage.

y the

verses

P II design. cle (T/

Figure 4-21, the x– and y–components of the gull-wing leads on 0.025 in. centers (PQFP andCQFP) fall into this category. The z-components are always large and demonstrate the impoof minimizing board flexing, which generates these z-components.

To assist in visualizing the stiffness and stress entries in Table 4-15, Figure 4-21 has been preparedThe gull-wing lead of the PQFP has been used for reference. In all entries, the center line represents the lead profile in the plane of interest. The heavy line represents the displacemeprofile associated with the displacement or rotation component indicated at the point on the connected to the solder. The line connected by shading to the undeflected profile shows thedistribution of the bending stress along the lead. In general, the maximum value is at or neasolder connection point; however, for displacements along (or rotations about) the z-axis, thebending stress maximizes at the package body. As mentioned previously, z-component displacements may generate high lead stresses. Figure 4-21 suggests that the package body is thesite of maximum stress and damage in the lead.

Under certain conditions, stresses in the lead may be large enough to cause reliability problethe lead as well as in the solder joint. The figures of merit presented in Table 4-16 extracted from Table 4-15, provides indicators of lead compliance and lead stress levels for current Intel pactypes. All the lead compliance and stress of various packages and lead designs are normalizethe lead configuration of a 68L PLCC package. The first two columns give the level of lead compliance along the lateral and transverse directions as compared to that of a 68L PLCC paThe lead stress is estimated by applying a unit displacement (1 mil) along the lateral or the transverse direction, the third and fourth columns provide the level of lead stress produced bproposed lead displacement. A correlation between the lead stiffness and the lead stress is observed; the greater the lead stiffness, the higher the lead stress. A plot of log [lead stress]log [lead stiffness] is shown in Figure 4-20. The trend of the lead stress dependence on lead stiffness is linear on a log-log plot for most of the Intel packages except the TSOP I and TSOpackages which show much stiffer lead response because of their low profile and short lead In general, a stiffer lead will introduce higher stress at the solder joint during temperature cy

Table 4-15. Surface Mount Package Lead Stiffness

Lead Stiffness Components Maximum Lead Stresses

PackageTrans. Stiffness

(lb/in.)Rotation Stiffness

(in.-lb/rad.)Trans. Stresses

(Ksi/m in.)Rot. Stresses(Ksi/m rad.)

Type Kx Ky Kz Kθx Kθy Kθz σx σy σz σθx σθy σθz

TSOP(I) 1900 2560 9730 0.579 0.435 0.115 514 521 1660* 7.89 9.55 1.78*

TSOP(II) 3820 18800 19500 4.42 0.869 0.704 514 990 1660* 15.1 9.55 2.86*

PLCC 44L 323 1250 7750 1.82 0.379 1.03 43.3 59.1 335 1.81+ 6.65 1.56+

PLCC 68L 187 1190 8813 1.03 0.166 0.641 43.7 89.1 474 3.08+ 6.99 2.60+

PQFP 39.8 85.9 955 0.245 0.133 0.0468 30.4 35.9 281* 1.98 2.05 0.438*

CQFP 9.05 23.0 250 0.361 0.0132 0.0232 16.6 24.8 173* 2.39 1.62 0.342*

DEFINITIONS: Kα = Force in lbs. needed to produce a displacement in inches in the α direction at the solder joint, all other forces and rota-tions = 0.Kθα = Moment in in-lbs. needed to produce a rotation in rad. about the α axis at the solder joint, all other moments and dis-placements = 0.σα = Maximum lead stress in Ksi due to a 0.001 in. displacement in the α direction at the solder joint, all other forces and rotations = 0. Unless otherwise noted, maximum stress occurs at the solder joint.σθα = Maximum lead stress in Ksi due to a 0.001 rad. rotation about the α axis at the solder joint, all other forces and rota-tions = 0. Unless otherwise noted, maximum stress occurs at the solder joint.x = Outward normal to the edge of the package in the plane of the unformed leadframe.y = Tangent to the edge of the package in the plane of the unformed leadframe.z = Perpendicular to the plane of the unformed leadframe.NOTES: 1. * Maximum at the package body.2. + Maximum at the site of lead width reduction.



C) stressing and subsequently degrades the solder joint fatigue performance. To assess solder joint reliability, a methodology is described in the following paragraphs to investigate the solder joint fatigue performance at various lead displacement amplitudes and frequencies.

Figure 4-20. Lead Stress Dependence on Lead Stiffness for Various Lead Designs

Table 4-16. Figures of Merit for Lead Compliance and Lead Stress Package

Compliance FOM 1 Stress FOM 2

Package Lateral Transverse Lateral Transverse

TSOP I 0.098 0.46 0.085 0.17

TSOP II 0.049 0.06 0.085 0.09

44L PLCC 0.58 0.95 1.01 1.51

68L PLCC 3 1.00 1.00 1.00 1.00

100L PQFP 4.70 13.85 1.44 2.48

CQFP 20.66 51.74 2.73 3.59

NOTES: 1. Compliance FOM = (Package Compliance) / (68L PLCC Compliance).2. Stress FOM = (68L PLCC Lead Stress) / (Package Lead Stress).3. 68L PLCC: Lateral Lead Stiffness = 187 lbf/in, Transverse Lead Stiffness = 1190 lbf/in.4. Lateral Lead Stress = 43.7 Kpsi/mil, Transverse Lead Stress = 89.1 Kpsi/mil.

A5618-01240819-48

CQ (L)

CQ (T)

PQ (L)PQ (T)

Cd (L)

PL68 (L)

PL44 (L)PL44 (T)

Log [Lead Stiffness (lbg / in.)]

PL68 (T)

Cd (T)

TSI (L) TSII (L)

TSI (T)TSII (T)

4.543.532.521.510.501.2

1.4

1.6

1.8

2

2.2

3

2.8

2.6

2.4

CQ : CQFP Package, (L) : Lateral, (T) : Transverse.

PQ : PQFP Package, (L) : Lateral, (T) : Transverse.

Cd : Cerquad package, (L) Lateral, (T) : Transverse.

PL68 : 68L PLCC Package, (L) : Lateral, (T) : Transverse.

PL44 : 44L PLCC Package, (L) : Lateral, (T) : Transverse.

TSI : TSOP (I) Package, (L) : Lateral, (T) : Transverse.

TSII : TSOP (II) Package, (L) : Lateral, (T) : Transverse.



Figure 4-21. Stress Distribution along a PQFP Lead

A5619-01240819-44

Z

YX

Z

Y X

Z

Y X

Z

YX

Sigmax UYUX

Sigmax

Sigmax

UZRotx

Sigmax



the c nents ent red. is ng

during

n

cement nergy

Figure 4-22. Stress Distribution Along a PQFP Lead (continued)

4.2.6.3 Effects of Loading Frequency and Amplitude on Solder Joint Damage

Cyclic strain energy dissipation, W, was analyzed for a simple two segment structure consisting of solder exhibiting elastic, plastic and creep behavior connected in series with copper exhibiting elastic behavior only. The structure is fixed at one end and subjected to a ‘square wave’ displacement at the other. The total strain energy consists of plastic and creep components,magnitudes of which depend on the amplitude and frequency of the square wave. The plasticomponents arise during the instantaneous changes in displacement while the creep compooccur during the dwell periods. At very low frequencies (long dwell times), the creep componprovides maximum contribution to the total, in the range of 15-50% for the examples consideAt very high frequencies (very short dwell times), only the plastic component contributes andsmaller than its low-frequency counterpart. This is because the creep relaxation during the lodwell period at the low frequency end enables a large value of plastic strain to be generatedthe instantaneous change in displacement following the dwell.

A quantitative picture of the dependence of the total strain energy dissipation, W, per cycle odisplacement amplitude and frequency is shown in Figure 4-23 and re-mapped to Figure 4-24. These iso-strain energy dissipation contours per cycle show strong dependence on the displaamplitude and weaker dependence on the cyclic frequency. The use of the cumulated total ecould provide reasonably good prediction on the solder joint fatigue life. The use of this methodology to predict a 68 L PLCC solder joint reliability is described in the next section.

Z

Y

X

Sigmax

Rotz

Z

X Y

Sigmax

Roty

A5620-01240819-46



of the d and on at for

ch is

Figure 4-23. Dependence of Total Strain Energy Dissipation per Cycle on Displacement Amplitude and Frequency

Figure 4-24. Isocontours of Strain Energy Dissipation in Displacement Amplitude and Frequency Space

4.2.6.4 Dependence of J-Lead Solder Joint Reliability on Lead Displacement Amplitude and Frequency

A 68L PLCC configuration was selected to study the J-lead solder joint reliability as a function of lead displacement amplitude (d) and frequency (t) (period of fatigue cycle). The general form of the constitutive relations for the solder and the lead is given elsewhere. A “square wave” displacement amplitude of 1.25-5 mils and periods of 0-30 minutes were applied to the end lead, the total inelastic energy dissipation (plastic and creep) in the solder joint was analyzedisplayed in Figure 4-25. The total energy, W, exhibits a monotonically increasing dependencethe lead displacement (d) and frequency (t) (period of fatigue cycle). In addition, it appears tha given displacement, the total energy, W, asymptotically approaches a maximum value whireasonably well approximated by W at t = 30 minutes.

35

30

25

20

15

10

5

00 0.2 0.4 0.6 0.8 1.0 1.2

D (10 in.)-3

Wf (

Ib.-

in/in

)

3

Wt = Inelastic Strain Energy f = Fatigue Cycle FrequencyD = Displacement

Wheref (Min )--1

0.0625

1.02.0

0.250.5

A5621-01240818-49

0.125

Wt = Inelastic Strain Energy f = Fatigue Cycle FrequencyD = Displacement

Where 1.2

1.0

0.8

0.6

0.4

0.2

00 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Wt (Ib-in / in )3

80

160

402010

f (Min )-1

D (

10

In.)

-3

A5622-01240819-50



Considering the solder joint fatigue life is governed by the total inelastic energy dissipation during fatigue stressing, estimations of its life expectancy may be conservative. Even though solder fatigue life predictions based on inelastic strain energy density buildup to a critical level alone might be conservative, it is still useful to examine the consequences of postulating a critical strain energy density buildup level and examining its impact on the life prediction. For example, if 100 cycles count is the cycle count for a critical strain energy density buildup for the displacement of 5 mils and a period of 30 minutes, then based on the data in Figure 4-25, the corresponding cycle count for various amplitude and period combinations to reach the same level of energy dissipation (damage) could be calculated (in a case of fatigue displacement of 5 mils and period of 30 minutes, if 100 cycles is the critical count to fracture, then, with data given in Figure 4-25, the corresponding critical cycle counts for various fatigue conditions to fail could be estimated). The plot of various cycle count in the form of log (d) versus log (N/100), where N is the total cycle counts for solder joint fatigue failures, is given in Figure 4-26. Common practice when displaying fatigue curves whose appearance is similar to Figure 4-26 is to obtain the slope for a fit to the Coffin-Manson relation. In this case, the exponent varies from -0.667 for t = 0 minutes to -0.786 for t = 30 minutes. Hence, although each curve appears linear, the slopes show a dependence on the period (inverse frequency) of the cycle. For the displacement amplitude ranges investigated, these values are close to those reported from experimental investigations. The consistency between the model and the experiments suggest that the critical strain energy density buildup criterion may be a useful approach for the development of a comprehensive failure prediction methodology for solder. However, it should be pointed out that for displacement amplitude larger than those shown in Figure 4-26, it is likely that the curves merge. Moreover, at very low displacement amplitude, the curves should become horizontal (asymptotically approach the cycle to failure axis) since negligible strain energy density buildup is possible and the solder should survive almost unlimited cycling.

Figure 4-25. Cyclic Strain Energy Dependence on Displacement Period

D = 5 MilsD = 2.5 MilsD = 1.25 Mils

0 5 10 15 20 25 300

20

40

60

80

100

140

120

W (

Ib -

in /

in

)-3

Period (Min.) A5623-01240819-51



Figure 4-26. Dependence of Log of Displacement Amplitude on Log of (N/100) for Different Displacement Periods

4.3 IC Package Thermal Characteristics

4.3.1 Importance of Thermal Management

Thermal management of an electronic system encompasses all the thermal processes and technologies that must be utilized to move and transport heat from individual components to the system thermal sink in a controlled manner.

Thermal management has two primary objectives. The first is to ensure that the temperature of each component is maintained within both its functional and maximum allowable limit. The functional temperature limit defines the maximum temperature up to which the electrical circuits may be expected to meet their specified performance targets. Operation of the circuits at temperatures higher than the functional limit may result in performance degradation or logic errors. The maximum allowable temperature limit is the highest temperature to which a component or part thereof may be safely exposed. Operation of the component at temperatures higher than the maximum allowable temperature limit may cause irreversible changes in its operating characteristics or may even cause physical destruction of the component.

The second objective of thermal management is to ensure that the temperature distribution in each component satisfies reliability objectives. Failure mechanisms encountered in electronic components are kinetic in nature and depend exponentially on the device operating temperature. The exact relationship between the failure rate and temperature depends upon the thermophysical properties of the packaging materials and the failure mechanism in operation. The relationship between the normalized failure rate and temperature, for changes in the device operating characteristics resulting from chemical or diffusive processes, can be defined by an Arrhenius equation as follows:

Tau = 0 Min.Tau = 1 Min.Tau = 2.5 MinTau = 30 Min.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 0.2 0.4 0.6 0.8 1 1.2

Log N / 100

Log

D (

Mils

)

A5624-01240819-52



0.8 in an

Equation 4-11.

Where:

Figure 4-27 shows a plot of Equation 4-11 for a reference temperature of 100 °C and activationenergies of 0.4 eV to 1.0 eV. The figure shows that for activation energies between 0.6 eV toeV, a 25 °C increase in the operating temperature, above the reference temperature, resultsapproximately five to six fold increase in the failure rate. Thus, precise control of componentoperating temperatures is absolutely essential to ensure product reliability.

Figure 4-27. Component Failure Rate as a Function of Junction Temperature

θn

θTθTr--------- Exp

EA

k-------

1Tr------ 1

T---–

= =

θ = Failure rate

θn = Normalized failure rate

T = Absolute junction temperature (K)

Tr = Reference temperature (K)

EA = Activation energy (eV)

k = Boltzmann’s constant: 8.616 X 10-5 (eV/K)

160150140100 110 120 130

10

100

AE = 1 eV

AE = 0.8 eV

AE = 0.6 eV

AE = 0.4 eV

Junction Temperature (˚C)

Nor

mal

ized

Fai

lure

Rat

e

A5625-01240819-24



4.3.2 Heat Transfer Modes

To understand the thermal characteristics of electronic components and packages, it is necessary to briefly review the processes by which heat is transferred from one point to another. Heat transfer occurs via one or more of three modes: conduction, convection, and radiation.Conduction

4.3.2.1 Conduction

Conduction is a mode of heat transfer in which heat flows from a region of higher temperature to one of lower temperature within a medium (solid, liquid, or gaseous) or media in direct physical contact. In conductive heat flow, the energy is transmitted by direct molecular communication without appreciable displacement of the molecules.

In a one-dimensional system (see Figure 4-22), conductive heat transfer is governed by the following relation:

Equation 4-12.

where:

Equation 4-12 indicates that in conduction, the heat flow rate is directly proportional to material thermal conductivity, temperature gradient, and cross-sectional area. Equation 4-12 can be written as:

Equation 4-13.

Using an electrical analogy, if q and T are analogous to current and voltage respectively, L/kA is analogous to electrical resistance. According to Equation 4-13, thermal resistance can be expressed in terms of material thermal conductivity and geometrical parameters and is independent of the power dissipation.

q -kA=∆TL

------- KAT1 T2–

L-----------------–=

q = Heat flow rate (W)

k = Material thermal conductivity (W/mC)

A = Cross-sectional area (m2)

T = Temperature difference, T1-T2, between the hot and cold regions (K or °C)

L = Linear distance between the locations of T1-T2 (m)

∆

q =∆ T

L kA⁄--------------

∆



Figure 4-28. One-Dimensional Heat Flow by Conduction

4.3.2.2 Convection

Convection is a mode of heat transport from a solid surface to a fluid and occurs due to the bulk motion of the fluid. The basic relation that describes heat transfer by convection from a surface presumes a linear dependence on the surface temperature rise over the ambient, and is referred to as Newton’s law of cooling:

Equation 4-14.

where:

Equation 4-14 can also be written as:

Equation 4-15.

Comparing Equation 4-15 to Equation 4-14, it is apparent that the convective thermal resistancecan be defined as 1/hcA.

L

q

T1 T2 A5630-01240819-29

qc hc A Ts Ta–( )=

qc = Convective heat flow rate from a surface to ambient (W)

A = Surface area (m2)

Ts = Surface temperature (C)

Ta = Average convective heat transfer coefficient

hc = Average convective heat transfer coefficient (W/m2C)

qc

Ts Ta–

1 hcA⁄------------------=



In forced convection, fluid flow is created by an external factor such as a fan. In free or natural convection, fluid motion is induced by density variations resulting from temperature gradients in the fluid. Under the influence of gravity or other body forces, these density differences give rise to buoyancy forces that circulate the fluid and convect heat toward or away from surfaces wetted by the fluid.

4.3.2.3 Radiation

Radiation heat transfer occurs as a result of radiant energy emitted from a body by virtue of its temperature. Radiation heat transport occurs without the aid of any intervening medium. Radiant energy is sometimes envisioned to be transported by electromagnetic waves, at other times by photons. Neither viewpoint completely describes the nature of all observed phenomena.

The amount of heat transferred by radiation, between two surfaces at temperatures T1 and T2 respectively, is governed by the following expression:

Equation 4-16.

where:

Note that the temperatures T1 and T2 in Equation 4-16 are absolute temperatures.

For radiation to make a rather significant contribution compared to either natural convection or forced convection mechanisms, a relatively large temperature difference must exist between T1 and T2. In the case of most low-power electronic applications, these temperature differences are relatively small and, therefore, radiation effects are normally neglected. But for power application, heat transfer by radiation should be considered. To compare radiative and convective effects, a radiation heat transfer coefficient is defined as:

Equation 4-17.

where hr is a radiative heat transfer coefficient.

4.3.3 Thermal Resistance in Packaging Design

The thermal performance of IC packages is typically measured using the junction-to-ambient and junction-to-case thermal resistance values. These parameters are defined by the following relations:

q ∈ σ A T14 T24–( ) F12=

q = Amount of heat transfer by radiation (W)

∈ = Emissivity (0 < ∈ < 1)

σ = Stefan-Boltzmann constant, 5.67 X 10-8 (W/m2 K4)

A = Area (m2)

F12 = Shape factor between surfaces 1 and 2 (A fraction of surface 1 radiation seen by surface 2)

T1, T2 = T1, T2 = Surface temperatures (K)

hr ∈σF12 T12 T22–( ) T1 T2+( )=



Equation 4-18.

Where:

The junction-to-case thermal resistance, θjc, is a measure of the internal thermal resistance of the package from the silicon die to the package exterior. θjc is strongly dependent on the thermal properties (i.e. thermal conductivities) of the packaging materials and on the package geometry. The junction-to-ambient thermal resistance, θja, includes not only the package internal thermal resistance, but also the conductive and convective thermal resistance from package exterior to the ambient. θja values depend on material thermal conductivities, package geometry as well as ambient conditions such as coolant flow rates and the thermophysical properties of the coolant.

To guarantee component functionality and long-term reliability, the maximum device operating temperature is bounded by setting constraints on either the ambient temperature or the package exterior temperature measured at predefined locations. Ambient temperature is most often measured at an undisturbed location at a certain distance away from the package. As defined in Intel experiments, the case temperature is measured at the center of the top surface of the package. Depending on the environment (ambient and board temperatures) within the computer system, thermal enhancements such as fins or forced air cooling may be necessary to meet requirements on the package case temperature, "Tc".

4.3.4 Factors Impacting Package Thermal Resistance

The thermal resistance of a package is not a constant. Package mounting configuration and many packaging and environmental parameters have an impact on the thermal resistance values. The following is a summary of some parameters which affect thermal resistance.

4.3.4.1 Package Size

As shown by the one-dimensional conductive and convective thermal resistance expressions (see Equation 4-14 and Equation 4-16), thermal resistance is inversely proportional to area. This means that as the package gets larger, the thermal resistance becomes smaller due to an increase in the

θjC

Tj Tc–P

-----------------=

θcaTc Ta–

P------------------=

θja θjc θca+=

θja = Junction-to-ambient thermal resistance (C/W)

θjc = Junction-to-case thermal resistance (C/W)

θca = Case-to-ambient thermal resistance (C/W)

Tj = Average die temperature (C)

Tc = Case temperature at a predefined location (C)

P = Device Power dissipation (W)

Ta = Ambient temperature (C)



heat transfer area. Figure 4-29 through Figure 4-31 show typical junction-to-ambient thermal resistance values as a function of lead count for different package families. According to this figure, thermal resistance is lower for packages with higher lead counts (i.e. larger package size) within the same package family.

Figure 4-29. Effect of Package Size on Thermal Resistance of PLCC, PQFP, and PGA Packages

Figure 4-30. Effect of Package Size on Thermal Resistance of Plastic and Ceramic Dual-In-Line Packages

0 100 150 200 250 300

Package Lead Count

0

10

20

30

40

50

60

70

Junc

tion-

to-A

mbi

ent T

herm

al R

esis

tanc

e (C

/W)NOTE: Pin Grid

and Plastic Surface Mount Packages

PQFPPLCCPGA (No Spreader)PGA (With Spreader)SPGA (No Spreader)SPGA (With Spreader)

A5631-01240819-30

50

A5632-01240819-31

160

140

120

100

80

60

40

20

05040302010

Side - Brazed CeramicCerdipPlastic / Alloy 42Plastic / Copper

Lead Count

Junc

tion

- T

o -

Am

bien

tT

herm

al R

esis

tanc

e (C

/ W

)



Figure 4-31. Effect of Package Size on Thermal Resistance of Leadless Ceramic Chip Carrier

4.3.4.2 Packaging Material Thermal Conductivity

Again, the one-dimensional conductive thermal resistance expression shows that thermal resistance is inversely proportional to the thermal conductivity of the packaging material. For example, aluminum oxide, the most commonly used ceramic material, has a thermal conductivity that is an order of magnitude larger than plastic materials. As a result, the internal resistance of a ceramic package is substantially lower than a plastic package from the same package family, resulting in lower overall thermal resistance (see Figure 4-32, CQFP versus PQFP).

Figure 4-32. Effect of Packaging Material on Thermal Resistance

A5633-01240819-32

LCCC

30 40 50 60 70

Lead Count

Junc

tion

- To

- A

mbi

ent

The

rmal

Res

ista

nce

(C /

W)

0

10

20

30

40

50

60

70

80

90

100

CQFPPQFP

200150100500

10

20

30

40

70

60

50

Package Lead Count

Junc

tion

- To

- A

mbi

ent

The

rmal

Res

ista

nce

(C /

W)

A5634-01240819-33



4.3.4.3 Heat Spreader And Heat Slug

Heat spreaders and heat slugs are commonly used to improve the heat spreading effect which results in lower package internal thermal resistance. For leadframe type packages (such as PQFP and SQFP) the heat spreader plate is typically made out of Copper or Aluminum and is attached to the bottom surface of the leadframe. For CPGA type packages, the heat spreader is typically made out of Copper or Copper-Tungsten alloy and is attached to the top surface of the ceramic packages. For both types of packages, the heat slug is a metal block which on the one side is attached to the die and on the other side is exposed to the outside environment. Figure 4-33 shows the difference of thermal resistance for different PQFP package types. Figure 4-34 shows the reduction of θja for CPGA packages by using heat spreader and heat slug when compared to standard packages. It can be seen that the effect of heat spreaders and heat slugs on thermal performance is more significant for smaller die sizes.

Figure 4-33. Effect of Heat Spreader and Heat Slug on Thermal Performance

40

30

20

10

0Standard Spreader Slug

JA(C

/ W

)

208L PQFP

A5635-01240819-54



Figure 4-34. Reduction of θja by Heat Spreader and Heat Slug when Compared to Standard Package

4.3.4.4 Die Size

As shown in Figure 4-35, thermal resistance decreases as the die sizes increases. Increase in die size results in lower power density and larger effective heat transfer area. The changes in thermal resistance are sharper at smaller die sizes, and as the die size approaches packages size, they become less significant.

Figure 4-35. Effect of Die Size on Package Thermal Resistance

300 400 500 600 700 800 900

2.5

2.0

1.5

1.0

0.0

0.5

Die Size (Mil Square)

∆T

heta

ja (

C /

W)

Heat Slug

Heat Spreader

Ceramic PGA

A5636-01240819-55

Junc

tion

- T

o -

Am

bien

tT

herm

al R

esis

tanc

e (C

/ W

)

40

30

20

100.00 0.05 0.10 0.15 0.20

Die Size (IN 2)

68 - Pin PGA168 - Pin PGA

A5637-01240819-34



4.3.4.5 Device Power Dissipation

An increase in device power, which will raise the temperature of the package, results in lower junction-to-ambient thermal resistance (θja) values in natural convection, while not affecting θja in forced convection. The values of θjc do not change significantly as a function of the device power both in natural and forced convection (see Figure 4-36). In natural convection, the convective heat transfer coefficient is proportional to the temperature difference between the case and the ambient, raised to the power n, where n = 0.25 for laminar flow and n = 0.33 for turbulent flow. Therefore, the case-to-ambient thermal resistance will be inversely proportional to this temperature difference raised to the power n, and as a result, to the device power.

Figure 4-36. Effect of Power Dissipation on Thermal Resistance

It should be noted that the error in θja also increases at lower power levels, because both temperature and power measurements are less accurate.

In the case of forced convection, the heat transfer coefficient does not depend on temperature explicitly. Dependency on temperature is only due to changes in material properties. The material properties for air do not vary significantly within the temperature ranges normally encountered. However, at low flow rates, natural and force convection may have effects that are of the same order of magnitude (mixed convection). A small dependency on power may be observed in mixed convection heat transfer. However, as the flow rate increases the power dependency disappears.

4.3.4.6 Air Flow Rate

In forced convection, case-to-ambient thermal resistance is a function of the air flow rate, as shown by Equation 4-19:

Equation 4-19.

Where:

A5638-01240819-35

The

rmal

Res

ista

nce

(C /

W)

20

30

40

10

00 2 4 6 8

jajc

Power Dissipation (W)

θca K Vm⁄=

K = Constant depending on air properties as well as package geometry



Figure 4-37 shows how θja varies as a function of air flow rate for 168-lead PGA with and without heat fins. At lower air flow rates, there is a strong dependency of θja on the air flow rate, but as the air flow rate increases, θja values become less sensitive to the changes in the flow rate.

Figure 4-37. Effect of Air Flow Rate on Thermal Resistance of 168-Lead PGA Package

4.3.5 Mounting Parameters

4.3.5.1 PC Board Size And Thermal Conductivity

The printed circuit board on to which components are mounted can act as a fin by virtue of its thermal conductivity. The effect of conduction in the printed circuit board is illustrated in Figure 4-38. The effect of the board size on overall thermal resistance may vary, depending on the thermal resistance between the junction and the board compared to the resistance between the case and the ambient. Smaller packages with a relatively high case-to-ambient thermal resistance value are more dependent on the board for transfer of heat to ambient than are the larger size packages. Consequently, board size will have a much larger impact on the junction-to-ambient thermal resistance for such packages.

Another factor that impacts the thermal resistance from board to ambient is board thermal conductivity. As board thermal conductivity or board thickness increases, the spreading resistance for lateral conduction of heat within the board decreases. As a result a larger board area becomes available for heat transfer to the ambient.

V = Air velocity (m/s)

m = 1/2 and 4/5 for laminar and turbulent flow respectively

θja θjc K Vm⁄+=

A5639-01240819-36

The

rmal

Res

ista

nce

(C /

W)

ja, Without Fin

Air Flow (LFM)

0 200 400 600 800 10000

5

10

15

20

ja, With Finjc, Without Finjc, With Fin



Figure 4-38. Effect of PC Board Material and Size on Thermal Resistance of 132-Lead PQFP

4.3.5.2 PC Board Temperature

The temperature of the printed circuit board may significantly impact package thermal resistance but is normally ignored in thermal packaging design. A board of specific size and material properties, with only the component under consideration mounted on it, will have a unique equilibrium temperature distribution under fixed environmental and mounting conditions. However, if there are other components on the board, or the board is attached to a heat sink, the maximum board temperature, Tb,may increase or decrease. A change in board temperature will affect the junction temperature and consequently the junction-to-ambient thermal resistance. The junction-to-ambient thermal resistance, θja, measured when the board is influenced by other heating or cooling factors, is referred to as the apparent thermal resistance or systems-level thermal resistance θja,s.

In almost all practical applications, printed circuit boards are populated by many components, and heating of one package influences the thermal performance of other packages. In order to get a relatively good estimate of system thermal resistance, θja,s and θja values must be correlated through another parameter. As it turns out, this parameter is Tb. A simple reistor network shown in Figure 4-39 can be used to obtain this correlation. In this model, it is assumed that the heat flows from the junction to the package boundary, and from there a portion of the heat is transferred directly to the ambient, while the rest goes into the board and is distributed and transferred to the ambient.

A5640-01240819-37

The

rmal

Res

ista

nce

(C /

W)

Junc

tion

- To

- A

mbi

ent

0

50

10 2040

60

K = 0.64 (w / m c)K = 2.2 (w / m c)

PC Board Area / Package Area



Figure 4-39. Simplified Resistor Network

It should be noted that the model shown in Figure 4-39 is simplified, and the actual package resistor network model can be more complex. The following expression shows the relation between θja,s and θja and board temperature rise (Tb - Ta):

Equation 4-20.

A5641-01240819-38

TJ

RC

RB

TB

BAR

TA

TA

CAR

RC

θja s, θja S+=Tb T–

P---------------

SRa

Ra Rb+--------------------=

SRaRbRa Rb Rba+ +( )

-----------------------------------------

where:

P = Power dissipation (W)

Ra = Case-to-ambient resistance (C/W)

Rb = Case-to-board resistance (C/W)

Rba = Board-to-ambient resistance (C/W)

Rc = Junction-to-case resistance (C/W)

S = Sensitivity parameter, Ra/(Ra + Rb) (O < S < 1)

Tb - Ta = Board temperature rise over ambient (C)



Equation 4-20 shows a linear dependence of θja,s on board temperature rise; as the board temperature increases or decreases, the system thermal resistance will increase or decrease. The rate of these changes is dictated by sensitivity parameter S, which in turn depends on Ra/Rb. As Ra/ Rb increases, thermal resistance becomes more sensitive to board temperature rise; in other words, the packages becomes more thermally coupled with other components on the board. Large values of Ra/Rb indicate that the package depends more on the board for transfer of heat to the ambient than on direct heat transfer to the ambient (larger packages vs. smaller packages). On the other hand, as Ra/Rb decreases, S decreases. Smaller Ra/Rb means a higher degree of insulation between the package and the board. For example, the thermal resistance of a package with a copper lead frame is more sensitive to board temperature rise than its counterpart with an Alloy 42 lead frame, as shown in Figure 4-40.

Figure 4-40. Effect of Board Temperature Rise on Thermal Resistance of 132-Lead PQFP with Copper and Alloy 42-Lead Frames

To determine sensitivity factors and intercept in expression 12, the package system thermal resistance can be measured under two different board temperature conditions (θja is assumed to be known).

4.3.5.3 System Thermal Design

As shown in Figure 4-41, the packaging of an electronic system starts with the design or selection of the structure that houses the silicon integrated circuit or chip, proceeds to the chip-to-chip interconnect, continues to the board-to-board level and concludes at the box or cabinet, which houses the complete system.

A5642-01240819-39

The

rmal

Res

ista

nce

(C /

W)

Junc

tion

- To

- A

mbi

ent

K = 0.64 (w / m c)K = 2.2 (w / m c)

0 20 40 60 80 1000

20

120

100

80

60

40

Board Temperature RiseAbove Ambient (C)



nected g. The

use ally. A

Figure 4-41. The Packaging Hierarchy

4.3.6 Typical Configuration of PCs

PC chassis are divided into two categories: desktops and notebooks. Desktops have two major categories: LPX (Low Profile) and Baby AT. A typical LPX PC is 17” x 16” X 4”. Figure 4-42 shows a general configuration. The add-in boards are inserted horizontally into the slots conto the mother board. There are two fans, one for the power supply and one for general coolintotal system power is usually around 100 Watts.

Figure 4-42. The Configuration of the LPX PCs

Figure 4-43 shows the configuration of the Baby AT PC. Its typical size is 20” x 17” x 6”. Becaof the larger available space, more add-in boards can be inserted into the mother board vertictypical system power is around 120 Watts.

A5643-01240819-56

Chip Package

Board

System

Air Flow

Mother Board

CPU

Fan

Add-InBoards

PowerSupply

HDD

FDD

Add-InBoards

A5644-01240819-57

Fan



U the d 12-

be in this

Figure 4-44 shows the configuration of a notebook with a typical size of 11” x 9” x 2”. The CPtypically consumes 4-8 Watts depending on the products used. Other components includingmother board, HDD, FDD and screen use about 6-10 Watts. The total system power is aroun15 Watts.

Figure 4-43. The Configuration of a Typical Baby AT PC

Figure 4-44. The Configuration of a Typical Notebook

4.3.6.1 Worst Case Design Methodology

For electronic systems to function properly under any circumstances, thermal designs must obtained under the worst case scenario. These worst case conditions are briefly discussed section.

Air Flow

Mother Board

CPU

Fan

Add-InBoards

PowerSupply

HDD

FDD

A5645-01240819-58

Fan

1 2 3 4

Air Flow

A5646-01240819-59

Mother Board

CPU Battery

Floppy DiskDrive

HardDiskDrive

Keyboard



the

ing a job. ent. e case, e to the rnal

ink-to-ion

e ailable

ss. olants

icient id

elow tly elp to drop in

he heat se of a less id g timized

CPU power: The use of the maximum CPU power is recommended for system thermal design purposes. The power dissipation values for the Intel family of processors are the maximum power levels for the corresponding processors.

Component power: The thermal impact of components such as the hard disk drive, video and memory cards, and PCMCIA must be taken into account for system level thermal design. In prototype testing, load boards with simulated components can be used to generate the maximum component heat dissipation to investigate the thermal performance of the system.

Ambient temperature: Although most electronic systems work at room temperatures (25 °C),thermal design must consider the extreme environments which the system may experience. Normally an ambient temperature of 35 °C to 40 °C is used by most system designers.

4.3.6.2 System Thermal Designs

As the total system level power dissipation increases and the system size decreases, designcost-effective thermal solution which satisfies all requirements is an increasingly challengingIn general, thermal management can be divided into internal and external thermal managemInternal thermal management handles the thermal resistance from the junction to the packagwhile the external thermal management handles the thermal resistance from the package casambient. For a general thermal system design problem, three factors namely Budgeting, InteThermal Management and External Thermal Management should be considered.

Budgeting: The total junction-to-ambient thermal resistance must be distributed among the various sections of the thermal path; from chip-to-package, package-to-heat-sink and heat-sinside-ambient and inside-ambient-to-outside ambient. The thermal resistance in each sectmust then be managed to meet the assigned thermal budget.

Internal thermal management: This involves selection of thermal interface materials, packagtype, bonding techniques, and via design. The design must also meet constraints of cost, avtechnologies, reliability, manufacturing processes, and yield.

External thermal management. This involves selection of the cooling mode (i.e. conduction, natural or forced convection, or radiation), heat sink design, and heat sink attachment proceFigure 4-45 shows the typical convective thermal resistance values obtained using various coand cooling modes.

When the component is cooled directly by contact with a gas or liquid, the resistance to the convective heat removal from the surface is inversely proportional to the product of the heattransfer coefficient and the wetted area, 1/(hA), where h is the convective heat transfer coeffand A is the wetted area. As shown in Figure 4-45, the convective coefficients range from 100 K/Wfor natural convection of air, to 33 K/W of forced air convection, to 1 K/W in flurochemical liquforced convection.

When direct cooling of the package surface is inadequate to maintain the chip temperature bdesired levels, a heat sink can be attached to the package. A heat sink provides a significanlarger wetted area for the heat transfer. In addition, the extended surfaces of the heat sink hspread the heat. However, the presence of the heat sink may increase the overall pressure the system, and the thermal interface between the package and the heat sink will introduce additional thermal conductive resistance. Proper management of the heat sink design and tsink attach method is required to achieve maximum thermal performance benefits from the uheat sink. Typical air-cooled heat sinks can reduce the external thermal resistance to valuesthan 15 K/W in natural convection and as low as 5 K/W for moderate forced convection. Liqucooled heat sinks can further reduce the external resistance to below 1 K/W. Once the coolinmode has been selected, heat sinks, fans, and the heat sink attachment process must be opfor the system level thermal solution.



Figure 4-45. Typical Convective Thermal Resistances for Various Coolants and Cooling Modes

4.3.6.2.1 Thermal Enhancement Options

There are many thermal enhancement options available to the package and system designer to reduce both the internal package thermal resistance as well as the package-to-ambient thermal resistance. Some of the commonly used enhancement techniques are summarized below.

Heat slug/spreader: In order for the heat to spread efficiently from the silicon die to the package, heat slugs or spreaders are used in the thermal design of many packages. The primary goal is to allow the heat to conduct from the die and spread into the heat spreader or slug. Since the heat transfer area provided by the slug is larger, it helps to reduce the thermal resistance. However, the use of heat slugs and spreaders present several design challenges; thermally induced stresses resulting from a mismatch between the coefficient of thermal expansion between the package and the heat slug or spreader, reliability of the attachment between the die and the slug, and manufacturability issues.

Thermal via and board design: Thermal vias are often used to reduce the thermal resistance of materials with low thermal conductivity like printed circuit boards or substrates. Via designs are divided into two configurations: stacked and staggered. In a stacked via design, successive via layers are stacked with vias on top of each other. In the staggered configuration, the vias are not stacked directly on top of vias in another layer.

Figure 4-46 shows an example of the stacked via designs on PCB. The via has an outside diameter D, height H and is plated with copper of thickness Tw. The thermal resistance of the n vias can be approximately estimated using one dimensional heat conduction analysis:

A5647-01240819-60

Air 1-3 atm

Fluorochemical Liquids

Air 1-3 atm

Fluorochemical Liquids

Water

WettedArea=10 cm2

ForcedConvection

NaturalConvection

0.01 0.1 1.0 10 100 1000

K/W



Equation 4-21.

where Rv is the total thermal resistance of the number (n) of vias and K is the thermal conductivity of the via plating material. Vias reduce the thermal resistance but increase the electrical routing difficulty. The density and size of the vias depends on many factors in the design criteria: electrical routing, thermal performance requirements, cost, etc. The final design is usually a trade-off among various considerations. For a fixed pitch to diameter (say, P/D = 2), the criterion favors vias with small diameters. However, when the pitch is fixed, the minimum thermal resistance is obtained with larger via diameters.

Figure 4-46. Via and Board Design

Heat sinks: Heat sinks vary in shape, size and material depending on applications. Figure 4-47 shows a regular cross cut pin fin heat sink and elliptical pin fin heat sink. The purpose of heat sinks is to spread the heat and to increase the heat transfer area wetted by the coolant. Although heat sinks help in heat spreading, the presence of the fins presents a blockage to the coolant flow causing an increase in the system level pressure drop. Increased pressure drop would require a larger fan to drive the required coolant flow through the computer chassis. The heat sink design (i.e. number, shape and size of fins) must be optimized in order to maximize the heat transfer from the heat sink with the smallest possible increase in the pressure drop.

Rv H Knπ⁄ DTw T2

w–( )=

A5648-01240819-62

H

Tw

DP



Figure 4-47. Square Pin and Elliptical Pin Heat Sinks

Metal plate or rod: Heat spreading should be considered in the thermal design of the system to minimize the temperature drop on the heat dissipating surfaces when: (1) concentrated heat must be transferred to places where space is available for more enhancements like heat sinks or fans, or simply where the thermal environment is more favorable; and (2) if a large surface area is required for heat dissipation. Table 4-17 compares the temperature drops at the ends of a 10" long 1" diameter rod with 1 Watt passing through the rod. Results show that the use of copper or aluminum decreases the thermal resistance by nearly two orders of over the typical PCB. In portable computer systems, flexible laminated copper foils called "flexible heat sinks" can be used in order to satisfy space and weight constraints.

Heat pipes: An increase in the cross-sectional area of a spreader plate made out of copper or aluminum can reduce the spreading thermal resistance. However, this approach is often constrained by the space and weight limitations of the system. Under such circumstances, heat pipes can be used for heat transfer. A typical heat pipe consists of a enclosed, partially evacuated chamber containing a small amount of liquid. The liquid evaporates in the heat pipe section in contact with a hot surface such as the processor package. The vapor travels to the colder sections of the heat pipe and condenses. The internal surface of the heat pipe consists of a mesh or sintered porous wick which transports the condensed liquid, via capillary fluid flow, to the hot section of the heat pipe. Thus, the heat pipe provides an enclosed, phase-change based system for transporting heat from hot to cold regions. Since heat removal in the hot section of the heat pipe, and condensation in the cold sections of the heat pipe involve phase change, there is almost no temperature gradient associated with transfering heat along the heat pipe. This is apparent from the temperature drop value for a heat pipe listed in Table 4-17. Heat pipe designs utilizing water, freons and dielectric fluorinert liquids are commercially available in a variety of configurations.

Fans: Fans provide forced air flow, which improves the convection coefficient significantly. Fans are widely used in desktop computers. However, their use in notebooks will require the resolution of issues typical of portables: power consumption (reducing battery life), space limitations, noise

A5649-01240819-64

Elliptical PinCross-CutSquare Pin

Table 4-17. Comparison of Spreading Efficiency of Different Rods

PCB Aluminum Copper Heat pipe

Temperature Drop (°C) 251 2.51 1.26 0.034

Thermal conductivity (W/m.K) 2 200 400 14800 (equivalent)



s it a very

TF ture

ystem, r has

hout

h

al used

he which ater to e test

nts from

test

voltage point nstant, to sed at 3

lation th

and reliability. In spite of these constraints, the use of fans in high performance notebooks is gaining acceptance because of the steady increase of CPU power and the fact that alternative non-fan solutions are becoming increasingly complicated and expensive.

Fan-sinks. Fans are most effective when combined with heat sinks. Fan-sinks have emerged to provide an integrated solution in improving the thermal performance while achieving smaller overall size and higher efficiency.

Active thermal feedback (ATF). The worst case design methodology often creates products that are “over-designed.” With the increasing complexity of thermal solutions, in many applicationmay not be economical to design products for the worst thermal case, which happens only tosmall portion of the products. Rather ATF can be implemented to deal with those extreme occasions. When the temperature of main components (say, CPU) reach certain threshold, Awill throttle the clock speed to reduce the power consumption of the system until the temperaof the system decreases to a safe level.

It should be noted that when developing a thermal management strategy for the electronic sit is no longer sufficient to focus only on temperature. Rather, the thermal/packaging engineeto understand, control and ultimately eliminate the thermally induced failures present througthe electronic system. The attainment of that goal, accompanied by the severe electrical, manufacturing, cost and reliability constraints, demands better collaboration of engineers witvarious backgrounds to better the design of the system so that it can provide all the desired functions reliably and inexpensively.

4.3.7 Design Methodology

Thermal packaging design at the component and system level may involve both experimentvalidation and modeling. The following sections describe the test methodology which can beto determine various package level thermal resistances.

4.3.7.1 Junction Temperature Measurements

In order to calculate thermal resistance values, the junction temperature is measured using ttemperature- sensitive parameter (TSP) method. This method employs special test structuresare the same size as the actual device. The test structure typically consists of a resistive hesimulate device power dissipation. The temperature sensors, located at different points on thstructure, may either be temperature sensitive diodes or resistors. Temperature measuremethese on-die temperature sensors are used to obtain an accurate estimate of the junction temperature.

A single package is mounted either directly or via a socket on a thermal test board. Differentboard designs , are used for surface mount and through-hole mount packages( see Figure 4-48 and Figure 4-49 respectively). The test chamber volume is 1ft3, and the ambient temperature is measured 12 inches away from the package (see Figure 4-50). In order to obtain accurate temperature measurements from the temperature sensing diodes/resistors, the diode outputor sensor resistance must first be correlated to the temperature. This is done using a three calibration technique. For calibration purposes, the test board assembly is immersed in a couniform temperature dielectric fluid bath The temperature of the dielectric fluid in the bath ismeasured using an RTD probe. The dielectric fluid in the bath is continuously stirred in ordermaintain temperature uniformity. If the temperature sensors are diodes, they are forward-biausing a 100 mA constant current source and the voltage drop accross the diode is measureddifferent bath temperatures. If the temperature sensors are resistors, a four wire resistance measurement is obtained at 3 different bath temperatures. A linear best fit straight line correis usually obtained to relate the diode voltage drop or sensor resistance to the measured batemperature



After calibration, the test structure is powered up to the desired power level. The on-die temperature sensors are continuously monitored until no change is detected in the temperature level, indicating an equilibrium state. At this stage, the chip surface temperatures, ambient and case temperatures, and device voltage drop and current are recorded. The device voltage drop and current are used to estimate the actual power dissipated in the test structure. When measuring thermal resistance under forced convection conditions, the test board assembly is exposed to a developed air flow. In this case, air velocity is measured at a location 12 inches upstream from the leading edge of the test board, using a hot wire anemometer. Air temperature is also measured at the same location.



Figure 4-48. Typical Thermal Test Board for Through Hole Mount Component

A5626-01

4.5 In.

6 In.

24019-25



Figure 4-49. Typical Thermal Test Board for Through Surface Mount Component

A5627-01

4.5 In.

5.5 In.

72 2

13284

240819-26



Figure 4-50. Test Chamber for Thermal Performance Testing

4.3.7.2 Case Temperature Measurement

Case temperature, "Tc", is measured at the center of the top surface of the package. This is typically the location with the highest temperature on the package case. Special care is required when measuring the case temperature to ensure an accurate temperature measurement. Usually, a thermocouple attached to the top surface of the package is used to measure Tc. Thermocouples must be calibrated before making temperature measurements. Moreover, different types of measurement errors are introduced when measuring the temperature of a surface which is at a temperature different from that of he surrounding ambient air. These errors could be caused due to poor thermal contact between the thermocouple junction and the package case, and due to heat loss by radiation or by conduction through the thermocouple leads. To minimize measurement errors, the following approach is recommended:

• Use 36 gauge or finer diameter, type K, T, or J thermocouples. Intel laboratory testing is performed using type K thermocouples made by Omega (part number: 5TC-TTK-36-36).

• Attach the thermocouple bead to the center of the package top surface using high thermal conductivity cements. The laboratory testing is performed by using Omega Bond (part number: OB-101).

• The thermocouple should be attached at a 90° angle as shown in Figure 4-51.

• If the case temperature is measured with a heat sink attached to the package, drill a hole (no larger than 0.15 inches) through the heat sink to route the thermocouple wire out Figure 4-51.

12 In.

Air FlowDirection

Hot WireAnemometer

Test Board

Thermocouple

A5628-01240819-27



Figure 4-51. Location of Package Case Temperature Measurement

4.3.7.3 Numerical Modeling

During the initial phases of the thermal design, numerical modeling can be very effectively used to investigate feasibility of the design. Numerical modeling provides significant savings because it eliminates the need for expensive prototype fabrication and time consuming experimental measurements. Package level numerical models, validated using experimental measurements, can be incorporated in system level models to compare various system level design options. A large selection of very sophisticated computational tools for thermal and fluid flow analysis are available commercially. Some of the tools like ANSYS, PATRAN/ABAQUS, and Ideas are suitable for detailed investigations of heat conduction within a board or a component. Other tools like IcePak, Flotherm, Ideas-TMG, Coolit etc. provide the ability to solve conjugate problems involving fluid flow and heat transfer. These tools provide sophisticated, easy to use graphic interfaces and can be used very effectively to analyse the fluid flow and heat transfer phenomena within complete electronic systems.

Numerical models usually incorporate highly simplified representations of electronic components. Additionally, detailed modeling of components results in large computational times but seldom adds much value to the thermal performance trends. The thermal properties of commonly encountered materials such as Silicon or Aluminum are well known and can be directly inserted in the thermal model. However, components like the printed circuit boards and substrates are made out of many layers of and other insulating materials. Moreover, the copper layers are not single sheets of copper; they have cutouts due to the presence of traces, vias and other electrical structures. Due to the complexity of the actual substrate construction, it is difficult to estimate the effective thermal properties with a high degree of accuracy. In almost all cases, these thermal properties must be determined by using experimental measurements to validate the model predictions.

For validation purposes, the component and test board are instrumented with thermocouples to measure the temperature distribution within and on the component and on the substrate. Thermocouples are also used to measure case and ambient temperatures. The experiments are conducted using a partial factorial design. A factorial design involves independently powering up individual components. Powering up a single component allows the ability to monitor the heat spreading inside the component and also within the substrate. This data is very useful to determine

A5629-01240819-51



the thermal properties for simplified component representations. Such experimental data can be used to determine the thermal properties which when used in the numerical model would provide temperature predictions to a reasonable degree of accuracy.

4.4 References

[1] Suhir E., "Calculated Thermally Induced Stresses in Adhesively Bonded and Soldered Assemblies", ISHM International Symposium on Microelectronics, Atlanta, Georgia, Oct 1986.

[2] "Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments", IPC-SM-785, Nov 1992.

[3] Born, M., and Wolf, E., Principles of Optics, pp. 286-300, 1980, Pergamon Press, Oxford.

[4] Guo, Y., and Liu, S., "Development in Optical Methods for Reliability Analyses in Electronic Packaging Applications," Experimental/Numerical Mechanics in Electronic Packaging, vol. 2, pp. 10-21, R. Mahajan, B. Han, and D. Barker, ed., Society for Experi-mental Mechanics, Bellevue, WA, June 1997.

[5] Post, D., Han, B., and Ifju, P., High Sensitivity Moiré, 1994, Springer-Verlag, Inc., New York.


• Re-wrote section 4.2

• Re-wrote several portions of section 4.3

• Added a section on numerical modeling

• General edit of all other sections


Physical Constants of IC Package Materials 5

Table 5-1 through Table 5-9 list typical values for selected properties of materials used in IC packages.

Table 5-1. Case Material Characteristics

Properties UnitsAlumina

(92%) KovarMolding

CompoundSealing Glass

Cu-W(90%) Cu

Density kg/m3

(g/cc)3600-3700

(3.6-3.7)

8400(8.4)

1790-1850(1.79-1.85)

4700(4.7)

17000(17)

8900(8.9)

Modulus of Elasticity GPa 55 138 E1 = 11.7E2 = 0.1

5.7 255 125

Tensile Strength MPa 157 627 19.98 270

Thermal Conductivity (20°C)

W/mK 18 17.5 0.58 -0.67 0.6 180 - 200

Coefficient of ThermalExpansion

ppm/°C

6.8(25° C - 400°C)

5.3(40°C - 250°C)

a1 < 23a2 < 80(40°C - 250°C)

6.3 - 7.0(40°C - 250°C)

6.5(25°C - 500°C)

16(25°C - 500°C)

Electrical Resistivity Ω cm 1014 49 X 10-6 5 X 1012 >1011 <6 X 10-6 <2 X 16-6

DielectricConstant (1 MHz)

7.9 - 10.0 NA < 5.0 11.5 NA NA

Flammability Rating * inches 1/8

NOTE: 1. * UL-94V-0

Table 5-2. Lead/Lead Frame Characteristics

Properties Units

Copper Alloy

MF 202 Alloy 42 Kovar TAMAC5 CDA 194OLIN7025

EFTEC64T

Density kg/m3

(g/cc)8880(8.8)

8100(8.1)

8400(8.4)

8900(8.9)

8800(8.8)

8800(8.8)

8900(8.9)

Modulus of Elasticity GPa 113 145 138 120 121 131 119

Tensile Strength MPa 490-590 588-735 627 527-562 480-519 527 560

Thermal Conductivity (20°C)

W/mK 160 15.7 17.5 138 263 166 300

Coefficient of Thermal Expansion

ppm/°C

17.0 4.5 5.3 16.7 16.3 17.1 17.0

Electrical Resistivity Ω cm 5.7 X 10-6 57 X 10-6 49 X 10-6 4.9 X 10-6 2.6 X 10-6 4.3 X 10-6 2.3 X 10-6


Physical Constants of IC Package Materials

Table 5-3. Solder Material Melting Temperatures

Solder Type Temperature (°C)

Sn-Pb Plating (85 wt% Sn) 200 - 225

Sn-Pb Eutectic (62 wt% Sn) 183

Tin 232

Lead 327

Gold 1063

Copper 1083

Silver 961

Copper/Silver Braze (28 wt% Cu) 850

Au-Sn Eutectic (80 wt% Au) 280

Table 5-4. Die Attach Material Characteristics

Property Units

Silver FilledGlass

Silver Filled

Adhesive

Silver FilledEpoxy

99.99%Au + 2% Si 99.99% Au

Density kg/m3

(g/cc)4500(4.5)

2500(2.5)

14500(14.5)

19300(19.3)

Modulus Elasticity GPa 0.77 69.5(Data for Au + 3%

Si)

62.5

Tensile Strength MPa > 10. 500-600 130

Thermal Conductivity W/mK 270 2.5 @ 121°C

1.6 @121°C

50 311


ppm/°C 8 α1 = 40α2 = 150

α1 = 46α2 = 240

50@ 25°C

14.2@ 25°C

Electrical Resistivity Ω cm 1 X 10-5 1 X 10-4 2 X10-4 3.1 X 10-4 2.21 X 10-6

Table 5-5. TCP Package Materials Characteristics

Property Units Polyimide AdhesiveCu-Foil Rolled

Cu-Foil Electro-

Deposited Encapsulant

Density kg/m3

(g/cc)1470(1.47)

1500 - (1.5)

8931(8.9)

8931(8.9)

1330(1.33 uncured)

Modulus Elasticity GPa 9 @ 25°C4 @ 300°C

8 @ 25°C 127.4 127.4 6.55 @ 25°C

Tensile Strength MPa 400 40 - 100 ~450 532

Thermal Conductivity

W/mK 0.2 0.1 - 0.2 390 390 0.52


ppm/°C 12 - 1825°C - 300°C

30 - 6025°C - 300°C

16.725°C

16.7 α1 = 31α2 = 118

Electrical Resistivity

Ω cm >1 X 1015 >1016

(0%RH)

>1015 (55%RH)

1.7 X 10-6 1.7 X 10-6

Dielectric Constant

relative 3.5 (KHz) 3.0 (1 KHz) NA NA 3.8 (1 KHz)



Table 5-6. PPGA Package Materials Characteristics

Property Units Silver Filled Epoxy Encapsulant

Density kg/m3

(g/cc)2500(2.5)

Modulus Elasticity GPa 10.2 @ 25° C

Tensile Strength MPa

Thermal Conductivity W/mK 1.6 @ 121°C 0.52


ppm/°C α1 = 46α2 = 240

α1 = 19α2 = 70

Electrical Resistivity Ω cm >1 X 10-4 2.18 x 1016

Dielectric Constant relative @ 1kHz=3.68

Table 5-7. PBGA Material Characteristics

Property Units Laminate Substrate Solder Mask Die Attach Molding

CompoundSolder

Spheres

Density g/cc 1.4 3.5 1.9 8.4

Modulus of Elasticity

GPa 12-18 0.3-2.0 Flexural Modulus

15 - 20

30

Tensile Strength

MPa 225-300 Flexural strength

95 - 150

35


W/mK 0.20 2.0 0.7-0.9 50.6

Glass Transition Temp

°C 195

(BT epoxy)

105 25-100 180-225 Eutectic point 183


ppm/°C 12-16 (x, y)

72 - 85 (z)

α1 = 60

α2 = 160

α1 = 40-80

α2 = 150-200

α1 = 12-18

α2 = 41-65

24.7

Volume Resistivity

Ω cm = 25 °C 1013 - 1016 > 1014



Table 5-8. High-Thermal, Low-Profile HL-BGA Material Characteristics

Property Units Copper Slug Tape Substrate Die Attach Encapsu-

lationSolder

Spheres

Density g/cc 8.96 1.4 (resin) 3.5 1.5-1.8 8.4

Modulus of Elasticity

GPa 110-20 0.3-2.0 5-13 30

Tensile Strength

MPa 220 24kpsi (resin) 70 35


W/mK 390-400 2.0 0.85-0.90 50.6


°C Melting Point 1083

260 25-100 90-170 Eutectic point 183


ppm/°C 16-18 (x, y)

50 (z)

α1 = 40-80

α2 = 150-200

α1 = 16-26

α2 = 70-80

24.7

Volume Resistivity

Ω cm = 25 °C 106 > 1015

Table 5-9. Flip Chip Style HL-PBGA Material Characteristics

Property Units Substrate Solder Mask Underfill

Modulus of Elasticity GPa 3 3 8

Tensile Strength MPa 70 60


°C 200 175 135


ppm/°C α1 ~ 70 α1 ~ 70 α1 ~ 30

Volume Resistivity Ω cm = 25 °C ~1010 ~1010


ESD/EOS 6

6.1 ESD

6.1.1 Electrostatic Discharge (ESD)

Electrostatic discharge (ESD) costs the electronics industry millions of dollars each year in damaged components, non-functional circuit boards and scrambled or missing information. ESD can occur in the manufacturing, shipping, receiving, and field handling of integrated circuits or computer boards with no visible signs of damage. A malfunction in these components or boards can occur immediately or the apparatus may perform for weeks, months, or even years before an unpredictable and premature breakdown causes a field failure.

6.1.2 Why Should I Care About Electrostatic Discharge?

When you incorporate electronic components or boards into your products, ESD damage can have a direct impact on your company’s reputation and profits. That is because electrostatic damage directly affects the quality and reliability of your products. However, for a small investment in time, manpower, and equipment, you can virtually eliminate ESD-caused problems. The tangible benefits to you include:

• Higher manufacturing yields

• Less rework and inventory

• Reduced overall costs

• Fewer field failures and warranty calls

• Increased product reliability

• More repeat business resulting in greater profits

6.1.3 Intel’s Commitment to Eliminate ESD Damage

Intel manufactures and uses electronic components, and has implemented a comprehensive ESD prevention program to ensure that its products are delivered to customers with the highest possible reliability. Our experts would like to share with our suppliers and customers what they have learned about ESD control. Using this information, you can implement similar preventive practices in your factories and warehouses. As a result, component failures can be minimized.

6.1.4 What is ESD?

ESD is the transfer of electrical charge between two bodies at different potentials, either through direct contact or through an induced electrical field. It is the phenomenon that gives you a mild shock when you walk across a carpeted floor and then touch a doorknob. While this discharge gives a harmless shock to humans, it is lethal to sensitive electronics. For example, the simple act of walking across a vinyl floor can generate up to 12,000 V of static electricity. That is many times the charge needed to ruin a standard Shottky TTL component.


ESD/EOS

Several technical failure mechanisms associated with ESD cause damage to microelectronic devices, including gate oxide breakdown, junction spiking, and latch-up.

• Gate oxide failure is a breakdown of the dielectric between the transistor gate and channel resulting in excessive leakage or a functional failure.

• Junction spiking failure is a migration of the metallization through the source/drain junction of MOS transistors causing leakage or a functional failure.

• Latch-up failure can be triggered by ESD, causing an internal feedback mechanism that gives rise to temporary or permanent loss of circuit function.

6.1.5 Common Causes of ESD

Electrostatic generation arising from friction between two materials is called triboelectric charging. It occurs when two materials are separated or rubbed together. Examples include:

• Opening a common plastic bag.

• Removing adhesive tape from a roll or container.

• Walking across a floor.

• Transporting computer boards or components around in their trays on carts.

• Sliding circuit boards on a work bench.

When handling parts or their containers, ungrounded personnel can transfer high static charges. Unless these static charges are slowly dissipated, ESD event can inflict damage to the devices.

Electrical fields can penetrate electrical devices. An ungrounded person handling a component or computer board in a non-static shielding container can inadvertently transfer an electrical charge through the container into the sensitive electronic device.

6.1.6 ESD Occurs at All Levels of Integration

Electrostatic discharge is not selective when affecting your products. It can strike components directly or indirectly by passing to the component via connectors and cables. Components mounted on circuit boards are also susceptible.

In-line film resistors between inputs and off-board connectors provide only marginal ESD protection and are often damaged themselves.

6.1.7 What Can I Do To Prevent ESD?

Fortunately, preventing ESD can be relatively easy and inexpensive. Two areas of focus are:

• Eliminating static charges from the workplace.

• Properly shielding components and assemblies from static fields.

Eliminating static electricity in the workplace is accomplished by grounding operators, equipment, and devices (components and computer boards). Grounding prevents static charge buildup and electrostatic potential differences. Electrical field damage is averted by transporting products in special electrostatic shielding packages.


ESD/EOS

ator’s traps a wrist when

e

hazard.

our on to

ESD

-8686

how to

Many vendors of ESD-protective equipment are willing to audit your facilities, recommend appropriate procedures and materials, and assist in their implementation. You may choose to consult with such a firm to determine your exact requirements; in the meantime, review this chapter to gain an understanding of the basic components of a sound ESD prevention program.

6.1.8 Outfitting An Effective Workplace

An effective workplace should be outfitted with the following items:

ESD protective clothing/smocks. Street clothing must not come in contact with components or computer boards since the various materials in clothing can generate high static charges. ESD protective smocks, manufactured with conductive fibers, are recommended.

Electrostatic shielding containers or totes. These containers (bags, boxes, etc.) are made of specially formulated materials which protect sensitive devices during transport and storage.

Antistatic or dissipative carriers. These provide ESD protection during component movement in the manufacturing process. It must be noted that antistatic materials alone will not provide complete protection. They must be used in conjunction with other methods such as totes or electrostatic shielding bags.

Dissipative table mat. The mat should provide a controlled discharge of static voltages and must be grounded. The surface resistance is designed such that sliding a computer board or component across its surface will not generate more than 100 V.

Personal grounding. A wrist strap or ESD cuff is kept in constant contact with bare skin and has a cable for attaching it to the ESD ground. The purpose of the wrist strap is to drain off the operstatic charge. The wrist strap cord has a current-limiting resistor for personnel safety. Wrist smust be tested frequently to ensure that they are undamaged and operating correctly. Whenstrap is impractical, special heel straps or shoes can be used. These items are effective onlyused in conjunction with a dissipative floor.

ESD protective floor or mat. The mat must be grounded through a current-limiting resistor. Thfloor or mat dissipates the static charge of personnel approaching the work bench. Special conductive tile or floor treatment can be used when mats are not practical or cause a safety Chairs should be conductive or grounded with a drag chain to the flooring.

6.1.9 Summary

Intel uses a full range of electrostatic discharge prevention techniques. We invest in proper employee training, purchase appropriate ESD protection equipment and supplies and adapthandling and manufacturing procedures for ESD prevention requirements. The same attentidetail is required of all our suppliers, factories, repair centers, and field service staff.

Intel is committed to helping its partners — both suppliers and customers — to manage the problem. If we can be of further assistance in your efforts to eliminate electrostatic dischargedamage, please contact the Intel Components Quality Question Line: In the USA 1-800-628or 1-916-356-7599, or contact your local Intel Sales Office.

6.2 EOS - Electrical Overstress

EOS is the number one cause of damage to IC components. This section describes EOS andprevent it.


ESD/EOS

caused

the

open

6.2.1 How EOS Damages a Component

Damage is caused by thermal overstress to a component’s circuitry. The amount of damageby EOS depends on the magnitude and duration of electrical transient pulse widths. We canbroadly classify the duration of pulse widths into long (>100 µs) and short (<100 µs) types, and magnitude into exceeding an individual component’s EOS threshold. For short pulse widths most common failure mode is junction spiking.

Figure 6-1. Junction Spiking Failure

For long electrical pulse widths the most common failure modes are melted metallization andbond wires.

Figure 6-2. Melted Metallization Failure

A5655-01

241422-1

Aluminum

Junction Spiking

n+

P

A5656-01

241422-2

Bond Wire

Metal Interconnect

SiliconChip

LeadFrame

Header


ESD/EOS

Figure 6-3. Open Bond Wire Failure

6.2.2 Common Causes of EOS

Inadequate work procedures:

• Lack of standard work procedures

• Incorrect device orientation

• Insertion/removal of components with power applied

• Boards/units not well connected, then power applied

Noisy Production Environments:

• Lack of power line conditioners

• Lack of AC line filters

Improper testing at device or board level can create EOS:

• Hot switching effect

• Incorrect test sequence such as application of signals to Device Under Test (DUT) before powering up chip

• Application of excessive voltages to chip beyond spec limits

• Poorly designed electrical stress tests such as burn-in which overstresses sensitive chips

Use of low quality power supplies:

• Poor design considerations can lead to noise sources especially in switching power supplies

• Lack of power supply overvoltage protection circuits

• Insufficient line filtering and/or transient suppression at the input stage of power supplies

• Incorrect selection of fuse providing inadequate protection

Lack of Proper Equipment and Line Monitoring:

• Equipment not grounded

• Loose connections causing intermittent events

A5657-01

241422-3

Bond Wire

Metal Interconnect

SiliconChip

LeadFrame

Header


ESD/EOS

pt.,

nd

ess

ntel

• Poor wire maintenance

• AC supply lines not monitored for voltage transients or noise

6.2.3 Prevention of EOS

Establish and follow proper work procedures.

Conduct regular AC supply line monitoring and, if necessary, install EOS line control equipment such as incoming line filtering and transient suppression circuits.

Ensure proper testing of components and boards:

• Check test programs for hot switching and incorrect test sequence.

• Solicit maximum specification ratings from manufacturers to ensure devices are not over-stressed.

• Ensure reliability stress tests are properly designed, especially during burn-in.

• Check for excessive noise levels.

• Use “transzorbs” to clamp voltage spikes.

Use quality power supplies with the following features:

• Overvoltage protection

• Proper heat dissipation

• Use of fuses at critical locations

Adhere to a strict equipment maintenance program to ensure:

• Equipment is properly grounded

• There are no loose connections

6.3 Reference

[1] Edward S. Yang, “Microelectronic Devices”, McGraw-Hill, 1988.

[2] Kohlhass, Phil, “Controlling Potential Static Charge Problems”, 3MNuclear Products DeSt.Paul, MN.

[3] “Electrical Overstress/Electrostatic Discharge Symposium Proceedings”, The EOS/ESDAssociation and ITT Research Institute, 1985 and 1986.

[4] DOD-HNBK-263,Electrostatic Discharge Control Handbook for Protection of Electrical aElectronic Parts, Assemblies and Equipment”, 2 May, 1980.

[5] McFarland, W.Y., “The electronic benefits of an effective electrostatic discharge awarenand control program—an empirical analysis”. 1981 Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

For more information regarding PGA insertion, request a copy of item # 8130 by calling the IFAXBACK line U.S. 1-800-628-2283 or 1-916-356-3105 Europe 44-793-4960646


ESD/EOS


• Renamed chapter

• Removed Mechanical Assembly Damage Section


ESD/EOS


Leaded Surface Mount Technology (SMT) 7

7.1 Introduction

Traditional through-hole Dual In-Line Package assemblies reached their limits in terms of improvements in cost, weight, volume, and reliability at approximately 68L. SMT allows production of more reliable assemblies with higher I/O, increased board density, and reduced weight, volume, and cost. The weight of printed board assemblies (PBAs) using SMT is reduced because surface mount components (SMCs) can weigh up to 10 times less than their conventional counterparts and occupy about one-half to one-third the space on the printed board (PB) surface. SMT also provides improved shock and vibration resistance due to the lower mass of components. The smaller lead lengths of surface mount components reduce parasitic losses and provide more effective decoupling

The smaller size of SMCs and the option of mounting them on either or both sides of the PB can reduce board real estate by four times. A cost savings of 30% or better can also be realized through a reduction in material and labor costs associated with automated assembly.

7.2 Types Of Surface Mount Technology

SMT replaces DIPs with surface mount components. The assembly is soldered by reflow and/or wave soldering processes depending on the mix of surface mount and through-hole mount components. When attached to PBs, both active and passive SMCs form three major types of SMT assemblies, commonly referred to as Type 1, Type II, and Type III (see Figure 7-1).

Type I is a full SMT board with parts on one or both sides of the board.

Type II is probably the most common type of SMT board. It has a combination of through-hole components and SMT components. Often, surface mount chip components are located on the secondary side of the Printed Board (PB). Active SMCs and DIPs are then found on the primary side. Multiple soldering processes are required.

Type III assemblies are similar to Type II. They also use passive chip SMCs on the secondary side, but on the primary side only DIPs are used.


Leaded Surface Mount Technology (SMT)

Figure 7-1. Surface Mount Technology Board Types

The process sequence for Type III SMT is shown in Figure 7-2. Leaded components are inserted, usually by automatic equipment. The assembly is turned over, and adhesive is applied. Next, passive SMCs are placed by a "pick-and-place" robot, the adhesive is cured, the assembly is turned over, and the wave-soldering process is used to solder both leaded and passive SMCs in a single operation. Finally, the assembly is cleaned (if needed), inspected, repaired if necessary, and tested. For this type of board, the surface mount components used are chip components and small pin count gull wing components.

A5664-02

PLCCSO

PassiveComponents

Solder Paste

SO PassiveComponents PLCC

PassiveComponent

PLCCSO

DIP

DIPs

Solder Paste

Type I

Type II

Type III

PassiveComponents Only*

PassiveComponents Only*

NOTE: Intel does not recommend active devices be immersed in solder wave.



The process sequence for Type I SMT is shown in Figure 7-3. For a single sided type I, solder paste is printed onto the board and components are placed The assembly is reflow soldered and cleaned (if needed). For double-sided Type I, the board is turned over, and the process sequence just described is repeated.

Type II assemblies go through the process sequence of Type I SMT followed by the sequence for Type III. In general practice, only passive chip components and low pin count gull wing components are exposed to solder wave immersion.

Figure 7-2. Typical Process Flow for Underside Attachment (Type III SMT)

Figure 7-3. Typical Process Flow for Total Surface Mount (Type I SMT)

7.3 Fine Pitch Devices

The need for high lead-count packages in semiconductor technology has increased with the advent of application-specific integrated circuit (ASIC) devices and increased functionality of microprocessors. As package lead count increases, devices will become larger and larger. To ensure that the area occupied by packages remains within the limits of manufacturing equipment, lead pitches have been reduced. This, coupled with the drive toward higher functional density at the board level for enhanced performance and miniaturization, has fostered the introduction of many devices in fine-pitch surface mount packages.

A5665-02

Place SurfaceMount

ComponentsCure Adhesive

ApplyAdhesive

InsertLeaded

ComponentsInvert Board

Invert Board Wave Solder Clean

(if needed)

Test

A5666-02

(if needed)

Screen PrintSolder Paste

Side 2

PlaceComponents Dry Paste

ReflowSolder

Clean Test

Invert Board

Screen PrintSolder Paste

Side 1

PlaceComponents Dry Paste

ReflowSolder Single

SideOnly



A fine-pitch package can be broadly defined as any package with a lead pitch finer than the 1.27mm pitch of standard surface mount packages like PLCCs and SOPs. Most common lead pitches are .65mm and .5mm. There are even some now available in 0.4mm pitch. Devices with these fine pitches and leads on all four sides are called Quad Flat Packs, (QFPs).

The assembly processes most dramatically affected by the fine-pitch package are paste printing and component placement. Fine pitch printing requires high quality solder paste and unique stencil aperture designs. Placement of any surface mount package with 25 mils or less of lead pitch must be made with the assistance of a vision system for accurate alignment.

Placement vision systems typically consist of two cameras. The top camera system scans the surface of the board and locates fiducial targets that are designed into the artwork of the board. The placement system then offsets the coordinates in the computer for any variation in true board location. The bottom camera system, located under the placement head, views the component leads. Since the leads of fine-pitch components are too fragile to support mechanical centering of the device, the vision system automatically offsets for variations in the X, Y, and theta dimensions. This system also inspects for lead integrity problems, such as bent or missing leads.

Other manufacturing issues for assembling fine-pitch components on PC boards include:

1. Printing various amounts of solder paste on the 25-mil and 50-mil lands. One stencil thickness will usually suffice. But stencils may be stepped down to a thinner amount for fine pitch aperture areas to keep volumes lower to prevent bridging.

2. Cleaning adequately under and around package leads,3. Baking of the packages to remove moisture,. Thin QFPs are susceptible to a problem known

as popcorning where moisture in the plastic can literally explode when heating in reflow or rework and crack the plastic package.

4. Handling of the packages without damaging fragile leads.

These challenges are by no means insurmountable. Many equipment choices have already found solutions to these issues.

7.4 Surface Mount Design

7.4.1 Design for Manufacturability

Design for manufacturability is gaining more recognition as it becomes clear that cost reduction of printed wiring assemblies cannot be controlled by manufacturing engineers alone. Design for manufacturability-which includes considerations of land pattern, placement, soldering, cleaning, repair, and test-is essentially a yield issue. Thus, companies planning surface mount products face a challenge in creating manufacturable designs.

Of all the issues in design for manufacturability, land pattern design and interpackage spacing are the most important. Interpackage spacing controls cost-effectiveness of placement, soldering, testing, inspection, and repair. A minimum interpackage spacing is required to satisfy all these manufacturing requirements, and the more spacing that is provided, the better.

With the vast variety of components available today, it would be difficult to list or draw the space requirements for every component combination. In general, most component spacing ranges from 0.040 in. to 0.060 in. The space is typically measured from pad to pad, lead to lead, or body to body, whichever is closest. Smaller spacing (0.040 in) is generally used for low or thin profile parts and small chip components. Taller parts such as PLCCs are usually spaced at 0.060 in. The placement capability of each individual piece of equipment will partially dictate minimum



requirements. However, often the ability to rework or repair individual leads, or entire parts, will have a stronger influence on the minimum spacing. Allowing enough space for rework nozzles or soldering irons can save considerable cost by allowing repair of a few bad solder joints versus scrapping the entire board. Thus, each user must set spacing requirements based on the equipment set used.

The spacing between the pads of conventional and surface mount components may be as large as 0.100 in. so that auto-insertion equipment may used for conventional components. Clear spaces of at least 0.050 in. should be allowed around all edges of the PC boards if the boards are tested off the connector, or 0.100 in. if vacuum seal is used for testing, such as bed-of-nails.

Another manufacturing consideration is the alignment of components on the PC board. Similar types of components should be aligned in the same orientation for ease of component placement, inspection, and soldering.

Via holes are used to connect SMC lands to conductor layers. They may also be used as test targets for bed-of-nails probes and/or rework ports. Via holes may be covered with solder mask material if they are not required for node testing or rework. Such vias are called tented or capped vias.

Via holes may be placed under surface mount components. However, in Type II and Type III SMT (mix-and-match surface mount), via holes under SMCs should be minimized or tented with solder mask to prevent trapping of flux under the packages during wave soldering. For effective cleaning, via holes should only be located beneath SMCs in Type I SMT assemblies (full surface mount) that are not wave soldered.

7.4.2 Land Pattern Design

The surface mount land patterns, also called footprints or pads, define the sites where components are to be soldered to the PC board. The design of land patterns is very critical, because it determines solder joint strength and thus the reliability of solder joints, and also impacts solder defects, cleanability, testability, and repair or rework. In other words, the very producibility or success of SMT is dependent upon the land pattern design.

The lack of standardization of surface mount packages has compounded the problem of standardizing the land pattern. There are a variety of package types offered by the industry, and the variations in a given package type can be numerous. For example, for the small outline package (SOP), there are not only two lead types (gull-wing and J-lead), but there are multiple body types such as narrow wide and thin. In addition, the tolerance on components varies significantly, adding to the manufacturing problems for SMC users.

In this section, general guidelines are presented for land pattern designs that accommodate reasonable tolerances in component packages, process, and equipment used in manufacturing. These guidelines are based on manufacturability and environmental testing of different land pattern designs for reliability.

To simplify the land pattern design guidelines, surface mount components are divided into four different categories:

1. 0.050" Pitch J-leaded Devices2. 0.050" Pitch Gullwing Leaded Devices3. Sub 0.050" Pitch Gullwing Leaded Devices4. Chip Components



Again, with the large variety of SMT part available today, listing every pad size would create a very long list. So, instead of providing specific pad sizes, the general formulas for the land pattern designs are given for each of these four categories. There are several different approaches to dimensioning pads. In addition to the guidelines below, IPC also publishes its own set of guidelines. Each customer should study several options and decide which is best for their application.

7.4.2.1 0.050" Pitch J-Leaded Devices

The following dimensions will be needed:

• Nominal pitch (without tolerance)

• Maximum lead span (use tolerance)

• If several vendors’ parts are proposed for the same pattern, be sure to consider them all when extracting the above dimensions.

An overview of the land pattern design method is:

1. Set the OD (outside distance) using the max lead span.

• Set the OD equal to the max lead span, plus 0.030", rounded UP to the nearest 0.010".

2. Derive the ID, using the standard pad for this pitch.

• Subtracting two standard pad lengths from the OD established in (1). The standard pad for this pitch is:

Pitch = 0.050” Pad Size = 0.025"x0.075"

3. Set the stencil aperture size.

• In CAD, make the stencil aperture the same as the metal pad. The stencil vendor will modify the solder paste artwork if necessary, with input from the Manufacturing or Process Engineer.

Comments:

• The outer (heel) fillet is the important one for J-leaded devices.

7.4.2.2 0.050" Pitch Gullwing Leaded Devices


• Nominal pitch (without tolerance)

• Maximum toe-to-toe lead span (use tolerance)

• Minimum heel-to-heel lead span (if not specified directly, can be calculated by subtracting twice the max foot length from the min toe-to-toe lead span)

The following spec is desirable:

• Minimum body width

If several vendors’ parts are proposed for the same pattern, be sure to consider them all when extracting the above dimensions.




1. Set the OD (outside distance) using the max lead span.

• Set the OD equal to the max toe-to-toe lead span, plus 0.020", rounded UP to the nearest 0.010".

2. Derive the ID, using the standard pad for this pitch.

• Subtract two standard pad lengths from the OD established in (1). The standard pad for this pitch is:

Pitch = 0.050” Pad Size = 0.025"x0.075"

3. Check the ID for adequate fillet.

• The ID should be no greater than the min heel-to-heel minus 0.030". This allows for a 0.015" fillet on each side. If it passes this test, then this ID is the final ID. If it fails this test, go on to (4).

4. If adequate fillet is not achieved, decrease the ID.

• If the ID fails the test in (3), then determine which of the following is the greater:

Min heel-to-heel minus 0.030"

Min body width minus 0.010"

• Set the final ID to whichever is greater rounded DOWN to the next 0.010".

• Calculate the pad length as (OD-ID)/2. Use the standard pad WIDTH from the table in (2).

5. Set the stencil aperture size


Comments:

• The inner (heel) fillet is the important one for gullwing devices. Toe fillets are not required, as they add little strength, and often don’t form anyway, due to lead trimming after plating (end of toe may be bare copper or alloy 42).

7.4.2.3 Sub 0.050" Pitch Gullwing Leaded Devices

On rectangular four sided parts, the steps below must be used twice, since different dimensions are required for each axis. For these parts, the same pad and stencil sizes are used on all four sides.


• Nominal Pitch (without tolerance)

• Maximum toe-to-toe lead span (use tolerance)’

• Minimum heel-to-heel lead span (if not specified directly, can be calculated by subtracting twice the max foot length from the min toe-to-toe lead span)



The following spec is desirable:

• Minimum body width



1. Set the ID (inside distance).

• Determine which of the following is greater:

Min heel-to-heel minus 0.030"

Min body width (if available) minus 0.010"

• Set the ID to whichever is greater, rounded DOWN to the next 0.010"

2. Derive the OD (outside distance), using the standard pad for this pitch.

• Add two standard pad lengths to the ID established in (1). The standard pad for each pitch is:

Pitch Pad Size

1.0mm (approx .0394") 0.025x0.075

0.8mm (approx .0315") 0.018x0.070

0.65mm (approx .0256") 0.015x0.070

0.025" 0.015x0.070

0.5mm (approx 0.0197") 0.012x0.070

3. Check the OD for adequate pad extension

• The OD should be greater than or equal to the max toe-to-toe plus 0.050". This allows for a 0.025" pad extension on each side. If it passes this test, then this OD is the final OD. Use the standard pad size from the table and skip to (5). If it fails this test, go on to (4).

4. If adequate pad extension is not achieved, increase the OD

• If the OD fails the test in (3), then set the OD equal to the max toe-to-toe plus 0.050", rounded UP to the next 0.010".

• Calculate the pad length as (OD-ID)/2. Use the standard pad WIDTH from the table in (2).



7.4.2.4 Chip Components


• Maximum overall component length.

• Minimum termination-to-termination gap (if not specified directly, can be calculated by subtracting twice the max termination thickness from the minimum overall component length).



• Maximum component height.

• Maximum termination height (may be the same as component height).

• Nominal termination width.

May be the component terminal width, such as 0.050" on an 0805 component. On components where the termination is narrower than the body (such as molded tantalum capacitors), use the nominal width of the termination alone. If a nominal is not stated, split the difference between the minimum and maximum width



1. Set the OD using the max component length.

• For components that can be wave or reflow soldered (most components), set the OD, using:

OD = Max component length + 2 * (max termination height, or 0.040", whichever is LESS) + 0.010" [for placement tolerance]. Rounded UP to the next 0.010".

This leaves plenty of room for wave soldering as well as reflow soldering.

• For components that will be reflow soldered only (such as those taller than 0.090"), set the OD, using:

OD = Max component length + 1 * (max termination height, or 0.040", whichever is GREATER) + 0.010" [for placement tolerance]

Rounded UP to the next 0.010.

2. Set the ID, using the min termination-to-termination gap

• ID = Minimum termination-to-termination gap. Rounded DOWN to the next 0.010.

Warning: For parts smaller than 0805, the rounding down to the next 0.010" in the above step may result in a gap that is too small. The formula has not yet been modified to consider these small parts.

3. Determine pad length from OD and ID

• Pad length = (OD-ID)/2

4. Set pad width, using nominal termination width

• If the component has a full width termination, set the pad width equal to the nominal device width, rounded to the nearest 0.005". For example, on 0805, use 0.050"; on 1210, use 0.100".

• If the component has a termination width smaller than the component width, set the pad width equal to the nominal termination width.





7.4.3 Design for Testability

In SMT boards, designing for testability requires that test nodes be accessible to automated test equipment (ATE). This requirement naturally has an impact on board real estate. In addition, the requirement impacts cost, which is dependent upon defects. A lower number of test nodes can be tolerated when defect rates are low, but higher defect occurrence demands adequate diagnostic capability by allowing ATE access to all test nodes.

Most companies use bed-of-nails in-circuit testing for conventional assemblies. Use of SMCs does not impact testability if rules for testability of assemblies are strictly observed. These rules require that (1) 0.050-in. and 0.100-in. test probes are used, (2) solder joints are not probed, and (3) through-hole vias or test pads are used to allow electrical access to each test node during in-circuit testing. If possible, this electrical access should be provided both at top and bottom, with the bottom access being necessary. The main drawback of providing all the required test pads is that the real estate savings offered by SMT are somewhat compromised. To retain these savings requires development of some form of self-test or reliance upon functional tests only. However, self-test requires considerable development effort and implementation time, and functional tests lack the diagnostic capability of in-circuit tests.

Designing for manufacturability, test, and repair are very important for yield improvement and thus cost reduction. The following sections address process issues in the manufacturing of surface mount assemblies that play a critical role even when boards are designed for manufacturability.

7.5 Solder Paste Application

7.5.1 Solder Paste Printing

Solder paste plays an important part in reflow soldering (Type I and Type II SMT). The paste acts as an adhesive before reflow and even may help align skewed parts during soldering. It contains flux, solvent, suspending agent, and solder of the desired composition. Characteristics such as viscosity, dispensing, printing, flux activity, flow, ease of cleaning, and spread are key considerations in selecting a particular paste. Susceptibility of the paste to solder ball formation and wetting characteristics are also important selection criteria.

In most cases, solder paste is applied on the solder pads before component placement by stenciling. Stencils are etched stainless steel or brass sheets. A rubber or metal squeegee blade forces the paste through stencil openings that precisely match the land patterns on the PB. Stencils are essentially the industry standard for applying solder paste. Screens with emulsion masks can be used but stencils provide more crisp and accurate print deposits.

The types of solder paste available fall under three main categories: Rosin Mildly Activated (RMA), water-soluble Organic Acid (OA), and no-clean. Each of these has advantages and disadvantages as listed in the Table 7-1, and choosing one over the others depends on the application and the product type.



7.6 Surface Mount Components and Their Placement

7.6.1 Component Packaging

Most active components are available in surface mount. However, connectors and sockets are still through-hole, often for strength considerations, which will keep us in mix-and-match format for some time to come.

Surface mount components are available in various shipping media The most common is tape and reel. It requires fewer machine reloads allowing more machine run time. Trays are also used, generally for large packages such as QFPs. The EIA specification RS-481A has standardized reel specifications for passive components and active components.

7.6.2 Component Placement

Requirements for accuracy make it necessary to use auto-placement machines for placing surface mount components on the PB. The type of parts to be placed and their volume dictate selection of the appropriate auto-placement machine. There are different types of auto-placement machines available on the market today: (A) in-line, (B) simultaneous, (C) sequential, and (D) sequential/simultaneous.

In-line placement equipment employs a series of fixed-position placement stations. Each station places its respective component as the PB moves down the line. These machines can be very fast by ganging several in sequence. Simultaneous placement equipment places an entire array of components onto the PC board at the same time. Sequential placement equipment typically utilizes a software-controlled X- Y moving table system. Components are individually placed on the PC board in succession. These are currently the most common high speed machines used in the industry. Sequential/simultaneous placement equipment features a software- controlled X-Y moving table system. Components are individually placed on the PC board from multiple heads in succession. Simultaneous firing of heads is possible.

Many models of auto-placement equipment are available in each of the four categories. Selection criteria should consider such issues as the kind of parts are to be handled, whether they come in tube, trays, or tape and reel, and whether the machine can accommodate future changes in other shipping media. Selection and evaluation of tapes from various vendors for compatibility with the selected machine is very important. Off-line programming, teach mode, and edit capability, as

Table 7-1. Comparison of Solder Paste Types

Type Advantages Disadvantages

RMA • Stable Chemistry

• Good properties

• Needs chemical solvent or saponification for cleaning

OA • Cleaned using pure water

• Very good cleanability

• Humidity sensitive, seen as: short shelf and working life, solder ball tendency

• Water leaches lead into waste stream

No-Clean • No cleaning process, equipment, or chemicals

• Eliminates effluent issues

• May leave some visible residue behind



well as CAD/CAM compatibility may be very desirable, especially if a company has already developed a CAD/CAM database. Special features such as vision capability, adhesive application, component testing, board handling, and capability for further expansion may be of interest for many applications. Vision capability is especially helpful in accurate placement of fine- pitch packages. Machine reliability, accuracy of placement, and easy maintenance are important to all users.

7.7 Soldering

Like the selection of auto-placement machines, the type of soldering process required depends upon the type of components to be soldered and whether surface mount and through-hole parts will be combined. For example, if all components are surface mount types, the reflow method will be used. However, for a combination of through-hole and surface mount components, reflow soldering for surface mount components followed by wave soldering for through-hole mount components is optimum.

7.7.1 Infrared/Convective Reflow Soldering

There are basically two types of infrared reflow processes: focused (radiant) and non-focused (convective). Focused IR, also known as Lamp IR, uses quartz lamps that produce radiant energy to heat the product. In non- focused or diffused IR, the heat energy is transferred from heaters by convection. A gradual heating of the assembly is necessary to drive off volatiles from the solder paste. This is accomplished by various top and bottom heating zones that are independently controlled. After an appropriate time in preheat, the assembly is raised to the reflow temperature for soldering and then cooled.

The most widely accepted reflow is now "forced convection" reflow. It is considered more suitable for SMT packages and has become the industry standard. The advantage of forced convection reflow is better heat transfer from hot air that is constantly being replenished in large volume thus supplying more consistent heating. While large mass devices on the PB will heat more slowly than low mass devices, the deltas are small allowing all parts to see nearly the same heat cycle.

7.7.2 Hot Bar Reflow Soldering

The ability to place and reflow high lead count ultra fine pitch components challenges traditional stencil, place and reflow processes at or below 0.4mm lead pitch. This is due to poor solder paste flow characteristics through very small stencil apertures and mechanical alignment difficulties with stencil to the substrate. Pulsed resistance thermode attachment or "hot bar" reflow is an outer lead bonding technique for component lead pitches down to 0.2mm. The package for this process is the Tape Carrier Package (TCP).

Component input into the placement system can be accomplished through many different format types: molded carrier ring, singulated slide carriers, or matrix trays. In this process, no solder paste is used. Only the solder plated on the PB lands form the solder joints. Hence, a PB vendor with tight solder plating control is needed. First, liquid flux is applied to the lands at the mounting site. No-clean "low solids" fluxes that can withstand the higher temperature of the thermodes (approximately 260°C - 300°C) without carbonizing are recommended for this application. An advanced machine vision system is used to perform component lead inspection, board fiducial location and calculate placement location. After component placement, the hot bar blades are brought down to "gang bond" all the leads simultaneously. The blades physically contact the top of the component leads, holding them in place during reflow and cool down. This hold down process results in fewer problems due to coplanarity. Heat is conducted through the leads and into the



solder deposit to form solder fillets. The blades are then allowed to cool to let the solder re-solidify before lifting. Computer control manages the temperature and force profiles for each component type. Different thermal masses make this essential.

With the introduction of Ball Grid Array (BGA) packages, high pin counts can be achieved on larger pitches, typically 1.00mm-1.27mm. So the hot bar process with very tight tolerance requirements is fading in use.

7.8 Cleaning

In general, cleaning of SMT assemblies is harder than that of conventional assemblies because of smaller gaps between surface mount components and the PB surface. The smaller gap can entrap flux, which can cause corrosion, which leads to reliability problems. Thus, the cleaning process depends upon the spacing between component leads, spacing between component and substrate, the source of flux residue, type of flux, and the soldering process. RMA cleaning requires chemicals and has waste affuents to deal with. OA cleaning uses water that must flush down the drain. However in this chemistry, lead is often found in the wastewater and creates an environmental concern. No clean is generally becoming the preferred solder process since it eliminates cleaning all together. This eliminates the environmental issues and saves in capital costs.

One of the key issues in SMT has been to determine the cleanliness of SMT assemblies. The Omega meter is a common tool originally used for DIP boards. For SMT, the industry also uses Surface Insulation Resistance (SIR) surface mount boards. These boards check for ionic contaminates left on the PB by measuring the electrical resistance between adjacent traces or circuits.

7.9 Repair/Rework

Repair and rework of SMT assemblies is easier than that of conventional components. A number of tools are available for removing components, including hot-air machines for removing active surface mount components. As with any rework tool, a key issue in using hot-air machines is preventing thermal damage to the component or adjacent components.

No matter which tool is used, all the controlling desoldering/soldering variables should be studied, including the number of times a component can be removed and replaced, and desoldering temperature and time. It is also helpful to preheat the board assembly to 150°F - 200°F for 15 to 20 minutes before rework to prevent thermal damage such as measling or white spots of the boards, and to avoid pressure on pads during the rework operation. To prevent moisture induced damage, SMT components may require bake-out prior to removal from the board. The guidelines outlined in Chapter 8 should be followed.

7.10 Conclusion

The major technical considerations for implementing SMT include surface mount land pattern design, PB design for manufacturability, solder paste printing, component placement, reflow soldering, wave soldering, cleaning, and repair/rework. These areas must be studied and thoroughly understood to achieve high quality, reliable surface mount products.




• Complete Revision of Chapter


Moisture Sensitivity/Desiccant Packaging/Handling of PSMCs 8

8.1 IntroductionThis chapter examines surface mount assembly processes and establishes preconditioning flows which encompass moisture absorption, thermal stress and chemical environments typical in the variety of surface mount assembly methods currently in use. Also discussed are the standardized moisture sensitivity levels which control the floor life of moisture/reflow sensitive PSMCs along with the handling, packing and shipping requirements necessary to avoid moisture/reflow related failures. Baking to reduce package moisture level and its potential effect on lead finish solderability is described. In addition, drying, shipping, and storage procedures are included.

8.2 Moisture Sensitivity of PSMCsThis section addresses technical issues related to maintaining package integrity during board level assembly processing using Plastic Surface Mount Components (PSMC). Surface mount processing subjects the component body to high temperature and chemicals (from solder fluxes and cleaning fluids) during board mount assembly. In through-hole technology the board assembly process uses wave soldering which primarily heats the component leads. The printed circuit board acts as a barrier to protect the through-hole package body from solder heat and flux exposure.

Note: No component body should ever be immersed directly in the solder during the wave solder operation.

To ensure PSMC package integrity throughout the surface mount process, precautions must be taken by both supplier and user to minimize the effects of reflow solder stress on the component. Plastic molding compounds used for integrated circuit encapsulation are hygroscopic and absorb moisture dependent on time and the storage environment. Absorbed moisture will vaporize during rapid heating in the solder reflow process, generating pressure at various interfaces in the package, which is followed by swelling, delamination and, in some cases, cracking of the plastic as illustrated in Figure 8-1 and Figure 8-2. Cracks can propagate either through the body of the plastic or along the lead frame (delamination). Subsequent high temperature and moisture exposure to the package can induce the transport of ionic contaminants through these openings to the die surface increasing the potential for circuit failure due to corrosion. Components that do not exhibit external cracking can have internal delamination or cracking which impacts yield and reliability.

It should be noted that PSMC moisture sensitivity relates only to the risk associated with direct exposure of components to reflow solder process stresses. No loss of package integrity is expected for socketed parts or for through-hole mounted components not subjected to the solder reflow environment. If through-hole components are exposed to SMT processing, then they can exhibit the same moisture sensitivity as PSMCs. If through-hole devices are exposed to solder reflow processes such as Convection, VPS, or IR, then they should be baked dry first, using the same baking procedures described for SMT packages. Current data indicates that there is no negative long term effects on reliability of PSMCs when package integrity is maintained through surface mount processing.


Moisture Sensitivity/Desiccant Packaging/Handling of PSMCs

The effect of moisture in PSMC packages and the critical moisture content which may result in package damage or failure is a complex function of package design and material property variables. These include: silicon die size, encapsulant thickness, encapsulant yield strength, moisture diffusion properties of the encapsulant, and adhesive strength and thermal expansion properties of the materials used in the package. The PSMC moisture sensitive phenomenon has been identified as a contributor to delamination related package failure mechanisms including bond lifting, wire necking and bond cratering, as well as die surface thin film cracking and other problems. External package cracking is commonly treated as the most visible and severe form of moisture sensitivity. It should be noted that internal cracking/delamination can be present even if there is no evidence of external cracks. Intel has evaluated PSMC moisture sensitivity for its current portfolio. Package moisture level has been measured as a function of temperature and relative humidity. Critical moisture level limits to avoid cracking/delamination and other internal damage have been determined and products susceptible to cracking/delamination have been identified. Intel implemented handling procedures to ensure that these products are delivered to users so that packages will not incur damage that could affect yield or reliability, during user solder reflow processing. The user must take responsibility during storage, board mount assembly and board rework to avoid package overexposure to moisture by following precautions recommended in the following pages. These steps help to ensure that package integrity is maintained throughout the surface mount process.

Figure 8-1. Package Crack Mechanism

A5736-01241187-1

MinimumPlastic Thickness

PlasticEncapsulant

LeadFrame

Moisture AbsorptionDuring Storage Die

Note:Moisture saturates the package to a level determined by storage RH, temperature, time andplastic moisture equilibrium solubility.



Figure 8-2. Package Crack Mechanism (continued)

8.2.1 Surface Mount Assembly ProcessesTraditional insertion (through-hole) assembly technology involves relatively few process steps and minimizes the exposure of components to harsh processing environments. Modern surface mount assembly can be very complex, especially when mixed technologies (surface mount and insertion) are used on the same board. Furthermore, the components are fully immersed in the solder heating media (vapor phase, convection heating or infrared reflow) in surface mount mass reflow processes whereas solder heat during solder dip (or wave solder) is applied only to leads of insertion mount packages. The circuit board shields the package body from the heat of the solder wave. Component exposure in both reflow solder and wave solder process environments is illustrated in Figure 8-3.

A5737-01241187-3

Moisture VaporizationDuring Heating

Note:Vapor Pressure and Plastic Expansion Combine to Exceed Adhesive Strength of Plastic Bond to Lead Frame Die Pad. Plastic Delaminates From Pad and Vapor-Filled Void Expands, Creatinga Characteristic Pressure Dome on the Package Surface.

Crack CollapsedVoid

Crack Generation During Solder

Delamination VoidPressure Dome

Plastic StressFracture

Note:Crack Forms and Pressure Dome Collapses, Emanating From Boundary of Delamination Area at Frame Pad Edge. Remaining Void Area Acts to Concentrate Stresses in Subsequent TemperatureCycling, Leading to Further Crack Propagation.



Figure 8-3. Component Exposure to Wave Solder and Reflow Solder Environments

8.2.2 Solder Reflow ProcessesNumerous solder processes are used in attaching components to boards. These range from manual soldering of individual leads with a soldering iron to high volume mass bonding techniques. The primary production methods are pure convection and infrared/convection reflow soldering (IR). Hot bar and VPS are also used in special circumstances. Pure convection is fast becoming standard as it provides more even heating across the board for a wide range of components than does IR. Current revisions of industry moisture sensitivity classificaton standards specify that convection is the preferred method.

Pure convection reflow processing uses convection heating to provide heat for soldering. Electric heaters heat the atmosphere inside the furnace which then heats the boards traveling on the conveyor. A gradual heating of the printed circuit board is necessary to drive off the volatile constituents of the solder paste and ensures a controlled heating rate. After an appropriate preheat time, the board is raised to the reflow temperature for soldering and then carefully cooled down

Vapor Phase soldering uses the latent heat of vapor condensation to provide heat for soldering. Latent heat is transferred to the component as the vapor of the inert liquid condenses on the component. The VPS temperature reaches its maximum possible value at the fluid boiling point (215° C - 219° C). The maximum heating rate of the component on the board occurs when it is initially immersed in the primary vapor, hence control of the heating rate for any component is limited to preheating the part before immersion in the primary vapor zone. Because of very high ramp rates and the high cost of fluids, VPS is used very little in production environments.

IR solder reflow processing uses radiant heating to provide heat for soldering. IR panels heat the board traveling on the conveyor from top and/or bottom.

Hot Bar (Thermode): This is a relatively new process that is ideal for smaller to midsize volumes of SMDs. The component's leads are held in direct contact to a heated clamp or holding device that presses the component into the solder paste and heats the leads to the reflow temperature. The advantage is that the plastic body does not experience the temperature extremes of a full reflow process. This is useful for heat-sensitive components or low volume production that does not warrant the purchase of production machinery and moisture sensitive storage equipment. (See Chapter 9).

A5738-01241187-4

140 C 220 C

220 C Solder ReflowTemperatures

260 C Solder Wave

Through-Hole40 C

SMD220 C˚

˚

˚

˚

˚

˚



8.2.3 Thermal Shock on ComponentsRapid heating and cooling rates also cause thermal shock. Surface temperature, being higher than the internal body temperatures during heating, results in a temperature differential which generates thermo-mechanical stress. The degree of thermal shock on components is higher in VPS than in IR or convection. The IR soldering profile is usually designed to heat the components at a rate of 2° C - 6° C per second while convection profiles usually heat the components at a rate of <2° C per second. Only limited control can be exerted on the heating rate of components and boards in VPS. The maximum heating rate during VPS is typically much higher (up to 25° C/second). Such high rates of temperature increase can damage components because of the differences in thermal coefficient of expansion (TCE) mismatch between materials. This problem is exacerbated when components have been allowed to become moisture saturated.

Note: No component body should ever be immersed directly in solder during the wave solder operation.

Intel has determined guidelines for mass reflow soldering and post solder reflow component rework which (see Chapter 9) when followed, minimizes thermal shock to packages and meets users' solder reflow requirements.

8.2.4 Solder FluxesFlux used in solder paste or in board pretinning processes is a major source of ionic contamination which can corrode IC chip metallization if transported to the chip surface. Those fluxes containing hydrochloric acid or other halogen compounds should be avoided. (Intel's processes are completely halide free.) Use cleaning methods which ensure complete removal of all flux residues. Avoid highly active fluxes such as organic acid (OA) types. Use RMA or lower activity fluxes whenever possible.

Because of the drive to eliminate CFC-containing materials in solder flux removal, alternative cleaning methods have been under development. Terpene based materials have not shown to cause any long term effects with PSMC components. A relatively recent development is the no-clean or low clean fluxes. These require virtually no cleaning other than a water rinse following SMT reflow.

8.3 Ultrasonic Cleaning of I.C. ComponentsVarious equipment companies are promoting the use of ultrasonic cleaning equipment to remove flux and other residues from finished boards. When cleaning plastic components using the ultrasonic cleaning method, refer to the criteria in Table 8-1.

With Ceramic or Hermetic packages (that have an internal cavity) higher power ultrasonic equipment has been shown to cause damage to the internal bond wires and solder joints when exposed to long cleaning times. Most of these problems have been overcome with the use of the lower power equipment. Each component's user must evaluate their application in light of the criteria in Table 8-1 to determine any reliability jeopardy to the boards.



8.3.1 Solderability

Intel currently supplies PSMCs with copper lead frames and solder plated (tin/lead) finished leads. A potential for lead finish solderability degradation can occur due to formation of Copper/Tin intermetallics. To meet users' solderability requirements the formation of intermetallics must be minimized. Intel has performed evaluations to determine solderability degradation of PSMC after burn-in and baking, which is necessary to drive out package moisture prior to sealing sensitive products in moisture barrier bags (MBBs). Based on the solderability work done at Intel it is recommended that PSMCs with copper lead frames be baked at high temperature (125°C) for no more than 48 hours by the user. Intel monitors outgoing solderability to ensure that product meets user's solderability requirements.

8.3.2 ConclusionComponent susceptibility to moisture damage can manifest itself in many ways. Some of these can be package cracking, bond lifts, die surface thin film cracking, bond cratering or delamination of internal interfaces. Package cracking is one of the most severe forms of moisture sensitivity. Package cracking has been correlated to be a function of die and package geometry and is aggravated by moisture absorption in the plastic encapsulant. Moisture damage to crack-susceptible components can be minimized through users’ processes if absorbed moisture is kept below critical levels and surface mount process thermal limits are observed. Maximum temperature profiles are recommended for these solder processes to minimize crack jeopardy due to thermal stresses. Moisture absorption and desorption characteristics of these sensitive packages have been characterized and moisture exposures sufficient to induce moisture damage have been determined. Intel bakes level 2a through level 6 PSMC packages dry and seals them in bags with desiccant before shipping*. Level 2 PSMC packages are not required to be baked prior to dry pack. Recommended shelf life, storage conditions, floor life, maximum reflow temperatures, redrying and handling procedures are described on the bag and in this Packaging Databook. The user must limit exposure of moisture sensitive components to environmental moisture during SMT assembly and rework processing to keep absorbed moisture below recommended limits and ensure package integrity is maintained throughout the assembly process.

8.4 Guidelines For Handling Units in Desiccant PackIntel ships moisture sensitive PSMCs in a dry state inside moisture barrier bags (MBBs)**. The following information describes the appearance and handling of components shipped in desiccant packing and the materials involved. The handling information applies only to those devices subjected to SMT processes. Handling information covers dry component storage life, manufacturing floor life (of exposed components), rebagging information and guidelines for rebaking units if necessary. Additional information/requirements can be found in IPC/JEDEC J-STD-033 "STANDARD FOR HANDLING, PACKING, SHIPPING AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE MOUNT DEVICES."

Table 8-1. Ultrasonic Cleaning

Power of Ultrasonic Cleaner < 30 Watts per Liter

Ultrasonic Range 39 KHz to 66 KHz

Cleaning Time 3 Minutes per Cycle for 5 Cycles Not to Exceed a Total of 15 Minutes

* 32-lead and 40-lead TSOP packages are not shipped bake and bag.** 32-lead and 40-lead TSOP packages are the only exceptions to this practice.



8.4.1 Packing MaterialsMoisture sensitive PSMCs packed in tubes, tape and reel or trays are shipped in desiccant packing. Each shipping medium contains units that have been baked as required and are enclosed in sealed Moisture Barrier Bags (MBBs) with desiccant pouches.

• Shipping Box. The label on the shipping box indicates that desiccant packed material is included (see Figure 8-4). This label indicates the seal date of the enclosed MBB and, thereby, the remaining shelf life. Quantities of units shipped per box also differs to accommodate the additional packing materials for shipments in tubes.

Figure 8-4. Example of a Barcode Label

• Moisture Barrier Bag (MBB). Inside the shipping box is a MBB containing components. The bag is strong, ESD-safe, and allows minimal moisture transmission. It is sealed at the factory and should be handled carefully to avoid puncturing or tearing of the materials. A Caution Label (Figure 8-5) and a Barcode label on the bag outlines precautions that should be taken with desiccant packed units.This bag protects the enclosed devices from moisture exposure and should not be opened until the devices are ready to be board mounted. Section 8.5, Supporting Technical Information in this document provides information on the technical aspects of the bag and characterization information.

• Desiccant. Each MBB contains pouches of desiccant to absorb moisture that may be present in the bag. The Humidity Indicator card (Figure 8-6) should be used as the primary method to determine whether the enclosed parts have absorbed excessive moisture.Do not bake or reuse the desiccant once it is removed from the MBB.

• Humidity Indicator Card (HIC). Along with the desiccant pouches, the MBB contains a humidity indicator card (HIC). This card is a moisture indicator and is included to show the user the approximate relative humidity level within the bag. A representation of the HIC is shown in Figure 8-6. If the 20% dot on the card is pink and the 30% dot is not blue, then the components have been exposed to moisture beyond the recommended limits for use in an SMT process. If this should happen, then to use these units safely in a surface mount application, the units should be baked dry (see Section 8.5.2 Rebaking of PSMCs). New cards being phased in will indicate that rebake is needed if the humidity has exceeded 10%. The HIC is reversible and can be reused. Recommendations to avoid expiration of the HIC and the need to rebake units are included in Section 8.4.3.

A5739-01241187-51

(1B) BOX ID: AA0009 50(P) CUST PROD:

(V) SUPPLIER:

LEVEL HOURS(1P) IPN:

(S) SPEC:

(1T) LOT:

(1T) LOT:

(Q) QTY

(Q) QTY

(9D) DATE

(9D) DATE

(R) ROM CODE:R

BAG SEAL DATE 23JAN95

AS

SE

MB

LED

IN M

ALA

YS

IA



• Labels. Labels relevant to this process are the “Barcode label”, “Caution label” and “ID label” mentioned in the section on MBBs. The Barcode label (Figure 8-4) contains the date that the bag was sealed (MM/DD/YY), the IPC/JEDEC J-STD-020 Moisture Sensitivity level and the maximum floor life is attached to the outside of the box and on the MBB itself. The remaining storage life of the units in the bag is determined from the seal date. All components are guaranteed 12 months of shelf life starting from the seal date on this label. See Section 8.4.3.The Caution label (Figure 8-5) is attached to the outside of the MBB and outlines precautions that must be taken when handling desiccant packed units if they are to be kept dry. The ID label is placed on the same end of the container as the barcode label.

Note: Starting in 2000 Barcode and Caution Labels that indicate the maximum reflow temperature allowed will be phased in.



Figure 8-5. Example of ID and Caution Labels

A5740-02

CAUTION

MO

IS

TURE SENSITIV

E

Note: Level and body temperature defined by IPC/JEDEC J-STD-020

LEVEL

If blank see adjacentbar code label

CAUTIONThis bag Contains

MOISTURE-SENSITIVE DEVICES

A. ID Label

B. (MBB) Caution Label

1. Calculated shelf life in sealed bag: 12 months at <40˚C and <90% relative humidity (RH).

2. Peak package body temperature: ________________________˚C

5. If baking is required, devices may be baked for 48 hrs at 125 ± 5˚ C

Bag Seal Date: _____________________________________________

Note: If device containers cannot be subjected to high temperature or shorter bake times are desired, reference IPC/JEDEC J-STD-033 for bake procedure.

3. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must be

a) Mounted within ________________________ hrs. of factory conditions

<30˚ C/60% RH, or

b) Stored at <10% RH.

(If blank, see adjacent bar code label)



4. Devices require bake, before mounting, if:

a) Humidity Indicator Card is >10% when read at 23 ± 5˚ Cb) 3a or 3b not met



Figure 8-6. Example of a Humidity Indicator Card

8.4.2 Packing of Shipments

• Tubes. Units shipped in tubes are packed with an additional precaution. Antistatic foam protects the bag from the sharp edges of the tubes and tacks. Otherwise, the units shipped in tubes are packed with materials as indicated in Figure 8-7 through Figure 8-11.

• Trays. Units shipped in injection-molded trays are packed with additional precaution. Antistatic foam lids enclose the trays to protect the bag from the sharp edges of the trays. Trays are packed with materials as indicated in Figure 8-12 through Figure 8-14. (See “Tray Recycle Program” in Chapter 10.)

• Tape and Reel. Units shipped in tape and reel are packed as indicated in Figure 8-15 through Figure 8-17.

Figure 8-7. Bag Packing for PLCC Full or Half Length Tubes

A5741-01241187-6

Humidity Indicator

ExamineItem

if Pink

ChangeDesiccant

if Pink

30

20

Warningif Pink 10

Discard if circles overrunavoid metal contact

A5742-01241187-7

FoamCavity

DesiccantPouches

HumidityIndicator

Card



Figure 8-8. Box Packing for PLCC Tubes

Figure 8-9. Bag Packing for PQFP Tubes

A5743-01241187-29

Fold Flaps Over

Bubble Wrap

Jedec Tray Box

A5744-01241187-9

DesiccantPouches

Humidity Indicator

Desiccant Bag

Foam End Cap



Figure 8-10. Box Packing for PQFP Tubes

Figure 8-11. Placement of Label on Shipping Box

Figure 8-12. Bag Packing for JEDEC Trays

A5745-01241187-10

ABCDEF ABCDEF

Top PortionFolded Under

End Pads

A5746-01241187-11

#3 Box(Front Flap)

#3 Box DesiccantBar Code Label

A5747-01241187-12

Foam Lid

Pin 1 CornerChamfer

Desiccant Pouches

HumidityIndicator

CardDesiccant Bag



Figure 8-13. F Box Packing for JEDEC Trays

Figure 8-14. Placement of Label on JEDEC Tray Box

A5748-01241187-13

Top PortionFolded Under

JEDEC Tray Box

To Box

A5749-01241187-14

JEDEC Tray Box(Front Flap)

#3 Box DesiccantBar Code Label



Figure 8-15. Bag Packing for Tape and Reel

Figure 8-16. Box Packing for Tape and Reel

A5750-01241187-15

ReelHumidity Indicator

Card

Desiccant Pouches

Desiccant Bag

A5751-01241187-16

Tape & Reel"Pizza" Box

(With Bubble Wrapand End Foams)

CornersFoldedUnder

ABCDEF

ABCDEF



Figure 8-17. Placement of Desiccant Included Label on Tape and Reel Box

8.4.3 HandlingThe following information details handling procedures that should be used with PSMCs packed in desiccant bags and intended for surface mount applications. Following these handling guidelines will ensure that components maintain their as-shipped, dry state alleviating package cracking and other moisture-related, stress-induced concerns that may be associated with the surface mount process.

1. Incoming Inspection. Upon receipt, shipments should be inspected for a seal date within the last six months. Bag integrity should also be verified. There should not be holes, gouges, tears, or punctures of any kind that expose either the contents or an inner layer of the bag. The barcode label can be reviewed for conformance to the purchase order, but the bag should not be opened until the contents are ready to be used (either inspected or board-mounted). Please see the following Manufacturing Conditions/Floor Life section for details of allowable exposure times once the devices are removed from the bag or exposed to the ambient.

2. Storage Conditions/Shelf Life. The customer receives components in the sealed MBB between 0 and 6 months after the seal date indicated on the Desiccant Barcode label. The sealed bag and enclosed desiccant have been designed to provide a minimum of 12 months of storage (Intel storage time + customer storage time) from the seal date in an environment as extreme as 40° C and 90% relative humidity. The customer will have at least six months of shelf life available on the components without the need to rebake them before use.If the worst-case storage conditions (time, temperature, or relative humidity) are exceeded and there is a need to verify whether inventory has been affected, then a bag can be opened and the HIC can be checked for expiration. If the HIC has not expired, then new desiccant can be added and the bag resealed. If the HIC has expired, then the devices should be 1) rebaked and used in manufacturing within the guidelines outlined in the Rebaking section, 2) rebaked and resealed in an MBB with fresh desiccant, or 3) rebaked and stored in an environment of ≤ 10%RH before they are used in a surface mount process. Please see Rebaking section for additional information.

3. Opening MBBs. To open a moisture barrier bag when the contents are ready to be used or inspected, simply cut across the top of the bag as close to the seal as possible, being careful not to damage the enclosed materials. By cutting close to the seal, you will allow as much room as possible for resealing. Once the bag has been opened, please follow the guidelines for ambient exposure time in the following section to ensure that the devices are maintained below the critical moisture level.

A5752-01241187-17

Tape & Reel Box(Front Flap)

ABCDEF

Reel Box DesiccantBar Code Label



4. Manufacturing Conditions/Floor Life. Intel is classifying surface mount components into levels of moisture sensitivity. Table 8-2 lists the 8 IPC levels of moisture sensitivity. Note that all levels are based on exposure time and environment. The latest information in the literature and from Intel studies indicates that percent weight gain moisture content is not useful other than for evaluation. Different package types/die attach area/lead count combinations will have different levels of absorbed moisture at which floor life limitations are exceeded. Therefore, Intel recommends that units be classified by allowable exposure times. The labels on the Moisture Barrier Bag lists the Moisture Sensitivity Level and the allowable floor life. See Figure 8-3.Once the barrier bag has been opened, Intel recommends that components be surface mounted and reflowed within the time indicated on the Moisture Barrier Bag label. This time is based on a manufacturing environment not more extreme than 30° C/60%RH and a maximum component body temperature during solder reflow of 220° C. If the component can not be mounted within this timeframe, then they should be put into a dry storage environment immediately, or sealed into a MBB with fresh desiccant as soon as possible. In either case, the remaining allowable ambient exposure time must be reduced by the time the units are out of the MBB or dry storage environment.

If the actual MET is less than 24 hours the soak time may be reduced. For soak conditions of 30 °C/60% RH the soak time is reduced by 1 hour for each hour the MET is less than 24 hours. For soak conditions of 60 °C/60% RH, the soak time is reduced by 1 hour for each 5 hours the MET is less than 24 hours.If the actual MET is greater than 24 hours the soak time must be increased. If soak conditions are 30 °C/60% RH, the soak time is increased 1 hour. for each hour that the actual MET exceeds 24 hours. If soak conditions are 60 °C/60% RH, the soak time is increased 1 hour for each 5 hours that the actual MET exceeds 24 hours.Please contact your local Intel Sales office for specific handling questions. All of the same restrictions for exposure time (outlined above) apply. Reference IPC/JEDEC J-STD-020 “MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NON-HERMETIC SOLID STATE FURFACE MOUNT DEVICES” and IPC/JEDEC J-STD-033 "STANDARD FOR HANDLING, PACKING, SHIPPING AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE MOUNT DEVICES".

Table 8-2. Sensitivity Classification Levels for SMCs

Level Floor LifeSoak Requirements

Standard Accelerated Equivalent

Time Conditions Time (Hours) Conditions Time

(Hours) Conditions

1 Unlimited ≤30 °C/85% RH 168 85 °C/85% RH

2 1 year ≤30 °C/60% RH 168 85 °C/60% RH

2a 4 weeks ≤30 °C/60% RH 6962 30 °C/60% RH 120 60 °C/60% RH

3 168 hours ≤30 °C/60% RH 1922 30 °C/60% RH 40 60 °C/60% RH

4 72 hours ≤30 °C/60% RH 962 30 °C/60% RH 20 60 °C/60% RH

5 48 hours ≤30 °C/60% RH 722 30 °C/60% RH 15 60 °C/60% RH

5a 24 hours ≤30 °C/60% RH 482 30 °C/60% RH 10 60 °C/60% RH

6 Time on Label (TOL)

≤30 °C/60% RH TOL 30 °C/60% RH

NOTES: 1. MET = Manufacturer's Exposure Time: The compensation factor which accounts for the time after bake that the compo-

nent manufacturer requires to process the components prior to bag seal, and including a factor for distribution handling.2. Standard soak time, which includes a default value for semiconductor Manufacturer's Exposure Time (MET) between

bake and bag plus the maximum time allowed out of the bag at the distributor's facility, of 24 hours.



Where exposure times and/or ambient conditions are difficult to control, Intel highly recommends dry storage capability.

5. In-Process Storage. Intel highly recommends having dry storage capability available for units that will not be used within the allowable exposure time. PLCCs and PQFPs (≤100 leads) can be stored outside of the barrier bag for long periods of time if the ambient relative humidity is less than 10%. This applies to both long term and in-process storage. A desiccator with dry nitrogen or air (≤5%RH source) is suggested for such storage. Desiccator storage conditions for larger PSMCs are currently being established.

6. Rebaking. PSMCs should be rebaked if and only if they have been exposed to excessive moisture as indicated by exceeding the recommended ambient exposure time or by expiration of the HIC.In the event that the units should be rebaked, see Section 8.5.2.

7. Resealing Moisture Barrier Bags. If there is a need to reseal Moisture Barrier Bags for any reason, then Intel recommends the following guidelines to ensure that the bag seal does not allow moisture into the bag. The seal area must not exhibit any separation when subject to load and temperature conditions specified in MIL-B-81705, and must be impermeable to moisture according to MIL-B-81705. Intel uses a seal pressure to 60 psi–70 psi, and a seal time of 3-4 seconds at approximately 225 °C. The integrity of the seal is vital to the storage life of the devices.

Intel ships moisture sensitive PSMCs which have been packed following a tightly controlled process. This flow is shown in Figure 8-18.

Figure 8-18. PSMC Packaging and Bagging Flow Chart

A5753-01241187-18

Text

Mark

Bake

PackageVisual

View Check

FQAVisual

Reject

Scrap

Rework

Desi. PackSeal

Ship Out



8.5 Supporting Technical InformationThe phenomenon of moisture induced plastic package cracking and internal delamination during high temperature reflow soldering for surface mount has been discussed by several investigators, including Intel. Moisture absorbed to a concentration dependent on the storage environment, can vaporize during the rapid heating of the solder reflow process and generate pressure at internal interfaces in the package. This, along with the stress of thermal expansion mismatches between the leadframe, silicon die and encapsulant, can affect yield and in the more extreme case visible cracking of the plastic will occur. Subsequent exposure to moisture can drive ionic contaminants through these cracks/delaminations to the die surface increasing the potential for device failure due to corrosion.

Once the cracking jeopardy of surface mounted PSMCs was identified, Intel characterized component absorption/desorption rates and saturation limits as a function of temperature and relative humidity. The handling and shelf life guidelines outlined in the first section of this document are based upon the experimental analysis of the desiccant pack materials. The water vapor transmission rate of the moisture barrier bag (MBB), desiccant absorption rate and saturation levels, and maintainable MBB internal relative humidity were all important factors in developing the recommendations given.

Manufacturers using PSMCs in non-SMT applications may continue to use PSMCs without altering their current process flow. Non-surface mounted PSMCs do not undergo the same temperature excursions and thermal stresses associated with the Convection, VPS or IR solder reflow processes and, therefore, do not have the same jeopardy related to them as unprotected PSMCs used in SMT applications.

8.5.1 Characterization Data• Desiccant Packing (General). When components are stored in MBBs with the appropriate

amount of desiccant, it takes much longer for packages to gain the critical moisture content. After 526 hours at 65° C/60% RH, 68-lead PSMC stored in desiccant pack had absorbed 0.008% moisture. The relative humidity inside the bag during this time was < 10% RH as measured by the humidity indicator card. The outside storage ambient has relatively little impact on the PSMC moisture absorption within the desiccant packing. The respective percent weight gains of bagged components stored at 40° C/25% RH, 40° C/85% RH, and 65° C/60% RH were found to be statistically indistinguishable even after 526 hours of continuous storage. Therefore, the moisture is being absorbed preferentially by the desiccant and the PSMCs see an effective environment of ≤10% RH.

• Moisture Barrier Bag (MBB). The opaque MBB is made of Tyvek and meets MIL-STD-81705 Type I for ESD, RFI, EMI and mechanical stability. The measured water vapor transmission rate (WVTR) of the bag meets the requirements specified in IPC/JEDEC J-STD-033 and surpasses the MIL-STD requirements for moisture protection.

• Desiccant. Intel is using molecular sieve desiccant for products requiring desiccant packaging. Desiccant moisture absorption rates at 25° C/28% RH as a function of desiccant type are shown in Figure 8-19. Desiccant capacity versus relative humidity is shown in Figure 8-20. The desiccant is supplied in 1 unit pouches. The amount of desiccant per MBB is a function of the bag surface area and water vapor transmission rate.



Figure 8-19. Absorption Rate 25° C/28%RH

Figure 8-20. Moisture Capacity Versus Relative Humidity

• Amount of Desiccant. The desiccant is supplied in a 1 unit pouch. A UNIT of desiccant is defined as the amount that will absorb a minimum of 2.85 g of water vapor at 20% RH and 25 °C. To meet the dry pack requirements of J-STD-033 the amount of water vapor that a UNIT of desiccant can absorb at 10% RH and 25 °C must be known.

The number of UNITS required per bag may be determined by the following equation:

A5757-01241187-22

41 2 3

1.0

0.9

0.8

0.7

0.6

0.5

0.3

0.2

0.1

0.4

Time (hrs)

Silica Gel

Calcium Chloride

Clsy

Calcium Sulfate

Molecular Sieve

Phosphorus Pentoxide

Ads

orbe

d M

oist

ure

(Gra

ms)

A5758-01241187-23

10040201010.1024

68

10

1214

16

1820

22

Per

cent

Moi

stur

e C

apac

ity

Percent Relative Humidity

Silica Gel

Molecular Sieves



Equation 8-1.

Where:U = Amount of desiccant in UNITSM = Shelf life desired in months WVTR = Water vapor transmission rate in grams/100 in2 in 24 hrsA = Total surface area of the MBB in square inchesD = The amount of water in grams, that a UNIT of desiccant will absorb at 10% RH

Note: If materials such as trays, tubes, reels, etc., are placed in the bag without baking, additional desiccant will be required to absorb the moisture contained in these materials.

• Shelf Life. Intel has determined the shelf life of bagged components based upon the bag WVTR, the desiccant absorption rate, and the desiccant saturation limit. The total shelf life (Intel + customer) for bagged components in worst case warehouse conditions of 40 °C/90% RH is 12 months.

8.5.2 Rebaking of PSMCsIf the component floor life has been exceeded or the HIC indicates that the contents of the MBB have expired, then the components can be baked to desorb moisture. Two bake temperature profiles are recommended, High and Low temperature. The higher temperature bake is 125 °C. This requires that components not shipped in high temperature trays be removed from plastic shipping tubes, low temperature trays or tape and reel and placed in metal or high temperature plastic containers. Components should be handled carefully to avoid lead coplanarity problems or any other type of damage. The low temperature bake is 40 °C. It allows component moisture desorption in the original plastic shipping containers and, thereby, avoids possible damage to component leads that might be introduced through additional handling. After baking, the units may be exposed to an environment no more extreme than 30 °C/60% RH for a maximum of the time specified on the label. Component drying options for various moisture sensitivity levels and ambient humidity exposures of ≤ 60% RH are given in Table 8-3. Drying per an allowable option resets the floor life clock. If dryed and seaaled in an MBB with fresh desiccant, the shelf life is reset.

U 0.304xMxWVTRxA( )D

-----------------------------------------------------=

Table 8-3. Reference Conditions for Drying Components

Package Thickness Level Bake @ 125 °C Bake @ 40 °C ≤ 5% RH

≤ 1.4 mm 2a345

5a

4 h.7h.9 h.10 h.14 h.

5 days11days13 days14 days19 days

≤ 2.0 mm 2a345

5a

18 h.24 h.31 h.37 h.48 h.

67 days67 days68 days68 days68 days



It is not advisable to store PSMC units at the low bake temperature longer than the time required to dry out the units for use in the reflow. Lengthy storage times at elevated temperatures can lead to problems with intermetallic formation between the lead frame material and the lead finish, increased oxidation of the lead finish which can contribute to added reflow and wetting problems, and extended elevated temperatures can cause the antistatic properties of the shipping media (tubes/tape and reel) to deteriorate.

• Solderability Considerations/Number of Rebakes. Solderability tests performed on PSMCs exposed to either bake cycle are the basis for Intel's recommendations and limits on the number of allowable bake cycles. PSMCs should not be baked more than 48 hours by the customer if using the high temperature bake of 125 °C for 48 hours. Following this guideline will limit the formation of Cu6Sn5 intermetallic and therefore, not promote solderability degradation. The low temperature bake of 40 °C does not require this restriction.

Note: Solderability work done on solder dipped (not plated) PLCCs.

• Because components are baked in the shipping containers at 40 °C, possible outgassing products as well as intermetallic formation impact on solderability were evaluated. Figure 8-21 is a "box plot" analysis of solderability measured by coverage of the leads in "number of squares". There is overlap in the distributions of, 1) the control units stored in metal trays, 2) units stored in plastic shipping containers and, 3) units baked in plastic shipping containers, therefore, there is no statistical difference between the treatments. No difference in solderability was observed after multiple rebakes at low temperature. Based on this data, there is no restriction on the number of times devices can be rebaked at the recommended low temperature before solderability is degraded beyond acceptable limits.

≤ 4.0 mm 2a3455a

48 h.48 h.48 h.48 h.48 h.

67 days67 days68 days68 days68 days

Table 8-3. Reference Conditions for Drying Components



Figure 8-21. Solder Coverage versus Temperature

8.6 Evaluation of PSMC Devices for Moisture Sensitivity/ Package CrackingThe problem of moisture stress sensitivity and package cracking during surface mount is not unique to any one computer design or manufacturer. A method is needed for evaluating the moisture sensitivity of devices supplied by different manufacturers. The method that Intel has developed to determine whether a package/die combination is “moisture sensitive” with respect to package cracking follows. Uniform application of this methodology is one way to evaluate devices from different vendors to determine which devices, if allowed to absorb moisture, have a high probability of cracking during surface mount procedures. Also included is a method which can be used to assess device failure rates in surface mount applications. This can also be useful for comparison purposes and can comprehend failure rates due to any kind of surface mount induced, stress-related failure. This method is commensurate with IPC/JEDEC J-STD-020.

8.7 PSMC Package CrackingIntel has evaluated PLCC packages for susceptibility to cracking during solder reflow processing by subjecting samples to preconditioning stresses which include moisture saturation in 85% RH/85 °C for 168 hours, and solder reflow environment exposure. Package saturation in 85% RH was chosen to simulate worst case storage humidity in customers' warehouses, and 85 °C is used to accelerate the moisture diffusion rate into the package. Cross sectional analysis of the package as shown in Figure 8-23, followed by optical inspection at 30X magnification was used to determine existence of package cracks. Cracking was found to emanate from the die attach pad edges and propagate either to the outside of the package or to bonding fingers of the lead frame. The results of

A5759-01241187-25

AControl

B22

Degrees

C40

Degrees

0

3

6

9

15

18

12

Treatment

Cov

erag

e in

No.

of S

QS



this evaluation are described in Figure 8-22 and show that package crack susceptibility for PLCCs is dependent on the die attach pad dimensions and the thickness of plastic between die attach pad and nearest external surface.

Figure 8-22. Crack Sensitive Packages: Package Die Attach Pad Area versus Package Minimum Plastic Thickness

8.7.1 Method for Evaluating Devices for Moisture SensitivityOne package or product cannot be used to categorize a vendor's entire portfolio as to its moisture sensitivity. Moisture sensitivity can manifest itself in many ways, including but not limited to: bond lifts on either the die surface or die paddle, wire heal cracks, die surface thin film cracking, bond cratering, and delamination. Package design, die layout, die topography and size, and materials used in the package contribute to the overall package moisture sensitivity. Since package cracking is the severest form of moisture sensitivity, evaluation of a package for its cracking sensitivity may not uncover other moisture concerns. Package cracking sensitivity has been found to be a function of die paddle area (the area of the lead frame where the die is attached) and minimum package plastic thickness (see Figure 8-22). Each product must be evaluated individually to determine its moisture sensitivity.

1. Bake 10 units of each product for 48 hours at 125 °C to dry out any absorbed moisture (preferably 5 units from each of 2 date codes).

2. Use acoustic microscopy to detect initial internal delamination and cracking. Record images and analyst's observations. If these parts do not meet the acceptability criteria listed below, then contact the vendor.

3. Saturate the units by soaking them in an unbiased Temperature/Humidity chamber for time and temperature/humidity combinations required for the level of moisture sensitivity being evaluated (see Table 8-2).

Use 85 °C/85% RH to simulate behavior under uncontrolled storage conditions.

A5761-01241187-26

.16.12.08.040

10

20

30

40

50

60

70

80

Safe

Crack Sensitive

Die Attach Pad Area (Inches )2

Pla

stic

Pac

kage

Min

imum

Pla

stic

Thi

ckne

ss (

Mils

)



Use 85 °C/60% RH or 30 °C/60% RH according to manufacturers recommendations, to simulate behavior of "dry" units shipped in desiccant pack or units baked prior to surface mount and then exposed to the ambient for the maximum allowable exposure time.

Note: Devices which exhibit package cracking after saturation at 85 °C/85% RH have an increased probability of cracking during the SMT process if they are surface mounted after storage under uncontrolled conditions. Such devices should be treated as moisture sensitive and only used in a dry state for SMT applications. This dry state can be achieved either by baking the units prior to surface mount or by receiving dry devices in desiccant pack from the vendor (as Intel currently provides).

4. Run the units through three passes of vapor phase solder or convection reflow (infrared reflow should not be used unless equivalence with VPS has been demonstrated) within 2 hours of removal from the Temperature/Humidity chamber.

5. Use acoustic microscopy to detect post-reflow internal delamination and cracking. Record images and analyst's observations. If these parts do not meet the acceptability criteria listed in Section 8.7.2, then they fail the tested level.

8.7.2 CriteriaThe general criteria defining moisture sensitivity are applied in a hierarchical manner.

1. If the components pass electrical test, there is no visual evidence of external cracks, and there is no evidence of delamination or cracks observed by acoustic microscopy, then the component is considered to pass that level of moisture sensitivity.

2. If the components pass electrical test and there is backside paddle or heatspreader delamination, but there is no evidence of cracking or other delamination, then the component is considered to pass that level of Moisture Sensitivity.

3. If internal cracks are observed by acoustic microscopy, then components will be cross-sectioned and the cracks evaluated according to the following criteria.

— Cracks are not allowed to intersect the bond wire, ball bond, or wedge bond.

— Cracks are not allowed to extend from any lead finger to any other internal feature (lead finger, chip, die attach paddle).

— Cracks are not allowed to extend more than two-thirds (2/3) of the distance from any internal feature to the outside of the package.

— Failing components must be evaluated to the next level of moisture sensitivity. Components with internal cracking that do not fail this criteria should be subjected to temperature cycle, and tested to full function electrical end points.

— If acoustic microscopy shows any surface-breaking feature which is delaminated over its entire length, the component must be tested to the next level of moisture sensitivity. A surface-breaking feature includes: lead fingers, tie bars, heatspreader alignment features, heat slugs, etc.

4. If acoustic microscopy scans exhibit any delamination which meets the following criteria, then the components will require further evaluation using Environmental stresses.

— Measurable change in delamination on the top surface of the chip.

— Measurable change in delamination on any wire bonding surface of the leadframe/die paddle.

— Measurable change in delamination along any polymeric film bridging any metallic features which are designed to be isolated.



— Any surface-breaking feature delaminated over its entire length. A surface-breaking feature includes: lead fingers, tie bars, heatspreader alignment features, heat slugs, etc.

The method outlined here indicates whether or not a device is susceptible to internal delamination or package cracking. To evaluate surface mount related failure rates over time, it is necessary to stress the units. The following section (Section 8.7.3) describes a method using temperature cycling and THB (temperature/humidity, biased) stressing to evaluate failure rates due to any kind of surface mount-related, stress-induced failure.

Figure 8-23. Package Crack Analysis Cross Sectioning Locations

8.7.3 Method for Evaluating Device Failure Rates

• Determination of failure rates and resulting comparisons should only be made after analysis of failures has been completed. Invalid failures may result and should not be used in the final failure rate assessment.

• Precondition 154 units per lot from three different lots of the same product (462 units total). This flow simulates the conditions and chemical exposures a device typically sees during board mount and rework as indicated. The component vendor should be contacted to determine the preconditioning flow and parameters appropriate for the component under evaluation.

• A reduced sample size of 90 units per lot (270) total can also be used. Sample sizes given are based on LTPD charts given in MIL-STD 38510.

• Please note that the preconditioning mentioned below is determined by the level of moisture sensitivity of the specific component.

A5762-01241187-27

Cross SectionLocations

Die Attach Pad



• Following pre-conditioning, divide each of the three lots in half and subject them to the following stresses:

• All read-outs are electrical read-outs.

• All failures should be analyzed before device failure rates are evaluated.

THB and Temp Cycle failure rates are not easily correlated to field failure rates unlike failures which occur during high temperature life testing (burn-in). However, failures which occur during THB and Temp Cycle stressing can indicate a potential problem and should be discussed with the vendor.

8.7.4 PreconditioningThe purpose of a preconditioning step in the qualification and reliability stressing flow is to simulate the actual board mounting process that the parts will see at the customer's site. By completing this stress on the units before the reliability data is gathered, the data more accurately reflects the life expectancy the units will experience in the field or customer's application.

To ensure that SMT process stressing is comprehended in component reliability evaluations, Intel has established product qualification precondition flows to which all surface mountable plastic products are subjected prior to standard component reliability stressing*. The effect of these preconditioning stresses and their impact on long term package performance continues to be quantified. User assembly processes not comprehended by this preconditioning flow should be discussed with Intel engineers to verify that package integrity of Intel PSMCs are maintained in the specific application.

8.8 Handling of Plastic Surface Mount Components (PSMCs)Maintaining the position integrity of leads on PSMC packages is a challenge. Basic precautions should be observed when handling PSMCs (such as PQFPs, QFPs, TSOPs, etc.).

THB (85° C/85% RH, Biased) Temp Cycle MIL STD Condition "B"

3 lots of 77 units each 3 lots of 77 units each(45) (45)

Read-out at 168 hours Read-out at 200 cycles500 hours 500 cycles

1000 hours 1000 cyclesNOTE: Numbers given in ( ) represent number of units if using reduced sample size.

* The flow is selected to match the level of moisture sensitivity classification of the specific component.



8.8.1 Handling Precautions

8.8.1.1 Never Touch The Leads

Any contact with the leads of a PSMC package will likely cause coplanarity or position problems. The leads of these packages are protected (suspended) via transport media designed to ensure integrity during shipping and handling. When handling PSMCs outside their transport media (i.e., tray, tube, tape and reel) automated equipment is highly recommended.

8.8.1.2 Keep PSMCS In Original Transport Media

PSMCs should be kept in their original transport media until used. Manual handling of PSMCs should be avoided. Transferring PSMCs into other approved media, onto PCBs, or into sockets should be performed using automatic or semi-automatic equipment specifically designed for that purpose.


• Complete Review and Edit of Chapter


Intel Packaging Databook 9-1 Board Reflow Process Recommendations Revised 12-2007

9 SMT Board Assembly Process Recommendations

9 SMT Board Assembly Process Recommendations .......................................................................9-1

9.1 Introduction............................................................................................................................9-2 9.2 Solder Paste Printing..............................................................................................................9-2 9.3 Component Placement ...........................................................................................................9-2 9.4 Reflow Soldering ...................................................................................................................9-3

9.4.1 Pb-free vs SnPb Reflow Soldering ................................................................................9-3 9.4.2 Reflow Profile Development Considerations ................................................................9-3

9.4.2.1 Reflow Profile Board Preparation .............................................................................9-4 9.4.2.2 Minimum Solder Joint Peak Temperature.................................................................9-5 9.4.2.3 Maximum Solder Joint Peak Temperature ................................................................9-5 9.4.2.4 Time Above (Initial) Melting Point ...........................................................................9-5 9.4.2.5 Rising and Falling Ramp Rate...................................................................................9-6 9.4.2.6 Reflow Equipment .....................................................................................................9-6 9.4.2.7 Reflow Atmosphere ...................................................................................................9-6 9.4.2.8 Board Warpage ..........................................................................................................9-7 9.4.2.9 Double Sided SMT Board Assembly ........................................................................9-7

9.4.3 Sample Reflow Parameters............................................................................................9-7 9.4.4 Sample Reflow Profiles .................................................................................................9-8

9.4.4.1 Sample Desktop Reflow Profile ................................................................................9-9 9.4.4.2 Sample Mobile Reflow Profile ..................................................................................9-9 9.4.4.3 Sample Server Reflow Profile .................................................................................9-10

9.5 Rework.................................................................................................................................9-10 9.5.1 Pb-free vs SnPb Rework..............................................................................................9-10 9.5.2 Risk of SnPb and Pb-free Mixing................................................................................9-10 9.5.3 Rework Profile Board Preparation...............................................................................9-10 9.5.4 Pad Cleanup After Component Removal ....................................................................9-11 9.5.5 Paste Printing Methods at Rework ..............................................................................9-12 9.5.6 Re-balling BGAs Not Recommended .........................................................................9-13 9.5.7 Sample Rework Parameters.........................................................................................9-14 9.5.8 Rework Profile Development ......................................................................................9-15 9.5.9 Sample Rework Profiles ..............................................................................................9-16

9.5.9.1 Sample BGA Rework Profile ..................................................................................9-16 9.5.9.2 Sample Socket Rework Profile................................................................................9-17


9.1 Introduction This chapter addresses the surface mount technology (SMT) board assembly process for reflow soldering SMT components to boards, as well as rework soldering for removing and replacing individual components on already-assembled boards. The information in this document is for reference only. Manufacturing processes are unique, and may require unique solutions to ensure acceptable levels of quality, reliability, and manufacturing yield. Due to differences in equipment and materials, customer-specific process parameter development and validation is required.

9.2 Solder Paste Printing Standard tin-lead (SnPb) solder paste alloy is composed of 63% tin (by weight) and 37% lead, which is commonly expressed as 63Sn/37Pb or Sn/37Pb, a eutectic composition that melts at 183C. Although there are a number of lead free (Pb-free) alloys, the most commonly used compositions contain tin, silver, and copper, commonly expressed as SAC, for SnAgCu. Within SAC solders, by far the most common usage is Sn/3Ag/0.5Cu, a near-eutectic which melts between 217°C and 220C. Apertures sizes can be 1:1 with pad size, but certain parts may require reduced apertures to reduce solder ball defects. Larger pads may benefit from crosshatched openings, to reduce the amount of paste applied, and to control scavenging. Pb-free solder paste may spread less during reflow than SnPb paste, potentially leaving extremities of pads unsoldered. Although full pad coverage by solder is not a requirement of IPC-A-610, some customers prefer to enlarge apertures to ensure that pads are covered. Using a metal squeegee reduces scavenging and provides more consistent printed paste volume. Equipment used to print SnPb paste can be used, without modification, to print Pb-free paste. Process parameters (such as squeegee speed, pressure, and separation speed) need to be optimized for the specific solder paste used.

9.3 Component Placement Pick and place machines used for SnPb boards can be used for Pb-free boards as well. Adjustments to lighting and vision algorithms may be required because of the slightly different appearance of some Pb-free solders compared to SnPb. Specifically, SnPb solders can have a grainy and dull (less shiny) appearance. This applies only when front-side lighting is used instead of backside (outline) lighting. Front-side lighting is often used for ball recognition on BGAs.


9.4 Reflow Soldering In reflow soldering, the solder paste must be heated sufficiently above its melting point and become completely molten, in order to melt the balls of BGA components, causing them to collapse and form reliable joints. In the case of components with leads, the solder paste must wet the plating on component leads to form the desired heel and toe fillets. Solder joint formation depends on temperature and time which are reflected in the reflow profile. In leaded devices the volume of solder paste on the land is significantly greater than the plated solder volume on the component lead and is the key contributor to joint formation. However in BGAs the balls on the component are the main contributor to the solder volume of the joint. In both cases, the paste volume applied is critical to the formation of the joint. There is no one best reflow profile for all board assemblies. Ideally, a reflow profile must be characterized for each board assembly using thermocouples at multiple locations on and around the device. The solder paste type, component and board thermal sensitivity must be considered in reflow profile development.

9.4.1 Pb-free vs SnPb Reflow Soldering Compared to SnPb reflow, Pb-free reflow requires higher temperatures, due to the higher melting range of typical Pb-free solders. While typical tin-lead solder (Sn/37Pb) has a single melting point of 183C, typical Pb-free solder such as SAC305 (Sn/3Ag/0.5Cu) has a much higher initial melting point of 217°C and a final melting point of 220C. In addition to having higher reflow temperatures, Pb-free reflow soldering also requires a narrower temperature range, in order to produce reliable joints, without damaging components. Maintaining this narrower range could require new reflow ovens, depending on number of zones and degree of control in ovens formerly used for SnPb soldering. Because of additional oxidation that occurs at higher temperatures, an inert reflow atmosphere (nitrogen) may be beneficial for Pb-free reflow soldering. Of course, higher temperatures drive the need for all Pb-free components to be rated to higher temperatures. Finally, these temperatures can also cause greater warpage in PCBs, and in some cases, may require alternate PCB materials, or carrier fixtures during reflow.

9.4.2 Reflow Profile Development Considerations Each customer should develop their own reflow profile and oven settings, appropriate to their materials, equipment, and products. As a starting point, this chapter contains considerations and recommendations for reflow solder parameters. Because some reflow parameters differ with solder paste formulation (even if they have the same metal composition), the profile envelope recommended by the solder paste manufacturer should be considered.


9.4.2.1 Reflow Profile Board Preparation Reflow profile measurement is a vital part of setting up reflow solder conditions. The measurements are typically carried out using thermocouples attached to a high temperature resistant recording device which travels through the reflow oven with the PCB under test. Special care must be taken to ensure proper placement of thermocouples to accurately measure temperature at the desired locations. Unless stated otherwise, all temperatures in this chapter are measured at solder joints, rather than at components bodies, PCB surface, or air around components. This provides the best repeatability and accuracy. Thermocouples (TCs) for solder joints should be placed in joints expected to be the hottest and coolest, so that the range of peak temperatures for all components on the board can be confirmed to be within specifications. The hottest joints on a board are typically on small passive components, so one of these should be monitored for peak temperature on the profile board. The coolest joints on a board are typically large BGAs and sockets. A TC should be used in a joint at one corner of the component, and in a joint at the center of the part, or as near to the center of the part as possible. Sockets with actuating mechanisms may require an additional TC at a joint near the mechanism, if its mass could make that area harder to heat. In addition to solder joints, component body temperature, measured at top center or as close as possible, may also need to be monitored, to avoid exceeding the body temperature spec of the part. Here are examples of TC locations for reflow profiling on BGAs or sockets, for both fully populated arrays and partially populated arrays (no balls in the center area of the part).

* *

**

*

Fully populated array. Partially populated array.

A topside TC to monitor body temp could also be placed at the center of

each part.

= Location of TC in solder joint.

Here is a method for placing TCs to measure SMT joint temperatures:

• Before the component is soldered to the board, drill a small hole through the pad of the joint to be measured.

• Insert the thermocouple from the bottom of the board. • Hold the thermocouple tip flush with the top surface of the board. • Apply epoxy from the bottom side of the board to keep the thermocouple in this position,

where it will be in contact with the joint, but not interfere with paste printing. • Print solder paste, place components, and reflow the board.


9.4.2.2 Minimum Solder Joint Peak Temperature With SAC305 or SAC405 Pb-free solder paste, the coolest joints on a board should generally reach at least 228C, preferably 230°C. For BGAs, this applies to ball alloys SAC305 or SAC405. For SAC305/405, 228°C represents at least 11°C superheating above the initial melting point (217°C). 230°C represents 13°C superheating. Temperatures lower than these can result in joints that are not fully formed, or in reduced reliability. Components with other Pb-free ball alloys, such as SnAg or SAC105, may require higher minimum peak temperatures to form reliable joints.

9.4.2.3 Maximum Solder Joint Peak Temperature 250°C is recommended as the maximum temperature for all solder joints on the board, except for components with temperature ratings lower than 250°C. If maximum solder joint temperatures exceed 250°C, PCB damage such as delamination and warpage may result when standard FR4 (Tg =130°C) material is used. Higher Tg material is not necessarily more resistant to this damage, and must be tested for compatibility. Components are typically rated as per J-STD-020C (or later), based on their package thickness and volume. Although Intel BGAs are generally rated at 260°C, other components, especially large ones, may be rated at 250°C or 245°C. This means that 250°C may not be usable as the max joint temperature for some components; a lower temperature may be required. Since larger parts normally reach lower maximum temperatures during reflow than smaller parts due to the physics of heat transfer, keeping them below their ratings may not be difficult, as long as 250°C is used as the maximum for the joints of smaller parts.

9.4.2.4 Time Above (Initial) Melting Point The length of time that joints spend above the min peak temp is also an important factor for solder joint reliability. Intel recommends that this time be measured from the time a joint goes above the initial melting point of the alloy (217°C for SAC305/405), until it goes below it during cooling. Time Above Liquidus, or TAL, is often used to describe this time. But technically speaking, 217°C is the solidus temperature of SAC305, the point at which the solder becomes fully solid during cooling. 220°C is the liquidus temperature, the point at which it becomes fully liquid during heating. Between these two temperatures, the solder is partially molten and partially solid.


Unfortunately, common usage in the lead free industry has often incorrectly used the term ‘liquidus’ to refer to the initial melting point, rather than the final melting point. This is probably a carry-over from SnPb soldering, where ‘liquidus’ was used correctly, since liquidus and solidus are both the same temperature (183°C). In order to avoid confusion, this document will avoid the use of ‘liquidus’ and ‘Time Above Liquidus (TAL)’. Reflow time will be stated as Time Above 217°C (TA217), rather than TAL. Intel recommends that TA217 of 40-90 seconds be used for SAC305 or 405 solder paste and balls. With large or massive boards, an exception may be required, allowing up to 120 seconds above 217°C.

9.4.2.5 Rising and Falling Ramp Rate To avoid component damage, manufacturers often recommend that rate of temperature increase during heating (Rising Ramp Rate) and cooling (Falling Ramp Rate) be kept below 3°C/sec. This applies throughout the heating and cooling process. During cooling from peak temperature down to 205°C, Intel also recommends that a minimum ramp rate be used. Solder joints with cooling rates of 1°C/sec or greater are characterized by finer microstructure features. Literature studies indicate that this is better for long term reliability. Faster cooling rates also inhibit growth of intermetallic compounds in the bulk solder.

9.4.2.6 Reflow Equipment The peak temperature envelope is typically narrower for Pb-free reflow than for SnPb reflow. Although ovens designed for SnPb soldering can generally reach the higher temperatures required for Pb-free soldering, they may not be able to produce the narrower temperature profile, at least not without significantly lengthening reflow time. Producing and controlling a narrower temperature range, while maintaining production speeds, typically relates to the number of heating zones in the oven. Assemblers with reflow equipment with greater temperature control (i.e. greater numbers of zones) will be better positioned to meet the tighter Pb-free process envelope requirements, particularly for larger, more complex boards.

9.4.2.7 Reflow Atmosphere Reflow soldering in an inert atmosphere, such as nitrogen, reduces the amount of solder and pad oxidation that occurs during soldering. This can improve the quality and appearance of SMT joints, and have a positive impact on hole fill at wave solder and on contact resistance during test, especially with PCBs using OSP surface finish. However, other measures can often be taken to achieve similar results without using nitrogen at reflow. Examples include:

• Solder paste selection. • PCB surface finish selection. • Printing solder paste on test pads rather than leaving them exposed during reflow. • Test probe head style selection.


Examples specific to wave soldered boards include: • Wave flux selection. • Wave flux application method. • Wave flux volume applied. • Wave flux distribution and depth of penetration in holes. • Wave solder parameters, such as:

o Preheat configuration. o Preheat profile. o Wave solder alloy selection. o Wave solder pot temperature. o Solder wave dynamics.

9.4.2.8 Board Warpage Because of the higher temperatures required for Pb-free assembly, boards may sag and warp more than during SnPb assembly. This is particularly noticeable on thin PCBs, such as those used in mobile applications. Although there is no common industry specification for the warpage of assembled boards (only for bare boards), board assemblers may prefer to reduce warpage.

• A picture-frame style pallet, with hold downs, can be used to support the board on all four sides. • Channel-type support rails can be attached to the leading and trailing edge of the board, after

solder printing but prior to reflow. • Oven manufacturers offer various center support mechanisms, such as an adjustable center

support wire or chain, but this imposes a placement stay-out zone on the design.

Warpage amount varies with PCB size/thickness/laminate, number of reflow cycles, and warpage control method. In experiments at Intel, warpage of 1.0 and 1.2mm thick boards did not cause any performance problems.

9.4.2.9 Double Sided SMT Board Assembly Both primary and secondary side reflow profiles should meet the same target specification. Because the board assembly has greater thermal mass during second reflow, different oven settings may be required first and second reflow, in order to meet the same target profile. This requires two profile boards to simulate actual board configuration (thermal mass) during each respective reflow.

9.4.3 Sample Reflow Parameters

Solder paste No-clean, flux class ROL0 per J-STD-004. Alloy Sn/3Ag/0.5Cu or Sn/4Ag/0.5Cu. Metal content 89%.

Soak Paste dependent: Consult paste manufacturer. Rising Ramp Rate Maximum 3°C per second.

Falling Ramp Rate Maximum 3°C per second. Minimum 1°C per second, from peak temp down to 205°C.

Time Above 217°C Prefer 40-90 seconds above 217°C. Min 40 seconds, Max 120 seconds

Minimum solder joint peak temp

228°C, if all BGA balls on board are SnAgCu 230°C, if any BGA balls on board are SnAg


Maximum solder joint peak temp

250°C, except as limited by components with lower temperature ratings. Preferred joint temp max 240C.

Maximum body temp Not to exceed manufacturer specification. If no spec, then not to exceed temps as per J-STD-020C.

Oven type Forced convection • Sample process applies to all types of SMT components on the board, not just the BGAs. • All temperatures are measured with thermocouples inside solder joints, for better accuracy • Max temp applies to the hottest joint on the board, typically a joint of a small passive device. • Reference process applies to all PCBs with nominal thickness .040” to .077” (1.02 to 1.96mm), and

to PCBs .078” to .093” (2.0 to 2.36 mm) with large active devices on one side only. Thick PCBs with thermally massive parts on both sides may require adjustments to Peak Temp and TA217.

Here is a graphical representation of information in the table above.

250ºC (240ºC preferred)

Time Above 217C: 40 - 120 seconds (prefer 40 - 90 sec)

228ºC for SnAgCu (230ºC for SnAg BGA balls)

217ºC

Max peak temp range

Rising Slope Max 3.0ºC/sec

Falling Slope Max 3ºC/sec,with Min 1ºC/sec from peak to 205ºC.

9.4.4 Sample Reflow Profiles Here are sample reflow profiles for certain Pb-free desktop, mobile, and server boards. These are not meant to indicate reflow requirements, merely to illustrate typical reflow profiles.

9.4.4.1 Sample Desktop Reflow Profile

9.4.4.2 Sample Mobile Reflow Profile



9.4.4.3 Sample Server Reflow Profile

9.5 Rework

9.5.1 Pb-free vs SnPb Rework Rework must provide higher temperatures for Pb-free solder. Greater temperature profile control is required, which may require different nozzles or equipment replacement. Rework can be the most difficult module to develop for Pb-free. Rework (both SMT and Through Hole) on thick PCBs is especially challenging.

9.5.2 Risk of SnPb and Pb-free Mixing During the transition from SnPb to Pb-free assembly, rework is a potential area for inadvertently mixing Pb-free with SnPb boards. Dedicate separate areas, tools, and equipment to Pb-free and SnPb. Clearly identify SnPb and Pb-free work areas. Ensure that boards are clearly identifiable as Pb-free or SnPb.

9.5.3 Rework Profile Board Preparation Because a rework profile is developed for a single component at a time, rather than the entire board, each component can have many thermocouples (TCs) on it, rather than the one or two locations used on reflow profile boards. TCs should initially be located at:

• Solder joints at all four corners of the hot air reworked component. • A solder joint at the center of the part, or as near to the center as possible, to represent the

coolest joints on the component.


• Sockets with actuating mechanisms may require an additional TC at a joint near the mechanism, if its mass could make that area harder to heat.

After developing the initial profile, place an additional TC at the topside location corresponding to the TC with the hottest joint temperature.

• Because of the nature of hot air rework, and the variety of nozzle designs, there may be a significant temperature gradient across the part during rework.

• Therefore, monitoring body temperature with a TC only in the center may not represent what the rest of the body is exposed to.

• Use this topside TC to confirm that component body temp is not exceeding its max rating. Adjust profile if needed.

Here are examples of TC locations for rework profiling on BGAs or sockets, for both fully populated arrays and partially populated arrays (no balls in the center area of the part).

*

* *

* *

* **

**

*A topside TC to monitor body temp would be also placed at one of these points, depending on which area has

the highest joint temps.

= Location of TC in solder joint.

Fully populated array. Partially populated array.

TCs to measure joint temperatures are installed through holes in the board, using the same method described earlier for reflow profile boards.

9.5.4 Pad Cleanup After Component Removal While wicking solder off of pads:

• Always clip off the used portion of the wick; it behaves as a heat sink. • Apply liquid flux to the wick, to minimize sticking of the wick to the pads. • Place the soldering iron on the solder wick off to the edge of the pads being soldered, to heat

iron tip and wick prior to desoldering. • Do not let the solder iron or wick freeze on pads, to prevent pad lift. • Do not lift the iron or wick up and down on the pads. • Apply very light pressure, similar to writing with a pencil. Soldering is achieved by

temperature difference, not by tip pressure. • Apply heat for 2 to 3 seconds after solder melts. Total contact time may be 6-7 seconds.

Excess heating causes solder brittleness and may lift pads. • Move the soldering iron in the same direction with each stroke, rather than going back and

forth. Going back and forth overheats pads at the ends of the row, increasing potential for damage.

Pb-free hand solder may require soldering iron tips hotter than used for SnPb rework. Hotter tips allow rework at a pace similar to SnPb rework. Without hotter tips, desoldering and resoldering is slower.


However, with hotter tips, caution must be used to prevent pad lift. If Pb-free tips are not available, Pb may be purged from standard SnPb tips by repeatedly flooding with Pb-free solder and then cleaning.

9.5.5 Paste Printing Methods at Rework When new BGAs are installed at Rework, after pad cleanup, additional solder paste may not be required. The BGA ball can provide enough solder for a good joint. When new processor sockets are installed at Rework, additional paste is generally needed to ensure that good joints are formed, due to greater coplanarity differences. Because of the difficulties of placing, aligning, and printing with a mini-stencil on the assembled PCB, a method is available that prints paste directly onto the socket BGA balls, rather than onto the PCB, as follows: 1. A stencil is inserted into the ball printing jig.

2. The part is hand placed with balls resting in stencil apertures. (An alignment frame is used, but not shown.)

3. A clamping frame holds the part in place for later operations.


4. The jig is inverted, and paste is applied over the apertures.

5. A mini squeegee prints paste onto the balls, and removes excess paste.

6. The jig is inverted once more, the clamping frame is opened, and the part is removed by the rework machine’s vacuum pick for placement onto the board.

Resulting side view of paste-printed balls.

9.5.6 Re-balling BGAs Not Recommended Removed BGAs should be discarded. The re-balling process (placing new balls on removed BGAs, so that they can be re-used) is not recommended, for these reasons: • Many BGAs (including Intel BGAs) are rated for three soldering cycles.

o Re-balling exposes BGAs to more than three soldering cycles. o (1) Initial installation, (2) Rework/removal, (3) Ball attach, and (4) Final installation.

re soldering cycles. o BGAs used on double sided boards could have even mo


• Exposing BGAs to more than three soldering cycles may void the manufacturer’s warranty (including Intel’s).

• The intermetallic compound (IMC) layer, on the PCB and on the package, gets thicker with every reflow cycle. Wicking solder off the PCB or package pads does not remove IMC. Excessive IMC thickness can negatively affect solder joint reliability.

9.5.7 Sample Rework Parameters Reworked part type > BGAs

(and other array area packages) Processor Sockets

Process parameters based on Sn/4Ag/0.5Cu and Sn/3.5Ag ball alloys. PCB nominal thickness 0.062-0.093” (1.6-2.4mm)

Rework machine type Hot air Flux applied to Pads on board Solder paste None Same as used at SMT Solder paste application None Printed on balls Rising Ramp Rate below 205°C 0.5 - 2.5°C/ sec Soak Time, from 150°C to 215°C < 100 sec (soak spec varies with solder paste selection) Critical Rising Ramp Rate between 205°C and 215°C 0.35 - 0.75°C/sec

Peak Temperature Range 230-245°C 230-250°C Time Above 217°C (TA217) 40-120 seconds 40-200 seconds Delta-T (temp difference) across joints on part while above 217°C ≤10°C ≤15°C

Maximum Body Temp and Time Not to exceed component supplier max specifications Except for body temps, all temperatures are measured at At solder joints, with thermocouple in a hole at center of a pad. Falling Ramp Rate 0.5 - 2.0°C/ sec Here is a graphical representation of information in the table above.

250º

Falling Ramp Rate0.5-2.0ºC/sec

Time Above 217C: 40-120 sec for BGAs,

40-200 sec for sockets

230º

217º

150ºSoak Time from 150 to 217ºC: < 100 sec

(varies with solder paste selection)

Socket max peak temp range 230-250ºC245º

BGA max peak temp range 230-245ºC

Critical Rising Ramp Rate 205-215ºC: 0.35-0.75ºC/sec

205ºRising Ramp Rate

below 205ºC: 0.5-2.5ºC/sec


9.5.8 Rework Profile Development Because of the rework profile requirements, and because of the interactions that each profile adjustment makes, it can be very difficult to develop a rework profile. This is especially true if all stages of the profile are targeted for development simultaneously. A recommended approach is to break the profile down into phases, and develop the first phase first, then the second, and so on. Here are some recommendations for successful rework profile development. • Maximize bottom heater temperature when creating the profile. • Keep the temperature of molten solder joints (above 217°C) within 10°C of each other across the

component for BGAs, and within 15°C for sockets. • Create the profile in steps. Don’t move on to the next step until the current step meets goals.

Developing the entire profile at once can be overwhelming. o Step 1: Board Preheat

Get joints into the 125 to 150°C range before lowering the nozzle. o Step 2: Soak

With nozzle down, get BGA joints into the 200 to 220°C range and socket joints into the 190 to 215°C range.

Check the Soak Time spec. o Step 3: Peak Reflow

With nozzle down, meet specs for peak reflow range and Time Above 217°C. o Step 4: Cool Down

With nozzle up, get board cool enough to handle safely. • After developing the initial profile, check component body temperature to avoid exceeding Max

component temps and times. Adjust profile as needed. o Place the body thermocouple at the topside location corresponding to the thermocouple

with the hottest joint temperature. Here is a graphical representation of the steps listed above.


9.5.9 Sample Rework Profiles

9.5.9.1 Sample BGA Rework Profile

Other specs to check

during this step

Target to exit this step

Falling Ramp Rate. Peak Temp Range. TA217.

Component Max Body Temp and Time.

Rising Ramp Rate. Critical Rising Ramp Rate. Soak Time.

Rising Ramp Rate.

Solder Joint Temp < 80°.

Peak Temp Range, and TA217 specs met.

BGA Solder Joint Temp: 200 to 220°C.

Socket Solder Joint Temp: 190 to 215°C.

Solder Joint Temp:

125 – 150°C

Preheat with bottom heater, before nozzle

is lowered.

Nozzle rises when joints go below 217°C.

Nozzle is down during peak reflow.

After nozzle is lowered, prior to peak reflow.

Start with solder joint temp < 40°C.

Step 4 Cool Down

Step 3 Peak Reflow

Step 2 Soak, or FAT

(Flux Activation Time)

Step 1 Board

Preheat


9.5.9.2 Sample Socket Rework Profile

Shipping and Transport Media 10

10.1 Product Transport Media All semiconductor products must be shipped in some type of handling media. The type used is specific to the type of package, die, or wafer that is to be shipped. The following sections outline the many different types of shipping and handling media that Intel uses and outlines how they can be recycled. This is not inclusive of the many different types of media available, but is meant to show the main types used and some of the methods for using them in the factory floor.

10.1.1 Plastic Tubes Plastic shipping and handling tubes are manufactured from polyvinyl chloride (PVC) with an antistatic surfactant treatment. Standard tubes for most package types are translucent and allow visual inspection of units within the tube. Carbon-impregnated, black conductive tubes are available for all parts where required by device or use characteristics. Tube profiles are designed with minimum clearance over the maximum package dimensions to reduce damage caused by movement of the device within the tube. For some package types, tubes have “riding rails” on which the packages rest while in the tube. The rails protect the fragile leads from touching anything in the tube. PVC tacks, nylon tacks, or rubber plugs are used to retain the units. All tube wall thickness are 0.025 inches to 0.040 inches. Table 10-1 through Table 10-8 show tube dimensions and cross-sections and quantity of packages per tube for most Intel package types. Additional information on new packages should be requested through Intel Field Sales.


Table 10-1. PLCC Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness

Outside Dimensions Quantity of Packages

PerTubeLength (L) Width (W) Height (H)

20 L Square 0.030 19.375 0.480 0.263 46

28L Square 0.030 19.375 0.580 0.263 38

44L Square 0.025 19.375 0.780 0.250 26

52L Square 0.030 19.375 0.880 0.263 23

68L Square 0.025 19.375 1.090 0.250 18

28L Rectangular

0.025 19.375 0.480 0.220 30

32L Rectangular

0.025 19.375 0.580 0.220 30

84L Square 0.040 19.375 1.300 0.288 15

Table 10-2. Cerquad Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness

Outside Dimensions Quantity Per

TubeLength (L) Width (W) Height (H)

44SQ 0.025 0.200 0.730 11.50 11

52SQ 0.025 0.200 0.820 11.50 11

68SQ 0.030 0.200 1.040 11.50 9

28SQ 0.030 0.200 0.520 11.50 15

32SQ 0.030 0.175 0.530 11.50 12


Shipping and Transport Media

Table 10-3. PQFP Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness



84L PQFP 0.030 9.50 0.999 0.280 10

100L PQFP 0.030 10.50 1.099 0.280 10

132L PQFP 0.030 12.50 1.299 0.280 10

Table 10-4. LCC Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness



18L 0.025 11.5 0.370 0.165 25

20L 0.025 11.5 0.370 0.165 25

28L 0.025 11.5 0.530 0.165 22

32L 0.025 11.5 0.535 0.207 18

44L 0.025 11.5 0.736 0.180 16

68LType “A”

0.025 11.5 1.060 0.235 10

68LType “B”

0.025 11.5 1.060 0.260 10

32LJ-Lead

Rectangular

0.030 11.5 0.590 0.235 16

32LJ-Lead

RectangularEPROM

0.030 11.5 0.600 0.260 16

44LJ-LeadSquare

0.025 11.5 0.786 0.250 15



Table 10-5. PGA Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness



68L 0.040 20 1.255 0.460 15

88L 0.050 20 1.470 0.720 12

132L 0.045 20 1.565 0.720 11

Table 10-6. Flatpack Shipping Tube Dimensions (In Inches)

LeadType

CrossSection(W x H)

WallThickness



18L* Ceramic 0.020 20 0.810 0.290 18

68L Plastic

0.040 20 2.138 0.628 9

68LCeramic

Quadpack

0.035 20 2.120 0.610 9

NOTE: 1. * Aluminum Tube

Table 10-7. PSOP Shipping Tube Dimensions (In Inches)

LeadType

Cross Section(W x H)

WallThickness

Outside Dimensions Quantity PerTubeLength (L) Length (L) Length (L)

44L 0.030 20 0.787 0.213 17

H

H

H



Table 10-8. DIP Shipping Tube Dimensions (In Inches)

LeadType

Cross Section(W x H)

WallThickness

Outside Dimensions Quantity PerTubeLength (L) Length (L) Length (L)

16L 0.020 20 0.600 0.510 24 (P)23 (D)23 (C)

18L 0.020 20 0.600 0.510 20 (P)21 (D), (C)

20L 0.020 20 0.600 0.510 18 (P), (D)17 (C)

24L(300 mil)

0.020 20 0.600 0.510 15

28L(300 mil)

0.020 20 0.600 0.510 14 (P)13 (D)

22L(400 mil)

0.030 20 0.727 0.535 17

24L(600 mil)

0.022 20 0.890 0.495 15

28L(600 mil)

0.022 20 0.890 0.495 13

32L 0.022 20 0.890 0.495 11

40L 0.022 20 0.890 0.495 9

48L 0.022 20 0.890 0.495 7 (P)8 (C)

NOTES: 1. (P) = PDIP2. (C) = Ceramic Sidbrazed3. (D) = CERDIP



10.1.2 CarriersAdditional protection from lead damage is necessary for the fragile leads of flatpack packages, which are shipped flat to be trimmed and formed at the customer site. Plastic carriers are used to hold each unit, then the loaded carrier is placed in the tube. Carriers are either coated with antistatic surface treatment are intrinsically static dissipative. Figure 10-1 through Figure 10-3 show a variety of carrier types.

10.1.2.1 Recycling for Carriers and Carrier Tubes

Figure 10-1. 18-Lead Ceramic Flatpack Carrier

United KingdomHolden EnvironmentalShore Road Recycling Centre Shore Road, Perth PH2 8BHContact: John CoxPhone: 0500 34 10 40 Fax: 01738 637150

Holden Environmental provides all shipping arrangements at no charge to the customer.

A5784-01240822-1

-C-

EDM0.05 (0.002) M F M

13.56 (0.534)

-E-

-F-

A

25.40 (1.000)

19.05 (0.750)

A

2X 10.16 (0.400)

2X 10.16 (0.400)(16X 1.27 (0.050)

4X 45 X 0.51 (0.020)˚

[Dimensions in mm (inches)]



Figure 10-2. 68-Lead Ceramic Flatpack Carrier

A5785-01240822-2

1.995

3X 2.000

[Dimensions in Inches]



Figure 10-3. 68-Lead Plastic Flatpack Carrier

10.1.3 TraysShipping trays are built in compliance with JEDEC thick and thin standard dimensions. Mid-temperature trays can be baked to 140° C while low temperature trays can withstand a maximum sustained temperature of 65° C. Trays are constructed in modified polysulfone (PS) or equivalent

A5786-01240822-3

[Dimensions in Inches]

A

0.3721.250

1.995 ± 0.005

3X 0.183 ± 0.002

2.000± 0.005

A

0.487

Section A-A



for mid-temperature applications and polycarbonate (PC) for low temperature applications because of their high deflection temperature, superior strength, and dimensional stability. All JEDEC trays have the same “X” and “Y” dimensions and are easily stacked for storage and manufacturing.

Intel offers trays for the following package types:

Illustrations of trays for various packages are shown on the following pages. Intel field sales engineers can provide detailed drawings and specifications upon request.

PQFP 84LD, 100 LD, 132 LD, 164 LD, 196 LD thick mid-temperature84 LD, 100 LD, 132 LD, 196 LD thin mid-temperature132 LD, 196 LD single unit thick mid-temperature

PGA 68-84 LD 11 x 11, 88-100 LD 13 x 13, 132-139 LD 14 x 14, 149 LD 15 x 15, 168-208LD 17 x 17, 240-296 LD 19 x 19, 273 LD 21 x 21, 325 LD 26 x 24 thicklow-temperature

PLCC 28 LD square, 28 LD rectangular, 44 LD square, 68 LD square, 84 LD square thickhigh-temperature

TSOP 32 LD, 40 LD, 48 LD, 56 LD thick mid-temperature 32 LD, 40 LD, 56 LD thin mid-temperature

SSOP 48 LD, 56 LD thick mid-temperatureCQFP 132 LD formed, 164 LD flat, 196 LD formed, 196 LD flat thick high-temperatureMQFP 44 LD (10 x 10), 64 LD (12 x 12), 80/100 LD (14 x 20) thick and thin

mid-temperatureSQFP 80 LD (12 x 12), 100 LD (14 x 14), 208 LD (28 x 28) thick and thin mid-temperature,

208 LD (28 x 28), single unit thick mid-temperatureTQFP 144 LD (20 x 20), 176 LD (24 x 24) thick and thin mid-temperature

TCP carrier high-temperatureMSC 19 x 19, 0.880 high spacer low-temperature

TCP carrier high-temperatureBGA 27 x 27 and 35 x 35 thin mid-temperaturePPGA 296 LD thick low temperatureµBGA 40B (12x22) and 48B (9x18) thin mid-temperature



Figure 10-4. Injection Molded Thick JEDEC Tray

A5787-01240822-6

0.008

-D-5.35

M3

M

-B-

-C-

M2M1

PackagePin-1 OrientationDetail C

Detail B 3X 0.06 R

Detail D5X

1.00

0.030-A-

-E-

M E M

0.480

0.400

12.27-7 Draft˚

10.05

12.40

12.70

0.008 M E M

12.25-7 Draft˚

5X0.10

Detail A

1.35

Y1



Figure 10-5. Injection Molded Thick JEDEC Tray

A5788-01240822-7

0.008 M D M

5.20-7 Draft˚

VENDORPART #Tray Made in XXX

REV

0.150.10 0.05

0.11

60˚0.18

0.053˚

Typ

Detail AScale 4:1

0.157

R 0.187

˚45

Detail BScale 4:1

Detail CScale 4:1

0.12

Device Information BlockRevision Level

Vendor Information BlackDetail D

Scale 2:1

0.008 M D M

5.22-7 Draft˚

4X R 0.0150.50

0.12Typ 0.62 Typ

End View

0.065Typ



Figure 10-6. Injection Molded Thin JEDEC Tray

A5789-01240822-98

0.008

-D-5.35

M3

M

-B-

-C-

M2M1

PackagePin-1 Orientation

Detail B 3X R 0.06

0.030-A-

M E M

12.27-7 Draft/Side˚

0.008 M E M

12.25-7 Draft/Side˚

Detail A

XX

X C

MA

X˚

TM

T P

QF

P 1

00

-E-12.40

12.70

Detail DDetail C

0.000

0.00

00.

060

Ref

2X 1

.350

4X 0.100

2X 1

0.05

0

0.0000.250

0.300

4X 1.000+2 /Side˚

0.015 Corner Radius

8X 0.03R



Figure 10-7. Injection Molded Thin JEDEC Tray

A5790-01240822-99

30˚

0.0500.138

0.0780.150

0.100

0.157

R 0.187

1.1203X 0.050

3X 0.150

0.200

XXXX XXXX

PackageDesignation Block

VendorInformation Block

0.700

0.175

0.200

Rev. LevelIndicator Block

Detail A4:1

2X Detail

Detail B4:1

Detail C4:1 [Rotated -90˚]

XXX C MAX˚

0.2000.7502.00 Label Area

0.200

2X 0.050

2X 0.150

Detail D4:1 [Rotated -90˚]

0.008 M D M0.015 Corner Radius

5.20Stacking Feature

2X 3.6262X 0.500

0.008 M D M0.015 Corner Radius

End View

5.22Stacking Feature

0.100Temperature Rating Block



Figure 10-8. Injection Molded Single Unit Tray

A5791-01240822-A0

0.008 M DE M

-E-2.500

M2

M3-D-

2.500

1.250

1.250-C-

-B-3X R 0.03

3X R 0.06Revision Level

2X 2.350 ±0.010 -7˚/S Stacking Feature

2.245 -2 /S˚

0.008 M DE M 2X 2.380 ±0.010 -7˚/S TSC

4X R 0.03

4X R 0.015

4X R 0.03

0.4800.400

0.10-A- 0.000

0.125 X 45˚

Detail A

Vendor/DevicePart #XXXX XXXL

Detail A

Vendor/DeviceInformationBlock



Table 10-9. Injection Molded Thick and Thin PQFP JEDEC Tray

PQFP Tray Dimensions

Pocket Locations Symbol 84 LD 100 LD 132 LD 164 LD 196 LD

Pocket Cntr Location to Edge Y M 0.701 0.701 0.824 1.161 1.030

Pocket Cntr Location to Edge X M1 0.706 0.750 0.944 0.957 1.064

Pocket-Pocket Cntr Distance X M2 0.999 1.090 1.314 1.498 1.712

Pocket-Pocket Cntr Distance Y M3 0.987 0.987 1.234 1.514 1.645

# of Rows of Pockets Rows 5 5 4 3 3

# of Columns of Pockets Columns 12 11 9 8 7

Total # of Pockets Pockets 60 55 36 24 21NOTE: 1. Dimensions are in inches.

Table 10-10. Injection Molded Thick PGA JEDEC Tray

PGA Tray Dimensions

Pocket Locations Symbol 68 L 88 L 132 L 168L 240/296L 273 L 325/

387L

Pocket Cntr Location to Edge Y M 1.072 1.573 1.556 1.506 1.473 1.456 2.675

Pocket Cntr Location to Edge X M1 1.152 1.077 1.285 1.513 1.446 1.861 1.700

Pocket-Pocket Cntr Distance X M2 1.683 1.708 1.966 2.344 2.377 2.892 3.000

Pocket-Pocket Cntr Distance Y M3 1.603 2.204 2.237 2.337 2.404 2.438 N/A

# of Rows of Pockets Rows 3 2 2 2 2 2 1

# of Columns of Pockets Columns 7 7 6 5 5 4 4

Total # of Pockets Pockets 21 14 12 10 10 8 4NOTE: 1. Dimensions are in inches.

Table 10-11. Injection Molded Thick PLCC JEDEC Tray

PLCC Tray Dimensions

Pocket Locations SymbolPLCC

28 LD(R)PLCC

28 LD(S)PLCC

44 LD(S)PLCC

68 LD(S)PLCC

84 LD(S)

Pocket Cntr Location to Edge Y M 0.670 0.767 0.899 1.079 1.070

Pocket Cntr Location to Edge X M1 0.755 0.880 0.890 1.163 1.148

Pocket-Pocket Cntr Distance X M2 0.990 1.064 1.180 1.679 1.684

Pocket-Pocket Cntr Distance Y M3 0.802 0.954 1.184 1.596 1.605

# of Rows of Pockets Rows 6 5 4 3 3

# of Columns of Pockets Columns 12 11 10 7 7

Total # of Pockets Pockets 72 55 40 21 21NOTE: 1. Dimensions are in inches.



Table 10-12. SOP Thick Tray Physical Dimensions

Pocket Locations Symbol48-LeadSSOP

56-LeadSSOP

Pocket Cntr Location to Edge Y M 15.8 13.61

Pocket Cntr Location to Edge X M1 15 29.46

Pocket-Pocket Cntr Distance X M2 19 32.00

Pocket-Pocket Cntr Distance Y M3 14.9 18.11

# of Rows Rows 8 7

# of Columns Columns 16 9

Total # of Pockets Pockets 128 63NOTE: 1. Dimensions are in millimeters.

Table 10-13. Thin High Density SOP Tray Dimensions

Pocket Locations Symbol32-Lead TSOP

40-LeadTSOP

48-Lead TSOP

56-Lead TSOP

Pocket Cntr Location to Edge Y M 8.53 14.40 15.80 13.00

Pocket Cntr Location to Edge X M1 17.25 17.25 17.25 17.24

Pocket-Pocket Cntr Distance X M2 25.50 25.50 25.50 25.50

Pocket-Pocket Cntr Distance Y M3 9.90 11.89 14.90 15.69

# of Rows of Pockets Rows 12 12 12 12

# of Columns of Pockets Columns 13 10 8 8

Total # of Pockets Pockets 156 120 96 96NOTE: 1. Dimensions are in millimeters.

Table 10-14. Injection Molded Thick Formed CQFP JEDEC Tray

CQFP Tray Dimensions

Pocket Locations Symbol 132 LEAD 196 LEAD


Pocket Cntr Location to Edge X M1 0.944 1.064

Pocket-Pocket Cntr Distance X M2 1.314 1.712


# of Rows of Pockets Rows 4 3

# of Columns of Pockets Columns 9 7

Total # of Pockets Pockets 36 21NOTE: 1. Dimensions are in inches.



Table 10-15. Injection Molded Thick Formed CQFP JEDEC Tray

CQFP Flat Leads Tray Dimensions

Pocket Locations Symbol 164 LEAD 132/196 LEAD




Pocket-Pocket Cntr Distance Y M3 — —




Table 10-16. Injection Molded Thick and Thin MQFP JEDEC Tray

MQFP Thick and Thin Tray Dimensions

Pocket Locations Symbol 44 LD (10x 10) 64 LD (12 x 12)80/100

(14 x 20) Thick

80/100(14 x 20)

Thin

Pocket Cntr Location to Edge Y M 0.720 0.608 0.843 0.608

Pocket Cntr Location to Edge X M1 0.680 0.701 1.034 0.886

Pocket-Pocket Cntr Distance X M2 0.736 0.846 1.148 1.063

Pocket-Pocket Cntr Distance Y M3 0.782 0.827 0.916 0.827

# of Rows of Pockets Rows 6 6 5 6

# of Columns of Pockets Column 16 14 10 11

Total # of Pockets Pockets 96 84 50 68NOTE: 1. Dimensions are in inches.

Table 10-17. Injection Molded Thick and Thin SQFP JEDEC Tray

SQFP Thick and Thin Tray Dimensions

Pocket Locations Symbol 80 LD (12 x12) 100 LD (14 x 14) 208 LD (28 x 28)

Pocket Cntr Location to Edge Y M 0.608 0.608 1.218

Pocket Cntr Location to Edge X M1 0.701 0.701 1.100

Pocket-Pocket Cntr Distance X M2 0.846 0.846 1.457

Pocket-Pocket Cntr Distance Y M3 0.827 0.827 1.457

# of Rows of Pockets Rows 6 6 3

# of Columns of Pockets Columns 14 14 8

Total # of Pockets Pockets 84 84 24NOTE: 1. Dimensions are in inches.

2004 Packaging Databook 10-17S


Table 10-18. Injection Molded Thick Formed TQFP JEDEC Tray

TQFP Thick and Thin Tray Dimensions

Pocket Locations Symbol 144 LD (20 x 20) 176 LD (24 x 24)








Table 10-19. Injection Molded MSC JEDEC Tray

Pocket Locations Symbol 19 x 19 - 0.880 TCP Carrier







Total # of Pockets Pockets 10 8

Tray Height Height 0.880 0.480NOTE: 1. Dimensions are in inches.

Table 10-20. Injection Molded Thin BGA JEDEC Tray

BGA Thin Tray Dimensions

Pocket Locations Symbol 27 x 27 35 x 35







Total # of Pockets Pockets 40 24NOTE: 1. Dimensions are in millimeters.



Table 10-21. Injection Molded Thick PPGA JEDEC Tray

PPGA Thick Tray Dimensions

Pocket Locations Symbol 296 Lead

Pocket Cntr Location to Edge Y M 1.473

Pocket Cntr Location to Edge X M1 1.448

Pocket-Pocket Cntr Distance X M2 2.377

Pocket-Pocket Cntr Distance Y M3 2.404

# of Rows of Pockets Rows 2

# of Columns of Pockets Columns 5

Total # of Pockets Pockets 10NOTE: 1. Dimensions are in millimeters.

Table 10-22. CSP Injection Molded Thin JEDEC Tray

µBGA Thin Tray Dimensions

Pocket Locatio

ns Sym

bol

28F0

08S3

28F0

16S3

28F8

00B

328

F008

B3

28F1

60B

328

F016

B3

28F1

60B

3A28

F016

B3A

28F1

60C

328

F160

F3

28F3

20B

328

F320

C3

28F1

60C

18

28F6

40J5

Pocket Cntr Location to Edge Y

M 17.246 12.052 12.390 13.386 18.9 15.7 11.85 13.386

Pocket Cntr Location to Edge X

M1 16.129 12.128 11.532 12.522 8.7 8.7 9.00 19.380

Pocket-Pocket Cntr Distance X

M2 13.462 19.380 15.367 17.043 12.4 12.4 11.00 25.121

Pocket-Pocket Cntr Distance Y

M3 9.220 12.420 13.919 13.640 10.9 9.5 10.20 13.640

# of Columns of Pockets

Columns

22 16 20 18 25 25 28 12

# of Rows of Pockets

Rows 12 10 9 9 10 12 12 9

Total # of Pockets

Pockets 264 160 180 162 250 300 336 108



Table 10-23. Easy BGA Package Thin Tray Dimensions

Pocket Locations Symbol All Products







Total # of Pockets Pockets 144

Table 10-24. S-CSP Package Thin Tray Dimensions

Pocket Locations Symbol 28F1602C3

28F1604C328F3202C328F3204C3


M 20.00 14.40


M1 14.70 14.70


M2 11.90 11.90


M3 13.70 15.30




Table 10-25. Injection Molded OLGA JEDEC Style Tray Dimensions

Pocket Locations Symbol 31 x 31 31 x 35 27.2 x 31 42.5 x 42.5


M 24.15 24.15 18.74 35.10


M1 19.50 21.69 19.50 28.25


M2 34.50 38.78 34.49 51.70


M3 43.80 43.79 32.79 65.70

# of Columns of Pockets

Columns 9 8 9 6

# of Rows of Pockets

Rows 3 3 4 2

Total # of Pockets

Pockets 27 24 36 12

Tray height Height 7.62 12.19 7.62 12.19



Table 10-26. Injection Molded FC-PGA JEDEC Style Tray Dimensions

Pocket Locations Symbol 49.53 x 49.53








Tray Height Height 7.62

Table 10-27. Injection Molded OOI JEDEC Style Tray Dimensions

Pocket Locations Symbol 34.22 x 28.25 32.6 x 36.8


M 18.75 24.15


M1 21.70 24.43


M2 38.80 44.35


M3 32.80 43.79




Tray Height Height 7.62 7.62

Table 10-28. MMAP Thick Tray Physical Dimensions

Pocket Locations Symbol 8x8



Pocket-Pocket Cntr Distance X M2 10

Pocket-Pocket Cntr Distance Y M3 10




Tray Height Height 360



10.2 Environmental Programs Overview:

Intel continues to evaluate current packaging methodologies to ensure that we meet or exceed global regulatory compliance with regards to environmental concerns. Our philosophy focuses on eliminating redundant or mixed materials as appropriate, implementing reuse applications and increasing the recyclability of our component packaging material. This chapter also contains information for recycling of the transport media materials listed after each section. For the latest information regarding reuse or recycling programs call 1-800-628-8686.

10.2.1 Intel’s Shipping Media Reuse Programs 10.2.1.1 JEDEC Tray Reuse Program

Intel has been successful in establishing a program for reuse of our low/high temperature JEDEC Trays. Not only does the program offer a nominal cash reimbursement but it lowers the cost of plastic shipping trays, employs several handicapped agencies and reduces environmental waste. JEDEC trays can now be returned for reuse at Intel through a variety of methods. To ensure trays are returned in a usable condition, trays should be placed in corrugated containers and palletized if volumes warrant. All containers should be labeled with the return address. All trays are subjected to a variety of inspections to ensure they meet Intel’s specifications prior to reuse by an Intel factory. Non-Intel trays or trays that fail to meet Intel’s quality requirements are sent to plastic reclamation vendors for utilization in other plastic applications. No trays are sent to land fills.

10.2.1.2 Intel’s Die Sales and Gel-Pak Reuse Program

Intel utilizes Gel-Paks as a method for transporting bare die from Intel to the end customer. The Gel-Paks are placed in Moisture Barrier bags with a desiccant card to absorb moisture and sealed. Gel-Paks can be reclaimed and reused. The reuse program for Gel-Paks changes depending on the region and the volumes involved. Please contact your local sales representative for details on how to reuse this shipping media For further details on Intel’s wafer and die sales procedures, refer to Chapter 18 of this Intel Packaging Databook. . Further information on GelPaks are available at: www.gelpak.com

10.2.1.3 Reel Reuse Program

Intel has established a Reel Reuse Program and encourages the return of reels using recyclers. Contact your local sales representative for details on how to recycle the shipping media.


Figure 10-9. Carrier Tape

A5792-01240822-4

Section A-A

T

W

E1

A

A

Detail B

P1

Po

0.20 ± 0.05

Detail B

R 0.75 Max

250.00

100.001.00 Max

1.00 Max

Camber Detail

*R

Tape and Components WillPass Around Radius ShownWithout Damage.

*

Note: All Dimensions Are in Millimeters.


Shippng and Transport Media

Table 10-32. Carrier Tape Dimensions by Package

Package Type Tape Size E1

Single/Double

Sprocket PO P1 R T W Units/Reel

PLCC 20 LD 16 mm 1.65-1.85 Single 3.9-4.1 11.9-12.1 30 MIN .25-3.5 15.7-16.3 1000

28 LD (REC) 24 mm 1.65-1.85 Single 3.9-4.1 11.9-12.1 30 MIN .25-3.5 23.7-24.3 750

28 LD (SQ) 24 mm 1.65-1.85 Single 3.9-4.1 15.9-16.1 30 MIN .25-3.5 23.7-24.3 750

32 LD (REC) 24 mm 1.65-1.85 Single 3.9-4.1 15.9-16.1 30 MIN .25-3.5 23.7-24.3 750

44 LD 32 mm 1.65-1.85 Double 3.9-4.1 23.9-24.1 50 MIN .25-3.5 31.7-32.3 500

52 LD 32 mm 1.65-1.85 Double 3.9-4.1 23.9-24.1 50 MIN .25-3.5 31.7-32.3 500

68 LD 44 mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 50 MIN .25-3.5 43.7-44.3 350

84 LD 44 mm 1.65-1.85 Double 3.9-4.1 35.9-36.1 50 MIN .25-3.5 43.7-44.3 250

PQFP84 LD 32 mm 1.65-1.85 Double 3.9-4.1 27.9-28.1 50 MIN .25-3.5 31.7-32.3 500

100 LD 44 mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 50 MIN .25-3.5 43.7-44.3 300

132 LD 44 mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 50 MIN .25-3.5 43.7-44.3 250

TSOP32 LD 32 mm 1.65-1.85 Double 3.9-4.1 15.9-16.1 50 MIN .25-3.5 31.7-32.3 2000

40 LD 32 mm 1.65-1.85 Double 3.9-4.1 15.9-16.1 50 MIN .25-3.5 31.7-32.3 2000

48 LD 32 mm 1.65-1.85 Double 3.9-4.1 15.9-16.1 50 MIN .25-3.5 31.7-32.3 2000

56 LD 32 mm 1.65-1.85 Double 3.9-4.1 19.9-20.1 50 MIN .25-3.5 31.7-32.3 1600

PSOP44 LD 44 mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 89 MIN .25-3.5 43.7-44.3 450

SSOP56 LD 44 mm 1.65-1.85 Double 3.9-4.1 23.9-24.1 89 MIN .25-3.5 43.7-44.3 700

BGA 15 x 15 32mm 1.65-1.85 Double 3.9-4.1 19.1-20.1 50 MIN .25-3.5 31.7-32.3 850

23 x 23 44mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 89 MIN .25-3.5 43.7-44.3 360

27 x 27 44 mm 1.65-1.85 Double 3.9-4.1 31.9-32.1 89 MIN .25-.35 43.7-44.3 360

35 x 35 56 mm 1.65-1.85 Double 3.9-4.1 39.9-40.1 89 MIN .25-.35 55.7-56.3 360

µBGA 28F008S3 12 mm 1.65-1.85 Single 3.9-4.1 11.9-12.1 50 MIN .27-.29 11.9-12.3

All other µBGA package variations

24 mm 1.65-1.85 Single 3.9-4.1 11.9-12.1 50 MIN .32-.34 23.9-24.3

All Easy BGA Products

24mm 1.75±.1 Single 4.0±.1 12.0±.1 50 MIN .33±.02

24±0.3/-0.1

S-CSP 28F1602C3 24mm 1.75±.1 Single 4.0±.1 12.±.1 50 MIN .33±.02

24±0.3/-0.1

S-CSP 28F1604C3S-CSP 28F3202C3S-CSP 28F3204C3

24mm 1.75±.1 Single 4.0±.1 16.0±.1 50 MIN .33±.02

24±0.3/-0.1

NOTE: 1. Dimensions are in millimeters.



Figure 10-10. Carrier Tape Reel

10.4 Protective BandsTo provide additional protection for product shipped in carrier tape, protective bands are wrapped inside the edges of the carrier tape reels. These bands consist of 1mm-thick strips of carbon-loaded polystyrene.

Table 10-33. Carrier Tape Reel Dimensions

Millimeters 12mm 16 mm 24 mm 32 mm 44 mm 56 mm

A Max. 330 330 330 330 330 609

D Min 20.2 20.2 20.2 20.2 20.2 20.2

W2 Max. 16mm 22.4 30.4 38.4 50.4 62.4NOTE: 1. Dimensions are in millimeters.

A5793-01240822-5

DA

W2 (Measured at Hub)

Full R

Tape Slot in CoreFor Tape Start.2.5 Min. Width10 Min. Depth

Access Hole atSlot Location

40 Min.

Table 10-34. Protective Band Dimensions

Carrier Tape Size Protective Band Dimensions

24mm 24.2mm wide X 1.09 meters long





,

10.5 Shipping Formats

10.5.1 Desiccant Pack MaterialsAll PSMCs are shipped in desiccant pack. For a thorough discussion of the packing process (bake and bag) and handling considerations unique to PSMCs, refer to Chapter 8, “Moisture Sensitivity/Desiccant Packaging/Handling of PSMCs”.

Intel uses the following materials in desiccant pack:

• Moisture Barrier Bag (MBB). Inside the shipping box is a moisture barrier bag containing components. The opaque MMB is constructed of three layers: a conductive polyethylene inner layer for sealing, an aluminum film mid-layer, and a tyvek outer layer. The bag meets MIL-STD-81705 TYPE I for electrostatic discharge (ESD) and mechanical stability. The measured water vapor transmission rate (WVTR) of the bag is better than the MIL-STD requirements for moisture protection. A “warning” label on the bag outlines precautions that should be taken with desiccant-packed units. A desiccant barcade label is also affixed to the bag.

• Desiccant. Each MBB contains one or more pouches of desiccant to absorb moisture that may be present in the bag. The desiccant is supplied in one-unit pouches. The number of pouches required is a function of the bag surface area. GelPaks use 3x4" desiccant cards.

• Humidity Indicator Card (HIC). Each MBB contains a humidity indicator card. This card is a military-standard moisture indicator and is included to show the user the approximate relative humidity (RH) level within the bag. The HIC is reversible and can be reused.

• Labels. The desiccant barcode label (shown in Figure 10-11) mentioned above in the section on MBB, contains the date that the bag was sealed (MM/DD/YY). The remaining storage life of the units in the bag is determined from this date. The “warning” label attached to the outside of the MBB outlines precautions that must be taken when handling desiccant-packed units if they are to be kept dry.

• Shipping Box. The barcode label on the shipping box indicates that desiccant-packed material is included. This label indicates the seal date of the enclosed MBB, and thus, the remaining shelf life.

10.5.2 Shipping Boxes and CartonsIntel products are placed in tubes or trays, or on reels, then packed for shipment in a box made of corrugated fiberboard with an inner coating of conductive carbon that prevents electrostatic damage. Various materials, such as bubble wrap or antistatic foam end pads, are used for cushioning inside the box. Outer boxes are used for increased protection during shipping. All packing materials are either conductive, static dissipative, or antistatic, and meet the electrostatic discharge (ESD) requirements of EIA standard 541. All of the packing materials used can be

recycled by any local recycling company. If details about a recycler are needed in your specific area please contact your local Intel Field Sales Representative.



10-27 2004 Intel Packaging Databook

10.5.2 Shipping Boxes and Cartons (continued):

Tube and Reel Labels. Tube labels with information on lot traceability, part and spec numbers, quantity of parts, and ROM and PROM codes are available by special order. Reel labels are standard and provide the same information. Customer part number references also can be included on either type of label by special order.

• Box Labels. Bar-coded labels for each box are standard on Intel product shipments. Box labels provide all the information on the tube labels, show order packing and shipping information, and allow more space to define special requirements.

• The standard box and bag labels identify the parts as Pb-free (or with a 2nd Level interconnect that meets

the requirement to be ROHS compliant) with the type of interconnect material, the peak reflow temperatures of the component, the quantity of parts in the box, the lot, and the pack dates.

• See chapter 17 of this Databook for further information on Pb-Free package marking and labeling.

10.6 Revision Summary • Reviewed & updated tray information

• Reviewed & updated carrier tape information

• Removed recycler contacts and updated file (July 2004).

10.5.2.1

Figure 10-11

International Packaging Specifications 11

11.1 Electronic Industries Association of Japan (EIAJ)

EIAJ publishes the following rules and standards as they apply to the preparation of outline drawings of integrated circuits.

Number Nomenclature

ED -7300 Recommended practice on standard for the preparation of outline drawings of semiconductor packages

ED -7301 Manual or the standard of integrated circuits package

ED -7302 Manual for integrated circuits package design guideline

ED -7303 Name and code for integrated circuits package

ED -7304 Measuring method for package dimensions of ball grid array (BGA)

ED -7304-1 Measuring method for package dimensions of Small Outline Package (SOP)

ED -7304-2 Measuring method for package dimensions of Small Outline J-leaded package (SOJ)

ED -7305 Unit design guide for the preparation of package outline drawing of integrated circuits (gullwing-lead)

ED -7311 Standards of integrated circuits package

ED -7311-1 Standard of integrated circuits package [TSOP(1)]

ED -7311-2 Standard of integrated circuits package [TSOP(2)]

ED -7311-3 Standard of integrated circuits package [Tape Ball Grid Array 1.0mm pitch (T-BGA)]

ED -7311-4 Standard of integrated circuits package [Tape Ball Grid Array 1.27mm pitch (T-BGA)]

ED -7311-5 Standard of integrated circuits package [32/48 pins Fine-pitch Ball Grid Array (FBGA)]

ED -7311-6 Standard of integrated circuits package [60/90 pins Fine-pitch Ball Grid Array (FBGA)]

ED -7311-7 Standard of integrated circuits package [Plastic Fine pitch Ball Grid Array (P-FBGA)]

ED -7311-8 Standard of integrated circuits package [Plastic Fine pitch Ball Grid Array 0.8mm pitch (P-FBGA)]

ED -7311-9A Standard of integrated circuits package [P-BGA (Cavity up type)]

ED -7311-10A Standard of integrated circuits package [P-BGA (Cavity down type)]

ED -7311-11A Standard of integrated circuits package (119/153 pins P-BGA)

ED -7311-12 Standard of integrated circuits package (52 pins 64 pins 80 pins and 100 pins low-profile quad flat package with exposed heatsink)

ED -7400 Standards for the dimensions of semiconductor devices (integrated circuits)

ED -7400-1 Standards for the dimensions of semiconductor devices (integrated circuits)

ED -7400-2 Standards for the dimensions of semiconductor devices (integrated circuits)

ED -7401-4 Method of measuring semiconductor device package dimensions (integrated circuits)

ED -7405 General rules for the preparation of outline drawings of integrated circuits zigzag in-line packages (ZIP)

ED -7405-1 General rules for the preparation of outline drawings of integrated circuits shrink zigzag in-line packages (SZIP)


International Packaging Specifications

11.2 Joint Electron Device Engineering Council (JEDEC)

JEDEC Publication 95 lists all package outlines. More information about JEDEC can be located on their web site at http://www.jedec.org.

ED -7406A General rules for the preparation of outline drawings of integrated circuits small outline J-lead packages (SOJ)

ED -7408A General rules for the preparation of outline drawings of integrated circuits pin grid array packages (PGA)

ED -7414 General rules for the preparation of outline drawings of integrated circuits guarding quad flat packages (GQFP)

ED -7415 General rules for the preparation of outline drawings of integrated circuits small outline packages with heat sink (HSOP)

ED -7417 General rules for the preparation of outline drawings of integrated circuits bumpered quad flat packages (BQFP)

ED -7418 General rules for the preparation of outline drawings of integrated circuits glass sealed quad flat packages (QFP-G)

ED -7419 General rules for the preparation of outline drawings of integrated circuits glass sealed dual in-line packages (DIP-G)

ED -7421 General rules for the preparation of outline drawings pf integrated circuits ceramic dual in-line packages (DIP-C)

ED -7422 General rules for the preparation of outline drawings of integrated circuits glass sealed quad flat J-leaded packages (QFJ-G)

ED -7423 General rules for the preparation of outline drawings of integrated circuits ceramic quad flat J-leaded packages (QFJ-C)

ED -7431-1A Recommended outline drawings for carriers quad tape carrier packages (QTP carrier)

ED -7431A General rules for the preparation of outline drawings of integrated circuits quad tape carrier packages (QTP)

ED -7432 General rules for the preparation of outline drawings of integrated circuits dual tape carrier packages (type1) (DTP(1))

ED -7433 General rules for the preparation of outline drawings of integrated circuits dual tape carrier packages (type 2)

ED -7441B Standard for the package of universal memory devices

ED -7500A Standards for the dimensions of semiconductor devices (discrete semiconductor devices)

EDR-7311 Design guideline of integrated circuits for quad Flat package (QFP)

EDR-7312 Design guideline of integrated circuits for thin small outline package (type1)

EDR-7313 Design guideline of integrated circuits for thin small outline package (type 2) (TSOP2)

EDR-7314 Design guideline of integrated circuits for shrink small outline package (SSOP)

EDR-7315A Design guideline of integrated circuits for ball grid array (BGA)

EDR-7316 Design guideline of integrated circuits for Fine-pitch Ball Grid Array and Fine-pitch Land Grid Array (FBGA/ FLGA)

EDR-7317 Design guideline of integrated circuits for Surface Vertical Package (SVP)

EDR-7318 Design guideline of integrated circuits for plastic very thin small outline non-lead package (P-VSON)

EDR-7319 Design guideline of integrated circuits for quad flat J-lead packages (QFJ)

EDR-7320 Design guideline of integrated circuits for small outline package (SOP)

EDR-7601 Guidance of embossed carrier taping for integrated circuits


International Packaging Specifications

11.3 Mil Standards

The following military standards include specifications required to meet U. S. Military requirements.

• MIL-M-38510 General Specifications for Microcircuits

• MIL-STD-883 Test Methods/Procedures for Microelectronics

11.4 Semiconductor Equipment and Materials Institute, Inc.

For a list of SEMI standards, reference the Book of SEMI Standards, 1990, Vol.4, Packaging Division, 605 E. Middlefield Road, Mountain View, CA 94043, U.S.A. Phone:(415) 964-5111. FAX: (415) 967-5375. TELEX: 856-777 SEMI-MNTV

11.5 Interconnecting and Packaging Electronic Circuits (IPC) Standards

Number Nomenclature

ANSI/IPC-S-815B General requirements for soldering electronic connections

ANSI/IPC-SM-780 Component packaging and inter-connecting, with emphasis on surface mounting

ANSI/IPC-SM-782 Surface mount land patterns

ANSI/IPC-SM-786 Impact of moisture on plastic I/C package cracking

For a list of additional IPC standards, contact: IPC, 7380 N. Lincoln Ave., Lincolnwood, Illinois, 60646. Phone: (708) 677-2850.


of

ustry

. eeting

n nent

l’s ite tions

Tape Carrier Package 12

12.1 Introduction To The Package Technology

As semiconductor devices become more complex they are being introduced into products that cover the spectrum of the marketplace. Portability of computing and information management is driving the reduction in size from desktop to laptop to notebook to palm top sized products. These products, require lightweight small footprint integrated packaging.

The Tape Carrier Package (TCP) format is one way to meet the small outline and high leadcount interconnection needs of high performance microprocessors. The TCP has been designed to offer reduced pitch, thin package profiles, smaller footprint on the printed circuit board, without compromising performance. Intel continues to provide packaging solutions which meet rigorous criteria for quality and performance. The Tape Carrier Package is no exception. Key package features include surface mount technology design, lead pitch of 0.25 mm, 48 mm tape format, polyimide-up for pick and place, and slide carrier handling. Shipped flat in slide carriers, the leads are designed to be formed into a “gull-wing” configuration and reflowed onto the PCB by oneseveral methods. Intel has done extensive optimization of the hot bar reflow process and suggestions for that process are included in this chapter. Satisfactory placement and reworkcapability has been demonstrated by industry sources using the hot gas reflow process. Inddata also exists which demonstrates process feasibility for laser reflow.

The TCP family has been characterized for thermal, electrical, and mechanical performanceComponent and system level thermal testing has shown the TCP package to be capable of msystem level thermal design needs. Additional potential board level enhancements have beeidentified and characterized to provide the most flexible design choices. A full suite of compoand board level stress testing has been completed to ensure that the component meets Intereliability targets. Evaluations of solder joints by stress testing, lead stiffness studies, and finelement modeling have demonstrated that the mounted component will meet field use condiand lifetimes. The TCP package is capable of meeting a wide variety of design and use applications. Table 12-1 provides an overview of TCP package attributes.

Table 12-1. Plastic Package Attributes

Tape Carrier Package (TCP) Attributes

Lead Count 320

Sq/Rect. S

Lead Pitch (mm) 0.25


Weight (gm) 0.5

Max. Footprint (mm) 24.0

Shipping Media:

Tubes X

Comments/Footnotes TCP components are shipped flat in slide carriers to protect the leads. The carriers are shipped in polyethylene sleeves which hold up to 50 carriers.


Tape Carrier Package

in

e act

be g

can ar” to

hown

12.2 Package Geometry And Materials

12.2.1 Package Materials

The TCP component consists of the device interconnected to 3 layer (carrier film, adhesive, and metal) Tape Automated Bonding (TAB) tape. The tape carrier film is polyimide and an advanced epoxy-based adhesive system is used. The interconnects are copper. The tape metallization, including the Outer Lead Bond (OLB) area of the interconnections, is gold plated over a nickel flash. The silicon chip and Inner Lead Bond (ILB) area is encapsulated with a high temperature thermoset polymer coating. The backside of the chip is left uncoated for thermal connection to the printed circuit board (PCB). While lower lead count TAB devices are often shipped in tape and reel format, Intel has chosen to ship components as individual devices. The individual units are shipped in high temperature plastic slide carriers packed in coin stack tubes.

12.2.2 Package Outline Drawings

Figure 12-1 through Figure 12-6 show the outline drawings for a 24 mm TCP component and its slide carrier. The TCP package meets JEDEC outline specification UO-018 for tape format, lead length, and test pads. The carrier conforms to JEDEC criteria for handling media. One TCP component debussed, singulated, and in the carrier is viewed from the topside of the carrier and bottomside of the tape in Figure 12-1. This is the test pad side.

The opposite side view—topside of tape, topside of die, and bottomside of the carrier is seenFigure 12-2.

The tape is in 48 mm format and includes test pads outboard of the OLB window (see Figure 12-3). Pads are 0.5 mm x 0.65mm on 0.40 mm pitch on two rows.

A cross section view of the TCP package is illustrated in Figure 12-4. The “five-sided” encapsulant covers the top surface of the device, the sides of the device, and the ILB area to the polyimidcarrier ring. The tape bow or offset across the polyimide carrier film is product specific. ContIntel Corporation for additional information. After forming and mounting to the PCB, the total height of the component above the PCB is less than 0.75 mm.

Details of the tooling holes can be seen in Figure 12-5. Intel uses the tooling holes shown in the upper left and lower right of Figure 12-1 for alignment during processing at Intel and should not used during board assembly. The other two tooling holes have been left pristine for use durinboard assembly.

The OLB window has been designed to facilitate excise and form. The polyimide carrier filmbe cut and a narrow strip left in place at the outer edge of the OLB area to act as a “Keeper Bmaintain lead coplanarity, and spacing, if so desired. The detail of the OLB Window area is sin Figure 12-6.



Figure 12-1. One TCP Site in Carrier (Bottom View of Die)

A5698-01272588-1

ToolingHoles#1 And #3Used ForIntelAssemblyProcess

Not ForUse InBoardAssembly

Pin # 1

63.00 ± 0.15

5.00 ± 0.05

63.00 ± 0.15

DIEBACKSIDE



Figure 12-2. One TCP Site in Carrier (Top View of Die)

A5699-01272588-2

Pin # 1

63.00 ± 0.15

33.00 ± 0.05

–B–

33.00 ± 0.05 –A–

51.00

36.15

0.10 SBSM A4X 01.925 ± 0.05

ø0.05 SBSM A3X R2.50 ± 0.05

36.15ENCAP

Polyimide Tape

OLB Area



Figure 12-3. One TCP Site (Bottom View)

Figure 12-4. One TCP Site (Cross-Section Detail)

A5700-01272588-3

Test HolesFor Intel UseOnly

21.90 ± 0.06DIE

BACKSIDE 36.15 ± 0.05

48.18 ± 0.12

21.90 ± 0.06

36.15 ± 0.05

(43.94)

4.75

A5701-01272588-4

0.430

0.560 ± 0.050

0.130 ± 0.040

(Die)

(Encap)

A2 Lead Thickness (LT)

0.125 ± 0.015(Polyimide)



Figure 12-5. One TCP Site (Top View)

A5702-01272588-5

28.50 ± 0.10

ENCAP

20.57 ± 0.10

22.59 ± 0.10

2x 24.00 ± 0.10

2x (30.00)

Top View

Tooling Hole DetailDetail A

4 x 1.72 ± 0.03(Polyimide)

2 x 1.42 ± 0.03(Copper)

4 x 0 0.60 ± 0.03

4 x 0 0.40 ± 0.03

Test Hole Detail(Intel Use Only)

Detail B

See Detail A

See Detail B



Figure 12-6. OLB Window Detail

12.2.3 Key Aspects of the Package Family

12.2.3.1 Package Weight

The 320 lead 0.25 mm TCP component weighs a maximum of 0.5 grams for the 24 mm body size component. In comparison, a 296 lead multilayer PQFP package weighs 9.45 grams. This makes the TCP package family extremely attractive for weight constrained applications.

Table 12-2. TCP Key Dimensions

Symbol Description Dimension (mm)

A2 Package Height Varies by Product. See Product Data Sheet

b Outer Lead Width 0.10 +/- 0.01

D1, E1 Package Body Size 24.0 +/- 0.1

DL, EL Die/Encap Length Varies by Product. See Product Data Sheet

DW, EL Die/Encap Width Varies by Product. See Product Data Sheet

e1 Outer Lead Pitch 0.25 nom

L Site Length (43.94) ref.

N Lead count 320 leads

W Tape Width 48.18 +/- 0.12

Table 12-3. Mounted TCP Package Dimensions

Symbol Description Dimension

A Package Height 0.75 max.

D, E Terminal Dimension 29.5 nom.

WT Package Weight 0.5 g max.

NOTES: 1. Dimensions are in millimeters unless otherwise noted.2. Dimensions in parentheses are for reference only.3. Package terminal dimension (lead tip-to-lead tip) assumes the use of keeper bar.

A5703-01272588-6

0.25 Ref

12.00 2.25

(Encap)

(Device Window)1.06

0.10 ± 0.01



I/O the d to

tter ical

12.2.3.2 Use Applications

The TCP package is designed for use with applications where height, footprint, and weight are tightly controlled. Because of the tight pitch of the component, 0.25 mm, the recommended board assembly process for TCP is localized reflow, either by hot bar, hot gas, or laser. Mass reflow processes such as infrared, convection, or vapor phase reflow processes may be difficult to control at these pitches. Intel has developed a suggested process for localized reflow, specifically by hot bar thermode. Process envelope suggestions for hot gas reflow are available and have been determined through direct external development efforts between Intel and industry sources. Solder finish on the land pattern on the PCB can be used in lieu of screened or syringe dispensed solder paste.

12.2.3.3 TCP Component Assembly Process

The basic assembly flow used to form TCP packages is shown in Figure 12-7. There are several methods of forming TAB-based packaging technologies. To achieve the highest reliability joint between the silicon and the TAB tape, Intel creates gold “bumps” on the wafer surface at thepads. This bumping process is a wafer fabrication process. Barrier metals are sputtered ontoactive surface of the wafer. Photoresist is applied, patterned and exposed and then developeopen areas for plating up the “bump”. The resist is stripped from the surface, the excess spumetal film is removed by etching and the gold bumps are annealed to optimize the metallurgproperties of the bump for subsequent bonding processes.



f the ILB

Figure 12-7. Tape Carrier Package Assembly Process Flow

In parallel with the bumping process, TAB tape sites are manufactured in reel-to-reel format. Polyimide carrier film with an adhesive in reel form, is punched to create the Inner Lead Bond (ILB) and Outer Lead Bond (OLB) windows and tooling holes for subsequent processing steps. Copper foil is laminated onto the polyimide and cured. Again, a photolithographic technique is used to create the specific pattern of metal leads and test pads. Once the tape metal pattern has been created, the exposed copper metal is plated with a Ni barrier metal and Au outer plating. Au outer plating is used for the entire tape interconnect path; both ILB and OLB lead areas are plated with gold. Intel has done extensive testing of the solder joint reliability of nickel-gold plated leads.

The silicon and the TAB tape are brought together at the TCP package process. After the wafers are sawn into individual devices, the TAB tape sites are matched to the device. During Inner Lead Bonding, the ILB area of the tape is aligned to the bumps on the device. They are brought into contact and a gold-to-gold weld is formed. This process establishes the silicon to PCB interconnection path. After ILB, the component sites are singulated from the reel, the tape plating bars are “debussed” from the tape, and the individual component sites are loaded into ESD protective slide carriers (see Figure 12-1 and Figure 12-2). Once in slide carriers, the devices areencapsulated in a high temperature polymer coating. The coating covers the top and sides osilicon, the bumps, and the ILB area to the polyimide carrier ring. Complete coverage of the area provides mechanical support to the ultra-fine pitch leads, protecting them from handling

A5704-01

Fabrication of Bumped Silicon Devicesin Wafer Format

Sputter

Coat

Expose

Develop

Descum

Plate

Strip

Etch

Anneal

Tape Manufacture in Reel to ReelFormat

Punch Polyimide/Adhesive Film

Laminate Copper Foil

Coat With Resist

Expose

Develop Reset

Etch Interconnects

Strip Resist

Au/Ni Plate

Tape Carrier Package Assembly

Saw Wafer

Reel-To-Reel ILB

Singulate/Debus/Slide Carrier Load

Encapsulate

Quality Control

Electrical Test

Pack in Coin-Stack Sleeves



damage and thermomechanical stress induced damage. The thermoset polymer is cured to ensure a high enough cross-link density to fully protect the device from environmental degradation. After quality control checks and electrical test, the components are ink marked, packed, and shipped. The components are shipped flat in slide carriers. This ensures that the outer lead area is undamaged at the time of board mount processing.

12.3 Shipping Media

The TCP components are shipped flat in slide carriers to protect the component leads. The tape sites are already debussed when in the slide carrier, therefore, the carrier is made of an intrinsically dissipative material for ESD protection. The carriers are molded of high temperature polymer and are suitable for hot and cold electrical test. The carriers meet JEDEC Outline CO-018 as shown in Figure 12-2. The carriers are shipped in polyethylene sleeves (also called coin stack tubes) which hold up to 50 carriers. The shipping tubes meet JEDEC outline CO-017 as shown in Figure 12-8. Figure 12-9 shows the detail of the tube in cross section.

For recycling information, contact Micro Plastics, Phoenix, Arizona.

Ship to:

Micro Plastics 3420 West Whitton Ave.Phoenix, AZ 85017Phone: (602) 278-4545Fax: (602) 278-4477

Contact Micro Plastics for specific Intel shipping instructions for your area.

Bill Shipping Costs to:

Intel Corp. C/O NWTA PO Box 4567Federal Way, WA 98063



Figure 12-8. Coin Stack Tube (Side & End Views)

A5705-01272588-7

End View A-A

Side View

294.00 ± 1.50

2x 7.62

1.20 ± 0.13 A

A



For

reflow P l has

Figure 12-9. Coin Stack Tube (Cross-Section Detail)

12.4 Handling: Preconditioning and Moisture Sensitivity

INTEL DOES NOT RECOMMEND SUBJECTING THE TCP PACKAGE TO ANY TYPE OF MASS REFLOW PROCESS. THE PACKAGE WAS NOT CHARACTERIZED FOR MASS REFLOW PROCESSES.

At this time Intel suggests hot bar and hot gas reflow processes that do not subject the component body to reflow temperatures. There is no jeopardy with moisture sensitivity when using these localized reflow processes. The TCP package has met all reliability requirements after exposure to the hot bar mounting process. Therefore, the TCP components are shipped without desiccant packing materials. There are no “out of bag” shelf life restrictions prior to component mount. additional information contact your Intel representative.

12.4.1 Suggested Process Flow

It is suggested that the TCP component be mounted using either a hot bar, hot gas, or laserprocess after all other board components have been completed, including cleaning. The TCcomponent mount can be accomplished in a number of different ways. The process that Intethe most direct experience with is illustrated in Figure 12-10. Note that lead form and hot bar reflow soldering are mounting options.

A5706-01272588-8

2.75 Max

25.50± 0.50

64.50 ± 0.50

64.5

0 ±

0.50

70.80 ± 0.25

70.8

0 ±

0.25

78.40 ± 0.25

78.4

0 ±

0.25

7.5 x 45˚ Chamfer

10 x

45˚

Cha

m.

3.00

± 0

.30



low. etric. o the

kage lead

nt d,

he d that

as

help

Figure 12-10. Suggested Process Flow

12.4.2 Land Pattern Design

The TCP land pattern varies depending on specific process conditions and lead form dimensions. Some general guidelines and a land pattern developed for Intel’s internal hot bar process folNote that the TCP is a metric package and that the land pattern should be dimensioned in mConverting dimensions to the English system can result in gross mis-match of the package tlands.

12.4.3 Solder Lands

Figure 12-17 shows the suggested land pattern for a 0.25 mm Tape Carrier Package. All pacdimensions are “as finished” and not necessarily the designed dimensions. For the 0.25 mmpitch component land pattern, the lands should be 0.125 mm + 0.025 mm in width with a land length = 2.5mm. A minimum land length of 2.25mm is suggested to avoid potential solder joireliability problems. A minimum spacing between land pads of 0.10 mm should be maintainemeasured at the copper/laminate interface. See Figure 12-11.

The land length should be long enough to allow a solder fillet to form at the toe and heel of tlead. To prevent a starved joint or excess gold concentration in the solder joint it is suggestethe total solder volume of the land and the resultant solder joint be greater than 0.004 mm3. The land pattern terminal dimension is defined as the distance from outer land edge to land edgeillustrated in a sample land pattern in Figure 12-13. This dimension is based on the lead toe location from center, the incremental land length allowed for solder fillet formation, and the tolerances. Generally, this is approximately 1.0 mm longer than the toe-to-toe dimension. Additionally, it is suggested that trace connection to lands be “necked down” by 0.013mm toeliminate “solder thieving” during reflow.

A5707-01

Parts Are Received in Coin Stack Tubes of 50 Each

Coin Stack Tubes Are Loaded Into The Assembly Equipment.

Parts Are Cut Out of The Carrier And Leads Are Formed

Flux Material is Dispensed on The TCP Leads or The TCP Site.

The Die Backside is Placed Into The Preapplied Die Attach Material, Attaching it to The Board.

Parts Are Immediately Soldered to The Board Using One of The Available Reflow Processes.



Figure 12-11. Land Width Specification

Figure 12-12. Solder Thickness Specification

A5708-01272588-18

Cu

125 ± 25 µmTop

125 ± 25 µmBottom

100 µmMin. Bottom

Between Copper

Land Width SpecificationThis Specification Applies to the Copper Geometry Only

(Before Solder Application)

Cu

A5709-01272588-19

Crest Height of Solder Finish

15 µm Minimum (Not to Scale)

Solder Crest Height Specification

This Specification Applies to Solder Crest Height After Reflow

CuCu

Solder



e a die

et.r Au

ds so as and

round

Figure 12-13. Sample Land Pattern for a TCP with 24 mm Body Size for Use with a Hot Bar Reflow Process

12.4.4 Land Pattern Solder Finish

The TCP component site should be finished with eutectic tin-lead solder (63/37) to a thickness sufficient to form acceptable fillets (reference IPC-SM-780). The thickness requirement may vary with reflow process, but in general the minimum solder thickness for reliable joint formation is 15 micrometers as measured at the crest of the reflowed land. Figure 12-12 shows the location of the crest height measurement. See Section 12-7 for a discussion of solder joint reliability as a function of component OLB metallurgy and solder finish on the land. See the section on Mechanical Behavior for a discussion of solder joint reliability as a function of component OLB metallurgy and solder finish on the land.

12.4.5 Die Attach Pad

Because Intel’s TCP components require backside thermal contact, it is necessary to providattach pad metallization area. The die attach pad should be 7.5 + 0.025 mm larger than the device in both X and Y directions to allow for placement tolerance and the formation a die attach fill The Die Attach Pad area must be metallized to obtain optimal thermal contact; either SnPb ometallization is acceptable.

12.4.6 Solder Mask

If solder mask is used on the board, then there should be adequate pull-back around the lannot to restrict the movement of the thermode or hot gas head in the Z-direction when placingreflowing the TCP component. In general, if the design permits (for example, if this area is not used for routing), then it is suggested that a square “donut” of solder mask clear area be left athe TCP lands and fiducials. A sample solder mask clear area is illustrated in Figure 12-14.

A5710-01272588-9

0.125Land Width

[Measurements in mm]

Land Pattern Terminal Dimension29.0

0.25Land Pitch

2.50Land Length

29.0

1.00 0 TypFiducial Dia.

Die Size + 7.5mm

Die Attach Pad



12.4.7 Fiducials

The ultra fine pitch of these components may require that pattern recognition systems be used to accurately locate the lead and the land. To facilitate the pattern recognition algorithms it is recommended that PCB lands have fiducials associated with each TCP site. Each equipment type will have specific requirements for fiducial configurations. For KME equipment, round fiducials of 0.3mm in diameter located on adjacent corners (same side of the site) are suggested. For Universal Instruments or Zevatech equipment, Surface Mount Equipment Manufacturers Association (SMEMA) Std. 3.1 compatible fiducials 1.0 mm (39 mil) in diameter should be placed at all 4 corners of the TCP site; at least 2 fiducials in opposite corners are required. Other equipment manufacturers may have other requirements. Please verify fiducial design requirements with the equipment supplier before finalizing board designs. A possible fiducial position is shown in Figure 12-13. They should be located within the terminal dimensions of the land pattern and equally spaced from the centroid of the site. The contrast of these fiducials is critical to providing adequate edge contrast. Therefore, the finish and finish morphology should not change during reflow processes. For example, Au or Sn are acceptable. Solder mask should be pulled back from the edge of the fiducial by 20 mils (SMEMA 3.1) to maximize Pattern Recognition System effectiveness. Figure 12-14 shows the solder mask pull back and the fiducials for a TCP land pattern site.

Figure 12-14. Solder Mask Clear Area

12.4.8 PCB Vias Design Rules

12.4.8.1 Interconnect Vias

Vias and connected pads placed too close to the TCP lands can sink heat away from the TCP component lands during localized reflow, resulting in longer process times. Additionally, if via pads or lands (connected or unconnected) are too close to the TCP lands, they can draw solder away from the TCP lead land resulting in a solder-poor joint. For this reason, it is suggested that vias be placed no closer than 0.65 mm (25 mils) from the edge of the lands.

A5711-01272588-10

Solder Mask

Lands

Clear Area

Fiducials

Die Attach Pad

1.25 mm ± 0.125 mm (8x)

0.23 mm ± 0.125 mm (8x)



area.

low s

p out” of the board he

out w for ain

ce in

12.4.8.2 Thermal Vias

Thermal vias in the die attach pad area can enhance heat transfer away from the die into and through the PCB where further heat spreading and transfer can be achieved. When designing the thermal via pattern, the tradeoffs between low thermal resistance and manufacturability (cost) must be considered. A full grid array provides the best heat transfer. Large, unfilled vias may cost less at the board fabrication level, but may also require special processing at board assembly to keep the die attach material from seeping through the holes. Either 100 percent open vias or 100 percent filled vias are best for manufacturability because they provide a consistent surface for the die attach medium. Thermal via design issues are discussed in the Package Performance section.

Traces can be routed on the signal layers between the thermal vias, however, this area of the board can get to near 100° C. This should be considered before routing critical traces through this

12.4.8.3 Lead Guard Hole Size

For those who want to protect the device after mounting, Intel has developed a light weight, profile and low cost TCP cover called a Lead Guard. This device is attached with snap fit pinwhich can be inserted into holes in the PCB. Hole size and location are shown in Figure 12-15. See the description of a sample lead guard design in the Mechanical Behavior section.

12.4.9 Keep-out Areas

Since TCP component assembly is the last process in the board assembly flow, certain “keeareas-areas that must remain clear of other components-are defined to allow for placement TCP component. A clear area must be left on the side opposite the TCP site to allow for theto be supported from the bottom side during the localized reflow (hot bar, hot gas) process. Tspecific pedestal (under-board support) design will dictate the exact dimensions of the keep area, but in general, a square area directly site-opposite the TCP should remain clear to alloTCP manufacturing and thermal enhancements. Additionally, sufficient clear area should remaround the TCP site to allow the reflow head to place the TCP component without interferenthe Z-direction.



Figure 12-15. Hole Size and Location Illustration for a 24 mm Body Size TCP Lead Guard

Table 12-4. Suggested Land Pattern Parameters

Land Pitch 0.25 mm

Land Width 0.125 (0.025 mm

Land Length 2.5 mm (2.25 mm minimum)

Land Pattern Solder Finish

Solder Composition

Solder Thickness

63/37 SnPb

15 micrometers minimum, measured at the crest of the reflowed land

D/A Pad

Size

Via Diameter

Via Location

Die Size + 7.5 mm (75 mil free area around periphery for wet-out)

13.5mils

Center of Vias should start 0.65 mm (25 mils) from the edge of the pad.

Fiducials

Size (Diameter)

Location

1 mm (39 mils) for Universal and Zevatech. 0.3 mm for KME equipment.

Minimum 2 cross-diagonal corners of the TCP site located within the terminal dimension of the land pattern for Universal and Zevatech equipment. Minimum of 2 adjacent side corners of the TCP site for KME equipment.

Solder Mask

Clear area around entire Land Pattern and Fiducials.

1.25 mm + 0.125 mm pull back from the edges of the land pattern and 0.23 + 0.125 mm from the ends of the lands.

Fiducials should be clear of Solder Mask.

NOTE: 1. Land Patterns should be dimensioned in metric.

A5712-01272588-20

0.554"

0.554"

1.108

TCP Center

0.070" ± 0.002" Dia (2x)(Finished Size, Unplated)

1.108"

± 0.008"(Max. True Position Tolerance)



e rial

fic

er and s tape ould

and e . The portion

12.4.10 Package-to-Board Assembly

Intel has demonstrated mounting a Ultra Fine Pitch TCP package to a substrate with a hot bar gang bond process. The hot bar process is a combination of the following processes:

1. Excise and Form

2. Die Attach Dispense

3. Fluxing

4. Placement and Alignment

5. Solder Reflow

12.4.10.1 Excise And Lead Form

Intel has developed the following lead form process which can be used as a starting point for the customer’s own development effort. The lead form dimensions may differ depending on the subcontractor or manufacturing site used. A no-form process has been demonstrated by sommanufacturers in the industry, but Intel has neither experience with nor reliability data on thismethod and can make no suggestions for it at this time. Please note that the die attach matedispense pattern bond line thickness suggestions which follow were developed for the specileadform profile shown in Figure 12-16.

TCP lead forming is a three step process which removes the component from the slide carriexcess carrier film, cuts the leads from the support structure, and bends the lead to specifiedconfiguration and dimensional accuracy. Excise, or removal of the component from the excesoccurs immediately prior to fluxing and component placement. The recommended tool set shcut the leads free of the tape and then bend them into a modified “gull-wing”. Although not required, a “keeper bar” or strip of polyimide carrier ring can be used to maintain coplanaritylead spacing during fluxing and placement. The keeper bar is a narrow strip of the carrier tapwhich is cut during the trim operation and remains in place on each row of leads after exciseexcise operation, itself, removes the device area and leaves the test pad and sprocket hole of the tape in the slide carrier. Figure 12-16 shows a recommended lead form configuration. Keyitems are tabulated in Table 12-5.



Figure 12-16. Sample Lead Form Configuration

It is necessary that sufficient distance between the bottom of the silicon device and the die attach pad be built into the leadform to allow for die attach material to attach the device to the board. A thermally conductive die attach medium is used to ensure optimum performance of the device. A suggested die attach material and processing flow are discussed in the next section.

Intel engineers have assessed several different lead form radii for shoulder, heel, and toe angles. To eliminate cracks in the outer plating of the lead which expose the copper base metal, a radius of at least 0.15 mm is suggested.

12.4.10.2 Die Attach for Backside Bias and Thermal Dissipation

Intel has selected a thermally conductive die attach material specifically for use with TCP components for printed circuit board applications. This material, Ablebond* 8380, is a silver-filled thermoset polymer. Intel suggests a cure profile of 6 minutes above 130° C.

A5713-01272588-11

12˚ ± 12˚

(0.90)

0.29

0.50

2x R0.175± 0.025

0.30

0.52

0.37

0.060

Lead Thickness (LT)

(0.125) Polyimide

12.7

4

13.6

4

14.2

2

14.3

2

35 ˚+10˚-05˚

Table 12-5. Key Lead Form Dimensions

Controlled Dimension Recommended Range

“Stand-Off” or “Set Back” of Die above Die Pad 0.035 mm to 0.085

Lead Foot Length Minimum 0.90 mm

Lead Foot Angle 0°

Keeper Bar Toe Angle 30° to 45°

Keeper Bar Width 0.5 mm

Toe Radius 0.15 mm (min.)

Heel Radius 0.15 mm (min.)

Lead Shoulder Length 0.3 mm

Lead Shoulder Radius 0.15 mm (min.)

* Other brands and names are the property of their respective owners.



ive

ed by

nd

n is ner.

and

ed

Electrically conductive, this material was selected for its thermal conductivity and mechanical performance characteristics.

Several die attach materials are available commercially for use as thermally conductive, electrically non-conductive adhesives. These materials may be adequate substitutes for a thermally and electrically conductive die attach material. For additional information on these materials contact your local Intel representative and request the applications note “Thermally ConductAdhesives.”

Alternate materials which meet these criteria may be available but have not been characterizIntel.

12.4.10.2.1 Handling Ablebond* 8380

Ablestik’s Ablebond* 8380 die attach adhesive should be stored frozen at the Ablestik recommended temperature of -40° C. Prior to use, the material should be removed from coldstorage and allowed to thaw to room temperature. The Ablestik recommended thaw times atemperatures for different adhesive containers is shown in Table 12-7.

Containers of Ablebond* 8380 that appear to have separated should not be used. Separatiovisually observable as a band of color (yellow or amber) along the length or top of the contai

To maintain high quality performance, adhesive dispensed from an unstirred reservoir (10 ccsmaller) must be completely used within a 24 hour period.

All pastes must be used in a 24 hour period from the time the syringe is opened. Any thawedadhesive not required for production should be returned to the freezer immediately. Any thawadhesives not used (not opened in a 24 hour period) may be refrozen once. Contact Ablestikdirectly for maximum recommended time between dispense, placement and cure.

A typical 7-step preparation procedure is shown below.

1. Remove syringe from freezer.

2. Thaw syringe at room temperature (23° C-27° C) for 1.5-2 hours.

3. Remove plunger from syringe.

4. Stir or mix the material. Contact Ablestik directly for more information.

5. Attach needle to the syringe.

Table 12-6. Baseline Material Properties for Thermoset Die Attach

Viscosity (5 RPM) Brookfield 10 ± 2 kcps

Thermal Conductivity > 2.00 w/mk

Typical Material Composition Silver-filled polymer

Rework Temperature ≤ 260°C

Cure Process Profile 130°C for 6 minutes

Table 12-7. Recommended Thaw Times and Temperatures for Different Containers and Container Sizes of Ablebond* 8380 (Courtesy Ablestik)

ContainerSize

Container Type

Recommended Thaw Time (Hours)

Recommended Thaw Temp (°C)

≤ 10 cc Syringe 1.5-2 23-27

≤ 1 lb Jar 2-3 23-27



ense, ay vary

owing

e

re bond l via

30° file

6. Insert syringe assembly into die attach subsystem.

7. Purge needle for 45-60 seconds.

Follow all manufacturer’s suggestions for use.

12.4.10.2.2 Dispense Methods

One of several different dispense methods may be used including needle time/pressure dispstamp dispense, positive displacement pattern dispense, etc. Dispense method and pattern mdepending on thermal via design, and should be developed by the customer to meet the follcriteria for a reliable die attachment. The bondline defined in Table 12-8 was developed for the leadform described in Figure 12-16. The percentage of voiding in the bondline directly affects ththermal performance, therefore voiding should be minimized.

Reference material dispense parameters for Ablestik Ablebond* 8380 are listed in Table 12-9, and a reference pattern for a die size of 13.302mm x 12.235mm and a single needle time-pressudispense system is illustrated in Figure 12-17 and Table 12-10. Further process development maybe required to optimize the amount of material dispensed in order to minimize voids, controlline thickness, and control fillet height. Dispense patterns should be verified for each thermapattern.

Figure 12-18 illustrates the low temperature cure profile used at Intel. This profile was set at 1C maximum temperature as a compromise between snap cure and the need to keep the probelow the glass transition temperature of a majority of PCB materials.

Note: THE PARAMETERS IN TABLE 12-9 ARE EVALUATION SETTINGS ONLY. VALUES WILL CHANGE DEPENDING ON SEVERAL FACTORS INCLUDING DIE PAD VIA PATTERN, DIE PAD PLATING TYPE, EQUIPMENT SET AND EPOXY VISCOSITY.

Table 12-8. Die Attach Acceptance Criteria

Post-Dry Bondline Thickness 0.025 mm to 0.095 mm

Device Tilt after Dry ≤ 0.05 mm

Table 12-9. Intel Developed Time/Pressure Dispense Parameters

Needle Size 20 gauge

Syringe Pressure 6 psi

Line Speed 5.5 mm/sec

Dot Time 0.3 sec

Needle Standoff 0.55 mm

Withdraw Speed 1.0 mm/sec

Withdraw Height 10 mm

Pre-Movement Delay 0 sec

Pre-Stopping Delay 0.3 sec



Figure 12-17. Basic Dispense Pattern Locations for Die Attach Material

This pattern provides baseline information for process development. The pattern requires verification by the board level assembly site.

A5714-01272588-12

Die Outline

Die Attach Material

Table 12-10. Sample Die Attach Medium Dispense Pattern: 24 mm Body Size Component and 13.302 x 12.235 mm Die Size Component

STEP TYPE GEO[1] [2] [3] [4] AMOUNT/SPEED

1 DOT 0 0 0 0 0.2

2 LINE -0.5 -0.5 -6.25 -6.75 5.5

3 DOT -4. 5 -1.61 0 0 0.2

4 LINE +0.5 -0.5 6.25 -6.75 5.5

5 DOT 4.5 1.61 0 0 0.2

6 LINE 0.5 0.5 6.25 6.75 5.5

7 DOT -1.66 4.-5 0 0 0.2

8 LINE -0.5 0.5 -6.25 6.75 5.5

9 DOT 1.61 -4.5 0 0 0.2

10 DOT 1.61 4.5 0 0 0.2

11 DOT -4.5 1.66 0 0 0.2

12 DOT -1.61 -4.5 0 0 0.2

13 DOT 4.5 -1.66 0 0 0.2



t (see eft e uring

Figure 12-18. Low-Temperature, Cure Profile Used on a Convection Belt Oven to Cure Ablebond* 8380

12.4.10.2.3 Alternate Die Attach Material

The majority of Japanese OEM manufacturers use Toray-Dow* DA6523. Several contract board assembly manufacturers use Alpha Metals Staystik* 591. Intel has no information on reliability stress test results or manufacturability. Contact Toray-Dow or Alpha Metals for additional information.

12.4.10.3 Fluxing

A Rosin Mildly Activated (RMA), halide free, no residue flux is suggested. Multi-core no-clean X33-04 has been used successfully for the hot bar application for both SnPb and Au lead finish. Optimum results have been obtained by immersing the leads of the TCP component in the flux. Immersion should cover the entire surface of the foot, top and bottom up to the top of the heel radius. The specific gravity of the flux controls the amount of flux which remains on the leads after immersion and should be closely controlled at 0.80 to 0.81. The solids content of the flux should remain in the range 1%-3%. Because this is a no-clean material the surface insulation resistance should be monitored and kept at >109 Ω minimum between adjacent leads. Extractable ions have been measured for this material at less than 100 ppm Cl-, Na+ and less than 50 ppm K+. The time between application of flux and solder reflow should be minimized.

12.4.10.4 Placement and Alignment

The pick and place accuracy should allow for better than 0.025 mm lead off land misalignment and 10° rotational alignment.

The alignment features of the TCP component include:

1. Sprocket holes in the tape to hold the tape in the carrier.

2. Four tooling holes at the periphery for alignment of the tape to the excise and form die sedetail of tooling holes in Figure 12-5). Intel has used the tooling holes shown in the upper land lower right of Figure 12-1 for alignment during processing at Intel. These should not bused during board assembly. The other two tooling holes have been left pristine for use dboard assembly.

3. If desired, a polyimide keeper bar design to maintain TCP lead position.

A5715-01272588-17

20 C

60 C

100 C

135 C130 C

Status-3Temp=56Batt-4.985Pts=900Acc=0002000:00:01.0

1

23˚

˚

˚

˚

˚

* Other brands and names are the property of their respective owners.



t of a C. The the flat

rmal

4. A gold plated copper lead identifier flag on pin one corner of the component.

12.4.10.5 Solder Reflow

12.4.10.5.1 Reflow Process Suggestions: Hot Bar

Reflow process parameters can vary significantly depending on board design, support pedestal design, and equipment. Some general guidelines for the hot bar process follow, which can be used by the customer as a starting point for their specific process development.

Intel engineers have done extensive process development of hot bar reflow for 0.25 mm TCP components. The reflow thermal and force profiles are shown in Figure 12-19. Blade design is crucial for effective hot bar reflow. Blades should maintain flatness across the active surface of the blade. Temperature variations across the blade should be less than 10° C. Four independenceramic blades with tungsten resistors are suggested. Each blade is used to reflow one sideTCP component. Mean blade-to-blade temperature differentials should be kept less than 5° blade width should be such that the contacted area of the TCP foot is less than the length of of the foot. A baseline thermal profile is shown below. This profile has been shown to yield acceptable solder fillets. Different temperature/time profiles may be required for different thedensities.

Figure 12-19.

A5716-01272588-13

Programmed Temp Profile

Actual Blade Temp

Blade Liftoff Temp

Time

Bla

de T

emp

Bon

d F

orce

Time



hould le joint

ess of rovide

the g on a 0.062 * ferent

CB the die tions on the

12.4.10.5.2 Suggested Template For Hot Bar Reflow Profile

Blade Temperature...................................................................280 +/- 10° C

Temperature Variation Across Blade........................................< 10° C

Blade-to-Blade Variation Between Mean Temperature.............5° C

Blade Force..................................approximately 12 lbs total (3 lbs./blade for 4 blades)

Dwell Time................................................................................25 sec.

Heel fillets should extend 1/3 to 1/2 the height of the heel radius. The solder wetting angle sbe positive. Reliability stress test data has shown that toe fillets are not required for acceptabreliability after 1000 cycles of -55° C to 125° C. However, the presence of toe fillets may be aquality indicator for the reflow process.

The pick-up head design can contribute to component alignment control and bond line thicknthe die attach medium. Pick-up contact on the polyimide carrier ring area has been found to pa wide process window for alignment in some equipment. Pick-up tooling design should be verified with your equipment supplier.

12.4.10.5.3 Removal Process Suggestions After Hot Bar Mount And Cure

Intel has developed the following removal process which can be used as a starting point for customer’s own development effort. The actual times and temperatures may differ dependinthe rework machine and equipment utilized. Please note that this process was developed onthick FR-4 PCB with Au die attach pad, using Intel’s suggested die attach material Ablebond8380. Other PCB assemblies with varying thickness, material and die attach, may require difremoval profiles.

TCP removal is a thermally profiled, stepped process, which removes the device from the Passembly after die attach cure. This process is centered around breaking the bond betweenattach material and the PCB and/or die, by using the coefficients of thermal expansion variaassociated with the die and PCB material. This characteristic of the removal process is basedthermoset properties associated with Intel’s suggested die attach material Ablebond* 8380.



e. n in f the ing

y.

um

the

e

The stepped process is derived from the underboard heating of the removal site, prior to top surface heating. This process allows for the PCB to expand for a longer period of time than the die, creating the forces necessary to break the thermoset die attach bond. Intel has developed the removal process with Air-Vac’s* DRS 26 Semi-Automated Soldering and Desoldering MachinThe removal time profile is approximately 135 seconds with the equipment settings as showTable 12-11. These actual settings and time may differ depending on the actual configuration oPCB assembly the TCP is being removed from. The time profile may even be reduced by ushigher wattage heating elements.

Even though this process is centered around a manual method, the DRS-26 allows the userprogramming capabilities to semi-automate the process to improve throughput and efficienc

The nozzle assembly that Intel used during the development of this process is a center vacuported design with the air flow directed to the outer perimeter of the nozzle. This allows for peripheral heating from the top side of the TCP, which is an advantage when trying to break thermoset bond created during the curing process. This nozzle was equipped with a high temperature O-ring to seal the vacuum for TCP pick up, around the inner tape perimeter. SeFigure 12-20 for the nozzle design.

Table 12-11. DRS-26 Settings

Air Pressure 85psi

Underboard Heater

Wattage

Airflow

250° C

300 W

60%

Nozzle Heater

Wattage

Airflow

260° C

900 W

80%

Mode Manual



.25”

be

f the

n the

.

zle

Figure 12-20. Nozzle Design for Rework Process

The following outline for TCP removal is for a manual operation under the DRS-26 operating environment.

1. Turn on the power and initialize the DRS-26 system.

2. A preheat stage for the underboard and nozzle heating elements should be used for cold system start-up. A 2 minute preheat cycle was utilized with the settings shown in Table 12-11.

3. Place the PCB assembly into the guide rails while positioning the TCP directly over the underboard heating element. The heating element should be positioned approximately 0below the underside of the PCB assembly.

4. Use the vision alignment system to center the removal nozzle to the TCP component toremoved.

5. The nozzle working height should be set to approximately 0.40” above the top surface oPCB. The system should now be set for the stepped, timed profile for removal.

6. Flux the leads of the TCP prior to starting the heating elements.

7. Turn on the underboard heating element for approximately 30 seconds prior to turning onozzle heating element. Once the nozzle heating element has been turned on, run both elements for approximately 1 minute 45 seconds.

8. With approximately 40 seconds left, lower the nozzle assembly to the top of the surface

9. With approximately 10 seconds left, turn on the system vacuum and slowly raise the nozassembly. If the component does not lift, then lower the nozzle assembly with continuedheating and try again. Repeat this procedure until the device is removed cleanly.

Follow all manufacturer’s suggestions for use.

A5717-01272588-21

0.6190.617SQ

0.6910.689SQ1.061

1.059SQ

0.060 Typ

0.063 R0.063 R

0.042 R0.078 R

0.188 Dia

[Measurements in inches]



e vias,

tions es l he vement ox

to the spread

such as

sted

e die) ut

be g

at evice, TCP pen

12.5 Package Performance

12.5.1 Thermal Performance

The thermal resistance of a TCP package, or theta-jc, is 0.8°C/W to 2°C/W depending on thproduct and the thermal design. Simple PCB enhancements such as the addition of thermalalone or with the use of low profile heatsinks, bring the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling opavailable. Key PCB design parameters which influence the thermal behavior of TCP packagmounted on printed circuit boards include the number of board layers, the number of internapower and ground planes, thermal vias and spreading area on the back side of the board. Taddition of heat pipe and spreader plate reduces thermal resistance further, up to 50% improover the unenhanced performance. This allows the system designer significant flexibility in bdesign for trade-offs in inter-card spacing, heat pipe design and location, and weight.

Thermal vias in the die attach pad allow the heat from the die to be transferred and spread inboard. Heat is also transferred through the board to the opposite side where it can be furtherand transferred. Figure 12-21 shows thermal vias connecting to a heat spreading plane on the opposite side of the board. A heat pipe is shown for illustration purposes. In the illustration, atransfer block made from copper or aluminum is used to clear the component height on the backside of the board. The other end of the heat pipe is connected to a heat spreading areathe keyboard plate or the bottom chassis.

Thermal vias can be arranged in several configurations within the die attach pad. It is suggethat a full grid of 0.34 mm (13.5 mil) as-drilled thermal vias be placed on 1.27 mm (50 mil) minimum centers across the die attach pad. Decreasing pitch (increasing via count under thwill further improve heat transfer into the board. The thermal vias should be connected withothermal relief to the ground planes(s). A ground plane that mirrors the die attach pad shouldplaced on the opposite side of the board from the TCP site to enhance system heat spreadinsolutions.

Additional use of heat pipes on the opposite side of the board further enhances thermal performance. Figure 12-21 illustrates a possible mounting. The advantages of mounting the hepipe to the board rather than the device include: coupling to the major thermal path for this dthe ability to select the adhesive or mechanical attachment method, mechanical isolation of leads from the load of the heatsink especially in vibration, and the ability to utilize potential oreal estate on the back side of the board to increase the thermally active area.



Figure 12-21. Heat Transfer Through the PCB

For detailed information on system thermal design solutions please contact your local Intel sales office.

12.6 Electrical Performance

Intel has developed a methodology to characterize the electrical performance of Intel TCP components. All information is generated on a product specific basis.

The construction of TCP components is unique compared to traditional CPU packages such as PGAs and PQFPs. Both the PGA and the PQFP use wire bond technology that connects the die to the package. The package leads then provide the final connection to the printed circuit board. The TCP package uses TAB (tape automated bonding) interconnect which provides a direct connection from the die to the outside world. The result is a low inductance path from the die to the board when compared to traditional PGA or PQFP packages.

Originally, the mobile processor required a thermally and electrically conductive path between the board and the device. Additional tests have revealed that an electrically conductive path between the board and the device is not required.

For more detail about the electrical performance of a specific product in the TCP package consult the datasheet or call your local Intel sales office.

12.7 Mechanical Performance

12.7.1 Lead Strength

Lead fragility testing has shown that the TCP component, mounted to a PCB without D/A material, can withstand up to 11X its own weight under random vibration testing up to a frequency of 1000 Hz. No solder joint degradation was seen.

A5718-01272588-14

Thermal Grease or Adhesive

TapeEncapsulant

Thermally ConductiveMaterial

Transfer Block

Heat Pipe

Thermal Plane

Thermal Vias



lead ,

urface circuit of an fter e

12.7.2 Solder Joint Reliability

Concern over the integrity of gold leadfinish in direct contact with tin-lead (Sn-Pb) solder has led to much study. The major cause of concern is the formation of Au-Sn intermetallic compounds in the joint which segregate at grain boundaries and metal layer interfaces. These compounds are in themselves brittle and can cause embrittlement of the joint as a whole. Such embrittlement can cause mechanical and electrical failure over time in high vibration environments or under situations with much thermal cycling induced fatigue. The TCP component was put through multiple tests to ensure mechanical integrity.

The TCP package lead has a nickel underplate and gold final plate in the outer lead bond area of the package. The nickel acts as a barrier between the copper lead and gold surface, ensuring a solderable lead at the customer site.

Intel has done extensive testing on the reliability of solder joints. Packages with Ni/Au were assembled onto boards with various plating thicknesses which bracket Intel’s recommendedfinish thickness. No failures were detected after the boards were subjected to vibration stressmechanical shock, and thermal cycling stresses performed in Figure 12-22.

Figure 12-22. Series of Stresses Performed

12.7.3 Lead Guard

Because the Intel TCP has thinner leads and a thin tape body compared with other plastic smount devices, it can be relatively more susceptible to handling damage once on the printedboard. A cover or “lead guard”, can be used to protect the device after mounting. A drawing Intel TCP lead guard is shown in Figure 12-23. The lead guard can be used to protect the TCP ait is mounted to the PCB for protection through the factory processes, as a shipping protectivcover, and/or before and after final assembly into the computer box.

Intel has developed a light weight, low profile and low cost TCP lead guard. For additional information on this design, please request a copy of the TCP Lead Guard Application Note from your Intel representative.

A5719-01

Vibration

Mechanical Shock

Temp Cycling

5 Hz--2000 Hz, 0.01g /Hz, (3 Axis, 15 Minutes/axis)

50g Shock Trapezoid With 11 Sec. Duration 1/2 Sine(3 Axis, 3 Drops/Axis)

-55˚C + 100˚C, 30 Minute Cycle:10 Minute Soak: 5 Minute Ramp

2



of

CA,

y of Appl.

i/

Figure 12-23. TCP Lead Guard

12.8 Selected Readings in TCP and Ultra-fine Pitch Hot Bar Reflow

12.8.1 Outer Lead Metallurgy References

Zakel, E., Azdasht, G., and Reichl, H., “Investigations of the Au-Concentration and ReliabilityOLB Solder Contacts”, in Proc., 5th ITAP, Feb 2-5, 1993, San Jose, CA, pp. 118-130.

Zakel, E., Azdasht, G., Kruppa, P., and Reichl, H., “Reliability Investigations of Different TapeMetallizations for TAB Outer Lead Bonding”, in Proc., 4th ITAB, Feb 16-19, 1992, San Jose, pp. 97-120.

Lee, C.K., Wong, Y.M., Doherty, D., Tai., K. L., Lane, E., Bacon, D.D., and Baiocchi, F. “StudNi as a barrier metal in AuSn soldering application for Laser chip/submount assembly”, in J. Phys., 72 (8) Oct 1992, pp. 3808-3815.

Bai, P., Gittleman, B.D., Sun, X-Y., McDonald, J.F., and Lu, T-M., Costa, M.J., “Diffusion in NCu bilayer films”, in Appl. Phys. Lett., 60 (15), April 1992, pp. 1824-1826.

Daebler, D.H., “An Overview of Gold Intermetallics in Solder Joints”, in Surface Mount Technology, October 1991, pp. 43-46.

A5720-01272588-22

Cross Section Detail

Die Opening

2.0mm Ref

Snap Fit Hooks(2 Located Across Diagonal)

Top View

34.0 mm Ref

34.0 mm Ref



?”, in

nted

MS,

1.

93.

the pp.

tance ,

Thompkins, H.G. and Pinnel, M.R., “Relative Rates of Nickel and Copper Diffusion Through Gold”, in J. of Appl. Phys., 48 (7) July 1977. pp. 3144-3146

12.8.2 Solder Joint Reliability References

Suhir, “Could Compliant External Leads Reduce the Strength of a Surface Mounted DevicesProc. 38th ECC, 1988, pp. 1-6.

Kotlowitz, R.W., “Comparative Compliance of Representative Lead Designs for Surface MouComponents”, IEEE Trans. CHMT, vol. 12, Dec. 1989, pp. 431-448.

Lau, J.H., “Stiffness of PQFP “Gull-wing” Lead and Its Effect On Solder Joint Reliability”, in IEEE-CHMT Proc., 1988, pp. 131-132.

Englemaier, W., “Test Method Considerations for Smt Solder Joint Reliability”, in Proc. IEPSConf., Oct. 1984, pp. 360-369.

Sandor, B.I., “Life Prediction of Solder Joints: Engineering Mechanistic Methods”, In Solder Mechanics--A State of the Art Assessment, D.R. Frear, W.B. Jones, and K. Kinsman, eds., T1990, pp. 363-419.

Morris, James, E. ed., Electronics Packaging Forum, Vol. 2, Van Nostrand Reinhold, NY, 199

IPC-SM-785, “Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments”, IPC, Chicago, Nov. 1992.

IPC-SM-782A, “Surface Mount Design and.n Land Pattern Standard”, IPC, Chicago, Aug. 19

ANSI/J-STD-001, “Requirements for Solder Electrical and Electronic Assemblies”, AmericanNational Standard/IPC, April 1992

12.8.3 Thermal Performance References

Pope, D.E. and Do, H.T., “Thermal Characterization of a Tape Carrier Package”, in Proc. of 44th Electronic Components and Technology Conference, May 2-4, 1994, Washington, DC, 532-538.

Takubo, C., Tazawa, H., Yoshida, A., Hirata, S., and Sudo, T., “A Remarkable Thermal ResisReduction in a Tape Carrier Package on a Printed Circuit Board”, in Proc., 5th ITAP, Feb 2-51993, San Jose, CA, pp. 44-51.

12.9 Revision History

• General review of the chapter


Pinned Packaging 13

13.1 Introduction

As Intel microprocessors become faster, more complex and more powerful, the demand on package performance increases. Improvements in microprocessor speed and functionality drive package design improvements in electrical, thermal and mechanical performance. Package electrical and thermal characteristics become attributes of component performance along with the mechanical protection offered by the package.

To meet these requirements, Intel has introduced a variety of innovative package designs. The development of the plastic pin grid array (PPGA) package, PPGA2, and Flip Chip Pin Grid Array (FC-PGA) have provided an improvement path for enhanced power distribution and improved thermal and electrical performance. While each consists of organic package materials, the primary differences within the package is that PPGA utilizes wirebond interconnect technology while the FC-PGA utilizes Flip Chip Interconnect. Externally, the PPGA thermal interface will be made to an integral package heat slug while the FC-PGA thermal interface will be made directly to the die backside. PPGA and FC-PGA are both socket compatible.Table 13-1 summarizes the key attributes of the PPGA package. The following sections detail the physical structure, electrical modeling and performance attributes of the PPGA package.

Table 13-1. PPGA Package Attributes

PPGA Attributes

Physical

Appearance Circuit board, exposed pins

Package Body Material BT laminate, Ni plated Cu heat slug, epoxy encapsulant, Au bond wires

Body Thickness 3.0 mm (overall, includes heat slug)

Weight 18 grams

Package Trace Metal Copper

External Heat Slug Yes

External Capacitors Yes

Performance

Thermal (θjc) with Heat Sink 0.30 - 0.50 °C/W

Power Distribution Cu traces and multiple planes enhance distribution

Package Trace Propagation Delay Cu traces have low resistance and reduce delay

Others

Thermal Interface Used for Heat Sink Attachment Thermally conductive and electrically non-conductive grease, phase-change material, film, or tape

Board Mount PPGA socket

Caution: For PPGA packages, electrically conductive surfaces should not touch any part of the processor except the heatslug. For example, an electrically conductive heat sink should not contact the exposed pins, external capacitors, or the exposed metal on the side of the package.


Pinned Packaging

The Micro Pin Grid Array (µPGA) is the latest innovative packaging approach, developed as a conveyance for Organic Land Grid Array (OLGA) package technology CPUs in the thin and light configuration of mobile notebook computers. The µPGA is also known as an Interposer based package.

The interposer is a pinned FR-4 carrier which affords the OLGA package to be surface mounted to the interposer for future socketing by the OEMs. The development of the interposed package is a result from the OEM’s requirement for a manufacturing alternative allowing flexibility in selecting whether to surface mount an OLGA or socket onto the motherboard at final assembly.

This High I/O interposed package utilizes a one for one, pin to BGA ball connectivity arrangement. Advantages to this packaging technique, is it’s minimally larger surface area than the OLGA CPU itself, and that it attains a height reduction over the earlier Mobile Module used in notebook computers.

The entry of the µPGA packaging technology continues the commitment to provide packaging solutions that meet Intel’s rigorous criteria for quality and performance.

Table 13-2. FC-PGA Package Attributes

FC-PGA Attributes

Physical

Appearance Circuit board - exposed pins, chip components, and die

Package Body Material Fiber-reinforced resin substrate, epoxy underfill, Au/Ni-plated Kovar pins

Body Thickness 3.18 mm pins + 1.1 mm substrate + 0.83 mm die (5.11 mm total)

Weight 7.5 grams

Package Trace Material Copper

External Heat Slug No

External Capacitors and Resistors Yes (pin side only)

Performance

Thermal (θjs) with Heat Sink 0.6 °C/W (12-15 lbf. Clip force)

Power Distribution Cu traces and multiple planes enhance distribution

Package Trace Propagation Delay Cu traces have low resistance and reduce delay

Other

Thermal Grease Used for Heat Sink Attachment Thermally conductive and electrically non-conductive

Board Mount Socket only

Warning: For FCPGA packages, electrically conductive surfaces should not touch any part of the processor except the die. For example, an electrically conductive heat sink should not contact the exposed pins, external capacitors, or the exposed metal on the side of the package.


Pinned Packaging

old The CB

Table 13-3 summarizes the key attributes of the PPGA package. The following sections detail the physical structure, electrical modeling and performance attributes of the PPGA package.

13.2 Packages Geometry And Materials

13.2.1 PPGA

13.2.1.1 Package Materials

The PPGA package body piece part is a pinned laminated printed circuit board (PCB) structure. Figure 13-1 illustrates the cross section of a typical PPGA piece part. The dielectric material, which is chosen for its high temperature stability, is a glass reinforced high glass transition temperature (Tg) Bismaleimide Triazine (BT) with a Tg ranging from 170° C to 190° C. Conductors are copper traces. For bondability the copper (Cu) bond fingers are plated with g(Au) over nickel (Ni). The heat slug is Ni plated copper, which gives high thermal dissipation.Kovar pins are plated with Au over Ni and are surrounded by solder after insertion into the Psubstrate.

Table 13-3. µPGA Package Attributes

µPGA

Lead Count 495 615

Sq./Rect. R R

Pitch (mm) 1.27 1.27

Interposer Thickness (mm) nominal 1.0 1.0

Socketable pin length (mm) nominal

1.25 1.25

Weight (grams)

Max. Footprint (mm) nominal 34.21 x 28.27w 37.51 x 35.56w

Shipping Media

Trays X X

Desiccant

Comments/Footnotes

NOTE: Interposer size are Die size dependent. Please contact Intel Technical support for latest specifications


Pinned Packaging

Figure 13-1. Cross Section View of PPGA Package

13.2.1.2 Package Outline Drawings

The PPGA package in Figure 13-2 includes a nickel plated copper heatslug and eight discrete capacitors. The capacitors are an optional feature used to decouple the power and ground supplies to enhance performance of the packaged device.

Figure 13-2. Top View of a PPGA Package

A5769-01

yyzz||

Kovar Pins

Signal

Signal

Power

VSS

Die

|Solder Reset

BT Core

Copper

BT Pre Preg

Slug Adhesive

Copper Slug

Solder

Chip Cap

Solder

A5770-01


Pinned Packaging

Figure 13-3, Table 13-4 and Table 13-5 illustrate the package outline drawings and dimensions for the 296 lead PPGA package. The package meets JEDEC outline spec MO-128 for pin count and package size. The package is square and 1.95 inches on a side and 3 mm in total thickness. The index corner has a 45° chamfer.

Figure 13-3. Principal Dimensions

Table 13-4. PPGA Package Drawing Definitions

Symbol Description of Dimensions

A Package Body Thickness Including Heat Slug


A2 Heat Slug Thickness

B Pin Diameter

D Package Body Dimension

D1 Pin Field Width

D2 Heat Slug Width

D3 Heat Slug Center to Package Edge

e1 Pin Pitch

F1 Outer Chip Cap Heat Slug Center to Package Edge

F2 Inner Chip Cap Heat Slug Center to Package Edge

L Pin Length

N Lead Count

S1 Outer Pin Center to Package Edge

A5771-01

1.65(Ref)

D2

B

F

F2

1

e1 A

L

Seating Plane

2

D

DD1

S1

A

A 1

2.291.5245 Chamfer(Index Corner)

Pin C3

measurements in mm˚

Chip Capacitor

Solder Resist

Heat Slug


Pinned Packaging

Table 13-5. 296 PPGA Package Dimensions and Tolerances

Family: Plastic Pin Grid Array Package - 296 Lead

Symbol Millimeters Inches

Minimum Maximum Minimum Maximum

A 2.72 3.33 0.107 0.131

A1 1.83 2.23 0.072 0.088

A2 1.00 0.039

B 0.40 0.51 0.016 0.020

D 49.43 49.63 1.946 1.954

D1 45.59 45.85 1.795 1.805

D2 23.44 23.95 0.923 0.943

D3 24.765 0.975

e1 2.29 2.79 0.090 0.110

F1 17.56 0.692

F2 23.04 0.907

L 3.05 3.30 0.120 0.130

N 296

S1 1.52 2.54 0.060 0.100

NOTES: 1. A2 Typical2. F1 Typical3. F2 Typical


Family: Plastic Pin Grid Array Package - 370 Lead



A 2.72 3.33 0.107 0.131

A1 1.83 2.23 0.072 0.088

A2 1.00 0.039

B 0.40 0.51 0.016 0.020

D 49.43 49.63 1.946 1.954

D1 45.59 45.85 1.795 1.805

D2 25.15 25.65 0.990 1.010

D3 23.495 0.925

e1 2.29 2.79 0.090 0.110

F1 17.56 0.692

F2 23.04 0.907

L 3.05 3.30 0.120 0.130

N 370

S1 1.52 2.54 0.060 0.100


Pinned Packaging

13.2.2 FC-PGA

13.2.2.1 Package Materials and Geometry

The FC-PGA package body piece part is a pinned, laminated printed circuit board (PCB) structure. Figure 13-4 illustrates the cross section of a typical FCPGA piece part. The circuit board is a laminate of two dielectric materials: a glass-reinforced high glass transition temperature (Tg) core with a Tg ranging from 165 °C to 175 °C and outer layers composed of non-reinforced resin. Conductors are copper traces. The Kovar pins are plated with Au over Ni and are attached to the substrate with high-temperature solder.

Figure 13-4. Cross Section View of the FC-PGA Package


The FCPGA package can include a combination of discrete capacitors and resistors. The capacitors are an optional feature used to decouple the power and ground supplies to enhance performance of the packaged device. The resistors have a variety of uses. All discrete components are located within a designated component keepin zone on the pin side of the package.

NOTES: 1. A2 Typical2. F1 Typical3. F2 Typical


A7646-01

FIBER-REINFORCEDRESIN

NON-REINFORCED RESIN

COPPER

PTH FILLER MATERIAL

SOLDER RESIST

EPOXY UNDERFILL

SOLDER

AU/NI-PLATED KOVAR

DIE

CHIP CAP


Pinned Packaging

Figure 13-5. Top/bottom View of an FCPGA Package

Figure 13-6, Table 13-7 and Table 13-8 illustrate the package outline drawings and dimensions for the 370 lead FCPGA package. The package meets JEDEC outline spec MO-128 for pin count and package size. The package is nominally 1.95 inches (49.53 mm) on each side and .076 inches (1.93 mm) in total thickness (not including the pins). There is no chamfered corner on this package, so pin 1 is indicated by a gold triangle.

A7647-01

Table 13-7. FC-PGA Drawing Symbol Definitions

Symbol Description of Dimensions

A1 Die Height (including C4 bumps)

A2 Substrate Thickness

B1 Die Length (x-direction)

B2 Die Length (y-direction)

C1 Epoxy Underfill Length (x-direction)

C2 Epoxy Underfill Length (y-direction)

D Package Body Length

D1 Pin Field Width

G1 Passive Components Keepin Zone Length (x-direction)

G2 Passive Components Keepin Zone Length (y-direction)

G3 Passive Components Keepin Zone Height

H Pin Pitch

L Pin Length

φP Pin Diameter

Pin TP Pin True Position Tolerance


Pinned Packaging

Figure 13-6. FC-PGA principal dimensions

Table 13-8. FC-PGA Package Dimensions

Family: Flip Chip Pin Grid Array Package



A1 0.787 0.889 .031 .035

A2 1.000 1.200 .039 .047

B1 19.838 max .781 max

B2 19.838 max .781 max

C1 30.480 max 1.200 max

C2 35.560 max 1.400 max

D 49.428 49.632 1.946 1.954

D1 45.466 45.974 1.790 1.810

G1 0.000 17.780 0 .700

G2 0.000 17.780 0 .700

G3 0.000 0.889 0 .035

H 2.540 nominal .100 nominal

L 3.048 3.302 .120 .130

φP 0.431 0.483 .017 .019

A7648-01

G2

G1

D

Bottom View Top View

Side View

D1

H

CapacitorPlacement

Area

H

D

Die

G3 Pin TP

Seating Plane

φP

A2

A1

Underfill Area

C2B2

B1C1

L


Pinned Packaging

glass r pins,

bled rties

ned set in other

13.2.3 µPGA

13.2.3.1 Package Materials and Geometry

The interposer as an OLGA carrier, consists of double-sided (¾ oz. per side) copper clad, onbased, epoxy resin impregnated FR-4 laminate. This substrate utilizes copper alloy or Kovareflowed into an array of plated through holes within the substrate.

Because of the material likeness between the OLGA package and the Interposer, the assempackage exhibits improved coefficient of thermal expansion (CTE) compliant package propein an assembled application.

The interposer has a die specific OLGA land pattern of .024" (0.609mm) diameter metal defilands on .050" (1.27mm) pitch. It correspondingly accommodates a .050" (1.27mm) pitch offpattern of pin lands. This pin land pattern is offset .025" (0.635mm) in the X and Y directionsrelation to the OLGA land pattern. The pin lands and BGA land pairs are connected to each with a .010" (0.254mm) wide trace. Figure 13-7 illustrates this concept.

Figure 13-7. Pin Spacing and BGA land offsett for .050” (1.27mm) pitch

The pin base material is copper alloy (C19400) or Kovar, chosen because of its excellent electrical characteristics and resistance to bending. During manufacturing, the pin wire is extruded through a series of progressive dies to arrive at its configuration. The sharp edges are broken to .002" (0.050mm) typical, and are plated with 80 microinches minimum, of nickel and then overplated with 8 microinches, minimum of gold to ensure like metal contact with the socket contacts. This configuration was specifically developed for the thin and light mobile application.

The pin configuration used with interposer -1 interposers are a contour shoulder type. This configuration is illustrated in Figure 13-8.

A7190-01

.050

.0078

.025

.050

.019

.025

.025

.035

.025

φ .024"BGA Land

φ .031"Pin Land


Pinned Packaging

These pins are nominally .012" (0.304mm) in diameter, have a .010" (0.254mm) maximum thick and a .024 (0.609mm) nominal, diameter shoulder. The socketable area of the pin, as defined, is from the bottom side of the interposer to the pin tip which is nominally, .049" (1.25mm) in length. This includes a .010" (0.254mm) high X .030" (0.965mm) diameter zone which accommodates the shoulder and solder fillet area when inserted into the socket.

After the pins are fixtured, 95% Sn 5% Sb solder is used to reflow the pins into the interposer. The solder height is maintained at .002" (0.050mm) maximum, above the land array of the pins to ensure no interference with the solderpaste stencil during solder application prior to OLGA assembly.

Figure 13-8. µPGA Pin Configuration

A7189-01

.031” Land Diameter

.041”Land Diameter

SoldermaskOpening .030”

Soldermask Opening.024”

.030” dia. zoneincludes solder

.010” Thick ZoneIncludes Solder

.002” maxSolder Protrusion

.014” + .002/ -.001dia. Finished Hole

.049” InsertableLength


Pinned Packaging


The Interposer -1 configuration is dependent upon the OLGA package used. This section will indicate reference package dimensions for both the 615 pin and 495 pin Interposer applications.

Figure 13-9. µPGA 615 Principle Dimensions

Table 13-9. µPGA Drawing Symbol Definitions


A Interposer Height Including Insertable Pin Length

A1 Interposer Substrate Thickness

A2 Insertable Pin Length

ØB Pin Diameter

C Pin Pitch X and Y

D Interposer Width "X" Direction

D1 Width of Pin Array

E Interposer Length "Y" Direction

E1 Length of Pin Array

F Distance of First Pin Row to Edge in "X" Direction

G Distance of First Pin Column to Edge in "Y" Direction

H OLGA Pattern Center Distance to Interposer Edge in the "Y" Direction

J OLGA Pattern Center Distance to Interposer Edge in the "X" Direction

K Fiducial to Fiducial Distance in the "Y" Direction

L Fiducial to Fiducial Distance in the "X" Direction

M Fiducial to Interposer Edge Distance in the "Y" Direction

N Fiducial to Interposer Edge Distance in the "X" Direction

A7191-01

G

El

FDl

D

E K

LφB

C

A1

A2

A

Seating Plane

M

H

N

J

OLGA Offset to Interposer


Pinned Packaging

Table 13-10. µPGA 615 Dimensions

Inches Millimeters

Symbol Min Nom Max Notes Min Nom Max

Pin Count 615 615

Interposer Height A -- .088 -- 1 -- 2.23 --

Substrate Thickness A1 .033 .039 .045 1 0.85 1.00 1.15

Socketable Pin length A2 .047 .049 .051 1 1.19 1.25 1.31

Pin Diameter ØB -- .012 .014 1 -- 0.30 0.36

Pin Pitch C -- .050 -- 1 -- 1.27 --

Interposer Width D 1.276 1.282 1.288 1 32.41 35.56 32.71

Array Width D1 -- 1.200 -- 1 -- 30.48 --

Interposer Length E 1.441 1.447 1.453 1 36.60 36.75 36.90

Array Length E1 -- 1.300 -- 1 -- 33.02 --

Pin to edge distance along "D" F -- .077 -- 1 -- 1.95 --

Pin to edge distance along "E" G -- .086 -- 1 -- 2.18 --

OLGA center "Y" Offset to Interposer edge

H -- .641 -- 1,2 -- 16.28 --

OLGA center "X" Offset to Interposer edge

J -- .723 -- 1,3 -- 18.36 --

Fiducial "Y" Distance K -- 1.369 -- 1 -- 34.77 --

Fiducial "X" Distance L -- 1.075 -- 1 -- 27.30 --

Fiducial to edge distance along "E" M -- .038 -- 1 -- 0.96 --

Fiducial to edge distance along "D" N -- .105 -- 1 -- 2.66 --

NOTES:1. Package dimensions are for reference only. See product drawings for specific dimensions.2. The offset of the OLGA pattern center to the offset of the pin pattern center in the "Y" direction is .013 inches (0.33mm).3. The offset of the OLGA pattern center to the offset of the pin pattern center in the "X" direction is .010 inches (0.25mm).


Pinned Packaging

Figure 13-10. µPGA 495 Principle Dimensions

A7192-01

G

El

FDl

D

EK

LφB

C

A1

A2

A

Seating Plane

M

H

N

J

OLGA Offset to Interposer


Inches Millimeters

Symbol Min Nom Max Notes Min Nom Max

Pin Count 495 495

Interposer Height A -- .088 -- 1 -- 2.23 --

Substrate Thickness A1 .033 .039 .045 1 0.85 1.00 1.15

Socketable Pin length A2 .047 .049 .051 1 1.19 1.25 1.31

Pin Diameter ØB -- .012 .014 1 -- 0.30 0.36

Pin Pitch C -- .050 -- 1 -- 1.27 --

Interposer Width D 1.107 1.113 1.119 28.17 28.27 28.37

Array Width D1 -- 1.000 -- 1 -- 25.40 --

Interposer Length E 1.341 1.347 1.353 34.06 34.21 34.36

Array Length E1 -- 1.150 -- 1 -- 29.21 --

Pin to edge distance along "D" F -- .067 -- -- 1.70 --

Pin to edge distance along "E" G -- .086 -- 1 -- 2.18 --

OLGA center "Y" Offset to Interposer edge

H -- .674 -- 1,2 -- 17.11 --

OLGA center "X" Offset to Interposer edge

J -- .557 -- 1,3 -- 14.14 --

Fiducial "Y" Distance K -- 1.270 -- 1 -- 32.25 --

Fiducial "X" Distance L -- .925 -- 1 -- 23.49 --

Fiducial to edge distance along "E"

M -- .038 -- 1 -- 0.96 --


Pinned Packaging

13.3 Applications

Both the PPGA and FC-PGA package has been developed for Intel’s advanced microprocessor family of products. They have been designed for use in socketed applications, using socket footprints which are compatible with the Intel ceramic Pin Grid Array package family. While the PPGA package can be used in both Zero and Low Insertion Force sockets (ZIF/LIF), the FC-PGA should only be used in a ZIF socket application.

13.4 Component Assembly Process

13.4.1 PPGA Component Assembly

The PPGA assembly process flow is similar to the CPGA process flow with the exception of the seal operation.

As preparation for die attach, wafers are mounted on a pressure sensitive carrier tape and diced with a high speed saw. The cut wafer is washed with a detergent solution to remove silicon dust.

A silver filled epoxy adhesive is applied to the package substrate at die attach. Dice are picked from the wafer and placed on the adhesive. The adhesive is then cured.

The die are connected to the gold plated package leads by way of gold wedge wire bond technology. Bond pad and package lead placement accuracy and wire pull strength monitors ensure high integrity connections.

PPGA packages are encapsulated with silica filled liquid epoxy in contrast to the CPGA lid seal process. The encapsulant provides mechanical and environmental protection for the die and wires. Process trays are moved beneath a valve which fills the package cavity with epoxy and are transferred to an in-line oven in which the epoxy is cured.

A matrix code containing the assembly date code information is marked on the top side of the package using a laser. The mark is inspected for orientation and readability. The packages are then ready for the testing, finishing and packing processes.

Fiducial to edge distance along "D"

N -- .096 -- 1 -- 2.66 --

NOTES:1. Package dimensions are for reference only. See product drawings for specific dimensions.2. The offset of the OLGA pattern center to the offset of the pin pattern center in the "Y" direction is .012 inches (0.30mm).3. The offset of the OLGA pattern center to the offset of the pin pattern center in the "X" direction is .010 inches (0.25mm).



Pinned Packaging

Figure 13-11. PPGA Generic Process Flow

13.4.2 FC-PGA Component Assembly

The FCPGA assembly process flow is similar to the OLGA process flow without ball attach and ball inspection steps but with the addition of the pin inspection step.

In preparation for chip attach, C4 wafer reflow process is to modify the shape and surface composition of the Pb/Sn bumps from the as-plated state to one acceptable for chip join. The wafers are then mounted on a pressure sensitive carrier tape and diced with a high speed saw. The cut wafer is washed with a detergent solution to remove silicon dust.

Die are picked from the wafer and mounted to the package. The units are then reflowed in a furnace to form C4 solder joints of the die and package.

The FCPGA units are then pre-baked in the oven to remove the moisture from the organic package before epoxy underfill materials is dispensed. The liquid capillary flow pull the underfill materials to fill the gaps around the solder joints in between the die and the package. The epoxy underfill materials are then cured in the oven.

The units are then ready for testing and finishing process. The finishing process includs laser marking the human readable product/assembly/test information along with pin inspection, final visual inspection and pack.

A5772-01

Wafer Mount

Wafer Saw and Wash

Die Attach

Wire Bond

Encapsulation and Cure

Top Side Serial Laser Mark

Test

Mark

Pack


Pinned Packaging

either tire ded

not e into

rs. The red on

e

Figure 13-12. FC-PGA Generic Process Flow

13.5 Package Usage

13.5.1 PPGA Package

13.5.1.1 PPGA Package Shipping Media

PPGA shipping trays are compliant to JEDEC standards. All external dimensions of the PPGA tray are the same as the CPGA tray. There is a slight difference in the distance from the top of the tray to the seating plane of the PPGA shipping tray compared to the CPGA shipping tray. The PPGA shipping tray pocket is smaller in the x- and y-axes. This slightly smaller pocket dimension reduces package free-play in the tray. Refer to Chapter 10 for the dimensions of the PPGA shipping tray. PPGAs are shipped in uniquely colored trays separately from CPGAs. This enables manufacturing personnel to readily identify which package type is being placed into manufacture at any time. This shipping media minimizes foreign material and meets ESD safe shipping requirements.

13.5.1.2 PPGA Moisture Sensitivity

PPGA packages have been designed for socketed applications. They are neither shipped in moisture barrier bags, nor is floor life exposure time tracking needed for socketed applications. The maximum body temperature which the component should see is 150° C. The component is nintended for direct through-hole mounting by wave solder processing nor for exposing the enpackage body to surface mount-like reflow profiles. Such thermal profiles are not recommenfor PPGA packages.

13.5.1.3 PPGA Socketing

Intel recommends that when performing insertion and extraction, the maximum force shouldexceed 100 lbs., and should be applied uniformly. The insertion and extraction tool should takaccount the clearance for the external capacitors and heat slug.

PPGA packages may be used in either low insertion force (LIF) or zero insertion force (ZIF) sockets. 296 lead sockets are available for PPGA packaged components from many suppliesocket design is a standard footprint on the PCB. Insertion and extraction forces were measusockets from various vendors. For all LIF socket designs tested, the maximum insertion forc

A7677-01

Wafer Reflow

Wafer Mount

Wafer Saw

Chip Attach

Chip Join

Deflux

Prebake

Underfill Dispense

Underfill Cure

Test

Laser Mark

Pin Inspection

FVI

Packing


Pinned Packaging

required was 80 lbs. Avoid uneven loading during insertion. The applied load overcomes the frictional resistance applied to the package pins as they are inserted into the socket. Table 13-12 summarizes the average measured insertion and extraction force for different sockets.

If the manufacturing flow requires inserting the package after the heat sink is applied to the component, then the same suggested force may be applied uniformly across the top surface of the heatsink.

13.5.2 FC-PGA Package

13.5.2.1 FC-PGA package shipping media

FCPGA shipping trays are of JEDEC style and may be of a thin or thick configuration. All external dimensions and perimeter handling features of the FC-PGA tray are the same as the CO-028 or CO-029 registered standards. All internal features are compliant to Intel Standard requirements. Density of the trays has been optimized and thus negates the possibility of automated empty-tray handling by vacuum pickup features. As is currently true of all new shipping trays, the seating plane has been adjusted to accommodate these packages within the top and bottom planes of a tray with appropriate head clearance. Pocket x, y dimensions are specific by form factor, as specified in the tray drawing, and are larger than previous form factors for PLGA or PPGA. Tray temperature rating for non-SMT products will be an Intel approved low temperature no-bake material.

Shipping trays are no longer color coded by particular product. Color standardization by process type will result in the new low-temperature no-bake trays meeting the requirements of the drawing regardless of form factor. Shipping trays will meet ESD safe shipping requirements.

13.5.2.2 FC-PGA Moisture Sensitivity

13.5.2.3 FC-PGA Socketing

FC-PGA packages use zero insertion force (ZIF) lead sockets which are available from many suppliers. Intel recommends that before performing insertion, the package pins have to be manually aligned to the socket. After insertion, FC-PGA has to be locked using the single lever actuation in the socket. Avoid package walkout (package being pushed upward) during insertion as it may cause unnecessary tilt to the heatsink assembly. Actuating force only require less than 10 lb without lubricant. The movement of the socket cover is limited to the plane parallel to the motherboard.

Table 13-12. PPGA Insertion/Extraction Force Measurement

Socket1 Average Insertion Force (LB) Average Extraction Force (LB)

Preci-Con LIF 44.69 57.43

Mill-Max LIF 38.09 49.65

Robinson Nugent LIF 78.35 73.51

AMP LIF 65.06 69.91

Andon LIF 54.26 58.58

Yamaichi ZIFs n/a 80.942

NOTES: 1. This data does not constitute a recommendation for any specific supplier or part number.2. This is measured when the lever is actuated to ensure that the package will not be pulled out during shock and

vibration test. When the lever is up, the extraction force is “zero”.


Pinned Packaging

13.5.3 µPGA Package

The interposer /OLGA package is designed for use in applications where CPU socketability, height, footprint geometry and weight are a high priority. Most importantly, the interposer/OLGA affords the OEMs the option to reflow either the OLGA or a socket to the motherboard at assembly. To accomplish this the objective, it is necessary to have the interposer land diameter equal to that on the motherboard at the CPU location. With this requirement, it is suggested that the OEMs use a .024" diameter metal defined land for the motherboard design. In general, .050" (1.27mm) pitch OLGA designs from Intel, require a .024" metal defined solderable land diameter. The exact diameter for any given OLGA package design should be obtained from Intel prior to the start of the motherboard design to ensure equivalent solderball height after reflow.

13.5.3.1 µPGA Package Shipping Media

The OLGA / Interposer assembly are shipped in a mid temperature thin matrix tray that complies with JEDEC standards. This shipping media minimizes foreign material and meets ESD safe shipping requirements. Typically, JEDEC trays have the same "X" and "Y" outer dimensions and are easily stacked for storage and manufacturing. For tray dimensions please refer to chapter X.X of this data book. The JEDEC trays are returnable to Intel for reuse. Chapter X.X contains detailed information on the return addresses for the different types of shipping trays.

13.5.3.2 µPGA Moisture Sensitivity

Most OLGA components are sensitive to moisture exposure before the reflow temperature exposure. Maintaining proper control of moisture uptake in OLGA components is critical.

13.5.3.3 OLGA to µPGA Assembly

The Pick and place accuracy of the placement system governs the package placement and rotational (theta) alignment. Slightly miss-aligned parts (less than 50% off the center of the land), will automatically self align during reflow due to solder surface tension properties. Grossly miss-aligned OLGA packages to interposer lands (greater than 50% off the center of the land) should be removed prior to reflow as they may develop electrical shorts (as a result to solder bridging) if they are subjected to reflow.

13.5.3.4 µPGA Socketing

Intel recommends that when performing insertion and extraction, the maximum force should not exceed 60 pounds pressure on the die surface, and should be applied uniformly.

13.6 Heat Sink Attachment

Intel recommends that when performing heatsink attach and the package is supported only on its periphery (such as in a shipping tray), the maximum force should not exceed 40 lbs.


Pinned Packaging

e ds and

se

al rce

13.6.1 Thermal Interface Material

To ensure PPGA packages are mechanically compatible with CPGA, a comprehensive evaluation of the effective method of heat sink attachment has been performed. It is suggested that the interface material used for heat sink attachment should have thermal conductivity greater than 0.8 W/mK, and be electrically non-conductive. The volume resistivity of the material should be greater than 1x106 Ohm-cm.

13.6.2 Clip Design and Attach

A minimum clip force of five pounds is recommended. Clips retain the heat sink assembly in the socket by exerting a force on the heat sink and the socket. The clip force, in turn, aids in forcing the grease to fill the many microscopic peaks and valleys on the heat sink and package surface, thereby reducing the interface thermal resistance. Since different clip forces result in different amounts of grease squeezed out, the corresponding bond line thickness of the grease will affect thermal performance.

The effect of foil sizes, clip force and voiding on Thermalcote I Conductacoat* thermal performance was also explored. If there is no grease on the Al foil, then voiding will exist in the bond line. This results in higher θja values. While up to 30% grease voiding can be tolerated without any impact on PPGA thermal performance, zero voiding is strongly recommended for any heat sink attachment methods.

A larger foil size will cover a larger area with grease, but a smaller foil size is preferred for handling. For example, thermal resistance θja, measured with a standard sized foil (1.0” x 1.0”) is0.1 C/W to 0.2 C/W lower than the θja measured with smaller foil (0.7” x 0.7”). Note that the Al foil is carrier specific for Thermalcote I Conductacoat* grease to aid volume manufacturing. Thdecision to use Al foils should be based on the OEMs particular heat sink attachment methoassembly line(s).

Clip force determines the thermal grease bond line thickness and directly impacts thermal performance. To determine the effect of clip force on thermal performance, θja and θcs values for the heat sink assemblies were measured at different clip forces. The actual clip forces of themodified clips were individually measured by using a Material Testing System (MTS) before thermal resistance measurement. All clip forces were also verified by using MTS after thermresistance measurement. Figure 13-13 shows θja and θcs values versus clip force. If the clip force ishigher than five pounds (corresponding to ~ 5 psi), then there is no significant effect of clip foon PPGA thermal performance.


Pinned Packaging

l lip is hat the age, the ctive,

age to eat

Figure 13-13. Comparison of θcs and θja for Different Clip Forces

13.6.3 Heat Sink Design

The PPGA package may affect some existing heat sink designs. In one design, shown in Figure 13-14, the heat sink has a lip designed for a CPGA package to prevent movement of the heat sink relative to the package, socket and clip during mechanical shock tests. However, the PPGA package has a heatslug, external capacitors, and exposed pins on the top side of the package. For use on the PPGA package, if the heat sink slips out of its secured position, the lip may touch the exposed pins. Therefore, the lip should be extended to a proper length to lock the heat sink in a secured position. Intel’s evaluations indicate that a 50 mil lip is not adequate and that a 70 mirequired to ensure reliable performance during shock and vibration testing. Tests also show t70 mil lip works well with CPGA packages. In addition, the side of the package is electricallyconductive. If the heat sink is electrically conductive, and the lip touches the side of the packthen electrical shorting may occur, causing damage to the processor. In addition, the side of package has exposed metal that is electrically conductive. If the heat sink is electrically conduand the lip touches the side of the package, then electrical shorting may occur, causing damthe processor. Manufacturers should work with their heat sink suppliers to ensure that their hsink designs can accommodate both PPGA and CPGA packages.

A5562-01

0.8

0.6

0.4

0.2

0.00 2 4 6 8 10

0 CS [C

/W]

Clip Force [lb]

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.20 2 4 6 8 10

0 ja

[C/W

]

Clip Force [lb]

0ja0cs

NOTES:= Junction to Ambient= Case to Sink Thermal Resistance (˚CW)


Pinned Packaging

Figure 13-14. A Heat Sink Design with a Lip

13.6.4 Method for PPGA Heatsink Attach

The impact of the PPGA package on board assembly was studied by assembling PPGA packages into sockets soldered on boards. A suggested sequence for mounting the PPGA packages is:

1. With the package in the socket, place the Conductacoat foil on top of the package.

The process flow for this step may be slightly different for the ZIF versus LIF sockets. For ZIF sockets the grease foil is placed on the CPU before insertion into the socket. For the LIF sockets place the thermal grease foil on the CPU after it is inserted into the socket. However, use manufacturing controls when stacking up the CPU, thermal interface and the heat sink to avoid foil misplacement on the PPGA slug.

2. Place the heat sink on the package and hook the heat sink clip onto the socket.

Note: Components on the top, and exposed metal on the side of the PPGA package can be shorted by any electrically conductive material including heat sinks, thermal grease (if electrically conductive) and thermal grease foil carriers.

13.7 PPGA Performance Characteristics

13.7.1 Thermal Characteristics

To improve thermal performance, the PPGA package uses a high thermal conductivity heat slug. The die is attached directly to the nickel plated copper heat slug, resulting in a lower thermal resistance than the comparable ceramic version. By effectively spreading the heat flux, the PPGA package is able to lower its thermal resistance. All data covered in this section is specific for P54CS die size only. However, the trend and advantage of PPGA over CPGA is identical for different die sizes. Similar advantages of PPGA over CPGA can be expected for all the other die sizes. Based on measurements of the components, Figure 13-15 demonstrates the advantage of PPGA over CPGA in terms of thermal resistance.

A5773-01

Board

Socket LeverZIF Socket

Heat Sink

PPGA PackageClip Heat Sink Lip


Pinned Packaging

rray

Figure 13-15. PPGA Has Better Thermal Conduction / Spreading

θja of PPGA is about 1.1° C/W lower than that of CPGA. Table 13-13 to Table 13-18 detail the thermal resistance values for the components in ceramic pin grid array and plastic pin grid apackages.

A5774-01

Larg

e D

ieS

mal

l Die

CPGA PPGA

T

T

PPGA Thermal Benefits (Tj Improvements) More Pronounced When:Absolute Power is Higher....Because of Lower Thermal RDie Size is Smaller....Better Spreading of Concentrated Heat Flux

....................

....................

....................

....................

Table 13-13. θca [°C/W] for Different Heat Sink Heights and Air Flow Rates (CPGA)

θca [oC/W] vs Air Flow Rate [LFM]

Heat Sink Height 0 100 200 400 600 800

0.25” 9.4 8.3 6.9 4.7 3.9 3.3

0.35” 9.1 7.8 6.3 4.3 3.6 3.1

0.45” 8.7 7.3 5.6 3.9 3.2 2.8

0.55” 8.4 6.8 5.0 3.5 2.9 2.6

0.65” 8.0 6.3 4.6 3.3 2.7 2.4

0.80” 7.3 5.6 4.2 2.9 2.5 2.3

1.00” 6.6 4.9 3.9 2.9 2.4 2.1

1.20” 6.2 4.6 3.6 2.7 2.3 2.1

1.40” 5.7 4.2 3.3 2.5 2.2 2.0

1.50” 5.5 4.1 3.1 2.4 2.2 2.0

None 14.5 13.8 12.6 10.5 8.6 7.5

NOTE: 1. θca is case-to-ambient thermal resistance. θca values shown in this table are typical values. The actual θca values

depend on the heat sink fin design, the interface between heat sink and package, the air flow in the system, and thermal interactions between CPU and surrounding components through the PCB and the ambient.


Pinned Packaging

Table 13-14. θjc [°C/W] for a CPGA Package with and without a Heat Sink (CPGA)

No Heat Sink With Heat Sink

Average θjc 1.7 1.25

Table 13-15. θa [°C/W] for Different Heat Sink Heights and Air Flow Rates (CPGA)

θja [oC/W] vs Air Flow Rate [LFM]

Heat Sink Height 0 100 200 400 600 800

0.25” 10.6 9.5 8.1 5.9 5.1 4.5

0.35” 10.3 9.0 7.5 5.5 4.8 4.3

0.45” 9.9 8.5 6.8 5.1 4.4 4.0

0.55” 9.6 8.0 6.2 4.7 4.1 3.8

0.65” 9.2 7.5 5.8 4.5 3.9 3.6

0.80” 8.5 6.8 5.4 4.1 3.7 3.5

1.00” 7.8 6.1 5.1 4.1 3.6 3.3

1.20” 7.4 5.8 4.8 3.9 3.5 3.3

1.40” 6.9 5.4 4.5 3.7 3.4 3.2

1.50” 6.7 5.3 4.3 3.6 3.4 3.2

None 16.2 15.5 14.3 12.2 10.3 9.2

Table 13-16. θca [°C/W] for Different Heat Sink Heights and Air Flow Rates (PPGA)

θca [oC/W] vs Air Flow Rate [LFM]

Heat Sink Height 0 100 200 400 600 800

0.25” 9.0 7.9 6.5 4.3 3.5 2.9

0.35” 8.7 7.4 5.9 3.9 3.2 2.7

0.45” 8.3 6.9 5.2 3.5 2.8 2.4

0.55” 8.0 6.4 4.6 3.1 2.5 2.2

0.65” 7.6 5.9 4.2 2.9 2.3 2.0

0.80” 6.9 5.2 3.8 2.5 2.1 1.9

1.00” 6.2 4.5 3.5 2.5 2.0 1.7

1.20” 5.8 4.2 3.2 2.3 1.9 1.7

1.40” 5.3 3.8 2.9 2.1 1.8 1.6

1.50” 5.1 3.7 2.7 2.0 1.8 1.6

None 13.0 12.3 11.4 8.0 6.6 5.7

NOTE: θca

is case-to-ambient thermal resistance. θca values shown in this table are typical values. The actual θca values depend on the heat sink fin design, the interface between heat sink and package, the air flow in the system, and thermal interactions between CPU and surrounding components through the PCB and the ambient.

Table 13-17. θjc [°C/W] for a PPGA CPGA Package with and without a Heat Sink (PPGA)

No Heat Sink With Heat Sink

Average θjc 1.3 0.50


Pinned Packaging

13.8 Electrical Characteristics

Electrical characteristic are discussed below. For more indepth coverage of electrical information please refer to Chapter 4: Performance Characteristics of IC Packages.

13.8.1 I/O Buffer

The package I/O model for components in PPGA packages is shown in Figure 13-16 as a first order buffer model. R0 and C0 values are independent of the package. Lp is the package inductance and includes bond wire inductance, trace inductance, pin inductance and socket inductance. Cp is the package capacitance and consists primarily of trace capacitance and socket capacitance. In this model, an effective inductance is used for the bond wire. Both self and mutual inductance are taken into account. The pin and its socket are considered as a single entity and a typical inductance value of 4.5 nH is used. A typical value of 1.0 pF is used for the socket capacitance.

Figure 13-16. First Order I/O Buffer Model for PPGA

Table 13-18. θja [°C/W] for Different Heat Sink Heights and Air Flow Rates (PPGA)

θja [oC/W] vs Air Flow Rate [LFM]

Heat Sink Height 0 100 200 400 600 800

0.25” 9.5 8.4 7.0 4.8 4.0 3.4

0.35” 9.2 7.9 6.4 4.4 3.7 3.2

0.45” 8.8 7.4 5.7 4.0 3.3 2.9

0.55” 8.5 6.9 5.1 3.6 3.0 2.7

0.65” 8.1 6.4 4.7 3.4 2.8 2.5

0.80” 7.4 5.7 4.3 3.0 2.6 2.4

1.00” 6.7 5.0 4.0 3.0 2.5 2.2

1.20” 6.3 4.7 3.7 2.8 2.4 2.2

1.40” 5.8 4.3 3.4 2.6 2.3 2.1

1.50” 5.6 4.2 3.2 2.5 2.3 2.1

None 14.3 13.6 12.7 9.3 7.9 7.0

A5775-01

R L

CC

0

0

p

pdV/dt


Pinned Packaging

13.8.2 Signal Quality

Intel has performed noise measurements on components in both CPGA and PPGA packages. The results show that at the component level, the PPGA packages are comparable to the CPGA packages. In addition, the results indicate that all PPGA parts have a higher mean-core-power supply level than CPGA parts.

13.8.3 EMI

The Federal Communications Commission (FCC) has set limits on the maximum radiation from electrical systems. Each component in a system should not exceed the level that is allocated to it. Electromagnetic Interference (EMI) levels from components in CPGA and PPGA packages have been measured with and without heat sinks attached. Measurements were performed up to a core clock frequency of 280 MHz. EMI levels are well below critical levels at all clock speeds tested. There is no significant EMI performance difference between CPGA and PPGA.


• Added µPGA

• Added FC-PGA

• General review of chapter with modifications


Ball Grid Array (BGA) Packaging 14

14.1 Introduction

The plastic ball grid array (PBGA) has become one of the most popular packaging alternatives for high I/O devices in the industry. Its advantages over other high leadcount (greater than ~208 leads) packages are many. Having no leads to bend, the PBGA has greatly reduced coplanarity problems and minimized handling issues. During reflow the solder balls are self-centering (up to 50% off the pad), thus reducing placement problems during surface mount. Normally, because of the larger ball pitch (typically 1.27 mm) of a BGA over a QFP or PQFP, the overall package and board assembly yields can be better. From a performance perspective, the thermal and electrical characteristics can be better than that of conventional QFPs or PQFPs. The PBGA has an improved design-to-produc-tion cycle time and can also be used in few-chip-package (FCPs) and multi-chip modules (MCMs) configurations. BGAs are available in a variety of types, ranging from plastic overmolded BGAs called PBGAs, to flex tape BGAs (TBGAs), high thermal metal top BGAs with low profiles (HL-PBGAs), and high thermal BGAs (H-PBGAs).

The H-PBGA family includes Intel’s latest packaging technology - the Flip Chip (FC)-style, H-PB-GA. The FC-style, H-PBGA component uses a Controlled Collapse Chip Connect die packaged in an Organic Land Grid Array (OLGA) substrate. In addition to the typical advantages of PBGA pack-ages, the FC-style H-PBGA provides multiple, low-inductance connections from chip to package, as well as, die size and cost benefits. By providing multiple, low-inductance connections the FC-style, HPBGA offers equivalent or better performance than an extra on-chip metal layer. The FC technology also provides die-size benefits through the elimination of the bond pad ring and better power bussing and metal utilization. The OLGA substrate results in a smaller package, since there is no cavity, and thermal management benefits since the thermal solution can directly contact the die.


Ball Grid Array (BGA) Packaging

14.2 Package Attributes

14.3 Package Materials

The PBGA package consists of a wire-bonded die on a substrate made of a two-metal layer copper

Table 14-1. PBGA Package Attributes

PBGA

Lead Count 196(15mm)

208(23mm)

241(23mm)

256 (17mm)

256 (27mm)

304(31mm)

324(27mm)

421(31mm)

468(35mm)

492(35mm)

544(35mm)

Sq/Rect. S S S S S S S S S S S

Pitch (mm) 1.0 1.27 1.27 1.0 1.27 1.27 1.27 1.27 1.27 1.27 1.27


1.61 2.33 2.38 1.56 2.13 2.33 2.13 2.38 2.38 2.38 2.38

Weight (gm) .67 1.56 .70 3.46 2.86 3.87 5.06

Max. Footprint (mm)

15.20 23.20 23.20 17.20 27.20 31.20 27.20 31.20 35.20 35.20 35.20

Shipping Media:

Tape & Reel X X X X X X X X

Trays X X X X X X X X X X X

Desiccant Pack X X X X X X X X X X X

Comments/Footnotes

Table 14-2. H-PBGA/HL-PBGA Package Attributes

H-PBGA HL-PBGA

Lead Count 495 540 615 304 352 432

Sq/Rect. R S R S S S

Pitch (mm) 1.27 1.27 1.27 1.27 1.27 1.27


2.54 2.13 2.54 1.54 1.54 1.54

Weight (gm) 4.52 15.25 4.11 8.90

Max. Footprint (mm)

27.2 x 31.0 43.0 31.0 x 35.0 31.10 35.10 40.10

Shipping Media:

Tape & Reel X X

Trays X X X X X X

Desiccant Pack X X X X X X

Comments/Footnotes

Can be thermally enhanced with heat

sinks


sinks


sinks


sinks



clad bismaleimide triazine (BT) laminate. Four-metal layer substrate designs generally contain ad-ditional power and/or ground planes to improve electrical and thermal performance. The die and bonds are protected and encapsulated with molding compound. Via holes drilled through the sub-strate provide routing from the lead fingers to the respective eutectic (63/37 Sn/Pb) solder balls on the underside. Thermal performance can be enhanced by adding heatsink fastened through mechan-ical means using thermal grease or by using conductive epoxy.

The H-PBGA and HL-PBGA, however, are configured differently to provide for greater thermal and if required, electrical performance. The thermal advantage provided by this design is based first upon attaching the die to the bottom surface of a heatspeader or slug that also forms the topside of the package. Secondly, because the copper heatspreader forms the top of the package, the thermal resistance is extremely low and exposes the package surface to available air flow. If required, this heatslug can be directly coupled to active or passive thermal management devices such as heat sinks or heat pipes. Improved electrical performance is achieved through additional power and/or ground planes.

The FC-style, H-PBGA package consists of a die reflowed onto an oraganic substrate. The substrate consists of four to ten layers of copper with insulating materials in between. The copper layers are connected by vias. BT (Bismaleimide Triazine) resin reinforced with glass fiber forms the core of the organic substrate. Solder bumps (3% Sn, 97% Pb) on the die surface are joined with solder pads (60% Sn, 40% Pb) on the organic substrate in a reflow furnace. These joints form the electrical/mechanical connection between the FC die and the OLGA package. An epoxy underfill fills the gap between die and the substrate. This underfill provides mechanical support and protection for the die-to-package interconnects and also minimizes thermal stress on the die due to CTE (coefficient of thermal expansion) mismatch with the substrate materials. The die backside is exposed allowing the thermal solutions and thermal interface material to have direct contact with the die surface.

See Figure 14-1, Figure 14-2, and Figure 14-3 for description of PBGA, HL-PBGA, and FC-style H-PBGA packages.

Figure 14-1. PBGA Die Up Cross-Section

A5764-01

Die Up Design Mold Compound

Solder Balls

BT PCBNon-laminate



Figure 14-2. HL-PBGA Die Down Cross-Section

Figure 14-3. FC-Style, H-PBGA Die Up Cross-Section

A5765-01

Copper Slug/Heatspreader

Encapsulant

Die Down Design Solder Balls

BT PCB Laminate

A7428-01

BT LamintateC4 Bumps Die-up Design

Underfill

Solder balls



14.4 Package Dimensions

Table 14-3. Plastic Ball Grid Array Family Attributes

Package Family Attributes

Category Plastic Ball Grid Array

Acronym PBGA, HL-PBGA, H-PBGA

Ball Counts PBGA: 196, 208, 241, 256, 304, 324, 421, 468, 492, 544.

HL-PBGA: 352, 304, 432.

H-PBGA: 540.

FC-style, H-PBGA: 495, 615.

Ball Material Solder (63/37)

Ball Pitch 1.0, 1.27 mm

Board Assembly Type Surface Mount

Table 14-4. Symbol List for Plastic Ball Grid Array Family


A Overall Height

A1 Stand Off

A2 Encapsulant Height

A3 Die Height with FC Bumps and Underfill

b Ball Diameter

c Substrate Thickness

D Package Body Length

D1 Encapsulant Length


E1 Encapsulant Width

F1 Die Width

F1 Die Length

e Ball Pitch

N Ball Count i.e. Lead Count

S1 Outer Ball Center to Short Edge of Body

S2 Outer Ball Center to Long Edge of Body

NOTE: 1. Controlling Dimensions: Millimeter



Figure 14-4. PBGA Package Ball Array Configuration

A5487-03

Pin #1Corner

PBGA 208Pin #1CornerPBGA 196

Pin #1CornerPBGA 304

Pin #1Corner

PBGA 241Pin #1CornerPBGA 256 (17mm)

Pin #1Corner

PBGA 256 (27mm)



Figure 14-5. PBGA Package Ball Array Configuration Continued

A6124-02


Pin #1Corner

PBGA 324Pin #1Corner

PBGA 421


Pin #1CornerPBGA 544 (35mm)



Figure 14-6. 15mm PBGA Outline Drawing

A5829-01

Pin #1Corner

Pin #1 Corner

15.00 ±0.20

45 Chamfer4 Places

Pin #1 I.D.1.0 Dia. 1.0

3 Places

30

Top View Bottom View196 Solder Balls

Side View

Seating Plane

˚

˚

ABCDEFGHJKLMNP

1.00 Ref 1.00

1413

1211

109

87

65

43

210.60

0.40

13.00 ±0.25

15.00 ±0.20

13.00 ±0.25

1.00

1.00 Ref

10.57 Ref

10.57Ref

0.85

0.40 ± 0.10

1.61 ± 0.19

0.36 ± 0.04

Notes:1. All Dimensions are in Millimeters



Figure 14-7. PBGA Outline Drawing

A5766-01

Pin #1 Corner

D

D1

45 Chamfer4 Places

E

E1

Pin #1 I.D.1.0 Dia.

bPin #1Corner

S1 e1.0

3 Places

30A2

A1

A

C

Top View Bottom View

Side View Seating Plane

˚

˚

1. All Dimensions are in Millimeters

Note:

Table 14-5. PBGA Package Family Dimensions

PBGA Package Dimensions

Min Max Min Max Min Max Min Max Min Max Min Max

N 196 208 241 256 (17mm) 256 (27mm) 304

A 1.37 1.75 1.94 2.32 2.17 2.59 1.37 1.75 1.94 2.32 2.12 2.54

A1 .30 .50 0.50 0.70 0.50 0.70 0.30 0.50 0.50 0.70 0.50 0.70

A2 .80 .90 1.12 1.22 1.12 1.22 0.75 0.85 1.12 1.22 1.12 1.22

D 14.80 15.20 22.80 23.20 22.80 23.20 16.80 17.20 26.80 27.20 30.80 31.20

D1 12.75 13.25 19.25 19.75 19.25 19.75 14.75 15.25 23.75 24.25 25.50 26.70

S1 1.00 REF 1.34 REF 1.34 REF 1.00 REF 1.44 REF 1.53 REF

b .40 .60 0.60 0.90 0.60 0.90 0.40 0.60 0.60 0.90 0.60 0.90

c

(2L/4L)

.32/.52 .40/.60 .32/.52 .40/.60 .32/.55 .40/.67 .32/.52 .40/.60 .32/.52 .40/.60 .52 .60

e 1.0 1.27 1.27 1.0 1.27 1.27



Table 14-6. PBGA Package Family Dimensions Continued

PBGA Package Dimensions

Min Max Min Max Min Max Min Max Min Max

N 324 421 468 492 544

A 1.94 2.32 2.17 2.59 2.17 2.59 2.14 2.52 2.14 2.52

A1 0.50 0.70 0.50 0.70 0.50 0.70 0.50 0.70 0.50 0.70

A2 1.12 1.22 1.12 1.22 1.12 1.22 1.12 1.22 1.12 1.22

D 26.80 27.20 30.80 31.20 34.80 35.20 34.80 35.20 34.80 35.20

D1 23.75 24.25 25.75 26.25 29.75 30.25 29.75 30.25 29.75 30.25

S1 1.44 REF 1.53 REF 1.63 REF 1.63 REF 1.63 REF

b 0.60 0.90 0.60 0.90 0.60 0.90 0.60 0.90 0.60 0.90

c

(2L/4L)

.32/.55 .40/.67 .52/.55 .60/.67 .52/.55 .60/.67 .52/.55 .60/.67 .55 .67

e 1.27 1.27 1.27 1.27 1.27



Figure 14-8. HL-PBGA/H-PBGA Package Ball Array Configuration

A5832-02

Pin #1CornerHL-PBGA 304

Pin #1CornerHL-PBGA 352

Pin #1CornerHL-PBGA 432 Pin #1

CornerH-PBGA 540



Figure 14-9. HL-PBGA Package Outline and Ball Array Configuration

Table 14-7. HL-PBGA Dimensions

304 352 LD 432

Symbol Min Max Min Max Min Max

A 1.41 1.67 1.41 1.67 1.41 1.67

A1 0.56 0.70 0.56 0.70 0.56 0.70

b 0.60 0.90 0.60 0.90 0.60 0.90

c 0.95 0.97 0.85 0.97 0.85 0.97

D 30.90 31.10 34.90 35.10 39.90 40.10

E 30.90 31.10 34.90 35.10 39.90 40.10

e 1.27 1.27 1.27

S1 1.53 REF 1.63 REF 0.95 REF

A5830-01

Pin #1 Corner

D

E

Pin #1 I.D.1.0 Dia.

bPin #1Corner

S1 e

A1

A C

Top View Bottom View

Side View Seating Plane 1. All Dimensions are in MillimetersNote:



Figure 14-10. H-PBGA with 25.4 mm square Slug Outline Drawing

Table 14-8. H-PBGA Package Dimensions

540

Symbol Min Max

A 3.59 4.10

A1 0.40 0.70

A2 0.95 1.10

b 0.60 0.90

c 2.00 2.30

D 42.30 42.70

D1 - 27.70

E 42.30 42.70

E1 - 27.70

e 1.27

S1 1.56 REF

NOTE: Measurement in millimeters

A5831-01

D

D1

E

E1

b

ePin #1CornerA2

A1

A

C

Top View

Bottom View

Side ViewSeating Plane

1

Pin #1CornerSlug

S

1. All Dimensions are in MillimetersNote:



Figure 14-11. FC-Style H-PBGA Package Ball Array Configurations

Figure 14-12. FC-style, H-PBGA 495 Outline Drawing

A7458-01

Pin #1Corner

FC-style,H-PBGA 615Pin #1

Corner

FC-style,H-PBGA 495

A7459-01


Pin #1Corner

S1

e

φbS2 e

1

ABCDEFGHJKLMNPRTUVWY

AAABACAD

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Bottom View

LabelMark

SubstrateKeepoutOutline

DieTop View

F1

F2D

E

Side View

Seating Plane

A3

A1A

C



Figure 14-13. FC-style, H-PBGA 615 Outline Drawing

Table 14-9. FC-style, H-PBGA Package Dimensions

495 615

Symbol Min Max Min Max

A 2.29 2.79 2.29 2.79

A1 0.5 0.7 0.5 0.7

A3 0.854 0.854

b 0.60 0.90 0.60 0.90

c 0.93 1.07 1.00 1.20

D 30.9 31.1 34.9 35.1

E 27.0 27.3 30.9 31.1

F1 9.2 10.3

F2 11.2 17.4

e 1.27 1.27

S1 0.895 1.625

S2 0.900 0.895

NOTE: Measurement in millimeters

A7460-01


Side View

Seating Plane

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F1

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14.5 Package Usage

BGA packaging can be used for high-performance applications with high thermal and electrical re-quirements. BGAs fit ICs into a smaller footprint, decreasing pitch spacing, by utilizing an array of solder ball connections. This allows for a higher density of I/O connections than that of conventional QFPs or PGAs. The result is a considerably smaller finished package size.

In general, the ball grid array features shorter electrical path lengths which reduce inductance. Me-chanical problems such as fragile leads are absent. The larger spacing between solder lands provide adequate tolerances for more reliable surface mounting. Some heat dissipation can be facilitated through the substrate. These characteristics make the ball grid array package suitable for a wide va-riety of devices: microprocessors/microcontrollers, ASICs, memory, PC chip sets, and other prod-ucts. A thin profile and smaller footprint make the BGA an attractive option when board space is a major concern. Small body size BGA packages come close to chip scale package size for use in space constrained applications.

The FC-Style, H-PBGA also allows for Voltage Indentification through an open circuit or a short to Vss on the processer substrate. These opens or shorts are achieved by selectively depopulating some of the balls. Voltage Identification can be used to support automatic selection of power supply volt-ages.

14.6 Handling: Shipping Media

14.6.1 Mid-temperature Thin Matrix Tray

The BGA packages are shipped in either a tape and reel or a mid-temperature thin matrix tray that complies to the JEDEC standards. Typically, JEDEC trays have the same ‘x’ and ‘y’ outer disions and are easily stacked for storage and manufacturing. For tray dimensions please refeChapter 10 of this data book. The JEDEC style shipping trays are returnable to Intel for reuse. ter 10 contains detailed information on the return addresses for the different types of shippingIntel will pay all shipping costs associated with the return.

14.6.2 Tape and Reel

Tape and reel handling is engineered to contain and protect surface mount components in emsemi-conductive PVC or polystyrene carrier tapes to aid the high speed board mounting opefound in many high volume board operations. The BGA packages are shipped from Intel in a ctape made of antistatic treated plastic. It offers exceptional strength and stability over extendeand wide temperature variations, while at the same time maintaining flexibility for use in automequipment. The cover tape used is heat sealable, transparent, and antistatic. The loaded carrwill be wound onto a plastic reel. The carrier tape dimensions meet the EIA standards. The tareel packaging standards offered by Intel for many of the PBGA/HL-PBGA packages meet thstandards, ie, EIA 481-1, 481-2, and 481-3. However, there are some products shipped fromin tape and reel that have a package orientation in the tape that is different from the EIA stanIt is advisable that the user of Intel BGA products obtain a product data sheet that shows theand reel shipping details to insure the correct cavity orientation is understood.

14.7 Moisture Sensitivity

Most PBGA components are highly sensitive to moisture exposure before the reflow temper



unt

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pack-inimal

apsed to store tively

Com-ures be-not the ve been tep is

at de-

CB pad during

r nd, thus

exposure. Maintaining proper control of moisture uptake in components is critical to the prevention of "popcorning" of the package body or encapsulation material. BGA components, before shipping, are baked dry and enclosed in a sealed desiccant bag with a desiccant pouch and a humidity indicator card. Most BGA components are classified as a level 3 or level 4 for moisture sensitivity as per the IPC/JEDEC Spec J-STD-020, “Moisture/Reflow Sensitivity Calculation of Plastic Surface MoDevices.”

With most surface mount components, if the units are allowed to absorb moisture beyond thof bag times for their moisture rating, damage may occur during the reflow process. Chapter 8 of this data book provides an in-depth view of package preconditioning methods and moisture tivity requirements. Please refer to Chapter 8 for more information regarding how moisture sensitivcomponents are classified.

Prior to opening the shipping bag and attempting solder reflow, the moisture sensitivity of theages being used should be understood so proper precautions can be taken to insure that a mout of bag time is maintained. This will insure that the highest possible package reliability is achieved for the final product. If previously bagged product cannot be mounted before the elout of bag time for that product, the parts can be rebaked as per Chapter 8. Another option is the opened units in a nitrogen cabinet or dry box until needed. Placing units in a dry box effec‘stops the clock.’

It should be understood that packages continue to gain moisture even after board mounting.ponents that need to be reworked must be completely processed throught all thermal exposfore the original out of bag limits are reached. If this is not possible, or the time allotment is ridgely followed, bake-out of the completed boards must be accompliished before subjectingcomponents to the heat of the rework process. Products being removed from boards that hareturned from the field for failure analysis, must be baked dry before heat expousure. If this sskipped, massive damage to the component will result, rendering useless any further effortstermining the cause of failure.

14.8 Designing Boards For BGAs

Most BGA packages use Solder Mask Defined pads on the package side of the solder ball. Psize is typically close to or identical to the package pad size. This provides for balanced stressthermal cycling, which helps to maximize fatigue life.

14.8.1 Solder Mask Defined (SMD) Pad

In the solder mask defined (SMD) pad shown in Figure 14-14, the copper for the pad area is largethan the desired land size. The opening in the solder mask is made smaller than the copper ladefining the mounting pad. A couple of points to consider with solder mask defined pad are:

• There is an advantage in that the overlap of the solder mask onto the copper enhances the copper adhesion to the laminate surface. When using resin systems where adhesion is low, this is an important consideration.

• One disadvanatage of SMD pads is that the fatigue life has shown to be lower then NSMD pads through long term reliaiblity testing. Because of this issue, the solder mask angle at the pad edge has been thinned on many new package designs to minimize the mask impingment on the solder ball.



Figure 14-14. Solder Mask Defined (SMD) Pad

14.8.2 Non-Solder Mask (i.e. Metal or Copper) Defined Pad

The non-solder mask (sometimes called metal or copper) defined pad Figure 14-15, has a solder mask opening larger than the copper area. Pad size is controlled by the copper etch quality control. This is generally less accurate than the solder mask photo image control. Non-solder mask pad size varies more than with the SMD pad. However, because the edges of the copper do not need to extend under the solder mask, the pad can be either made larger, or provided more line routing space be-tween pads. Pattern registration is also as accurate as the copper artwork, which is generally much more accurate than the solder mask pattern. Vision registration on copper fiducials (reference points) will give exact location of the site. With SMD pads, the misrepresentation error of the solder mask will also shift the location of the entire site relative to vision fiducials.

Figure 14-15. Non Solder Mask Defined (Non-SMD) Pad

A5826-01

Solder MaskCopper Pad Area

A5833-01

Solder MaskDefined

Copper Pad Area



14.8.3 BGA Package Considerations

The following subsections address the BGA package layout and includes guidelines for pad size, vias and routing. It is important to implement a keep-out zone around BGAs for rework purposes. The keep-out zone distance is determined by the type of rework equipment to be used. See Section 14.9.8 for more information.

14.8.3.1 Routing and Pad Size

Many perimeter style BGA package typically contains four or five rows of solder balls; as such, it is possible to route one or two traces between pads to route signals in a four-layer board.

• When routing one trace between pads, the manufacturers preferred line width and spacing technology becomes a limiting factor.

• When routing two traces between pads, 5 mil traces and 5 mil spaces are required for a 24 mil pad size. For a 20 mil pad size, 6 mil traces and 6 mil spacing can be used. Figure 14-15 shows a routing example for 20 mil ball pads. Either pad size is acceptable, so the decision is primarily determined by the manufacturers preferred line width and spacing technology.

• When larger trace widths are desired, another alternative is to route 5/5 or 6/6 (mil space/mil trace) within the BGA pads, and then neck up to the larger trace widths once you have cleared the BGA component

Using the routing scheme shown in Figure 14-16, the first two ball rows are routed on the top signal layer and the inner two rows are routed on the bottom side of the package substrate. In this case vias are required between the BGA pads. Using the routing scheme shown in Figure 14-10, the first three ball rows are routed on the top signal layer and the inner row is routed on the boards bottom side. In this case the vias are not required in between the BGA pads. Vias are discussed in Section 14.8.3.3.

Figure 14-16. Board Side BGA Routing Example One

A5822-01

row 4 row 3 row 2 row 1

24 Mil Dia Pad

12 Mil Dia Via Plated

6 Mil Space

6 Mil Trace

24 Mil Dia Mask

20 Mil Dia Pad

50 mil pitch

Component Edge

Top Signal Layer



plated unt-

ctors, dict-

ing int can e sol-om dis-

ed. All hat, at vered.

ften

Figure 14-17. Board Side BGA Routing Example Two

14.8.3.2 Bottom Layer Routing

Figure 14-16 shows a routing example for the solder side of a four-layer board. The first two rows (R1, R2) are routed on the component side, while the inner two rows (R3, R4) are routed on the board’s solder side. This example shows 6 mil trace widths.

14.8.3.3 Plated Through Hole (PTH) Isolation

Regardless of the technique used for the mounting pads shape or definition, isolation of the through hole (PTH) from the mounting pad is important. If the PTH is contained within the moing pad, solder will wick down the PTH. The amount of solder that wicks depends on many faincluding PTH finish and coating variations. Because of this, the results are somewhat unpreable. Some solder joints may be unaffected, while others will be starved to the point of creatopens. The worst result is a partially starved joint with severely reduced cross section. This johave significantly lower fatigue life and result in early system failure. Because the quality of thder joint is guaranteed by control rather than inspection, designs/processes that result in randtributions are generally considered unacceptable, and the PTH-in-pad design is not suggestvias located between the BGA ball pads must be covered with solder mask. It is suggested tminimum, vias on the top side be covered with solder mask. The bottom side can also be co

Figure 14-14 shows the connection between the BGA ball pad and a via. This connection is oreferred to as the dogbone footprint.

A5823-01

row 4 row 3 row 2 row 1

24 Mil Dia Pad

12 Mil Dia Via Plated

5 Mil Space 5 Mil Trace24 Mil Dia Mask

20 Mil Dia Pad

50 mil pitch

Component Edge

Top Signal Layer



for trate bal-ptable f high oduc-sure

rations pera- elec-

low prop-nt ehouse limit ation

h sides

Figure 14-18. BGA Pads and Vias

14.8.3.4 PCB Quality and Co-planarity

The assembly yields of mounting BGA components is influenced by the PCB properties and process control procedures followed by the manufacturer of the PCB. PCB co-planarity requirements are di-rectly related to the package size. Typical PCB manufacturing specifications allow up to 0.01 mm (1%) of warpage. For a 35 mm component, this would equate to nearly 0.35 mm of warpage in the area under the package footprint. It is obvious that no large body (>20 mm) component, peripheral leaded or BGA, would consistently solder to a site with this amount of bow. Most responsible PCB vendors take precautions to be well below the 0.010 mm specification that is recommended in the industry standard specifications.

14.8.3.5 Solderability Testing of BGA Components

Standard solderability test methods for through-hole and other leaded devices aren’t suitabletesting BGA components. A ‘dip and look’ process will strip much of the solder ball off the subssurface, leaving little to examine for determining if the solder surface was wettable. A wettingance will only be able to sample specific solder balls on the substrate, which can be an accemethod for sampling, but would take a considerable length of time to do the whole surface olead count devices, and would still only be representative of one unit. The untestablility of prtion BGA packages has led most suppliers to further develop their ball attach processes to inminimal solder oxidation occurs. In some instances, this means doing all test and burn-in opebefore ball attach. Where this is impossible, it means establishing stringent control over all otions after ball attach that would impact solderability. These operations, which usually includetrical testing, burn-in, inspection, bake and bag, shipping, storage, etc., are characterized to minimize oxidation and solder ball damage. However, with today’s fluxes and controls on reffurnaces, it is very unlikely that board mount problems can be traced to solder ball oxidation. Ifer solder type, viscosity, screen print, and reflow practices are followed, very high board mouyields are being obtained even with product that has been stored for a couple of years on warshelves. Most product is used within one year from the manufacturing date, which is also thefor the desiccant in the moisture barrier bags. If solderability problems persist, a careful evaluof the PCB solder pads should be done to insure that there is proper wetting occurring on bot

A5824-01

30 Mil Dia Solder Ball

20 or 24 Mil Dia Pad

24 or 28 Mil Dia Solder Mask

10 Mil Trace

27 or 24 Mil Dia Pad

16 or 14 Mil Dia Via Plated

Solder MaskMust Cover The Via



of the connection. Soderability problems on BGAs are often traced to oxidation of the pads on the boards.

14.9 Package To Board Assembly

14.9.1 Fluxing

Most BGA assembly is done with a solder paste that contains flux, however, there are some compa-nies reporting adequate results from mounting BGAs when using low residue, no clean or an aque-ous clean flux. To obtain high yields and reliable joints this may require monitoring the surface insulation resistance of the board to insure there are no foreign contaminates on the board or slder ball surface that will show up as reliability problems later on.

Fluxing without paste does come with disadvantages; the ball reflowed with only flux will have a smaller solder volume than the initially attached ball. Therefore, the package will result in a slightly (usually 0.001-0.002mils) lower standoff height from the PCB. The thermal cycle reliability of BGA component could be slightly compromised because of the reduced standoff height, especially if sol-der balls are under the die area as in full array BGA types. The self centering ability decreases be-cause of the smaller solder volume. The formation of the fillet between the ball and the board can be hindered if the ball is mis-shapen or there is some minor imperfection with the pad area.

14.9.2 Solder Paste

Assembly with solder paste has advantages over just fluxing the pads. The paste is the vehicle to provide the flux necessary to both the PCB and solder ball surfaces to enable proper soldering of the component to the board. A no-clean or aqueous clean solder paste with 63Pb/37Sn is commonly used in mounting the PBGA. Typically the choice of solder paste determines the profile and reflow parameters. Most paste manufacturers provide a suggested thermal profile for their products which should be referenced prior to developing a reflow process.

Since the BGA balls consist of solder, the flux activity on the ball surface is assured, so long as the paste reaches the ball surface. The selection of paste is generally made to fit the entire component mix being assembled, not driven by the use of BGA packages. It is necessary, however, to ensure that all the thermal and environmental requirements of the paste can be met.

On the average, the BGA packages do not need any specialized solder paste. However, most solder suppliers have developed a BGA paste that has minimal voiding during reflow. This paste may also be used for non BGA components as well. It is advisable that a time limit of 45 minutes or less be maintained from screen pasting to reflow (30 minutes is optimum) to avoid the paste drying out and affecting solderablity or contribuing to voids in the solder balls. Some manufacturers ratings (of 2 to 6 hours) for air exposure is judged by using 500 gram jars, not small dots of solder sitting on a board which dry out considerably faster.

14.9.2.1 Paste Deposit Inspection

The quality of the paste print is the single most important factor in producing high yield BGA as-semblies. Defects detected after paste print require a strip and rescreen of the PCB. Any deviation can turn into a defect downstream requiring rework and repair. Thus the most economic area to in-tensify process controls when beginning BGA assembly is in the paste screening step.

Excessive volume of paste will have some negative effects on the self centering properties of the BGA (see Section 14.9.4.1) and could cause yield or reliability issues (shorts or bridges). However,



adequate paste thickness is required to compensate for board warp, poor component coplanarity, and to achieve acceptable board reliability. Another factor in yield or reliability is the presence of ade-quate flux. Any situation, such as a plugged stencil hole, that causes flux or paste to be omitted or severely limited on a pad can lead to an open connection after reflow. Print misregistration or ex-cessive slumping that connects adjacent conductors (either pads or PTHs) is also a source of con-cern, as a short may be the final result. Therefore, it, is usually beneficial to perform a paste inspection step, especially during early manufacturing runs. Whether to use visual/microscope in-spection, manual measurement, or invest in an automated system depends on the volume to be run and the overall manufacturing philosophy.

14.9.3 Solder Stencils

The stencil thickness, as well as the etched pattern geometry, determines the precise volume of sol-der alloy deposited onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform reflow-solder processing. Stencils are usually made of brass or stainless steel, with stainless steel being more durable. Hole designs are dependant on the solder ball size, squeegee type, board layout, and the paste used. There appears to be no single hole style that is used by everyone. There are companies that are using square, diamond, round and oval shapped holes. Round holes are definitely the dominate design. Many companies are promoting a stencil with a rounded corner, square hole with five degree tapered opening has been shown to be a good hole design to use for BGAs with 20 mil or smaller solder balls. Thickness of the stencils are usually in the 6 to 8 mil (.15 to .20 mm) range. A squeegee durometer of 95 or harder should be used. The blade angle and speed must be fine tuned to ensure even paste transfer. Ensuring proper stencil application is the most important factor with regards to reflow yields further on in the process. The paste materials tend to dry out when not properly environmentally controlled (see14.9.2 for more explanation).

Maintaining a diameter to stencil thickness ratio of at least 3 to 1 can provide good BGA print char-acteristics, with larger openings providing better print quality. It is also beneficial to use an opening at least as large as the mounting pad to give a wide placement window. A typical design might be a 0.028 opening in a 0.006 thick stencil, going over a 0.024 pad on the PCB with 30 mil solder balls.

The printing of small amounts of paste onto the solder mask surrounding the pad has not proven to be a problem in either yield or reliability.



Figure 14-19. Typical BGA Paste Deposit

14.9.4 Placement and Alignment

14.9.4.1 Placement

BGA packages have shown excellent self-centering properties. Because of this, wide variation in placement location is accommodated during reflow of the solder joints. The general rule for BGA packages is that the placement be at least 50% on pad. This is illustrated graphically in Figure 14-16. The self centering characteristics of the BGA are attributed to surface tension which will pull the component onto the pad during peak reflow temperatures.

Figure 14-20. Ball to Pad Placement Misregistration (A4470-01)

A5849-02

5 degree angle to allow for reliefwhen removing screen from board

Stencil side of Screen

Board side of Screen

SqueegeeDirection of squeegee travel

A5825-01

Mounting Pad

Solder Ball



Most common placement tools used for flatpack or other non-discrete packages have much better accuracy than necessary, and placement variability is rarely an issue for BGAs.

14.9.4.2 Alignment

The pick and place accuracy governs the package placement and rotational (theta) alignment. This is equipment/process dependent. Slightly misaligned parts (less than 50% off the pad) typically au-tomatically self-align during reflow. Self centering on the pads is greatly reduced for grossly mis-aligned packages (greater than 50% off the pad) and may develop electrical shorts, as a result of solder bridges, if they are subjected to reflow.

14.9.4.3 Pick-n-Place Machines

The main areas of concern for Pick-n-Place machines are:

• Component body alignment

• Component ball alignment.

• Inspection of component balls before placement.

Most alignment inspections can be done from either the top or the bottom. As there is no defining mark on the bottom of the BGA package, the only way to ensure Pin 1 is located in proper position is from the top by using the Pin one mark as the orientation indicator. Proper placement is then done:

• From the top by alignment marks on the board (which must be done on the stencil, see Figure 14-17).

• By aligning off the bottom of the component by using an up-down vision system to accurately place the balls on the solder paste.

Because the top surface of some of the BGA packages (like the HL-PBGA types) are highly reflec-tive, some top side vision systems do better with their inspection process if they use a diffuse light-ing source instead of polarized source. A round fluorescent tube type light near the package or a light filter over the polarized fixture seems to enhance the operation of some systems.

14.9.4.4 Outline for Machine Placement

Variability of the body dimension specification is 0.10 mm (~4mils) worst case. The same data in-dicates that the ball location variability is 0.075 mm (~3mils) worst case. The impact on alignment during the placement (vision) process is:

• If the package edge is used to determine the true center of the component, alignment of the balls is within 0.075 mm of true position.

• If only the package edge is used, alignment of the balls is within 0.10 mm + 0.075 mm (0.175mm, ~6mils) of true position.

Given that the allowable misalignment of the balls is 50% or less of the pad width (e.g.; 12mils for a 24mil pad), a manufacturable process can be achieved using only the package edge (outline) and alignment marks on the stencil for machine placement, see Figure 14-16.



Figure 14-21. BGA Alignment

14.9.5 Solder Reflow

Except for semi-accurate placement of packages, there are no special requirements necessary when reflowing BGA components. As with all SMT components, it is important that profiles be checked on all new board designs. In addition, if there are multiple PBGAs on the board, the profile should be checked at the different PBGA locations on the board. Component temperatures may vary be-cause of nearby surrounding components, location of the part on the board, and areas of package densities. Temperatures may also be different at the edge of the package than in the center. Chapter 9 provides a more in-depth look at how to manage these types of concerns. Table 14-10 provides specific parameters to be followed during SMT preheat, preflow, and reflow processes. Proper des-iccant handling procedures should be followed prior to reflow to insure optimal reliability of the fi-nal product. See Chapter 8 for details.

When doing second pass wave solder of mixed technology components on the same board as BGAs, insure that the solder wave profile is very tightly controlled. A high temperature on the wave solder process can warp the board and break the joints on the topside of the BGA component.

A5827-01

Four Corner AlignmentMarks on Silkscreen

35 x 35mm 35 x 35mm

Alignment on Silkscreen



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14.9.6 PCB Cleaning

Cleaning can be done with aqueous, semi-aqueous, or solvent based systems, or not done at all. With the need to eliminate Chloroflourocarbon (CFC) containing materials, many companies have moved to using a no-clean or aqueous based system. The proper cleaning of solder flux residues and other ionics left on the boards from the assembly process is necessary for long term reliability of the fin-ished product. “NO clean” fluxes simply mean that there is no harmful residues left on the boawill cause any corrosion or damage to the components if left on the board. This residue has times shown to be a collection point for outside contamination on the board surface. For anycation, an evaluation needs to be done to see if the remaining residue still needs to be removthe boards in final application.

14.9.7 SMT Process

Many factors contribute to a high yielding BGA assembly process. A few of the key focus areatheir contributing factors are highlighted in Table 14-11.

14.9.8 Rework of BGA Packages

SMT yields of BGA packages are very high, but there may still be a possible need for reworkcomponents. Component defects, SMT defects, or other functional problems require rework package from the PCB.

Table 14-10. PBGA/HL-PBGA Example SMT Reflow

Zones Characteristic Description Windows/Limits

Preheat Initial heating of lead/component Peak temperature

1-3 ° C/second100-140 ° C

Pre-Reflow Dryout and solder paste activationSoak Time

120 -170 ° C120 Seconds

Reflow Time above 183 ° CPeak component body

temperature.

45 - 120 Seconds205 - 225 ° C

220 ° C Maximum

Cool Down Cooling rate 2 -3 ° C/second

Table 14-11. Essentials for Assembly Quality

Solder paste quality Uniform viscosity and texture. Free from foreign material. Solder paste should be used before the expiration date. Shipment and storage temperatures are maintained at the proper temperature. Paste is protected from drying out on the solder stencil.

Motherboard quality Clean, flat, well-plated solder ball land area. Good soldermask coverage.

Placement accuracy Tight tolerances are not usually required. The BGA can self-center itself as long as a major portion (more than 50%) of the solder ball is in contact with the fluxed solder paste land area on the board. Alignment marks (targets) on the PCB are helpful for placing parts.

Moisture Sensitivity Precautions Know your components moisture sensitivity classification and adhere to IPC/JEDEC moisture control conditions or package delamination or cracking may occur.



ent s hand sed to ly ad-

paste

zed to ckages. B. De-bly

head. profile is ap-

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Rework is the process of removing a component from a PCB, and replacing it with a new compo-nent. The removed component is not immediately reusable. The shape and volume of the solder balls will not be the same as a new package. If component reuse is desired, a separate process for replace-ment of solder balls should be used.

14.9.8.1 Rework Tooling

There are several systems currently on the market for reworking BGA components. Some systems direct the heat under the package while other systems direct hot gas on the top of the package. Back-side heating is a common feature of all BGA rework tools. While some systems attempt to backside heat with local hot gas behind the package to be reworked, this often results in large-scale PCB warpage during processing, especially if the PCB is large. The suggested method is to use a global heat that brings the entire PCB up to a specified temperature (100-125° C).

14.9.8.2 Rework Processing

The rework process is relatively simple. The biggest challenge of BGA rework is the requiremof a controlled process. Often SMT rework is accomplished with very coarse methods such aplacement and soldering iron reflow. Such approaches do not work for BGA. If the process urework the package is not understood and controlled (similar to initial attach), the result is likeditional defects and additional rework.

To perform BGA rework, there are four basic steps: removal, site preparation, flux or solder application, and replacement/reflow. The following subsections describe each.

14.9.8.3 Component Removal

The BGA package is removed with a hot gas tool, usually fitted with a custom head that is sithe BGA package. Proper sizing of the gas head reduces the thermal impact on adjacent paCorrect tool settings depend on the tool being used, the package being removed, and the PCtermining the settings is an exercise in profiling, similar to initial reflow. By using a profile assemwith thermocouples mounted in solder joints, tool settings can be determined which assure that all solder joints reflow properly. Monitor both the top and bottom of the PCB.

The component is removed from the PCB by a vacuum nozzle within or integral to the hot gasWhen profiling, shut the vacuum off so the component is not removed to avoid damage to the card. Control the pressure of the head down onto the component during removal. If pressureplied after the solder balls are melted, the solder is pressed between the “plates” of substratPCB, resulting in bridging that must be removed manually. Two possible solutions are:

• Establish the head height prior to reflow and control the stroke.

• Place shims under the edges of the component to prevent collapse

Consider the effects on other components. If other SMT packages are near the package being re-worked, monitor their solder joint temperature. If the temperature approaches reflow temperatures, shielding may be necessary.

Preheating the PCB assembly is good practice when reworking BGA packages. Advantages are:

• It can reduce heating time required using the rework head. In cases where one PCB assembly can be preheated while another is reworked, cycle time can be greatly reduced.

• More uniform profiles are achieved. One challenge of profiling is the temperature spread between center and edge solder joints. Preheating reduces the spread by bringing the baseline temperature closer to the reflow temperature.



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me

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cool rred to

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• PCB warpage is minimized. Warpage is caused by the higher local temperature at the site than the surrounding area. By raising the PCB assembly temperature, the mismatch is minimized and warpage is reduced.

• It reduces problems with adjacent components, as it allows shorter gas heat times or lower gas temperatures to be used, thus reducing risk of affecting neighboring solder joints.

14.9.8.4 Site Preparation

Once the component is removed, prepare the site to accept the new component. The removal process generally leaves varying amounts and shapes of solder on the mounting pads. To ensure maximum probability of success, it is suggested that all sites be made as uniform as possible prior to reattach of the new component. Solder removal is accomplished in a variety of methods — from solderto custom solder vacuum tools — the desired result is similar mounting surfaces across all mopads.

14.9.9 Removal and Replacement Process

A removal and replacement procedure for a PBGA package is as follows:

1. Plastic Ball Grid Array Package Removal from Board.

a. Preheat the board to a minimum temperature of 80° C (max. temperature is 220° C). Any part of the board over 160° C-170° C is close to the solder melting temperature of 183° C and risks damaging the joints of other components on the board, especially the bottom side parts which are closer to the heat source. It is recommended that each manufacturer conducts time and temperature experiments to determine the optimum conditions to minimize board/package warpage. Monitor both top and bottom-side board temperatures.

b. Dispense liquid, no-clean flux between the package and the board.

c. Attach a vacuum pick-up tip onto the package and apply hot air (preheat, ramp time, and temperature to be determined by manufacturer’s own experimentation). Note that socases of mother-board pad lifting problems have been reported possibly due to the machine type used and how much upward tension there is on the vacuum pick-up. Tproblem may be solved by the manufacturer determining the typical time to release using the vacuum pick-up, adding 30 seconds and then not applying the vacuum picduring removal until this amount of time had passed.

d. Lift the package from the board.

e. Turn off the hot air and carefully remove the board from the heat source and allow toto a safe, handling temperature. Inspect the board to determine no damage has occuadjacent components or to the board itself.

2. Inspection, Preparation and Replacement of New Package

a. Remove any excess solder from the PBGA solder pads using a solder wick or vacu

b. Clean the PBGA solder pads with alcohol and brush. Allow the board to dry and inspensure a clean surface.

c. Preheat the board to a minimum temperature of 80° C. Any part of the board over 160° C-170° C is really close to the solder melting temperature of 183° C and risks damaging the joints of other components on the board, especially the bottom side parts which are closer to the heat source. It is advised that each manufacturer conduct temperature experiments to determine optimum conditions to minimize board/package warpage. Monitor both top and bottom-side board temperatures.



nical

t is

ature.

erials, erials, rrounds 5mils

d vari-unt. Sub-

cal vias esigns effect A and even con-

rds that em-

con-in con-f pable sipate.

r or ther appli-e case ecom-duct to

d. Use of stenciled solder paste is optional (and as PBGA packages get larger, may be required). For applications where a solder stencil is not possible or not desired, acceptable results may be obtained by only applying flux to the pre-tinned pads. This is done by using a non-metallic spreader and applying a no-clean flux paste to the pads on the board. Be careful not to scratch the pads or the board.

e. Apply liquid flux to the solder balls of the new package. Once the liquid flux is applied, within two minutes, place the package on the board and then reflow (be sure to use the board’s alignment features fudicials and then place component using either a mechaor manual means).

f. Reflow solder balls using hot air directed at the edge and under the package body. Irecommended that temperature experiments be conducted to determine optimum conditions.

g. Remove the board from the heat source and allow to cool to a safe handling temper

h. Inspect the board and package to verify proper solder ball collapse and observe anydefects that may have been caused by the rework procedure.

14.10 Package Performance

14.10.1 Thermal Performance

In general, three factors affect the thermal performance of the BGA: package and board matpackage geometry, and use environment. Obviously, the more thermally conductive the matthe better the package dissipates heat. On a PBGA package, the molding compound that suthe chip, which provides mechanical protection as well as a surface for marking, is typically 4in thickness and is the main barrier to the elimination of the heat from the BGA package.

In general design-related factors have greater thermal effect on the PBGA than material-relateables. A large die spreads heat easier, as does a larger package size and thus a higher ball costrate design features have tremendous effect on the package’s ability to dissipate heat. Vertirunning through the substrate help to transfer heat from the die to the solder balls. Four-layer doften incorporate conductive 2-ounce copper ground planes, which have a significant, positiveon thermal performance. The Enhanced PBGA has thermal balls under the die while H-PBGthe HL-PBGA utilize a heat spreader or slug across the top of the package to dissipate heat more efficiently. PBGAs with center thermal balls dissipate considerable heat into the board. Asiderable increase in thermal effectiveness of a BGA package can be obtained by using boaare thermally efficient, increasing the airflow, or providing thermal paths from the board. Rember, with PBGAs, the board is your primary heatsink.

Environmental conditions play a critical role in the thermal performance of PBGAs. Ambient ditions, junction and case temperatures, the device’s placement and orientation on a board, junction with the volume and temperature of air flowing past the unit present a broad range opossible thermal solutions and problems for IC packaging. Typically a package cannot be caof handling a given power requirement unless the environmental conditions allow heat to dis

When environmental or geometric constraints limit a BGA’s ability to dissipate heat, a coppealuminum heatsink is often used to provide an additional method for heat transfer. As with otypes of packages, the heatsinks for BGAs vary in design and methods of attachment. Mostcations recommend a maximum case temperature for the package. Various factors effect thtemperature including ambient conditions and airflow. If the case temperature exceeds the rmended rating, a heatsink may be required. Contact an Intel applications engineer for the prodetermine if a heatsink has been developed for the particular package or application.



Refer to Chapter 4 of this handbook for more information on thermal characteristics.

14.10.2 Electrical Performance

Generally, due to the fine-line laminate base and to the lack of long pins, the electrical performance of BGAs are typically better than the pinned packages. The shortening of the electrical paths by the solder balls through the plated via-holes to the conducting plane/ground plane reduces electrical par-asitics. This can be improved further by optimizing the shortening of the overall trace length. For electrical performance details of the package, please consult the product data sheet or call your local Intel sales office.


• General review & edit of the chapter• Added new package proliferations• Added FC Style, H-PBGA information


have y and ever,

ll.

ew nclude ation, ols. olve.

the

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ign

and

rface in

, some lt of the die h a ball

ecause many se refer

The Chip Scale Package (CSP) 15

15.1 Introduction

Since the introduction of Chip Scale Packages (CSP’s) only a few short years ago, they have become one of the biggest packaging trends in recent history. There are currently over 50 different types of CSP’s available throughout the industry and the numbers are increasing almost daily.

Intel Flash memory products began using CSP's in the µBGA* package a few years ago andexpanded into multiple types of CSP's in order to meet the needs of new product functionalitapplications. Currently, the majority of Intel's CSP's are used for flash memory products. Howother types of Intel products are beginning to take advantage of the benefits of CSP's as we

CSP's are evolving so rapidly, that by the time you read this chapter, there will probably be npackage information and design considerations to take into account. Intel has attempted to ias much as possible in this chapter, reviewing many different areas such as package informapplication considerations, printed circuit board (PCB) design and manufacturing tips and toHowever, since CSP's are continually evolving, the contents of this chapter will continue to evTherefore, until new versions of this package guide are printed, new CSP information and manufacturing considerations for Intel Flash Memory products will continue to be updated inFlash Memory CSP User's Guide on the WWW at:

http://developer.intel.com/design/flash/packtech/index.htm.

There are many reasons why CSPs have been so well accepted within the industry. One of biggest advantages of CSPs is the size reduction of the package (see figure 15.1) vs. more traditional peripherally leaded packages. This is mainly due to the Ball Grid Array (BGA) desof the package. By designing all interconnects under the package in the BGA style, you can increase the number of interconnects while saving PCB routing space. Other manufacturingadvantages of CSPs include the self alignment characteristics during PCB assembly reflow lack of bent leads which cause coplainarity issues. Both of these CSP features increase PCBassembly yields and lower manufacturing costs.

One of the barriers for new packages to be accepted in the industry is the lack of existing SuMount Technology (SMT) infrastructure such as assembly and manufacturing processes andequipment. This is not the case for CSPs which take advantage of existing infrastructure andmost cases require no capital equipment investment to implement CSPs .

In the past, CSP's have been defined as a package that is 1.2X the size of the die. Howevertypes of CSPs maintain their package size as the internal silicon die reduces in size as a resufabrication lithography process gets smaller (die shrink). This effect changes the package tosize ratio. As CSP's have evolved, the definition has changed to "near die size packages witpitch of 1mm or less".

As mentioned earlier, Intel has introduced several different types of CSP packages. This is beach application has different requirements. Since almost every application varies, there areconsiderations to take into account when selecting the best package for the application. Pleato the "Package Usage" section of this chapter to review this in more detail.


The Chip Scale Package (CSP)

ions are for the

iscrete uples PCB

Figure 15-1. CSP vs. SOP Size Comparisons

15.2 Package Dimensions & Attributes

Note: Please refer to the web-based mechanical Spec for up to date package dimensions at:

http://www.intel.com/design/flash/packtech/index.htm

This section reviews CSP specific information such as various CSP construction, material sets, attributes, and dimensional examples. It also explains the use and construction of various mechanical samples referred to as Silicon Daisy Chain (SDC) samples to be used for mechanical /process equipment set-up and evaluation.

15.2.1 The µBGA Package

The µBGA package is a true chip size package. Because of this, the actual package dimensdependent on the size of the silicon die. This section will show general package dimensions µBGA package. Please refer to the mechanical specification document on Intel's website, orcontact your Intel representative for the latest, complete package dimensions, pinouts, and schematics.

The µBGA package (Figure 15.2) is a .75mm and .5mm ball pitch package and takes full advantage of any reduction of silicon die size. This makes the µBGA package the smallest dIntel flash memory package. Its unique construction utilizes a layer of elastomer which decothe stresses caused by the coefficient of thermal expansion (CTE) of the silicon die and the material during temperature variations.

A7583-01


evels

Figure 15-2. The µBGA* Package

Since the size of the package equals the size of the die, as the die gets smaller due to fabrication lithography process reductions (die shrinks), so does the package. At a certain point, the associated ball pitch will get smaller as well, in order to accommodate the smaller size of the die. This eventually leads to ball pitches as small as .5mm and below. Currently the majority of µbga packages are in .75mm pitch.

15.2.2 µBGA* Package Drawing and Dimensions

Figure 15-3. Example µBGA* Package Drawing and Dimensions

Note: The µBGA package is die-size dependent and may vary. Actual products vary with different lof matrix ball depopulation. Refer to the µBGA* Package Mechanical and Shipping Media Specifications for specific product/package dimensions/drawings and pinouts at:


A7584-01

Silicon Die

Elastomer

.75mm Pitch

Elastomer construction disconnectsCTE of die & PCB to provideexcellent reliability.

1.0mm

A4805-01

ABall A1

Indicator

Top View - Silicon Backside(Complete Ink Mark Not Shown)

Bottom View - Bump Side Up

FE

DC

B

A

F

SeatingPlane

E

DC

B

81 2 3 4

D

E

S1

S2

e

b

AA2

A1

Y

5 6 78 1234567

Ball A1Corner

Side View



Table 15-1. Generic µBGA* Package Dimensions


Min Nom Max Notes Min Nom Max

Package Height A 0.850 1.000 0.0335 0.0394

Ball Height A1 0.150 0.0059

Package Body Thickness A2 0.600 0.700 0.800 0.0236 0.0276 0.0315

Ball (Lead) Width (all .75mm pitch) b 0.300 0.350 0.400 0.0118 0.0138 0.0157

Ball (Lead) Width (all .50mm pitch) b 0.259 0.309 0.359 0.0102 0.0122 0.0141

Seating Plane Coplnarity Y 0.100 0.0039

Package Body Width D

See µBGA Package Attribute Table

Package Body Length E

Pitch [e]

ball (Lead) Count N

Corner to Ball A1 Distance Along D S1

Corner to Ball A1 Distance Along E S2

Table 15-2. µBGA Package Attributes

µBGA Product Name

Ball Pitch

Square/ Rect.

Package Weight

(mg)

Matrix (active)

Actual Ball

Count

D Nom

E Nom S1 S2 SDC’s2

GT28F008/800B3 .75 R 60 6x8 46 7.910 6.500 1.330 1.375

GT28F016/160B3GT28F160C3 .75 R 51 6x8 46 7.286 6.964 1.018 1.607 Y

GT28F320C3 .75 R 83 6x8 47 7.286 10.850 1.018 3.550

GT28F160F3 .75 R 102 6x10 53 8.000 10.240 .625 3.245

G28F640J5 .75 R 59 9x8 52 7.670 16.370 1.214 5.935 Y

BG28F160C18 .5 R TBD 5x11 46 6.794 7.530 .897 2.765 Y

GT28F320D18 .75 R TBD 7x8 58 7.520 13.420

Shipping Media All µBGA products are available in Tape & Reeel or Trays

Desiccant Pack 1 All µBGA products are IPC Level 2

1. Desiccant Pack levels relate to IPC Moisture Sensitivity Levels2. SDC’s represent the mechanical samples available in the various package size/type equivalents

NOTE: All Dimensions in mm


uch as ad of stacks ough &.

the two

15.2.3 The Intel® Stacked CSP

Another type of CSP gaining momentum in the industry is the "stacked" CSP (IntelÆ StackedCSP). These packages are taking advantage of multiple application requirements, sSRAM and Flash, and combining both die into one package (see figure 3.3). However, insteplacing the individual die side by side (such as multi-chip modules), the IntelÆ StackedCSP the two die on top of each other to get the maximum space savings advantage possible. Alththe package may have a larger ball pitch as compared to the µBGA packages (.8mm vs. .755mm), the overall PCB area of the IntelÆ StackedCSP is smaller than the combined area of separate components.

Figure 15-4. Intel® Stacked CSP

A7585-01

.8mm Pitch

1.4mm

Silicon Die

Silicon Die



r

15.2.4 Intel® Stacked CSP Package Drawings & Dimensions

Figure 15-5. Example Intel® StackedCSP Drawing and Dimensions

Note: Refer to the IntelÆ StackedCSP Package Mechanical and Shipping Media Specifications fospecific product/package dimensions/drawings and pinouts at:


Table 15-3. Generic Intel® StackedCSP Dimensions


Min Nom Max Min Nom Max

Package Height A 1.20 1.30 1.40 0.047 0.051 0.055

Ball Standoff A1 0.30 0.35 0.40 0.012 0.014 0.016


Seating Plane Coplanarity Y 0.1 0.004

Pitch e 0.80 0.031

Lead Count N 72 72

Package Body Width D

See Intel® Stacked CSP Attributes TablePackage Body Length E

Corner to First Bump Distance Along E S1

Corner to First Bump Distance Along D S2

A7587-01

e

S1

A1A2A

A1IndexMark

A1

b

1

AB

C

D

EF

G

H

2 3 4 5 6 7 8 9 10 11 12

S2

E

D

Top View - Ball Down Bottom View - Ball Up

Y


nt

ct to eed for es the

ory edded ality.

their ypes of

15.2.5 The Easy BGA Package

The Easy BGA package (fig 3.5) was designed to be the flash memory package of choice for embedded applications. While offering a larger ball pitch as compared to other CSPs, the Easy BGA package maintains the size benefits, measuring about ¾ the size of it's TSOP equivalepackage.

Another advantage of the Easy BGA package is its constant package size/footprint in respememory density upgrades and die shrinks. A key element of embedded applications is the nlong product life cycles (5-7 years) that require the same package size/footprint. Not only dopackage size/footprint need to stay constant over time; it does not change as a result of memdensity upgrades or die process shrinks. This attribute is very beneficial because many embapplications increase in memory density over time in order to incorporate additional function

Figure 15-6. The Easy BGA Package

Many embedded applications require a high level of reliability due to the usage conditions ofenvironments. The Easy BGA package has been constructed specifically to address these trequirements. The Easy BGA package construction incorporates many key features that

Table 15-4. Intel® Stacked CSP Package Attributes

Intel® Stacked CSP Product Name

Square/ Rect.

Package Weight

(mg)

Matrix (active) D Nom E Nom S1 S2 SDC’s 2

RD28F1602C3 R 1803 8x8 10.00 8.00 1.20 .60 Y

RD28F1604C3 R TBD 8x8 12.00 8.00 1.20 1.60

RD28F3202C3 R 2316 8x8 12.00 8.00 1.20 1.60

RD28F3204C3 R 2278 8x8 12.00 8.00 1.20 1.60

Shipping media All µBGA products are available in Tape & Reeel or Trays

Desiccant Pack 1 All µBGA products are IPC Level 2

1. Desiccant Pack levels relate to IPC Moisture Sensitivity Levels2. SDC’s represent the mechanical samples available in the various package size/type equivalents

NOTE: All Dimensions in mm

A7586-01

Easy / Inexpensive to use1.0mm BGA Pitch

Large EutecticSolder Balls forHigh Reliability

Au Wire

Proven RigidSubstrateInterposer Technology

Encapsulation (Mold)

Silicon Die



differentiate it from other CSP packages. Besides the wider ball pitch as previously discussed, the Easy BGA uses large diameter eutectic solder balls and a thick BT laminate rigid substrate. The combination of large solder balls and thick BT laminate substrate provide very good reliability by buffering and maximizing the separation between the silicon die and PCB surface to minimize the affects of CTE induced stresses.

15.2.6 Easy BGA Package Drawing and Dimensions

Figure 15-7. Easy BGA Package Drawing and Dimensions

A7588-01

Pin #1Indicator

Pin #1Cormer

1A

B

C

D

EF

G

H

2 3 4 5 6 7 8 8A

B

C

D

EF

G

H

7 6 5 4 3 2 1

D

E

Top View - Plastic Backside[Complete Ink Mark Not Shown]

Bottom View - Ball Up

S2

e

b

S1

A1

A2 ASeatingPlane

Y


Table 15-5. Easy BGA Package Dimensions (all products)



Package Height A 1.200 0.0472

Ball Height A1 0.250 0.0098


Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209

Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976

Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157

Pitch [e] 1.000 0.0394

Ball (Lead) Count N 64 64


Corner to First Ball Alnog D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630

Corner to First Ball Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220

Table 15-6. Easy BGA Package Attributes Table

Easy BGA Product Name Square/Rect. package Weight Matrix SDC’s2

RC28F800F3 R 213.8 8x8

RC28F160F3 R 230.6 8x8 Y

RC28F800C3 R 198.9 8x8

RC28F160C3 R 206.5 8x8

RC28F320C3 R 214.5 8x8

RC28F320J3 R 207.9 8x8

RC28F640J3 R 220.9 8x8

RC28F128J3 R 241.8 8x8

Shipping Media All products available in Tape & Reel or Trays

Desiccant Pack 1 Refer to moisture barrier bag label for specific IPC level

1. Desiccant Pack levels relate to IPC Moisture Sensitivity Levels. Refer to the handling section of this guide for the complete moisture level table.

2. SDC’s represent the mechanical samples available in the various package size/type equivalentsNOTE: All Dimensions in mm



® he

15.2.7 Molded Matrix Array Package (MMAP) Package Drawings & Dimensions

Note: Unlike other chip scale packages included in this chapter, the MMAP packages are not IntelFlash Memory Products. Any additional information for MMAP packages will be released in tfuture.

Figure 15-8. Molded Matrix Array Package (MMAP) 144/225/256 ball count

A7589-01

Pin #1 Corner Pin #1Corner

D

E

b

12 1110 9 8 7 6 5 4 3 2 1

ABCDEFGHJKLM

φ

Top View

Side View

Bottom View

Note: All dimensions are in Millimeters

S2

S1 e

A2A1A

C

Seating Plane

Table 15-7. 144/225 Ball MMAP BGA Package Dimensions



Package Height A 1.17 1.40 0.0461 0.0551

Ball Height A1 0.30 0.36 0.0118 0.0142


Ball (Lead) Width b 0.35 0.40 0.45 0.0138 0.0157 0.0177

Package Body Width D 12.90 13.00 13.10 1 0.5079 0.5118 0.5157

Package Body Length E 12.90 13.00 13.10 1 0.5079 0.5118 0.5157

Pitch [e] 1.00 0.0394


Ball (Lead) Count N 144/225 144/225


Corner to First Ball Alnog D S1 0.90 1.00 1.10 1 0.0354 0.0394 0.0433

Corner to First Ball Along E S2 0.90 1.00 1.10 1 0.0354 0.0394 0.0433

NOTES:1. The tolerances above indicate projected production accuracy. This product is in the design phase. The

minimal, nominal, and maximum package body width and length are subject to change dependent on final die size. Actual die size could shift these values by ± 0.008 inches for the 28F320J5 product.

2. Some ball locations may not be populated on some products. See the specific product signal list for complete details.

Table 15-8. 256 Ball MMAP Package Dimensions



Package Height A 1.35 1.45 1.55 0.0531 0.0571 0.0610

Ball Height A1 0.35 0.40 0.45 0.0138 0.0157 0.0177


Ball (Lead) Width b 0.40 0.50 0.60 0.0157 0.0197 0.0236

Package Body Width D 16.80 17.00 17.20 1 0.6614 0.6693 0.6772

Package Body Length E 16.80 17.00 17.20 1 0.6614 0.6693 0.6772

Pitch [e] 0.90 1.00 1.10 0.0354 0.0394 0.0433

Ball (Lead) Count N 256 2 256


Corner to First Ball Alnog D S1 0.90 1.00 1.10 1 0.0354 0.0394 0.0433

Corner to First Ball Along E S2 0.90 1.00 1.10 1 0.0354 0.0394 0.0433

NOTES:1. The tolerances above indicate projected production accuracy. This product is in the design phase. The

minimal, nominal, and maximum package body width and length are subject to change dependent on final die size. Actual die size could shift these values by ± 0.008 inches for the 28F320J5 product.

2. Some ball locations may not be populated on some products. See the specific product signal list for complete details.

Table 15-7. 144/225 Ball MMAP BGA Package Dimensions



Æ t ons M and signed ital

nts.

s a y. In allows l uring

15.3 Package Materials

15.3.1 CSP Construction Material Sets

Table 2 provides a listing of the package construction material sets for CSP packages.

15.4 Package Usage

Intel provides a full range of CSPs for your specific application. Each application has it’s own set of packaging requirements that may vary from the smallest possible size, reliability, long-term footprint/size compatibility, unit cost, total cost, or ease of use. The CSP of choice will vary depending on which packaging requirements are most important to your application.

If your application requires the smallest possible package, the µBGA* package and the IntelStacked-CSP are the best package choice for your design. For the smallest size and highesreliability, the µBGA package remains the best single-die CSP for your design. For applicatithat use flash and SRAM, the Intel Æ Stacked-CSP adds value by integrating Flash and SRAstacking both individual die into one package. This unique packaging approach provides theultimate in size reduction by eliminating a component from the board. These CSP's were deto meet the demands of handheld applications such as cellular phones, pagers, personal digassistants (PDA) and Global Positioning Systems (GPS) units.

Other embedded applications such as networking, automotive, set-top boxes, tele/data communications, and measurement equipment products have different packaging requiremeWhile size is still an important factor in these applications, lowest total-cost (such as PCB manufacturing) and long term size/footprint compatibility are highly valued. The Easy BGA package is the package of choice for these types of applications. The Easy BGA package harelaxed 1.0mm ball pitch that allows for easy PCB routing using conventional PCB technologaddition, the large .45mm ball diameter size and rigid BT laminate substrate package design for excellent solder joint reliability over a wide temperature range. While offering a larger balpitch as compared to other CSPs, the Easy BGA package maintains the size benefits, measabout ¾ the size of it's TSOP equivalent package.

Table 15-9. CSP Material Sets

CSP Type µBGA Easy BGA Intel® Stacked-CSP

Sq/rect R R R

Ball Material 63/37 SnPb

Encapsulation Material Elastomer Epoxy Mold Compound

Die Attach Material Elastomer Epoxy

Substrate Material Polyimide Tape BT Laminate

Substrate Trace Material (Cu) Copper

Substrate Finish Material (Au) Gold

Bond Material (Cu) Copper (Au) Gold Wire

Bond Method Thermosonic Lead Bond Wire Bond


ays ions nd

ertain

are

. For milar

15.4.1 Silicon Daisy Chain (SDC) Evaluation Units

Intel also offers evaluation units that have been internally shorted together (to the silicon) in a "daisy chain" pattern. This ensures that the package’s I/O path is complete through the ball, substrate, lead beam or bond wire, silicon, and back down through a separate I/O path.These units can be useful for set-up/evaluation of manufacturing equipment.

15.5 Handling: Shipping Media

Intel® Stacked-CSP's are shipped in either tape and reel or in mid-temperature thin matrix trthat comply to JEDEC standards. All JEDEC standard trays have the same 'x' and 'y' dimensand are easily stacked for storage and manufacturing. For tape and reel or tray dimensions aquantities, refer to Chapter 10, "Transport Media and Packing" of this manual.

15.6 Preconditioning And Moisture Sensitivity

With most surface mount components, if the units are allowed to absorb moisture beyond a cpoint, package damage may occur during the reflow process. Chapter 8, "Moisture Sensitivity/Desiccant Packaging/Handling of PSMCs" provides an in-depth view of package preconditioning and moisture sensitivity requirements. Specific moisture classification levelsdefined on the box label for each product

15.7 Designing Boards for CSPs

In most cases, CSPs use the same PCB design and assembly processes as BGA packagesgeneral background information on these subjects, refer to chapter 14 which covers these siprocesses for PBGA packages. Any CSP specific variations are listed below.

For additional detailed information about Intel® Flash memory CSPs, refer to the Intel FlashMemory CSP Users Guide located on the web at:

http://developer.intel.com/design/flash/packtech/index.htm

You will find extensive information on IntelÆFlash memory CSPs covering a wide variety in topics such as:

• CSP assembly flow diagrams

• CSP package attributes

• CSP Materials, and packaging dimensions

• CSP shipping media and handling

• Printed Circuit Board (PCB) design considerations (trace/space, via, etc.)

• CSP to PCB assembly and manufacturing process recommendations

• CSP manufacturing support tools

• Intel’s quality criteria

• CSP solutions for diverse applications



• CSP on-board programming

• CSP rework

• PCB surface tension and self centering of CSPs

• PCB solder stencils and process refinements

• PCB surface finishes

Table 15-10. PCB Design Guidelines for .75mm mbga, Easy BGA, and Intel® Stacked-CSP

Feature .75mm µBGA CSP .8mm Stacked CSP 1.0mm Easy BGA

Land Pad Size .30 (0.12) .30 (0.12) .30 (0.12)

Solder Mask Opening .431 (.018) .431 (.018) .431 (.018)

Metal to Mask Clearance (Min) .050 (.002) .050 (.002) .050 (.002)

Max Trace Width .127 (.005) .127 (.005) .233 (.009)

Typical Spaces .160 (.00625) .187 (.0073) .233 (.009)

Max Via Capture Pad .51 (.020) .51 (.020) .711 (.028)

Max Via Drill Size .25 (.010) .25 (.010) .457 (.018)

NOTE: All Dimensions in mm (inches)

Table 15-11. PCB Design Guidelines for .5mm pitch µBGA

Feature .5mm µBGA* CSP

Land Pad Size .279 (.011)

Solder Mask Opening .356 (.014)

Typical Trace Width .1016 (.004)

Reduce Trace Width Between Land Pads .0737 (.0029)

Typical Micro Via (Via-in-Pad) Size .1016 (.004)


Table 15-12. Solder Stencil Design for µBGA, Easy BGA, and Intel ® Stacked-CSP

Feature .5mm mBGA* CSP .75mm mBGA* CSP .8mm Stacked CSP 1.0mm Easy BGA

Top of Stencil Aperature .279 (.011) .33 (.013) .33 (.013) .33 (.013)

Bottom of Stencil Apperature .30 (.012) .356 (.014) .356 (.014) .356 (.014)

Stencil Thickness .127 (.005) .127 (.005) .127 (.005) .127 (.005)



15.8 Package to Board Assembly

In most cases, CSPs use the same PCB design and assembly processes as PBGA packages. For general background information on these subjects, refer to chapter 14 which covers these similar processes for PBGA packages.

For additional detailed information about Intel ® Flash memory CSPs, refer to the Intel FlashMemory CSP Users Guide located on the web at:

http://developer.intel.com/design/flash/packtech/index.htm


• Complete revision of chapter

• Added MMAP


Intel site.

with an rovides n a here

Cartridge Packaging 16

16.1 Introduction

Intel has introduced a variety of innovative package designs over the years: surface mount, small out-line, very thin package, multilayer molded plastic quad flatpacks (PQFP), and the Tape Carrier Package (TCP) format. Recent configurations for optimum microprocessor performance are the Single Edge Contact (S.E.C.) cartridge and the Mobile Mini-Cartridge.

The S.E.C. cartridge typically combines an area array packaged processor core, L2 cache, other components, and a thermal solution attach point. The entry of the S.E.C. cartridge technology continues the commitment to provide packaging solutions which meet Intel’s rigorous criteria for quality and performance.

The mobile mini-cartridge is a packaging technology aimed at the notebook PC market, where minimum form factor is required. It is designed to protect the electronic components of the product and enables a controlled thermal interface between the processor and the thermal solution in the notebook system (see Figure 1). The mini-cartridge provides a socketable microprocessor solution, i.e. it enables the OEM to mount the processor via a motherboard-mounted connector, rather than by soldering it, and mechanically securing it with screws in a manner similar to other notebook components such as hard disk drives.

Several times throughout this chapter you will be referred to Intel’s website. The URL for thewebsite is http://www.intel.com. Intel’s developers website can also be accessed through this

16.2 Single Edge Contact Cartridge Technology

The S.E.C. cartridge has the following standard features: a plastic enclosure and a substrateedge finger connection. The plastic enclosure protects the surface mount components and pfeatures for mechanical stability when the processor is mounted in a retention mechanism omotherboard. The edge finger connection maintains socketability for system configuration. Tare two edge finger connectors: SC 242 for the Pentium II® and SC 330 for the Pentium II® XeonTM Processor.

There are several variations to the S.E.C. Cartridge form factor. They are the Single Edge Contact Cartridge (S.E.C.C.) which has a cover and a thermal plate, the Single Edge Contact Cartridge 2 (S.E.C.C.2) which has a cover, but no thermal plate, and the Single Edge Processor Package (S.E.P.P.) which has no cover or thermal plate. In implementations with no thermal plate, the customer can attach a heatsink directly to the MP Package or die.

16.2.1 Terminology

The following terms are used in this document and are explained here for clarification.

S.E.C. cartridge — The processor packaging technology is called a "Single Edge Contact cartridge."

S.E.P.P. — The processor packaging technology known as “Single Edge Processor Package.”


Cartridge Packaging

.

.C.C

Processor substrate — The structure on which the components are mounted inside the S.E.Ccartridge (with or without components attached).

Processor core — The processor's execution engine.

Thermal plate — The surface used to connect a heatsink or other thermal solutions to the S.Eprocessor.

Cover — The processor casing on the opposite side of the processor core.

Figure 16-1. S.E.C. Cartridge 2 — Isometric Views

A6153-01

Front View

Back View


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Figure 16-2. S.E.P.P — Isometric Views

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Front View

Back View


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Figure 16-3. S.E.C. Cartridge (330 contacts)— Thermal Plate and Cover Side Views

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Front View of Package

Back View of Package


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30

C

Figure 16-4. Mobile Mini-Cartridge Top and Bottom Cover Views

Additional terms referred to in this and other related documentation are the Mechanical Support Pieces (MSPs), which are used on the system to connect the processor to the system baseboard, and are responsible for retention of the processor during system shock and vibration. The MSPs represent one solution for retention of the processor in the SC 242 connector. This chapter focuses on the use of these pieces:

SC 242 & SC 330 Contact Connector — The connectors that the S.E.C. cartridges uses.

Retention Mechanism — A mechanical piece which holds the cartridge in the SC 242 or SC 3connector.

Retention Mechanism Attach Mount — An enabled mechanical piece which secures the retention mechanism to the baseboard.

Dual Retention Mechanism — A mechanical piece which holds two S.E.C. cartridges in two S242 contact connectors for a 2-way SMP processor system.

Note: Other mechanical solutions may be available.

A7487-01

Top View of Cartridge

Bottom View of Cartridge


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16.2.2 S.E.C. Cartridge Assembly and Construction

16.2.2.1 S.E.C. Cartridge Assembly

Figure 16-5, and Figure 16-6 show exploded views of the S.E.C. cartridge. The S.E.C. cartridge core, substrate, thermal plate (SC330), thermal plate attach clips (SC330), and protective cover are shown. For complete mechanical dimension information for the S.E.C. cartridge, see the datasheet.

Figure 16-5. Exploded View of S.E.C. Cartridge 2

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Processor Substratewith Core and SecondLevel Cache

Cover


Cartridge Packaging

Figure 16-6. Exploded View of SC330

Figure 16-7 and Figure 16-8 shows an exploded view of the mobile mini-cartridge assembly. The PCB substrate is populated on both sides with surface-mount passive and active components consisting of the processor core and tag RAM memory on the primary side, and two L2 cache memory devices and the connector on the secondary side. After the substrate is populated, it is placed into the top cover and then the bottom cover is snapped into place and retained by nine snap lances around its perimeter.

The connector plug is designed to mate with either of the two available receptacle versions. The receptacle versions enable connector stack heights of approximately 3.4 mm and 4.2 mm. Final connector stack height is dependent on the characteristics of the surface-mount process used to place the receptacle onto the motherboard.

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Pin Fasteners

Thermal PlateRetention Clips

Primary Side Substrate

Primary Side Substrate

Plastic Enclosure

CPU & CSRAM in PLGA

Aluminum Thermal Plate


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Figure 16-7. Mobile Mini-Cartridge Exploded Views, 1 of 2

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Memory device

InternalPCB Substrate

Processor Core

Mini-cartridgeTop Cover

Upper View


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plane ted to a edge e r the ector.

Figure 16-8. Mobile Mini-Cartridge Exploded Views, 2of 2

16.2.2.2 S.E.C. Cartridge Substrate

The S.E.C. cartridge typically contains an area array packaged processor core and L2 cache components (TagRAM and BSRAMs for the processor) mounted onto a substrate. The substrate has contact fingers on one edge that provide the electro-mechanical connection to the connector (and thus to the system baseboard). The substrate is fabricated of standard FR-4 based organic laminate material and has a minimum flammability rating of 94V–0. Copper trace and power parametrics, along with other key performance and manufacturing designs, have been selecprovide optimum electrical performance. The edge finger contacts are plated with gold over nickel barrier layer for a reliable substrate edge finger to the connector electrical contact. Thefingers are equally distributed between the primary and secondary sides of the substrate. Thcontact areas of these edge fingers are maximized by using a two-sided staggered design foplacement of the fingers. A key slot is provided in the edge finger array, off center of the cardlength, to prevent improper placement of the S.E.C. cartridge substrate into the contact conn

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Mini-cartridgeBottom Cover

Product Label

Memory Devices

TemperatureSensor

BGA-TechnologyConnector

Lower View


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16.2.2.3 Thermal Plate

In designs incorporating thermal plates, the thermal plate is made of aluminum, with a black anodized coating. To improve thermal conduction, the thermal plate is attached directly to the heat slug on the processor core using a thermal interface material. Stainless steel spring clips attach to pins, which extend from the thermal plate through the substrate, securing the thermal plate to the logic core package body. Intel has performed extensive testing to ensure that the thermal interface material is non-volatile, and that it will continue to provide an effective thermal path over the lifetime of the S.E.C. cartridge processor.

16.2.2.4 Mobile Mini-Cartridge Stackup Dimensions

Figure 16-9. Mobile Mini-Cartridge Stackup Dimensions

Table 16-1. Mini-Cartridge Stackup Dimension Values (in millimeters)

16.2.3 S.E.C. Cartridge Assembly and Test

The processor core, TagRAM, BSRAMs and other components are assembled onto the substrate using traditional SMT processes and methodologies. The S.E.C. cartridge assembly and test flow is shown in Figure 16-10.

Dimension Minimum Nominal Maximum

BLT 0.01 0.12 0.23

H 4.40 4.55 4.70

M 0.91 1.03 1.15

P 2.81 REF

PCB 0.90 1.00 1.10

R* 3.09 3.21 3.33

S* 4.34 4.44 4.54

BC* 1.60 1.89 2.18

SH* 7.74 7.96 8.17

NOTE: * For 4.0mm connector

A7406-01

BC

P

BLT

PCB

MSR

H

SH


Cartridge Packaging

Figure 16-10. S.E.C. Cartridge Assembly/Test Process Flow

Standard SMT processes are used to place components on the mini-cartridge substrate. The cover is a two piece snap together assembly. A simplified process flow is shown in Figure 16-11.

Figure 16-11. Mini-Cartridge Simplified SMT Process Flow

A5802-01

ComponentsTested bySupplier

ComponentsPrep

PastePrint

VisionSystem

Inspection

ChipShoot

Pickand

PlaceReflow

DepanelVisual

Inspection ReflowPickand

Place

ChipShoot

VisionSystem

Inspection

PastePrint

In-CircuitTest

ThermalPlate

Attach

FunctionalTest

CoverAttach

MarkCover

FinalVisual

Inspection

OutgoingQualityAudit

Pack

Secondary Side SMT

Primary Side SMT

WhereRequired

WhereRequired

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ComponentsTest by Supplier

CoverAttach

Primary SideSMT

Depanel

ComponentsPrep

In-CircuitTest

SecondarySide SMT

VisualInspection

Pack and Ship OutgoingQuality Audit

CoverAttach

CoverMark

FunctionalTest

Final VisualInspection


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erent

) with ed

lam-g the tions) ucted rostatic

16.3 Package Handling And Shipping Media

The S.E.C. cartridge was designed to be a robust packaging solution for processors. Sealed, desiccant, ESD protective bags are not required, and thus not used during shipping of the processors from Intel. The S.E.C. cartridge processor, however, should be unpacked at ESD workstations. The package is NOT meant to survive mishandling such as dropping the processors, breaking the latch arms, inserting long metal objects into the thermal plate holes and slots, allowing foreign material to contact substrate edge fingers, and attempting to disassemble the cartridge. Surface mount technology (SMT) moisture levels are not applicable for the cartridge processor.

This section will provide additional handling guidelines and information on the shipping media used for the processors. The “datasheet cross reference” contains specific operational and storagespecifications for the processor.

16.3.1 Shipping Media Description And Specifications

The S.E.C. Cartridge Processor is packaged in a shipping box using materials which are difffrom PGA processors. See Figure 16-12 and Figure 16-13 illustrations of the processor shipping media. As shown, a plastic insert is first placed into the shipping box. The S.E.C. cartridge processors are loaded into the thermo-formed ESD plastic (industry name is XERSTAT 1000the substrate edge fingers down. The ESD plastic insert is an electrically dissipative, RecyclHigh Density Polyethylene (RHDPE) molded plastic which meets JEDEC registered outline drawings. As shown in Figure 16-12, the insert closes over the S.E.C cartridge processor in a cshell fashion. There are multiple cartridges per insert, oriented edge finger side down, allowinlaser mark on the top edge of the S.E.C. cartridge (S.E.C.C.2 and S.E.C.C SC 330 configurato be visible when the top of the shipping box and insert are opened. The outer box is constrfrom corrugated cardboard and has a conductive carbon coating inside to dissipate any electcharge.

The Static-Dissipative insert (see Figure 16-12) is recyclable. The inserts may be shipped to:

Richmond Technology1897 E. Colton AvenueRedland, CA. 92373(909)794-2111


Cartridge Packaging

Figure 16-12. S.E.C. Cartridge Shipping Box — Exploded View

Figure 16-13. S.E.C Cartridge Shipping Box — Assembled View

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S.E.C. Cartridges

Static-DissipativeInsert

Shipping Box

A5804-01


Cartridge Packaging

Figure 16-14. Mobile Mini-Cartridge Packing Procedure

Warning: Only handle the mini cartridge by holding at the edge of the unit and with clean personal protective equipment (PPE) eg: vinyl ESD dissipative gloves. Do not touch the connector, die and flat metal surface area.

Figure 16-15. Mini-Cartridge Handling Areas

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Packing Label goeson this end of the box.

Connector/label side of unit goesdownward and to the left, facingtoward the label end of the box.

Load Unit ConnectorEnd Down

Label

Clamshell

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Handle HERE Handle HERE

Handle HERE


Cartridge Packaging

16.4 S.E.C. Cartridge Mechanical Support Pieces (MSP)

It is imperative to ensure good electrical contact between the S.E.C. cartridge substrate and the connector. To keep the connector simple, the connector does NOT have features to retain the S.E.C. cartridge during significant, but realistic, environmental conditions. These conditions are encountered during normal transport of baseboards (with processor installed) and systems in an OEM production line and eventual shipment to an end user.

Intel has enabled a Mechanical Solution (MS) to support the S.E.C. cartridge and to ensure retention of the processor into the SC 242 and SC 330 contact connectors. This solution is referred to as the Mechanical Support Pieces (MSPs). These pieces represent only one solution to ensure that the processor stays in the connector. Other methods and mechanical solutions will NOT be covered by this document. This document only provides details on the use and operation of the MSPs. While each OEM must perform actual validation for mechanical performance ensuring that the processor stays in the connector, Intel has shown that, through shock and vibration test validation, these pieces provide adequate mechanical support of the processor when used correctly.

The mechanical support pieces consist of the connector, retention mechanism, retention mechanism attach mount (RMAM) and heatsink support (HSS). The connector provides the electrical path between the processor and the other logic components on the baseboard. The retention mechanism holds the processor into the connector during mechanical shock and vibration. The RMAM attaches the retention mechanism to the baseboard. Figure 16-17 provides illustrations of all MSPs and how they interact with the processor.

Figure 16-16. S.E.C Cartridge with All Mechanical Support Pieces, Full Assembly

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2.038 ± 0.010

1.00 ± 0.01

1.095 ± 0.015


Cartridge Packaging

ntel

Figure 16-17. Exploded View of S.E.C. Cartridge with All Mechanical Support Pieces

Intel does not supply the MSPs or equipment detailed in this chapter. Information for suppliers is provided in this document as applicable. An updated supplier’s guide can be located at the Iwebsite by searching for the terms “suppliers of support components.”

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S.E.C. Cartridge withExample Heatsink Attached

Retention Mechanism

Slot 1 Connector

Retention MechanismAttach Mount


Cartridge Packaging

16.4.1 SC 242 Contact Connector

The SC 242 contact connector is a 242 contact, 1.0 mm pitch edge connector intended for high volume desktop systems based upon the processor using S.E.C. cartridge technology. The SC 242 contact connector mounts on the baseboard and allows insertion and removal of the processor from the baseboard (see Figure 16-18).

Figure 16-18. SC 242 Contact Connector

16.4.2 SC 330 Contact Connector

The SC 330 contact connector is a 330 contact, 1.0 mm pitch edge connector intended for high volume server and workstation systems based upon the processor using S.E.C. cartridge technology. The SC 330 contact connector mounts on the baseboard and allows insertion and removal of the processor from the baseboard (see Figure 16-19).

16.4.2.1 Other Connector Form Factors: Restrictions and Requirements

The SC 242 and 330 contact connectors are only two of the possible connector solutions for the S.E.C. cartridge processor. Any other solution for providing the electro-mechanical connection between the processor and the baseboard must meet the processor specifications as defined in the datasheet.

A5808-01001008

B121

48 Contact Pairs

A121

73 Contact Pairs

B1

A1 Top View

Side View


Cartridge Packaging

Figure 16-19. SC 330 Contact Connector

16.4.3 Retention Mechanism

16.4.3.1 Retention Mechanism Mechanical Description

The retention mechanism holds the S.E.C. cartridge in the connector during mechanical shock and vibration. The retention mechanism is not symmetrical. If it is placed around the connector incorrectly, the processor will not engage into the retention mechanism. The retention mechanism, however, is designed to engage with a matching polarization key on the connector for correct assembly onto the baseboard. The retention mechanism is also designed to aid in processor alignment to the connector during insertion of the processor. The retention mechanism contains draft angles, lead-ins and chamfers to allow smooth travel of the processor down the posts and into the connector (see Figure 16-20).

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Top View

Side View

Pin B1

Pin B2

Pin A2

Pin B165

Pin A166

Pin A1


Cartridge Packaging

Figure 16-20. Retention Mechanism, Assembled, Isometric View

The mechanical force of the connector contacts provide some friction grabbing of the processor. The retention mechanism is designed to allow a small amount of back-out of the connector before stopping the travel of the processor. The vertical travel associated with this back-out is comprehended in specifications for the processor (particularly the substrate), connector and the retention mechanism.

16.5 Suggested Integration Flow

16.5.1 Introduction and Suggested Integration Flow

Figure 16-21 provides the overall manufacturing flow for the integration of the S.E.C. cartridge processor and mechanical support pieces into the baseboard and system manufacturing flow.

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Figure 16-21. Suggested Baseboard/System Integration Manufacturing Flow

16.5.1.1 Connector Insertion Requirements

Figure 16-22 provides criteria that should be met to ensure that the S.E.C. cartridge interacts correctly with the remaining enabled mechanical pieces. The tilt criteria along both axes is to ensure that the S.E.C. cartridge can interface correctly with the connector and other enabled mechanical pieces (retention mechanism, etc.).

Figure 16-22. Criteria to Ensure Correct Interaction of S.E.C. Cartridge and Mechanical Support Pieces

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InsertConnector

Insert RetentionMechanism

Attach Mount

Attach RetentionMechanism to

Baseboard

Continue SystemAssembly

Ensure Processor isEngaged in Retention

Mechanism

Insert Processor intoRetention Mechanism

and Connector

Attach Heatsinkto Processor

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0.015 inches max tilt

Unacceptable - No lead protrusionShort Axis

Unacceptable - No lead protrusion

Long Axis

0.015 inches max tilt Connector


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at:

16.6 System Integration Manufacturing Guidelines

16.6.1 Introduction and Suggested Integration Flow

System integration manufacturing guidelines and suggested integration flow can be found in the following Application Notes and or Data Sheets based on product specific Information

• S.E.C.C. (242 Contacts): Order Number 243502-001• S.E.C.C. (330 Contacts): Order Number 243770-001• S.E.P.P.: Order Number 243658• Mobile Mini-Cartridge: Order Number 245108-002

All of these material are available electronically at Intel’s Developer’s Insight Web Site online

http://developer.intel.com/design/litcentr/index.htm


• Revised & Updated Slot 1 and Slot 2 content• Added Mobile Mini-Cartridge Section


Cartridge Packaging


intel package data book

Documents

jedec standard jep

leaded molded technology

specific product package dimensions drawings

tweezing surface planarity

projected production accuracy

allowable mold protrusion

lead count sq rect

filled epoxy cyanate ester