INTEGRATION, the VLSI journal 58 (2017) 295–302

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INTEGRATION, the VLSI journal

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Energy efficient EEG acquisition and reconstruction for a Wireless BodyArea Network

Wazir Singh, Ankita Shukla, Sujay Deb n, Angshul MajumdarElectronics and Communication Engineering Department, Indraprastha Institute of Information Technology, Delhi, India

a r t i c l e i n f o

Available online 5 September 2016

Keywords:EEGWBANCompressed SensingAnalog-to-Information Converter SAR ADC

x.doi.org/10.1016/j.vlsi.2016.08.00660/& 2016 Elsevier B.V. All rights reserved.

esponding author.

a b s t r a c t

In Wireless Body Area Networks (WBAN) the energy consumption is dominated by sensing and com-munication. Previous Compressed Sensing (CS) based solutions to EEG telemonitoring over WBAN'scould only reduce the communication cost. In this work, we propose a matrix completion based for-mulation that can also reduce the energy consumption for sensing. At the heart of the system is anAnalog to Information Converter (AIC) implemented in 65 nm CMOS technology. The pseudorandomclock generator enables random under-sampling and subsequent conversion by the 12-bit SuccessiveApproximation Register Analog to Digital Converter (SAR ADC). AIC achieves a sampling rate of 0.5 KS/s,an ENOB 9.54 bits, FOM 187 fj/conv-step and consumes 69.66 nW from 1 V power supply. We test ourmethod with state-of-the-art CS based techniques and find that the reconstruction accuracy of ourmethod is significantly better and that too at considerably less energy consumption. Our method is alsotested for post-reconstruction signal classification where it outperforms previous CS based techniques.

& 2016 Elsevier B.V. All rights reserved.

1. Introduction

EEG signals are useful for monitoring brain activities for med-ical (seizure detection) and cognitive tasks (emotion recognition,Brain Computer Interface). In recent times, there is a growing in-terest in telemonitoring of EEG signals using Wireless Body AreaNetwork (WBAN). The main challenge in a WBAN is to conserveenergy; energy is consumed by three tasks – sensing, processingand communication. The communication cost is the highest; thesensing cost is also significant for our problem; the processing costis negligible compared to the other two tasks.

As communication is the most power hungry operation, theprimary target till now has been to reduce it to some form ofsignal compression. However, traditional transform coding tech-niques are too computationally intensive for a simple sensor nodeand have been precluded at the onset. One easy way to compressthe signal is to project it to a lower dimension using a randommatrix. It has been shown in recent studies [1,2] that a binaryrandom ensemble (of 1's and 0's) is effective for this task forstoring and operating on such a sparse matrix is efficient. Re-covering the EEG signal from its lower-dimensional projection is achallenge. Non-linear recovery algorithms based on CompressedSensing (CS) need to be employed. Since the signal recovery takes

place at the base station, this is not a challenge as computingpower (at the base) is not at a premium.

Previous works could reduce the communication energy in acomputationally efficient manner, but could not reduce the sen-sing energy. The only way to reduce sensing energy is by under-sampling the EEG signal. Periodic under-sampling is not an optionfor obvious reasons. Even with random under-sampling, CS basedtechniques are unable to recover the signal. Since CS requires thesampling operator (in this case the Dirac basis) to be maximallyincoherent with the sparsifying basis (Wavelet or Gabor for EEG).Unfortunately, this condition is not satisfied, i.e. wavelet and Gabor[2] basis is not very incoherent from the Dirac sampling basis.Thus, CS based techniques are not theoretically suitable for thetask. This is the main reason, why past researchers did not attemptreducing the sensing energy by leveraging CS techniques.

For the first time in this work, we propose a technique for re-ducing the sensing cost in EEG signal acquisition. There are twoassociated problems:

a) Design of an efficient Analog-to-Information Converter (AIC)b) Choosing a signal reconstruction algorithm for the said

problem.

The detailed answer to both these problems is discussed later.A crucial part of a medical diagnostics system is a monitoring of

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302296

the biopotential signals. Commonly, patients are connected to abulky and mains powered biopotential acquisition system. How-ever, this not only impedes with the diagnostics requiring long-term monitoring but also disturbs the patient's daily routine. Apossible solution is to use the ultra-low power acquisition system.Analog to digital converter (ADC) is an integral part of any bio-potential acquisition systems. Successive approximation (SAR)converters exhibit the lowest dissipated power levels with mod-erate resolution at relatively lower data rates. That is why we haveexplored SAR ADC in this paper. Here, the Analog-to-InformationConverter (AIC) consists of an SAR ADC with a random clock edgegenerator. In this paper, charge redistribution Digital-to-AnalogConverter (DAC) is used for area efficiency. Compared to conven-tional DAC architecture, a charge redistribution DAC array intern-ally performs the sample and hold operation. Therefore, thesample and hold block is not needed in this implementation. Ty-pically the analog building blocks like DAC and comparator con-sume more than 60% of the total SAR ADC power. In order to re-duce the power consumed by the DAC, we have employed smallersize capacitors. To reduce the power consumption further, a dy-namic latch type comparator is incorporated in the design. In alow-resolution ADC, the power consumed by the analog compo-nents is exponentially related to the number of bits while thepower consumed by the digital control logic is linearly propor-tional to the resolution.

EEG signals are always acquired via multiple channels. Thesignals from all the channels are correlated. These correlated sig-nals can be stacked as columns of a matrix; the formed matrix islow-rank since the columns are not independent. Since each of thesignals are randomly under-sampled, the full matrix is not avail-able. Therefore, the problem is to recover this low-rank matrixfrom its under-sampled entries. This is a classical low-rank matrixcompletion problem [3].

An elaborate discussion on our proposed signal reconstructionis given in the following section. Section 2 provides related works.The design of the data acquisition hardware is described in Section3 and basic building blocks are briefly discussed with simulationresults in Section 4. Prior studies in CS based EEG signal re-construction are discussed in Section 5. We discuss the experi-mental results in Section 6. Finally, the conclusions of this workare discussed in Section 7.

2. Related works

Bio-potential signals are sparse in time-domain, sampling witha fixed frequency is not suitable. Hence, adaptive-sampling is usedin bio-potential recording systems in which the sampling fre-quency changes with the rate of signal variations [4–6].

A sampling technique for the bio-potential signal is presentedin which the sampling rate is controlled by an activity detectorblock [4]. The analog to digital conversion is done by an 11-bit SARADC. Using this technique the data volume is decreased by a factorof 7.3 compared to the case where the sampling is done by aconstant frequency of 1024 Hz. Although the ratio of the totalnumber of data without any compression to the number of com-pressed data is a relatively good, the implementation of thistechnique requires more complex digital circuitry and several re-latively power hungry analog blocks; like opamp, filter, SC differ-entiator and comparators [4]. Hence, this technique would not bevery power-efficient. Moreover, using a differentiator increases thenoise sensitivity of the circuit. Also, in the calculation of thecompression ratio, the extra data that should be saved as an in-dication of the exact time of sampling (typically known as the timestamps or time flags) are not considered. Hence, the effectivecompression ratio is lower.

A non-uniform sampling technique is presented in which twodifferent sampling frequencies are used [5]. In this method, themaximum and minimum points of the signal are detected and thesampling frequency is increased around these points. Circuit levelsimulations have shown that this technique can reduce the aver-age sampling frequency and the volume of data by 50% and 35%respectively. For the implementation of this system, two differ-entiators are used. Using differentiator increases the noise sus-ceptibility of the system.

Another sub-Nyquist sampling technique is the asynchronoussampling and has been known since 1950. In the asynchronoustechnique instead of sampling the signal at fixed instants, thesignal is sampled whenever it crosses a threshold voltage. Thisway the sampling rate matches the rate of change of the signal [7].

In the adaptive asynchronous sampling, the threshold ischanged according to the slope of the signal which may lead toloss of some of the features of the signal. In paper [6] a modifiedadaptive asynchronous sampling is used. In this technique, eachpeak and valley of the signal are saved and used to calculate thehigh and low threshold voltages for the next period. When thesignal rises (falls) and crosses the high (low) threshold the systemstarts sampling with the highest rate.

A relatively new method for sampling sparse signals with un-der-Nyquist rate is compressive sampling (CS). The CS allows fullrecovery of the original signal. It has been recently considered forEEG and ECG compression [8–12]. Digital CS is proposed in whichcompression is done after digitization with an ADC [8]. The ulti-mate goal in CS is to bring CS algorithm down to the analog part ofthe system before the ADC. However, there is still a long way toreach this goal. Moreover, compression techniques based on CSrequire a complex digital post-processing. In fact, the main reasonfor using CS is to reduce the work load and complexity of the coderat the expense of more complex decoder. There are other samplingtechniques [13] that can theoretically decrease the volume of databut they require a complex function to be implemented. Thesekinds of techniques are not desirable from a circuit point of view.

Based on the above discussions, it is clear that the best way forsampling a sparse signal with minimum data volume and powerconsumption is to sample the signal at a sub-Nyquist rate suchthat it can be accommodated in the sampler circuit (before orduring the ADC). The under-sampling should be done in anadaptive way (and not stochastically) so that the signal can berecovered without much difficulty.

3. Hardware design for Analog-to-Information Converter

A conventional EEG acquisition system with ADC is shown inFig. 1(a) and the block diagram for AIC based acquisition system isshown in Fig. 1(b). The AIC repeatedly takes M random samples ofthe N input signal which are digitized with a low power ADC. Theinput signal is then reconstructed using Kronecker CompressedSensing (KCS). We effectively replace the Nyquist sampling SARADC with SAR ADC and a pseudorandom clock generator to pro-vide random under-sampling of the input signal [14]. This reducesthe power consumption of the signal acquisition process and re-laxes the requirements of the ADC [15]. We also no longer need tocompress the data from the ADC since it will be directly com-pressed by the AIC at a rate of N/M compared to Nyquist. Thepseudorandom clock signal is generated by Linear Feedback ShiftRegister (LFSR).

If the pseudorandom sequence is generated completely ran-domly, then the sample rate of the ADC must be equal to at leastthe Nyquist rate. We can relax the ADC requirements by restrictingthe minimum sample spacing. This allows the full benefits of theCompressed Sensing architecture, mainly a reduction in sample

ADC TXAMP

(a) EEG acquisition system.

ADC TXAMP

AIC

(b) Compressed sensing AIC based EEG acquisition system.

Fig. 1. (a) EEG acquisition system. (b) Compressed Sensing AIC based EEG acqui-sition system.

Comparator

DACCapacitorArray

SARControlLogic

EEGSignal

VcomVdac

12-bit

Vcm

DigitalOutput

PseudorandomClock

Generator

Fig. 2. Block diagram of Analog-to-Information Converter.

Vcm

C11 C10 C9 C1 C0 C0

SA Vdac

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302 297

rate or an increased instantaneous bandwidth, that can be realizedwith additional pseudorandom clock generator. The pseudoran-dom clock sequence used to randomly sample the input signal willhave a large effect on both the reconstruction performance as wellas the overall efficiency of the AIC when implemented in hard-ware. Medical monitoring is an emerging application area thatexemplifies the stringent energy constraints imposed on wirelesssensor nodes and their corresponding circuits.

Fig. 1(a) incorporates an input instrumentation amplifier toamplify the small EEG signals from the head, an ADC to convertthe EEG signals into the digital domain ready for transmission, anda transmitter.

The power consumption (Psys) of the system shown in Fig. 1(a) is given by,

= ( + + ) ( )P P P JF R 1sys Amp ADC s

where Psys is the power consumption of the system, PAmp is thepower consumption of instrumentation amplifier, PADC is thepower consumption of ADC, FS is the ADC sampling frequency, Rthe number of bits per sample and J the net transmission powerper bit and JFSR gives the transmitter power consumption [16].

The power consumption for Compressed Sensing AIC basedsystem as shown in Fig. 1(b) is,

_ = + + ( )P P PMN

JF R 2sys cs Amp AIC s

Here the instrumentation amplifier consumption is same for boththe cases. For CS system, a pseudorandom clock generator (PN) isused to generate random clock sequence and that adds to totalsystem power. In this work, PAIC includes that overhead. In addi-tion to this, the power required to transmit the number of data bits(JFSR in (1)) has been reduced by a factor of M/N (M randomsamples of the N input signal).

Compressed Sensing AIC consists of an SAR ADC with randomsampling capability [17]. The power efficiency of the AIC can bemaximized by taking advantage of the variable time betweensamples. To meet the requirements, we designed a 12-bit AIC asshown in Fig. 2.

SB SB SB SB SB SBVin

Sample

D11 D10 D9 D1 D0

Fig. 3. 12-bit charge redistribution DAC.

4. Basic building blocks Of AIC

Fig. 2 shows the block diagram of the AIC. It consists of a PNclock generator, a dynamic latch comparator, a SAR control logicand a capacitive array DAC incorporating a sample-and-hold

function. The PN generator contains a LFSR to generate the pseu-dorandom clock sequence, which is then used to clock the ADC forthe Compressed Sensing operation. The SAR control logic blockcontains a successive approximation register for the binary searchalgorithm. The DAC contains a switching network at the bottomplate of the capacitor array to perform the conversion and sampleand hold function. A single-ended structure is chosen for lesspower consumption.

For DAC operation, mainly three types of switched capacitornetworks such as a conventional binary-weighted capacitor, chargeredistribution, and capacitor splitting arrays are employed [18]. Thebinary weighted capacitor array is not preferred for its large area andpower consumption. Typically there are two types of comparatorsused in ADCs such as with clock and without a clock.

The without clock based comparator is not preferred due to itshigher power consumption. In general, there are mainly twofundamentally different approaches to designing the SAR logic.The first one which is proposed by Anderson consists of a ringcounter and a shift register. At least 2N flip-flops are employed inthis kind of SAR [19]. The other, which is proposed by Rossi, con-tains N flip flops and some combinational logic [20]. SAR controllogic encompasses a ring counter and a code register. It is com-monly used in SAR ADCs due to its straightforward design tech-nique. The ring counter is actually a shift register. The charge re-distribution DAC and dynamic latch comparator and SAR controllogics are briefly discussed below.

4.1. Charge redistribution DAC

Fig. 3 shows the DAC based on charge redistribution [18]. Theconversion is accomplished by a sequence of three operations such

Fig. 4. Transient response of charge redistribution DAC.

Fig. 6. Transient response of dynamic latch comparator.

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302298

as ‘sample mode’, ‘hold mode’, and ‘redistribution mode’. In sam-pled mode, the top plates of all capacitors are connected to thevoltage (VCM) and bottom plates to VIN. Thus, the input voltage issampled on the capacitor array. During hold mode, switchesconnect the bottom plates to the ground, therefore, a charge of�VINþVCM is stored on the capacitor array. At the starting of re-distribution mode, digital code determines the status of theswitches and actual conversion is performed in this mode. In thebeginning of the conversion, D11 is high so the MSB capacitor isconnected to VREF. At this step, output voltage VDAC of the chargeredistribution DAC is given by

= − + + ( )V V VV

2 3DAC IN CMREF

This process continues up to next sample mode operation andfinally at the end of one conversion period, the output voltage ofthe DAC is given by

= − + + + + + +( )

V V V DV

DV

DV

DV

2 2..

2 2 4DAC IN CMREF REF REF REF

11 0 10 1 1 11 0 12

The simulation result of the 12-bit DAC is depicted in Fig. 4. Thelinearity of ADC is restricted by the linearity of the DAC which iscaused by the capacitor mismatch. Therefore, choosing an appro-priate value for the unit capacitance is vital. Reducing the unitcapacitance value improves the linearity but deteriorates the noiseperformance at the same time due to KT

Cthermal noise. The mini-

mum value of the unit capacitor is limited by several factors in-cluding thermal noise, capacitor matching and the value of theparasitic capacitances or design rules of the technology [21]. Inorder to save the power consumption, the value should be as small

Fig. 5. Dynamic latch comparator.

as possible. Considering the process and the resolution mentionedin [21], we selected the unit capacitance value to be 20 fF. Thevalues of the other capacitors in the capacitor array are definedbased on the unit capacitance.

4.2. Dynamic latch comparator

A dynamic latch comparator is shown in Fig. 5. An analogvoltage comparator compares the output VDAC of the DAC with areference voltage VCM. The comparison output is given to the SARlogic which provides an approximate digital code of VIN to the DAC.The DAC operates as a sample and holds circuit to acquire theinput voltage (VIN) for some duration and for the remaining timeDAC supplies an analog voltage equivalent of the digital code tothe comparator. Based on the output of the comparator, the SARlogic performs the binary search algorithm to determine the di-gital output code. This comparator works in two phases [22].

One is reset phase where CLK¼0 and another one is decisionphase where CLK¼1. The output will be decided in the decisionphase. The latch draws maximum current during the decisionphase.

The simulation result of the comparator is given in Fig. 6. Thesimulation result clearly shows that when Vin is greater than thereference voltage and the clock is low then Voutþ is low and whenthe clock is high then Voutþ is high. So we conclude that thiscomparator is working when the clock is present.

4.3. SAR control logic

SAR control logic contains a sequencer and a shift register isshown in Fig. 7 [19]. It performs a binary search on the output

Fig. 7. 12-bit SAR controls logic.

Fig. 8. Transient response of SAR controls logic.

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302 299

value of comparator. The conversion process begins by samplingthe input. In the first cycle of the redistribution mode, SAR is in-itialized with the most significant bit (MSB) as ‘1’ and remainingbits as ‘0’. This code is applied to the DAC and it produces theequivalent analog voltage of V

2REF . It will be added to the previous

DAC output and subsequently given as input to the comparator(VDAC). If the comparator output is high, the digital control logicretains the MSB as ‘1’. If the comparator output is low, the digitalcontrol logic changes the MSB to‘0’. The next bit (i.e. MSB-1) willbe set to ‘1’ in both the cases mentioned above. This processcontinues until all bits of the digital word have been decided bysuccessive approximation. The resulting code will be the digitalapproximation of the sampled input voltage and at the end of theconversion output of the DAC. The simulation result of 12-bit SARcontrol logic is shown in Fig. 8.

4.4. Pseudorandom clock generator

We effectively replace the Nyquist sampling SAR ADC with aSAR ADC with pseudorandom clock generator to provide randomunder-sampling of the input signal. This reduces the power con-sumption of the signal acquisition process and relaxes the re-quirements of the ADC by restricting the minimum sample spa-cing. The pseudorandom clock signal is generated by LFSR. The AICrepeatedly takes M random samples of the N input signal whichare digitized with a low power ADC. We also no longer need tocompress the data from the ADC since it will be directly com-pressed by the AIC at a rate of N/M compared to Nyquist.

If we view the input EEG(t) as a discrete time signal EEG[n], theproposed random under-sampling operation can be viewed aschoosing M samples at random from each successive length Nwindow of EEG[n]. After each set of M samples is taken, the inputspectrum during the corresponding window is reconstructed byCS method.

A transistor level design of the PN clock generator was im-plemented in the same 65 nm CMOS process as the ADC design.LFSR as shown in Fig. 9 is used to generate the pseudorandom

Fig. 9. 12-bit LFSR.

clock sequence, which is then used to clock the ADC for theCompressed Sensing operation.

There will be power dissipation overhead because of the ad-dition of the PN clock generator to build the AIC [15]. To limit thatoverhead the transistors are sized appropriately to meet theminimum power consumption target. All the transistors areminimum size with double length to mitigate the leakage pro-blem. By employing both high Vt and low Vt transistors (e.g. Tailtransistor with high Vt and input transistors with low Vt), lowleakage power is achieved without any speed reduction.

5. EEG signal reconstruction

One of the earliest works that applied CS for EEG signal com-pression and transmission is [10]. The EEG signal is projected ontoan i.i.d Gaussian basis for compression and employs a synthesisprior formulation for sparse signal recovery using Gabor as asparsifying basis. Synthesis prior only works for orthogonal andtight-frame sparsifying transforms such as DCT, wavelets, curveletsetc. Unfortunately, Gabor is not an orthogonal or tight frametransform. Their formulation [10], can successfully recover thesparse Gabor coefficients of the signal, but in theory, it can onlyrecover the EEG signal approximately.

In [16], different sparsifying transforms were compared – wa-velets, Gabor, splines; it was reported that Gabor yielded the bestreconstruction results. This is an interesting result but this paperhas the same issue as [10]; here also the EEG reconstruction wasposed as a synthesis prior problem using the Gabor basis.

The possibility of exploiting inter-channel correlation in orderto improve EEG signal reconstruction was mentioned in [10], butno concrete idea regarding how to model it was proposed. Thisproblem was partially addressed in [1]. In [1], the inter-channelcorrelation was not modeled, instead a joint reconstruction pro-blem was framed where the signals from all the channels werereconstructed simultaneously. This work used wavelets as thesparsifying basis.

A more recently proposed model assume a block structure ofthe EEG signals in a transform domain (DCT or wavelet) [2]. Thereis no theoretical or physical intuition behind this assumption;however it is shown in [2] that a Block Sparse Bayesian Learning(BSBL) algorithm yields good recovery results. The earlier studieslike [10,16] used standard CS measurement operators like i.i.dGaussian matrices to project the sampled EEG signal onto a lowerdimension. Unfortunately such Gaussian matrices are dense; theyare inefficient both in terms of memory and computation. To al-leviate this problem a sparse random binary matrix was proposedin [23]. Such matrices have been found to work very well for EEGreconstruction [1,2].

In [11], an unusual sparsifying basis was proposed to re-construct the EEG signals. It claims that the Slepian basis is a goodbasis for recovery.

A study which addresses a similar problem but in a slightlydifferent note is proposed in [24]. The EEG signals are collectedremotely and the data analysis is performed centrally. What isinteresting about this study is that it showed that certain dataanalysis tasks such as seizure detection, can be directly performedin the compressed domain; i.e. one does not require to reconstructthe signal. For general purpose applications however, the EEGsignal indeed needs to be reconstructed.

As we mentioned before, the only way to reduce acquisitionenergy is by under-sampling the EEG signals [25]. This operationcan be expressed as

ο η= + ∀ ( )y R x i, 5i i i

Fig. 10. Decay of singular values for the multi-channel signal ensemble.

Fig. 11. Transient response of AIC.

Fig. 12. AIC output spectrum.

Table 1AIC performance summary.

Parameter Value

Technology 65 nm CMOSSupply voltage 1 VResolution 12 bitsSample rate 0.5 KS/sPower consumption 69.66 nWSFDR 66.32 dBSNDR 59.19 dBSNR 60.12 dBENOB 9.54FOM 187 fj/conv-step

Table 2Comparison with state-of-the-art designs.

References Technology Supplyvoltage

Resolution(bits)

Sampling rate Power

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302300

where i, denotes the ith channel, xi is the EEG signal (to be re-constructed), yi is the under-sampled measurement, Ri is thebinary sampling mask (ο denotes bit-wise multiplication) and η isthe noise assumed to be Normally distributed.

The EEG signal ensemble from all the channels can be arrangedin the following form:

ο η= + ( )Y R X 6

where Y, X and R are the Casorati matrices formed by stacking theyi's, xi's and Ri's as columns.

The problem is to recover X from the acquired Y and knowledgeof R. This is an under-determined inverse problem with infinitelymany solutions. To find a reasonable solution, we need to haveprior knowledge regarding X. In this case, we model X to be a low-rank matrix. This is true since the EEG signals from differentchannels are correlated with each other; therefore, the columns ofX are not linearly independent. In order to corroborate our claim,we show the decay of singular values of a multi-channel EEG en-semble in Fig. 10. The singular values decay fast, implying that thesignal ensemble is approximately low-rank.

In low-rank matrix completion [3], one ideally needs to mini-mize the rank of the matrix. However, rank minimization is an NP-hard problem. Theoretical studies [3,26] have shown that, relaxingthe NP-hard rank minimization problem to its closest convexsurrogate – Nuclear Norm still guarantees a low-rank solution.Following these studies, we propose to recover X via:

ο λ‖ − ‖ + ‖ ‖* ( )Y R X Xmin 7XF2

Here ‘F’ denotes the Frobenius' norm and ‘*’ denotes the NuclearNorm which is defined as the sum of singular values.

There are several algorithms to solve the low-rank matrix re-covery problem, e.g. Singular Value Thresholding (SVT) [27] andFixed Point Continuation (FPC) [28]. However, by far the best al-gorithm in terms of speed and accuracy is the Split Bregman basedSingular Value Shrinkage (SVS) [29].

[32] 180 nm 1.8 V 12 120KS/s 2.95 mW[31] 180 nm 1.8 V 12 100KS/s 47.86 mW[30] 180 nm 1 V 12 100KS/s 25 mW[33] 180 nm 1 V 9 150KS/s 30 mW[34] 130 nm 1 V 12 1MS/s 58 mW[15] 90 nm 1.2 V 10 9.5MS/s 550 mW[35] 65 nm 1.2 14 80MS/s 31.1 mW

This Work 65nm_TT 1 V 12 0.5KS/s 69.66 nW65nm_FF 1 V 12 0.5KS/s 120.5 nW65nm_FS 1 V 12 0.5KS/s 150.9 nW65nm_SF 1 V 12 0.5KS/s 36.42 nW65nm_SS 1 V 12 0.5KS/s 27 nW

6. Experimental and simulation evaluation

In this section, we focus on the circuit simulation and re-construction evaluation to testify the performance of AIC. All theAIC blocks are simulated in transistor-level by Cadence Spectre.The recorded data from Cadence is executed in Matlab for calcu-lating the performance (SNDR/SFDR/ENOB).

6.1. Results of analog to information converter

The AIC is designed and simulated using 65 nm CMOS tech-nology. The performance of the AIC is measured at 1 V supply with

Table 3Comparative Reconstruction Results (NMSE) on BCI Competition III Dataset 1.

Method Compression Ratio

2:1 (mean, std) 4:1 (mean, std)

BSBL [2] 0.212, 70.120 0.368, 70.188Sparse reconstruction [1] 0.380, 70.154 0.518, 70.196Proposed reconstruction 0.066, 70.028 0.102, 70.080

Table 4Classification accuracy in %.

Method Classification accuracy

Compression 2:1 Compression 4:1

Original 81% (No compression)BSBL Reconstruction [36] 73% 52%Sparse Reconstruction [29] 70% 50%Proposed Reconstruction 80% 60%

W. Singh et al. / INTEGRATION, the VLSI journal 58 (2017) 295–302 301

a sampling rate of 0.5 KS/s. The SAR ADC is designed in singleended DAC architecture. The applied input ac signal frequency andamplitude (VPP) are 200 Hz and 500 mV respectively. The timingresponse of the AIC is depicted in Fig. 11.

The output spectrum for a full-scale 179.69 Hz sinusoidal input,at a supply voltage of 1 V and sampling rate of 0.5 KS/s, is shown inFig. 12. The signal-to-noise and distortion ratio (SNDR), spuriousfree dynamic range (SFDR), effective number of bits (ENOB) are59.19 dB, 66.32 dB, and 9.54 bits, respectively. The Figure of Merit(FOM) of ADC is given by

=( )

FOMPower

F2 . 8ENOBs

where FS is the sampling frequency. The FOM obtained is 187 fJ/conv-step. The performance results of the AIC are summarized inTable 1.

We compared our design for power consumption with thestate-of-the-art designs as shown in Table 2. For a fair comparison,the technology node used for simulation should be same andsimple scaling of the existing designs reveal that our design will bemore power efficient compared to the scaled versions of the stateof the art designs.

6.2. Evaluation of reconstruction algorithm

There is no actual benchmark to compare our proposedmethod. Previous Compressed Sensing based methods are incap-able of operating in the sensing paradigm where the EEG signalsamples are partially sampled. However in order to test ourmethod, we compare it against two state-of-the-art CS-based re-covery schemes-sparse recovery [1] and BSBL recovery [2].

The experiments are carried out on the BCI Competition IIIdataset 1 [36]. During the BCI experiment, a subject had to per-form imagined movements of either the left small finger or thetongue. The time series of the electrical brain activity was pickedup during these trials using a 8�8 ECoG platinum electrode gridwhich was placed on the contralateral (right) motor cortex. Thegrid was assumed to cover the right motor cortex completely, butdue to its size (approx. 8�8 cm) it partly covered also surroundingcortex areas. All recordings were performed with a sampling rateof 1000 Hz. After amplification the recorded potentials werestored as microvolt values. Every trial consisted of either an ima-gined tongue or an imagined finger movement and was recordedfor 3 s duration. To avoid visually evoked potentials being reflected

by the data, the recording intervals started 0.5 s after the visualcue had ended.

We tested the recovery results for two different sampling ra-tios – 50% (2:1) and 25% (4:1). The metric used for evaluation is theNormalized Mean Squared Error(NMSE) [37]. It is defined as theratio of l2-norm of error to the l2-norm of original signal X andgiven by

=‖ − ‖

‖ ‖ ( )NMSE

original reconstructedoriginal 9

2

2

where reconstructed signal is obtained from Eq. 7. The re-construction results are shown in Table 3. For each signal en-semble and for each configuration, the random sampling matrixhas been simulated 100 times. The mean and standard deviations(of NMSE’s) for all the EEG signals in the dataset are reported.

Our proposed method yields significantly better reconstructionresults than the previously known CS techniques [1,2] for bothunder-sampling ratios.

NMSE is a well-accepted measure for comparing reconstructionaccuracy in CS recovery problems. However, signal reconstructionis not the end of the story. In most cases, the recovered EEG signalsare analyzed by human experts or via some automated process. Itis not feasible to obtain feedback from human experts on a largenumber of EEG signals; thus in this work we carry out an auto-mated classification task on the BCI competition III Dataset 1 inorder to see how the reconstruction has affected the performance.We carry out the classification of the original and the re-constructed signals using algorithm [38] – this is one of thecompeting algorithms for BCI competition. The classification re-sults are given in the following Table 4.

We find that our proposed method yields better classificationaccuracy than the previous CS based techniques. It is only mar-ginally worse than the original data.

Tables 1 and 2 show the energy efficiency of our proposedsolution. Tables 3 and 4 show that using our proposed re-construction technique one can get almost the same quality ofresults from only partial samples as that of the original data. Thisin turn means that it is possible to save a large amount of energyusing our end to end solution without compromising the task.

7. Conclusion

Current CS based techniques in energy efficient transmission of EEGsignals on WBAN's can only reduce the communication costs. For thefirst time in this work, we propose to reduce the sensing and pro-cessing energy costs as well. We achieve this by sub-sampling the EEGsignals in the time domain and recovering the multi-channel signalensemble using low-rank matrix completion techniques. We compareour proposal with previous CS based techniques. Our method yieldsbetter recovery results. Quantitative evaluation shows that the re-construction is almost indistinguishable from the fully sampled signal.Analog-to-Information Converter implemented in 65 nm CMOS tech-nology and achieves a sample rate of 0.5 KS/s, an ENOB 9.54 bits, FOM187 fj/conv-step and consumes 69.66 nW from 1 V power supply.

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Wazir Singh received his M.Tech. degree in VLSI Design and CAD from ThaparUniversity, Punjab, India in 2011. He is currently pursuing his Ph.D. degree at IIIT-Delhi, India. His research interests include Interconnects, Network-on-Chips (NoCs)and Mixed-signal Circuit Design. He has published more than 10 journal andconference papers. Winner of travel grant award from IEEE-CAS to present apublication at IEEE iNIS, Dec 2015, at Indore, India. He is a graduate studentmember of IEEE.

Ankita Shukla received her M.Tech. degree in Electronics and CommunicationEngineering from IIIT-Delhi, India in 2014. She is currently pursuing her Ph.D. de-gree at IIIT-Delhi, India. Her research interests include compressed sensing andsparse recovery, machine learning and computer vision. She has published morethan 5 journal and conference papers. She is a graduate student member of IEEE.

Sujay Deb received the B.Tech. degree in electronics and communication en-gineering from North Eastern Regional Institute of Science and Technology, Ar-unachal Pradesh, India, in 2004, the M.S. degree in telecommunication engineeringfrom the Indian Institute of Technology, Kharagpur, India, in 2007, and the Ph.D.degree in electrical and computer engineering from the Washington State Uni-versity, Pullman, in 2012. Since 2012, he has been as Assistant Professor with theElectronics and Communication Engineering Department, Indraprastha Institute ofInformation Technology, Delhi. His broader research interest is the design of novelinterconnect architectures for multi-core chips. Specifically, it comprises analysis ofnetwork-on-chip communication fabrics in the presence of long-range millimeter-wave wireless links, Dr. Deb received the “Outstanding Ph.D. student award inComputer Engineering” at Washington State University for his contributions inresearch and Innovation in Science Pursuit for Inspired Research (INSPIRE) FacultyAward in 2012.

Angshul Majumdar is an Assistant Professor with the Indraprastha Institute ofInformation Technology, Delhi, India, since 2012. He was a Graduate Student withthe Signal and Image Processing Laboratory, University of British Columbia, Van-couver, BC, Canada, He has authored more than 95 journals and conference papers.His research interests include Compressed Sensing and sparse recovery, low-rankmatrix recovery, magnetic resonance imaging, and color imaging.