input/output interface circuits and lsi peripheral …

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INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE

國立台灣大學生物機電系林達德611 37100 微處理機原理與應用 Lecture 10-2


10.1 Core and Special-Purpose I/O Interfaces10.2 Byte-Wide Output Ports Using Isolated

I/O10.3 Byte-Wide Input Ports Using Isolated I/O10.4 Input/Output Handshaking and a

Parallel Printer Interface10.5 82C55A Programmable Peripheral

Interface10.6 82C55A Implementation of Parallel

Input/Output Ports

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10.7 Memory-Mapped Input/Output Ports10.8 82C54 Programmable Interval Timer10.9 82C37A Programmable Direct Memory

Access Controller10.10 Serial Communication Interface10.11 Programmable Communication

Interface Controller10.12 Keyboard and Display Interface10.13 8279 Programmable Keyboard/Display

Controller

10.1 Core and Special-Purpose I/O Interfaces

Special-Purpose I/O interfacesKeyboard interfaceDisplay interfaceParallel printer interfaceSerial communication interfaceLocal area network interface

Core I/O interfacesParallel input/output portsInterval timersDirect memory access control

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10.2 Byte-Wide Output Ports Using Isolated I/O

Sixty-four-line parallel output circuit for an 8088-based microcomputer


1XXXXXXXXXXX11102Port 71XXXXXXXXXXX11002Port 61XXXXXXXXXXX10102Port 51XXXXXXXXXXX10002Port 41XXXXXXXXXXX01102Port 31XXXXXXXXXXX01002Port 21XXXXXXXXXXX00102Port 11XXXXXXXXXXX00002Port 0

I/O AddressI/O Port

I/O Address decoding for ports 0 through 7

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Sixty-four-line parallel output circuit for an 8086-based microcomputer


EXAMPLETo which output port in the 8088-based microcomputer are

data written when the address put on the bus during an output cycle is 800216? Solution:

Express the address in binary form, we getA15…A0 = A15L…A0L = 10000000000000102

That is A15L = 1, A0L = 0 and A3LA2LA1L = 001Moreover, whenever an output bus cycle is in progress, IO/M is logic 1, Therefore the enable inputs of the 74F138 decoder are

G2B = A0L = 0G2A = IO/M = 0G = A = 1

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These inputs enable the decoder for operation. At the same time,its select inputs are supplied with the code 001. This input causes output P1 to switch to logic 0:

P1 = 0

The gate at the CLK input of port 1 has as its inputs P1 and WR. When valid output data are on the bus, WR switches to logic 0. Since P1 is also 0, the CLK input of the 74F374 for port 1 switches to logic 0. At the end of the WR pulse, the clock switches from 0 to 1, a positive transition. This causes the data on D0 through D7 to be latched and become available at output lines O8 through O15 of port 1.


EXAMPLEWrite a series of instructions that will output the byte contents

of the memory address DATA to output port 0 in the circuit shownin the previous figure of the 8088-base microcomputer.

Solution:To write a byte to output port 0, the address is

A15A14 … A0 = 1XXXXXXXXXXX00002Assuming that the don’t-care bits are all made logic 0, we get

A15A14 … A0 = 10000000000000002 = 800016The instruction sequence is

MOV DX, 8000HMOV AL, [DATA]OUT DX, AL

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Time-delay loop and blinking an LED at an output port

Driving an LED connected to an output port


Time-delay loop and blinking and LED at an output port

MOV DX, 8000H ; Initialize address of port 0MOV AL, 00H ; Load data with bit 7 as logic 0

ON_OFF OUT DX, AL ; Output the data to port 0MOV CX, 0FFFFH ; Load delay count of FFFFH

HERE: LOOP HERE ; Time delay loopXOR AL, 80H ; Complement bit 7 of ALJMP ON_OFF ; Repeat to output the new bit 7

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10.3 Byte-Wide Input Ports Using Isolated I/O

Sixty-four-line parallel input circuit for an 8088-based microcomputer


EXAMPLEWhat is the I/O address of port 7 in the circuit of the previous

figure? Assume all unused address bits are at logic 0

Solution:For the I/O address decoder to be enable, address bits A15 and

A0 must beA15 = 1 and A0 = 0

To select port 7, the address applied to the CBA inputs of the decoder must be

A3LA2LA1L = 111Using 0s for the unused bits gives the address

A15 … A1LA0L = 10000000000011102 = 800E16

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EXAMPLEFor the circuit in the previous figure, write an instruction

sequence that inputs the byte contents of input port 7 to the memory location DATA_7

Solution:In the previous example we found that the address of port 7 is

800E16. This address is loaded into the DX register byMOV DX, 800EH

Now the contents of this port are input to the AL register byIN AL, DX

Finally, the byte of data is copied to memory location DATA_7 byMOV DATA_7, AL


Polling the setting of a switch

Reading the setting of a switch connected to an input port

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Polling the setting of a switch

MOV DX, 8000H POLL_I7: IN AL, DX

SHL AL, 1JC POLL_I7

CONTINUE:

10.4 Input/Output Handshaking and a Parallel Printer Interface

I/O synchronization is achieved by implementing what is known as handshaking as part of the input/output interface.Three general types of signals at the printer interface:

DataControlStatus

ParallelPrinter

Port

Data

PrinterControl

Status

Parallel printer interface

Status

Send data

Send control

True

False

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Parallel printer port in assignments and types of interface signals

Select13Paper Empty12

Busy11Ack10

Data 79Data 68Data 57Data 46Data 35Data 24Data 13Data 02Strobe1

AssignmentPin

Ground25Ground24Ground23Ground22Ground21Ground20Ground19Ground18Slctin17

Initialize16Error15

Auto Foxt14AssignmentPin

Data: Data0, Data1, …, Data7

Control: StrobeAuto FoxtInitializeSlctin

Status: AckBusyPaper EmptySelectError


I/O interface that employs handshaking

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Handshake sequence flowchart


Handshaking printer interface circuit

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EXAMPLEWhat are the addresses of the ports that provide the data lines,

strobe output, and busy input in the circuit shown in the previous figure? Assume that all unused address bits are 0s.

Solution:The I/O address that enable port 0 for the data lines, port 1 for

the strobe output, and port 2 for the busy input are found as follows:

Address of port 0 = 10000000000000002 = 800016

Address of port 1 = 10000000000000102 = 800216

Address of port 2 = 10000000000001002 = 800416


EXAMPLEWrite a program that will implement the sequence for the

circuit in the previous figure. Character data are held in memory starting at address PRNT_BUFF, and the number of characters held in the buffer is identified by the count at address CHAR_COUNT. Use the port address from the previous example.

Solution:First, the character counter and the character points are setup

with the instructionsMOV CL, CHAR_COUNT ; (CL) = character countMOV SI, PRNT_BUFF ; (SI) = character pointer

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Next, the BUSY input is checked with the instructionsPOLL_BUSY MOV DX, 8004H ; Keep polling till busy = 0

IN AL, DXAND AL, 01HJNZ POLL_BUSY

The character is copied into AL, and then it is output to port 0:MOV AL, [SI] ; Get the next characterMOV DX, 8000HOUT DX, AL ; and output it to port 0


Now, a strobe pulse is generated at port 1 with the instructionsMOV AL, 00H ; STB = 0MOV DX, 8002HOUT DX, ALMOV BX, 0FH ; Delay for STB duration

STROBE: DEC BXJNZ STROBEMOV AL, 01H ; STB = 1OUT DX, AL

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At this point, the value of PRNT_BUFF must be incremented, and the value of CHAR_COUNT must be decremented:

INC SI ; Update character counterDEC CL ; and pointer

Finally, a check is made to see if the printer buffer is empty. If it is not empty, we need to repeat the prior instruction sequence. To do this, we execute the instruction

JNZ POLL_BUSY ; Repeat till all character; have been transferred

DONE: -The program comes to the DONE label after all characters are transferred to the printer

10.5 82C55A Programmable Peripheral Interface

The 82C55A is an LSI peripheral designed to permit easy implementation of parallel I/O in the 8088- and 8086-microcomputer system.Flexible parallel interface:

Single-bit, 4-bit, and byte-wide input and output portsLevel sensitive inputsLatched outputsStrobed inputs or outputsStrobed bidirectional input/outputs

Timing of the data transfers to the 82C55A is controlled by the read/write control (RD and WR) signals.

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Block diagram and pin layout of the 82C55A

InterfaceThe source or destination register within the 82C55A is selected by a 2-bit register select code (A1A0).The chip-select (CS) input must be logic 0 during all read or write operations to the 82C55A.The reset (RESET) is used to initialize the 82C55A.Three byte-wide ports (port A, port B, port C) can be configured for input or output operation. This gives us a total of 24 I/O lines.The 82C55A contains an 8-bit internal control register for software control.A write bus cycle to the 82C55A with register-select code A1A0 = 11, and an appropriate control word is used to modify the control register.


Addressing an 82C55A using the microcomputer interface signals


EXAMPLEWhat is the addresses of port A, port B, port C of the 82C55A

device?

Solution:To access port A, A1A0 = 00, A15 = A14 = 1, A13 = A12 = … = A2

= 0, which gives the port A address as

1100 0000 0000 00002 = C00016

Similarly, it can be determined that the address of port B equals C00116, that of port C is C00216, and the address of the control register is C00316.

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Control-word bit functions


Mode 0 – Simple I/O operation

Mode 0 port pin functions

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EXAMPLEWhat is the mode and I/O configuration for ports A, B, and C of

an 82C55A after its control register is loaded with 8216?

Solution:Expressing the control register contents in binary form, we get

D7D6D5D4D3D2D1D0 = 100000102

Since D7 is 1, the modes of operation of the ports are selected by the control word.

D0 = 0 Lower four bits of port C are outputs.D1 = 1 Port B is an input port.D2 = 0 Mode 0 for both port B and the lower four

bits of port C.

InterfaceThe next for bits configure the upper part of port C and port A:

D3 = 0 Upper four bits of port C are outputs.D4 = 0 Port A is an output port.D6D5 = 00 Mode 0 for both port A and the upper four

bits of port C

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Mode 0 control words and corresponding input/output configurations.




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Mode 1 – Strobed I/OIn mode 1, the A and B ports are configured as two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and upper nibbles of port C, respectively.In mode 1, data applied to an input port must be strobed in with a signal produced in external hardware.An output port in mode 1 is provided with handshake signals that indicate when new data are available at its outputs and when an external device has read these values.


Mode 1 – Strobed I/O




Mode 1, port A output and input configuration



Mode 1, port A input and output timing diagram

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EXAMPLEThe following figures show how port B can be configured for

mode 1 operation. Describe what happens in the left figure when the STBB input is pulsed to logic 0. Assume that INTEB is already set to 1.


SOLUTION:

As STBB is pulsed, the byte of data at PB7 through PB0 is latched into the port B register. This causes the IBFB output to switch to 1. Since INTEB is 1, INTRBswitches to logic 1.

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Mode 2 – Strobed bidirectional I/O




Mode 2 input/output configuration

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Mode 2 bit set/reset format


EXAMPLEThe interrupt-control flag INTEA for output port A in mode 1 is

controlled by PC6. Using the set/reset feature of the 82C55A, what command code must be written to the control register of the 82C55A to set it to enable the control flag?

Solution:To use the set/reset feature, D7 must be logic 0. Moreover,

INTEA is to be set; therefore, D0 must be logic 1. Finally, to select PC6, the code at bits D3D2D1 must be 110. The rest of the bits are don’t-care states. This gives us the control word

D7D6D5D4D3D2D1D0 = 0XXX11012

Replacing the don’t-care states with the 0 logic level, we getD7D6D5D4D3D2D1D0 = 000011012 = 0D16

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Mixed modes

Combined mode 2 and mode 0 (input) control word and I/O configuration


Mixed modes

Combined mode 2 and mode 1 (output) control word and I/O configuration

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EXAMPLEWhat control word must be written into the control register of

the 82C55A such that port A is configured for bidirectional operation and port B is set up with mode 1 outputs?Solution:

To configure the operating mode of the ports of the 82C55A, D7must be 1. Port A is set up for bidirectional operation by making D6logic 1. In this case, D5 through D3 are don’t-care states:

D5D4D3 = XXX2Mode 1 is selected for port B by logic 1 in D2 and output operation by logic 0 in D1. D0 is a don’t-care state.This gives the control word

D7D6D5D4D3D2D1D0 = 11XXX10X2= 11000100 = C4


EXAMPLEWrite the sequence of instructions needed to load the control

register of an 82C55A with the control word formed in the previous example. Assume that the control register of the 82C55A resides at address 0F16 of the I/O address space?Solution:

First we must load AL with C416 . This is the value of the control word that is to be written to the control register at address 0F16. The move instruction used to load AL is

MOV AL, 0C4HThese data are output to the control register with OUT instruction

OUT 0FH, ALBecause the I/O address of the control register is less than FF16, this instruction uses direct I/O.

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When the 82C55A is configured in mode 1 or mode 2 operations, most of the pins of port C perform I/O control functions.

Mode 1 status information for port C Mode 1 status information for port C

10.6 82C55A Implementation of Parallel Input/Output Ports

82C55A parallel I/O ports in an 8088-based microcomputer

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EXAMPLEWhat must be the address bus inputs of the circuit in the

previous figure if port C of PPI 14 is to be accessed?Solution:

To enable PPI 14, the 74F138 must be enabled for operation and its O7 output switched to logic 0. This requires enable input G2B= 0 and chip select code CBA = 111. This in turn requires from the bus that

A0 = 0 to enable 74F138and A5A4A3 = 111 to select PPI 14Port C of PPI 14 is selected with A1A0 = 10, which from the bus requires that

A2A1 = 10The rest of the address bits are don’t-care states.


EXAMPLEAssume that in the previous figure, PPI 14 is configured so that

port A is an output port, both ports B and C are input ports, and all three ports are set up for mode 0 operation. Write a program that will input that data at port B and C, find the difference (port C) –(port B), and output this difference to port A.Solution:

Port A address = 001110002 = 3816

Similarly, Port B address = 3A16,, Port C address = 3C16Therefore, IN AL, 3AH ; Read port B

MOV BL, AL ; Save data from port BIN AL, 3CH ; Read port CSUB AL, BL ; Subtract B from COUT 38H, AL ; Write to port A

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82C55A parallel I/O ports in an 8086-based microcomputer

10.7 Memory-Mapped Input/Output Ports

The full 20-bit address is available for addressing I/O. Therefore, memory-mapped I/O devices can reside anywhere in the 1Mbyte memory address space of the 8088.During I/O operations, memory read and write bus cycles are initiated instead of I/O bus cycles.Memory instructions, not input/output instructions, are used to perform data transfer.


Memory-mapped 82C55A parallel I/O ports in an


EXAMPLEWhich I/O port in the previous figure is selected for operation

when the memory address output on the bus is 0040216?Solution:

We begin by converting the address to binary form. This givesA19…A1A0 = 000000000100000000102

In this address, bits A10 = 1 and A0 = 0. Therefore, the 74F138 address decoder is enabled whenever IO/M = 0.

A5A4A3 = 000 This input code switches decoder output O0 to logic 0 and chip selects PPI 0 for operation.The address bits applied to the port select inputs of the PPI are A2A1 = 01. These inputs cause port B to be accessed. Thus, the address 0040216 selects port B on PPI 0 for memory-map I/O.

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EXAMPLEWrite the sequence of instructions needed to initialize the

control register of PPI 0 in the circuit of the previous figure so that port A is an output port, ports B and C are input ports, and all three ports are configured for mode 0 operation.

Solution:The control byte required to provide this configuration is:

Ports

From the circuit diagram, the memory address of the control register for PPI 0 is found to be

000000000100000001102 = 0040616

Since PPI 0 is memory mapped, the following move instructions can be used to initialized the control register:

MOV AX, 0 ; Create data segment at 00000HMOV DS, AXMOV AL, 8BH ; Load AL with control byteMOV [406H], AL ; Write control byte to PPI 0 control

; register

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EXAMPLEAssume that PPI 0 in the previous figure is configured as

described in the previous example. Write a program that will input the contents of ports B and C, AND them together, and output theresults to port A.Solution:

The addresses of the three I/O ports on PPI 0 are:Port A = 0040016 Port B = 0040216 Port C = 0040416

Now we set up a data segment at 0000016 and the program is:AND AX, 0 ; Create data segment at 00000HMOV DS, AXMOV BL, [402H] ; Read port BMOV AL, [404H] ; Read port CAND AL, BL ; AND data at port B and C


Memory-mapped 82C55A parallel I/O ports in an 8086-based microcomputer

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10.8 82C54 Programmable Interval Timer

Block diagram of the 82C54The 82C54 is an LSI peripheral designed to permit easy implementation of timer and counter functions in a microcomputer system.The 82C54C can be memory-mapped into the memory address space or I/O-mapped into the I/O address space.The microcomputer interface of the 82C54 allows the MPU to read from and write into its internal registers.The 3 counters in 82C54 are each 16 bits in length and operate as down counters


Block diagram of the 82C54

Block diagram and pin layout of the 82C54 interval timer


Block diagram of the 82C54

Clock or pulse output of counter 0OUT0

Gate must be switched to logic 1 to enable the counter 0

GATE0

Pulses applied to the clock input are used to decrement counter 0

CLK0

Chip-select input to enable the 82C54’s microprocessor interface

CS

Control signals indicating whether 82C54 is to be read from or written into

RD, WR

Register address inputs used to select the register to be accessed

A0, A1

8-bit bidirectional data busD7 – D0

FunctionsSignals


Architecture of the 82C54

Internal architecture of the 82C54 interval timer

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Control word format of the 82C54 interval timer


EXAMPLEAn 82C54 receive the control word 100100002. What

configuration is set up for the timer?

Solution:SC bits = 10 indicating counter 2 is selected.RW bits = 01 sets counter 2 for the read/write sequence

identified as the least significant byte only.The mode code M2M1M0 is 000, this selects mode 0 operation for

counter 2.The last bit, BCD, is also set to 0 and selects binary counting.



Accessing the registers of the 82C54 interval timer


EXAMPLEWrite an instruction sequence to set up the three counters of

the 82C54 in the figure that follows:Counter 0: Binary counter operating in mode 0, value = 1234HCounter 1: BCD counter operating in mode 2, value = 0100HCounter 2: Binary counter operating in mode 4, value = 1FFFH

Solution:First, we need to determine the base address of the 82C54. The

base address, which is also the address of counter 0, is determined with A1A0 set to 00. In the figure, we find that to select 82C54, CS must be logic 0. This requires that

A15A14…A7A6A5…A2 = 000000000100002

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Combining this part of the address with the 00 at A1A0, gives the base address as

00000000010000002 = 40HSince the base address of the 82C54 is 40H, and to select the mode register requires A1A0 = 11, its address is 43H. Similarly, the three counters 0, 1, and 2 are at addresses 40H, 41H, 42H, respectively. Lets determine the mode words for the three counters.

Mode word for counter 0 = 001100002 = 3016

Mode word for counter 1 = 010101012 = 5516

Mode word for counter 2 = 101110002 = B816

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MOV AL, 30H ; Set up counter 0 modeOUT 43H, ALMOV AL, 55H ; Set up counter 1 modeOUT 43H, ALMOV AL, 0B8H ; Set up counter 2 modeOUT 43H, ALMOV AL, 1234H ; Initialize counter 0 with 1234HOUT 40H, ALMOV AL, 12HOUT 40H, ALMOV AL, 0100H ; Initialize counter 1 with 0100HOUT 41H, ALMOV AL, 01HOUT 41H, ALMOV AL, 1FFFH ; Initialize counter 2 with 1FFFHOUT 42H, ALMOV AL, 1FHOUT 42H, AL


EXAMPLEWrite an instruction sequence to read the contents of counter 2

on the fly. The count is to be loaded into the AX register. Assume that the 82C54 is located at I/O address 40H.Solution:

First, we latch that contents of counter 2 and then read this value from the temporary storage register.

MOV AL, 1000XXXXB ; Latch counter 2, XXXX must be as per; the mode and counter type

OUT 43H, ALIN AL, 42H ; Read the low byteMOV BL, ALIN AL, 42H ; Read the high byteMOV AH, ALMOV AL, BL ; (AX) = counter 2 value

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Architecture of the 82C54Read-back mode permits a programmer to capture the current count values and status information of all three counters with a single command.A read back command has bits D6 and D7 both set to 1.

Read-back command format



Read-back command examples

input/output interface circuits and lsi peripheral …

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