I np ut/Output I nterfaceCircuits and LSIPeripheral Devices

A INTRODUCTION

In Chapter 8 we introduced the input/output interface of the 8088 and 8086 microproces-sors. At that time, we discussed the topics of isolated and memory-mapped I/O, minimum-and maximum-mode isolated I/O interface signals, I/O bus cycles, and I/O instructions.Here we continue our study of input/output by examining circuits and large-scale-integrated peripheral ICs that are used to implement input/output subsystems for themicrocomputer systems. The following topics are covered here:

10.1 Core and Special-Purpose I/O Interfaces

I0.2 Byte-Wide Output Ports Using Isolated I/O

10.3 Byte-Wide Input Ports Using Isolated I/O

10.4 Input/Ou@ut Handshaking and a Parallel Printer Interface

10.5 82C55A Programmable Peripheral Interface

10.6 82C55A Implementation of Parallel Input/Output Ports

10.7 Memory-Mapped Input/Output Ports

10.8 82C54 Programmable Interval Timer

10.9 82C37A Programmable Direct Memory Access Controller

10. 10 Serial Communications Interface

463

10. I 1 Programmable Communication Interface Controllers10.12 Keyboard and Display Interface

10.13 827 9 Programmable Keyboard/Display Controller

A I O.I CORE AND SPECIAL-PURPOSE I/O INTERFACES

In Chapter 1 we indicated that the input/output unit provides the microcomputer with themeans for communicating with the outside world. For instance, the PC keyboard permitsthe user to input information such as programs or data for an application. The displayoutputs information about the program or application for the user to read. These exam-ples represent one type of input/output function, which we will call special-purpose I/Ointerfaces. Other examples of special-purpose I/O interfaces are parallel printer inter-faces, serial communication interfaces, and local area network interfaces. They arereferred to as special-purpose interfaces because not all microcomputer systems employeach of these types.

The original PC is capable of supporting a variety of input/output interfaces. In factall the interfaces just mentioned are available for the PC. Since they are special-purposeinterfaces, they are all implemented in the original PC as add-on cards. That is, to supporta keyboard and display interface on the PC, a special keyboard/display controller card isinserted into a slot of the PC and then the keyboard and display are attached to the cardwith cables connected at connectors.

In rnicrocomputer circuit design, various other types of circuits is also classified asinputloutput circuitry. Parallel input/output ports, interval timers, and direct memoryaccess control are examples of interfaces that are also considered to be part of the I/Osubsystem. These I/O functions are employed by most microcomputer systems. For thisreason, we will refer to them as core input/output interfaces.

The core I/O functions are not as visible to the user of the microcomputer; however,they are just as important to overall microcomputer function. The circuitry of the originalPC contains all core microcomputer functions. For example, parallel I/O is the methodused to read the settings of the DIP switches on the processor board. Also an interval timeis used as pafi of the DRAM refresh process and to keep track of the time of day. The cir-cuitry for these core I/O functions is built right on the PC's main processor board. Theyare also included as part of the MPU IC in some highly integrated processors, such as the80C188XL and 80C186XL.

In the sections that follow, we explore the circuits and operations of both the coreand special-purpose input/output functions.

A IO.2 BYTE-WIDE OUTPUT PORTS USING ISOIAIED I/O

We start with circuits that can be used to implement parallel output ports in a microcom-puter system employing isolated I/O. Figure 10-1(a) shows such a circuit for an 8088-based microcomputer, which provides eight byte-wide output ports that are implementedwing 74F374 octal latches. In this circuit, the ports are labeled port 0 thrcugh port 7.These eight ports give a total of 64 parallel output lines, which are labeled Os through 0u,.

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Looking at the circuit, we see that the 8088's address/data bus is demultiplexed just

as was done for the memory interface. Note that two 74F373 octal latches are used to

form a 16-bit address latch. These devices latch the address As through A15 synchfonously

with the ALE pulse. The latched address outputs are labeled Ae1 through 4151. Remem-

ber that address lines A16 through A1e are not involved in the I/O interface. For this rea-

son, they are not shown in the circuit diagram.Address/data bus lines AD6 through AD7 are also applied to one side of the 74F245

bus transceiver. At the other side of the transceiver, data bus lines Ds through D7 ate

shown connecting to the input side of the output latches. It is over these lines that the

8088 writes data into the output ports.

Address lines Ass and A151 provide two of the three enable inputs of the 74F138

input/output address Jecoa"t These signals are applied to enable inputs G2s and G1,

respectively. The decoder requires one more enable signal at ttt Gzo input, which is sup-

plied by the complement of IO/IVI. The enable inputs must be G2sG2aG1 : 001 to enable

the decoder for operation. The condition G2s : 0 corresponds to an even address, and

Gre : 0 represents the fact that an I/O bus cycle is in progress. The third condition,

Gr : 1, is an additional requirement that ,4,151 be at logic 1 during all data transfers for

this section of parallel output ports.

Note that three address lines, A3LA2aA1s, are applied to select inputs CBA of the

74F138 3 line-to-8 line decoder. When the decoder is enabled, the P output conespond-

ing to these select inputs switches to logic 0. Logic 0 at this output enables the WR sig-

nal to the clock (CLK) input of the corresponding output latch. In this way, just one of

the eight ports is selected for operation.Whin valid output data are on D6 through Dr, the 8088 switches WR to logic 0.

This change in logic level causes the selected 74F374 device to latch in the data from the

bus. The 0 logic level at their OE inputs of the latches permanently enables the outputs.

Therefore, the latched data appear at the appropriate port outputs.

The74F245 in the circuit allows the databeing output to pass Erm the 8088 to the

output ports. Enabling the 74F245's DIR and G inputs with the DT/R and DEN signals,

which are atlogic 1 and 0, respectively, accomplishes this.

Note in Fig. 10-1(a) that not all address bits are used in the I/O address decoding'

Here only latched address bits A'L, A,', Azt, A31, and 4151 are decoded. Figure 10-1(b)

shows the addresses that select each of the I/O ports. Unused bits are shown as don't-care

states. By assigning various logic combinations to the unused bits, the same port can be

selected by different addresses. In this way, we see that many addresses will decode to

select each of the I/O ports. For instance, if all don't-care address bits are made 0, the

address of port 0 is

10000000000000002 : 800010

However, if these bits are all made equal to 1 instead of 0, the address is

11111111111100002 : FFF016

and it still decodes io enable port 0. In fact, every I/O address in the range from 800016

through FFF016 that has its lower four bils equal to 00002 decodes to enable port 0. Some

other examples are 8FF016 and F00016.

Sec. lO.2 Byte-Wide Output Ports Using lsolated l,/O 467

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EXAMPLE I O.I

To which output port in Fig. 10-1(a) are data written when the address put on the bus dur-ing an output bus cycle is 800216?

Solution

Expressing the address in binary form, we get

, Ars. . A0 : Arsr. .Aor : 10000000000000102

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Atsl : I

A o l : 0

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A3;A1A1 :001

Moreover, whenever an output bus cycle is in progress, IO/IVI is logic l. Therefore, theenable inputs of the 74F138 decoder are

C t z s : A o L : Q

G z r = I O / l v I : 0

G r : A r s l - 1

These inputs enable the de0oder for operation. At tlie same time, its select inputs are sup-plied with the code 001. This input causes output P1 to switch to logic 0:

P r : 0

The gate at the CLK input of port t has as its inputs P1 and WR. When valid output dataare on the bus, WR switches to logic 0. Since Pr is also 0, the CLK input of the74F374for port 1 switches to logic 0. At the end of the WR pulse, the clock switches from 0 to1, a positive transition. This causes the data on De through D7 to be latched and becomeavailable at output lines 03 through O15 of port 1.

EXAMPLE I0.2

Write a series of inskuctions that will output the byte contents of the memory addressDAIIA to output port 0 in the circuit of Fig. 10-1(a).

464 Input/Output Interface Circuits and LSI Peripheral Devices Chap. | 0

Solution

To write a byte to output port 0, the address that must be output on the gogg's addressbus is

ArsAr+. .A0 : 1XXXXXXXXXXX00002

Assuming that the don't-care bits are all made logic 0, we get

ArsAr+. . .Ao: 10000000000000002

: 800016

The instruction sequence needed to output the contents of memory address DATA to port0 i s

MOV DX, BOOOHMOV AL, [DATA]OUT DX, AL

Figure 10-1(c) shows a similar output circuit for an 8086-based microcomputersystem. Here again, 64 output lines are implemented as g byte-wide paraller ports, port 0lhlough port 7. Comparing this circuit to that for an 8088-based microcomputer in Fig.!0-1(a)' we find just one difference, that the control signal M/Ib is applied directly to ttieG2a input of the 74F138 input/output address decoder since M/I-o isine comptement ofthe 8088's IO/IvI signal, it does not huu" to be inverted.

Time-Defay Loop and Bfinking an LED at an output port

The circuit in Fig. r0-2 has an LED attached to output 07 of paraller port 0. Thiscircuit is identical to that shown in Fig. lo-l(a). Therefore, the port address as found inExample 10.2 is 8000H, and the LED corresponds to bit 7 of the tyte of data that is writ-ten to port 0. For the LED to turn on, 07 must be switched to logit 0, and it will remainon until this output is switched back to L. The 74F374 is not an iiverting latch; therefore,to make 07 logic 0, we simply write 0 to that bit of the octal latch. To make the LEDblink, we must write a program that first makes 07 logic 0 to turn on the LED, delays fora short period of time, and then switches 07 back to 1 to turn off the LED. This piece ofprogram can run as a loop to make the LED continuously blink.

Let us begin by writing the sequence of instructions needed to initialize 07 to logic0. This is done as follows:

ON_OFF:

MOV DX, SOOOHMOV AL, OOHOUT DX, AL

; fn i t ia l i ze address o f por t 0;Load da t .a w i th b i t 7 as log ic 0;Output the data to port 0

After the out operation is performed, the LED will be turned on.

Sec. 10.2 Bytewide Output ports Using lsolated t,/O 469

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HERE: f3xn"il;*1""""" ;iffi: 3:i# ;:li. of FFFFH

First the count register is loaded with FFFF16. Then the loop instruction is executedrepeatedly. With each occulrence of the loop, the count in CX is decremented by 1. After65,335 repeats of the loop, the count in CX is 000016 and the loop operation is iomplete.These executions perform no software function for the program other than to use time,which is the duration of the time delay. By using FFFF16 as the count, the maximum delayis obtained. Loading a smaller number in CX shortens the duration of the delay.

Next the value in bit 7 of AL is complemented to 1 and then a jump is performedto return to the output operation that writes the data to the output port:

XOR AL, BoH ;Complement b i t 7 of ALJMP ON_OFF ;Repeat to output the new bit. Z

By performing an exclusive-OR operation on the value in AL with the value g0,u, themost significant bit is complemented to 1. The jump instruction returns control it tneOUT instruction. Now the new value in AL, with MSB equal to 1, is output to port 0, andthe LED turns off. After this, the time delay repeats, the value in AL is complementedback to 0016, and the LED turns back on. In this way, we see that the LED blinks repeat-edly with an equal period of on and off time that is set by the count in cX.

I O.3 BYTE-WIDE INPUT PORTS USING ISOI-ATED I/O

In Section 10.2, we showed circuits that implemented eight byte-wide output ports for the8088- and 8086-microcomputer systems. These circuitr ur"d the 74F374 octal latch toprovide the output ports. Here we will examine a similar circuit that implements inputports for the microcomputer system.

The circuit in Fig. 10-3 provides eight byte-wide input ports for an 8088-basedmicrocomputer system employing isolated I/O. Just like in the output circuit in Fig.10-1(a)' the ports are labeled port 0 through port 7; however, this time ihe 64 parallel portlines are inputs, Ie through 163. Note that eight 74F244 octal buffers are used to implementthe ports. The outputs of the buffers are applied to the data bus for input to tfre IrApU.These buffers have three-state outputs.

When an input bus cycle is in progress, the I/O address selects the port whose dataare to be input. First Ae through A15 is latched into the 74F373 address latches. Thisaddress is accompanied by logic 1 on the IO/M control line. Note that IO/Ir4 is invertedand applied to the G2a input of the I/O address decoder. If during the bus cycle addressbit AoL : 0 and Arsr- : 1, the address decoder is enabled for operation. Then the codeA3aA2aA11 is decoded to produce an active logic level at one of the decoder's outputs. Forinstance, an input of A31A21A11 : 001 switches the p1 output to logic 0. p1 is gut"d *itttRDp produce the G enable input for the port 1 buffer. If both IOAvI and p, are logic 0,the G input for port 1 is switched to logic 0 and the outputs of the 74F244 are enabled.

Sec. | 0.3 Byte-Wide lnput ports Using lsolated l,/O 471

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In this case, the logic levels at inputs Is through I15 are passed onto data bus lines Ds

through D7, respectively. This byte of data is carried through the enabled data bus trans-ceiver to the data bus ofthe 8088. As part ofthe input operation, the 8088 reads this byteof data into the AL resister.

EXAMPLE I0.3

What is the I/O address of port 7 in the circuit of Fig. 10-3? Assume all unused addressbits are at logic 0.

Solution

For the I/O address decoder to be enabled, address bits A15 and 4'6 must be

A t s : 1

and

A o : 0

To select port 7 , the address applied to the CBA inputs of the decoder must be

A31A21A11 : 111

Using 0s for the unused bits gives the address

Arsr. .AlAor- : 10000000000011102

: 900E16

EXAMPLE I O.4

For the circuit of Fig. 10-3, write an instruction sequence that inputs the byte contents ofinput port 7 to the memory location DATA-7.

Solution

In Example td.3 we found that the address of port 7 is 800E16. This address is loaded intothe DX register with the instruction

MOV DX, BOOEH

Now the contents of this port are input to the AL register by executing the instruction

TN AL, DX

Finally, the byte of data is copied to memory location DATA-7 with the instruction

MOV DATA_7, AI,

sec. 10.3 Byte-wide lnput Ports using lsolated l,/o 47i'

. In practical applications, it is sometimes necessary within an I/O service routine torepeatedly read the value at an input line and test this value for a specific logic level. Forinstance, input 13 at port 0 in Fig. 10-3 can be checked to determine if it is at the 1 logiclevel. Normally, the I/O routine does not continue until the input under test switches tothe appropriate logic level. This technique is known as polling an input. This polling tech-nique can be used to synchronize the execution of an I/O routine to an event in externalhardware.

Let us now look at how a polling software routine is written. The first step in thepolling operation is to read the contents of the input port. For instance, the instructionsneeded to read the contents of port 0 in the circuit of Fig. 10-3 are

POLLT, 13 :

MOV DX, BOOOHIN AL, DX

A label has been added to identify the beginning of the polling routine. After executingthese instructions, the byte contents of port 0 are held in the AL register. Let us assumethat input 13 at this port is the line that is being polled. Therefore, all other bits in AL aremasked off with the instruction

AND AL, OBH

After this instruction is executed, the contents of AL will be either 00H or 08H. Moreoverthe zero flag is 1 ifAL contains 00H or else it is 0. The state ofthe zero flag can be testedwith a jump-on-zero instruction:

'JZ POLL_f3

If zeroflag is 1, a jump is initiated to POLL-I3, and the sequence repeats. On the otherhand, if it is 0, the jump is not made; instead, the instruction following the jump instruc-tion is executed. That is, the polling loop repeats until input 13 is tested and found to belogic 1.

Polfing the Setting of a Switch

Figure 10-4, which is similar to Fig. 10-3, shows a switch cirnnected to input 7 of inputport 0. Note that when the switch is open, input 17 is pulled to +5 V (l,ogic 1) through pull-up resistor R1. When the switch is closed, 17 is connected to ground (logic 0). It is acommon practice to poll a switch like this with software waiting for it to close.

The instruction sequence that follows will poll the switch at It:

MOV DX, SOOOHPoLL-r7' ',I"

ti; ?"JC =POLL-I7

CONTINUE:*

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AL register. Since the logic level at 17 is in bit 7 of the byte of data in AL, a shift left by

one bit position will put this logic level into CF. Now a jump-on-carry instruction is exe-

cuted to test CF. If CF is 1, the switch is not yet closed. In this case, control is returned

to the IN instruction and the poll sequence repeats. On the other hand, if the switch is

closed, bit7 inAL is 0 and this value is shifted into CF. When the JC instruction detects

this condition, the polling operation is complete, and the instruction following JC is

executed.

A I0.4 INPUT/OUTPUT HANDSHAKINGAND A PARALLEL PRINTER INTERFACE

In some applications, the microcomputer must synchronize the input or output of infor-

mation to a peripheral device. Two examples of interfaces that may require a synchro-

nized data transfer are a serial communications interface and a parallel printer interface.

Sometimes it is necessary as part of the I/O synchronization process first to poll an inputfrom an I/O device and, after receiving the appropriate level at the poll input, to acknowl-

edge this fact to the device with an output. This type of synchrsnization is achieved by

implementing what is known as handshaking as part of the input/output interface.Figure 10-5(a) shows a conceptual view of the interface between the printer and a

parallel printer port. There are three general types of signals at the printer interface: data,

control, and status. The data lines are the parallel paths used to transfer data to the printer

Transfers of data over this bus are synchronized with an appropriate sequence of controlsignals. However, data transfers can only take place if the printer is ready to accept data.Printer readiness is indicated through the parallel interface by a set of signals called sta-

fus lines. This interface handshake sequence is summarized by the flowchart shown inFig. l0-5(b)

The printer is attached to the microcomputer system at a connector known as theparallel printer port. On a PC, a 25-pin connector is used to attach the printer. Figure10-5(c) shows the actual signals supplied at the pins of this connector. Note that there are

five status signals available at the interface, and they are called Ack, Busy, Paper Empty,

Select, and Error. In a particular implementation only some of these signals may be used-For instance, to send a character to the printer, the software may test only the Busy sig-

nal. If it is inactive, it may be a sufficient indication to proceed with the transfer.Figure 10-6(a) shows a detailed block diagram of a simple parallel printer inter-

face. Here we find eight data-output lines, Ds through D7, control signal strobe (STB),

and status signal busy (BUSY). The MPU outputs data representing the character to beprinted through the parallel printer interface. Character data are latched at the outputs of

the parallel interface and are carried to the data inputs of the printer over data lines Dethrough D7. The STB output of the parallel printer interface is used to signal the printer

that new character data are available. Whenever the printer is already busy printing acharacter, it signals this fact to the MPU with the BUSY input of the parallel printer inter-face. This handshake signal sequence is illustrated in Fig. 10-6(b).

Let us now look at the sequence of events that take place at the parallel printeripterface when data are output to the printer. Figure 10-6(c) is a flowchart of a subrou-

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Input/Output Interface Circuits and LSI Peripheral Devices Chap. l0476

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tine that performs a parallel printer interface character-transfer operation. First theBUSY input of the parallel printer interface is tested. Note that this is done with apolling operation. That is, the MPU tests the logic level of BUSY repeatedly until it isfound to be at the not-busy logic level. Basy means that the printer is currently printinga character. On the other hand, not busy signals that the printer is ready to receiveanother character for printing. After finding a not-busy condition, a count of the numberof characters in the printer buffer (microprocessor memory) is read; a byte of characterdata is read from the printer buffer; the character is output to the parallel interface; andthen a pulse is produced at STB. This pulse tells the printer to read the character off thedata bus lines. The printer is again printing a character and signals this fact at BUSY.The handshake sequence is now complete. Now the count that represents the number ofcharacters in the buffer is decremented and checked to see if the buffer is empty. Ifempty, the print operation is complete. Otherwise, the character transfer sequence isrepeated for the next character.

The circuit in Fig. 10-6(d) implements the parallel printer interface in Fig.10-6(a).

EXAMPLE I0.5

What are the addresses of the ports that provide the data lines, strobe output, and busyinput in the circuit shown in Fig. 10-6(dX Assume that all unused address bits are 0s.

Solution

The I/O addresses that enable port 0 for the data lines, port 1 for the strobe output, andpott 2 for the busy input are found as follows:

Address ofport0 : 10000000000000002 : 8000re

Address of port 1 : 10000000000000102 : 800216

Address of port 2 : 10000000000001002 : 800416

EXAMPLE I0.6

Write a program that will implement the sequence in Fig. 10-6(c) for the circuit inFig. 10-6(d). Character data are held in memory starting at address PRNT_BUFF, andthe number of characters held in the buffer is identified by the count at addressCHAR_COUNT. Use the port addresses from Example 10.5.

Solution

First, the character counter and the character pointer are set up with the instructions

MOV CL, CHAR_COUNT

MOV SI, PRNT-BUFF, (cL) = character count

; (S I ) = charac ter po in te r

480 Input,/Output Interface Circuits and LSI Peripheral Devices Chap. l0

Next, the BUSY inpqt is checked with the instructions

POLL_BUSY: MOV DX, 8004H ;Keep pol l ing t i l1 busy = IIN AIJ, DX

3# ii;"oll,"The character is copied into AL, and then it is output to port 0:

LIOV AL, ISII ;Get the next characterMOV DX, SOOOHOUT DX, AL ;and output i t to port 0

Now, a sffobe pulse is generated At port 1 with the instructions

MOV AL, OOH ;STB- = 0MOV DX, BOO2HOUT DX, ALMOV BX, OFH ;Delay for STB duration

STROBE: DEC BXJNZ STROBEMOV AL, OLH ;Sre = 1OUT DX, AL

At this point, the value of PRNT_BUFF must be incremented, and the value of

CHAR-COUNT must be decremented:

fNC SI ;Update character counterDEC CL ;and pointer

. a

Finally, a check is made to see if the printer buffer is empty. If it is not empty, we needto repeat the prior instruction sequEnce. To do this, we execute the instruction

INZ POLL_BUSY ;Repeat t i11 al l characters;have been transferred

DONE:

The program comes to the DONE label after all characters are transferred to the printer.

A 1O.5 82C554 PROGRAMMABLEPERIPHERAL INTERFACE

The 82C55A is an LSI peripheral designed to permit easy implementation of parallel I/Oin the 8088- and 8086-microcomputer systems. It providos a flexible parallel interface,which includes features such as single-bit, 4-bit, and byte-wide input and output ports;

Sec. 10.5 82C55A Programmable Feripheral lnterface 481

level-sensitive inputs; latched outputs; strobed inputs or outputs; and strobed bidirectionalinput/outputs. These features are selected under software control.

A block diagram ofthe 82C55A is shown in Fig. 10-7(a) and its pin layout appea$in Fig. 10-7(b). The left side of the block represents the microprocessor'E intetface. ltincludes an 8-bit bidirectionql data bus D6 through D7. Over these lines, commands, sta-tus information, and data are transferred between the MPU and 82C55A. These data aretransferred whenever the MPU performs an input or output bus cycle to an address of aregister within the dwice. Tr@g of the data transfers to the 82C55A is controlled by theread/write control (RD and WR) signals.

The source or destination register within the 82C55A is selected by a2-bit registerselect code. The MPU must apply this code to the register-select inputs As and A, of the82C55A. The port A, port B, and port C registers correspond to codes AlAe : 00,ArAo - 01, and ArAo : 10, respectively.

Two other signals are shown on the microprocessor interface side of the block dia-gram. They are the reset (RESET) and chip-select (CS) inputs. CS must be logic 0 duringall read or write operations to the 82C55A. It enables the 82C55A s microprocessor inter-face circuitry for an input or output operation.

On the other hand, RESET is used to initialize the device. Switching it to logic 0 atpower-up causes the internal registers of the 82C55A to be cleared. Initialization config-ures all I/O ports for input mode of operation.

The other side ofthe block corresponds to three byte-wide I/O ports, ca)ledport A,port B, and port C and represent I/O lines PAq through PA7, PBg through PB7, and PC6through PC7, respectively. These ports can be configured for input or output operation.This gives us a total of 24 I/O lines.

We already mentioned that the operating characteristics of the 82C55A could beconfigured under software control. It contains an S-bit internal control register for thispurpose. The group A and group B control blocks in Fig. 10-7(a) represent this register.Logic 0 or I can be written to the bit positions in this register to configure the individualports for input or output operation and to enable one of its three modes of operation. Thecontrol register is write only and its contents can be modified using microprocessorinstructions. A write bus cycle to the 82C55A with register-select code A1A6 : 11, andan appropriate control word is used to modify the control registers.

The circuit in Fig. 10-8 is an example of how the 82C55A can be interfaced to amicroprocessor. Here we see that address lines A6 and A1 of the microprocessor drive the82C55A s register-select inputs A1 and 46, respectively. The CS input of the 82C55A issupplied from the output of the address decoder circuit whose inputs are address lines Azthrough A15 and IO/IVI. To access either a port or the control register of the 82C55A, CSmust be active. Then the code AlAo selects the port or conffol register to be accessed. Theselect codes are shown in Fig. 10-8.

Forinstance, toaccessportA,AlAo : 00,Ars : A14 : 1,Ar: : Atz: . . : Az: 0,which gives the port A address as

1 1 0 0 . . . . . 0 0 2 : C 0 0 0 1 6

Similarly, it can be determined that the address of port B equals C00116, that of port C isC00216, and the address of the control register is C00316.

442 Input/Output lnterface Circuits and LSI Peripheral Devices Chap. l0

FU

f * t f l g u ; ; d d o o o ' d d 1 8 f f f E " f

f f f r " lP182e6 t c 4 4 d r c 4 c o c

9 g B D S E S S S E E R R N R R F R S E

o

N@

F N o r o @ F o o 9 : g P : 3 9 : P g R

XEr \ g

Eb

ts. ;_ a= i

. Y Fa ^4 y' F *

F >ei -oa E> r A

# d

! ' t r! ) 0 .. F &. v

& a, ) '

< 5\ah Er \ ' FX Roa a^I - ;6E Ao 'E 9 9t r = P

bF?.I rl c)

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- i o he .E 6-

h UF 6 - - :- t o 6i i !

9 . 9 B5 E P,9D b -AIr o.(.

64

S R

4

v o

oE

X RI

e d- d

l al o

o

F

z

trg

66

> o6 z+ ( 9r tt tt l

oU

E'agEo: tL 6 lS lg { fb

uE

oI

o

J

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O E F Y

se68E ' ' ) J

483

MicroprocessorInterface

D z - D o

HD

WR

RESET

Fromthemicro-processoraddressbus

To Selecl

ro/M

Figure 10-8 Addressing an 82C55A using the microprocessor interfacesienals.

The bits of the control register and their control functions are shown in Fig. 10-9.Here we see that bits D0 through D2 correspond to the group B control block in the dia-gram of Fig. 10.7(a). Bit D0 configures the lower four lines of port C for input or outputoperation. Notice that logic 1 at Do selects input operation, and logic 0 selects outputoperation. The next bit, Dr, configures port B as an S-bit-wide input or output port. Again,logic 1 selects input operation, and logic 0 selects output operation.

The D2 bit is the mode-select bit for port B and the lower 4 bits of port c. It per-mits selection of one of two different modes of operation, called, mode 0 andmode l.Logic 0 in bit Dr selects mode 0, whereas logic 1 selects mode 1. These modes are dig-cussed in detail in subsequent sections.

The next 4 bits in the control registeq D3 through Du, correspond to the group Acontrol block in Fig. 10-7(a). Bits D3 and Da of the control register are used to configurethe operation of the upper half of port C and all of port A, respectively. These bits workin the same way as D6 and D, to configure the lower half of port C and port B. However,there are now two mode-select bits, Dr and D6, instead ofjust one. They are used to selectbetween three modes of operation, mode 0, mode l, and mode 2.

Al

&

ArsAtq

Arg

4

D z - D o

HD Port A82s5

WF

RESET PoTt

lE""tt"tR"$l

AlAo,eSPort A 0 0 , 0

484 Input,/Output Interface Circuits and LSI peripheral Devices Chap. | 0

flTFOt rciD

o, % % D! o r l o r %

J

/ n^ou" \

rcRrc |lmnll - | f f0. OwAn

rcnT3! r l P W0. OWPU

m€SELEdtOr0 . m € 0l. ilOO€ !

/ c^o*o

mnr c luftRlI - lilruT0 . m r

rcaral . l i l m0.OWM

ME SELECTIOXO . m E 00 r . r c D € !tX. reE 2

mE sEr tuct . rcTlV€

Figure 10-9 Control-word bitfunctions. (Reprinted by permission ofIntel Corporation. Copyright/IntelCorp. 1980)

The last control register bit, D?, is the mode-set flag. [t must be at logic 1 (active)whenever the mode of operation is to be changed.

Mode 0 selects what is called simple I/O operation. By simple I/O, we mean thatthe lines of the port can be configured as level-sensitive inputs or latched outputs. To setall ports for this mode of operation, load bit D7 of the control register with logic 1, bitsDoDs : 00, and Dz : 0. Logic 1 at D7 represents an active mode set flag. Now port Aand port B can be configured as 8-bit input or output ports, and port C can be configuredfor operation as two independent 4-bit input or output ports. Setting or resetting bits D4,D:, Dr, and Ds does this. Figure 10-10 summarizes the port pins and the functions theycan perform in mode 0.

For example, if 8016 : 100000002 is written to the control register, the 1 in D7 acti-vates the mode-set flag. Mode 0 operation is selected for all three ports because bits D6,D5, and D2 ure logic 0. At the same time, the zeros in D4, D3, D1, and D6 set up all portlines to work as outputs. Figure 10-11(a) illustrates this configuration.

By writing different binary combinations into bit locations D+, Ds, D1, and Do, anyone of 16 different mode 0 I/O configurations can be obtained. The control word and I/Osetup for the rest of these combinations are shown in Fig. I 0-l I (b) through (p).

Sec. f 0.5 82C554 Programmable Peripheral Interface 485

Pin

MODE O

IN OUT

PAoPAtPAzPA.P&PAuP&PAt

I NI NI NI NI NI NI NI N

OUTOUTOUTOUTOUTOUTOUTOUT

PBoPBtPB,PBsPBoPB,PBsPBt

ININI NINININININ

OUTOUTOUTOUTOUTOUTOUTOUT

PCoPCrPC,PC.PCaPCsPCoPCt

I NI NI NI NI NI NI NI N

OUTOUTOUTOUTOUTOUTOUTOUT Figure 10-10 Mode 0 port pin

functions.

EXAMPLE I0.7

What is the mode and I/O configuration for ports A, B, and C of an 82C55A after its con-trol register is loaded with 8216?

Sofution

Expressing the control register contents in binary form, we get

D7D6D5D4D3D2D1D6 : 100000102

Since D7 is 1, the modes of operation of the ports are selected by the control word. Thethree least significant bits ofthe conffol word configure port B and the lower four bits ofport C:

Do : 0 Lower four bits of port C are outputs.

Dr : 1 port B is an input port.

Dz : 0 Mode 0 operation for both port Band the lower four bits of port C.

486 Input/output lnterface circuits and Lsl peripheral Devices chap. l0

cot{TRot rroFo #0

oofrTRoL wonD *tq o . q o . D !

oof{lRol tYoRo *2

O(XTROL fi'RO lr3

| } % % D r D r

Upper four bits ofport C are outputs.

PortA is an output port.

Figure 10-11 (a-p) Mode 0 control words and corresponding input/output config-urations. (Reprinted by permission of Intel Corp. Copyright/Intel Corp. 1980)

The next four bits configure the upper pafi of port C and port A:

D r : 0

D + : 0

D6Dr : 96 Mode 0 operation for both portA and the upper part ofport C.

Figure 10-11(c) shows this mode 0 I/O configuration.

Mode 1 operation represents what is known as strob;d I/O. The ports of the

82C55A are put into this mode of operation by setting Dz : 1 to activate the mode-setflag and setting DoDs : 01 and Dz : 1.

A

82C55A

TIc 1L

I

A

82C55A

rI

c lL

I

0 0 o 0 0 I I

A

82C55A

fc l

a

A82C554

rc -.1

IL

a

Sec. 10.5 82C55A Programmable Peripheral Interface 487

sraot rciD fr

o, D. o. or or D, or o.

r l o l o l o l r l o l o l r

@xtRol wonDfr

o, o. D6 o. Dr o, ot on

r l 0 l o l 0 l r l 0 l r l 0

ffiorwGos

@URO[ WOFD :t0

o, oa o, o. D, 02 D' oo

l l o l o l r l o l o l r l o

coxlBot mo *tl

D , D . Q D . O r O r D r D n

r l 0 l o l t l 0 l 0 l r l !

1 f o . % D . D l 0 2 o i D o

q % q o . o r o r D i o o

Figure 10-11 (continued)

OONTFOL WOFD #14

D, D€ DE Oa D3 D2

@NTROL WORD f15

o, oa Dr D. D3

Figure 10-11 (continued)

In this way, the A and B ports are configured as two independent byte-wide I/Oports, each of which has a 4-bit control/data port associated with it. The controVdataports are formed from the lower and upper nibbles of port C, respectively. Figure 10-12lists the mode 1 functions of each pin at ports A, B, and C.

When configured in this way, data applied to an input port must be strobed in witha signal produced in external hardware. An output port in mode 1 is provided with hand-

shake signals that indicate when new data are available at its outputs and when an extef-

nal device has read these values.As an example, let us assume for the moment that the control register of an 82C55A

is loaded with DrD6DrD4D3D2D1Dg : 10111XXX. This configures port A as a mode 1input port. Figure 10-13(a) shows the function of the signal lines for this example. Notethat PAt through PAe folm an 8-bit input port. On the other hand, the function ofthe upper port C lines are reconfigured to provide the port A controVdata lines. The PCaline becomes strobe input (STBJ, which is used to strobe data at PA7 through PAe into

0 0 I I 0 o

82C55A

tc - l

L

I

82C55A

TI

c J

L

B

I 0 o I I 0 0

82C554

tI

c l

L

B

A

82C55A

fc l

L

a

Sec. 10.5 82C554 Programmable Peripheral Interface 489

Pin

MODE 1

IN OUT

PAoPArPAzPAsP44PAuP&PA,

I NI NI NI NI NI NI NI N

OUTOUTOUTOUTOUTOUTOUTOUT

PBoPBrPB,PB.PBoPBsPBoPBt

I NI NI NI NI NI NI NI N

OUTOUTOUTOUTOUTOUTOUTOUT

PCoPCrPCzPC.PCoPCsPCePCt

INTRB-IEESTBBIN_BoSTBAIBFAt/ovo

!t\1_I8tOBFBACKBINTBAvovo

ACKA,OBFA

Figure 10-12 Mode I port pinfunctions.

the input latch. Moreover, PCs becomes input buffer ful/ (IBFJ. Logic 1 at this outputindicates to external circuitry that a word has already been strobed into the latch.

The third control signal is at PC3 and is labeled interrupt request (INTRJ. Itswitches to logic 1 when STBA : 1 making IBFa : l, and an internal signal interruptenable (INTEJ : 1. INTEa is set to logic 0 or 1 under software control by using the bit

ooittRol woRo OOI{?ROL HORD

Figure 10-13 (a) Mode 1, port A input configuration. (Reprinred by permission of Intelc_orporation. copyright/Intel corp. 1980) (b) Mode l, port A ouput configuration.(Reprinted by permission oflntel Corporation. Copyright/Intet Corp. ilaO)

MODE r (POFTA)

: rinE !i a i

MOOE r (POFTA)

r - - II tf{tE It A l

490 lnput,/Output Interface Circuits and LSI peripheral Devices Chap. | 0

set/reset feature of the g2c55A. This feature will be discussed later. Looking at Fig.10-13(a), we see that logic 1 in INTEa enables the logic level of IBF^ ro the INTRa out_put' This signal can be applied to an intemrpt input of the Mpu to signal it that new dataare available at the input p_ort. The corresponding intemrpt-service ,oirtin" reads the data,which clears INTRA and IBF^. The timing diagram in Fig. l0-r4(a) summarizes theseevents for an input port configured in mode 1.As another example, let us assume that the contents of the control register arechanged to D7D6D5DaD3D2D1D0 : 10100XXX. This I/o configuration is shown in Fig.10-13(b). Note that port A,is now configured for output op"ruti"on i^t"ao of input oper_

?ti::' ftl Pgh PAo ma.ke u.r the- g-bit outpur porr. The control rine at pc7 is outputbuffer full (OBFJ. when data have been written into the output port, oBF4 switches tothe 0 logic level' In this way, it signals extbrnal circuitry that new data arcavailable at theoutput lines.

(b)

Figure 10-14 (a) Timing diagram lor an.inprl! nort in mode r configuration. (Reprintedby permission of Intel corporition. copyrigtrvtriiei corp. r9g0) (b) Timing diagram fbran output port in mode 1 configuration. (Riprinted uy iermrssion oi roi"i"io.po.utron.Copyright/Intel Corp. 19g0)

Sec. 10.5 9ZC5iA programmable peripherat Interface 491

Signal line PC6 becomes acknowledge leCf;. which is an input. An externaldevice reads the data and signals the 82C55A that it has accepted the data provided atthe output port by switching ACKalq logic 0. When the ACKa : 0 is received by the82C55A, it in turn deactivates the OBFa output. The last signal at the control port isthe interrupt request (INTRf output, which is produced at the PC3 lead. This output isswitched to logic 1 when the ACKa input becomes inactive. It is used to signal the MPUwith an intemrpt that indicates that an external device has accepted the data from the out-puts. To produce the INTRa, the intemrpt enable (INTEJ bit must equal 1. AgainINTEA must be set using the bit set/reset feature to write a 1 to PC6. The timing diagramin Fig. 10-14(b) summarizes these events for an output port configured in mode 1.

EXAMPLE IO.8

Figures 10-15(a) and (b) show how port B caa be configured for mode 1 operation.Describe what happens in Fig. 10-15(a) when the STB' input is pulsed to logic 0.Assume that INTEg is already set to 1.

Solution

As STB3 is pulsed, the byte of data at PB7 through PB6 is latched into the port B register.This causes the IBF" output to switch to 1. Since INTEB is 1, INTR' switches to logic 1.

The last mode of operation, mode 2, represents what is known as strobed bidirec-tional I/O. The key difference is that now the port works as either inputs or outputs andcontrol signals are provided for both functions. Only portA can be configured to work inthis way. The I/O port and control signal pins are shown in Fig. 10-16,

To set up this mode, the control register is set to D7D6D5D4D3D2D1Dg :

llXXXXXX. The I/O configuration that results is shown in Fig. 10-17. Here we findthat PA7 through PA6 operate as an 8-bit bidirectional port instead of a unidirectional

CONTROL WOf,D

07 06 06 o. 03 D2 D1 oO

Figure 10-15 (a) Mode l, port B input configuration. (Reprinted by permission of IntelCorporation. Copyright/Intel Corp. 1980) (b) Mode 1, port B output conflguration.(Reprinted by permission oflntel Corporation. Copyright/Intel Corp. 1980)

MODE I (PORT B)

ooitTRoL wonD

D, 0a D! D. Or

MODE 1 (PORT B)

r INTE Ir B lL " - - J

492 Input/Output Interface Circuits and LSl Peripheral Devices Chap. | 0

Pin

MODE2

GROUPAONLY

PAoPArPAzPA:PA,PAsPAoPA"

.e

<-->

<---->

€.e

<__->

<---->

<:---->

PBoPBrPBzPB:PB+PBsPBoPB"PCoPCrPCzPC:PC"PCsPCoPCt

UO orINTRgVO or OBF3 or IBF3VO or AC-Kg orSTBs

UlRosrBAEI"495"OBF^ Figure 10-16 Mode 2 port pin

functions.

MODEOORMODE 1ONLY

port. Its control signals are OBFA at PC7, ACKA at PC6. Sfno at pC4, IBFA at pC5, andINTRA at PC3. Their functions are similar to those already discussed for mode 1. Onedifference is that INTRa is produced by either gating oBFa with INTE, or IBFA withINTE2.

In our discussion of mode 1, we mentioned that the bit set/reset feature could beused to set or reset the INTE bits. For instance, to enable INTRA for port A as output, pCa

EF^

Figure 10-17 Mode 2 input/oulputconfiguration. (Reprinted bypermission of Intel Corporation.Copyright/Intel Corp. 1980)

E-f^

Sec. 10.5 82C55A Programmable Peripheral lnterface 493

Figure 10-18 Bit set/reset foimat.(Reprinted by permission of IntelCorporation. Copyright/Intel Corp.1980)

should be set to make INTE2 (dotted box next to PCa in Fig. 10-17) logic 1. The bitset/reset feature also allows the individual bits of port C to be set or reset. To do this, wewrite logic 0 to bit Dt of the control register. This resets the bit set/reset flag. The logic

. level that is to be latched at a port C line is included as bit Do of the control word. Thisvalue is latched at the I/O line of port C, which corresponds to the three-bit code atD3D2D1.

The relationship between the set/reset control word and input/output lines isillustrated in Fig. 10-18. For instance, writing D7D6D5D4D3D2D1D0 : 000011112 into thecontrol register of the 82C55A selects bit 7 and sets it to 1. Therefore, output PC7 at portC is switched to the 1 losic level.

EXAMPLE I O.9

The intemtpt-control flag INTEa for output port A in mode 1 is controlled by PC6. Usingthe set/reset feature of the 82C55A, what command code must be written to the controlregister of the 82C55A to set it to enable the control flag?

Solution

To use the set/reset feature, D7 must be logic 0. Moreover, INTEA is to be set; therefore,Ds must be logic 1. Finally, to select PC6, the code at bits D3D2D1 must be 110. The restof the bits are don't-care states. This gives us the control word

D7D6D5D4D3D2D1D9 : 0XXX1 1012

Replacing the don't-care states with the 0logic level, we get

D7D6D5D4D3D2D1D9 : 000011012 : ODro

We have just described and given examples of each of the modes of operation thatcan be assigned to the ports of the 82C55A. It is also possible to configure the A and Bports with different modes. For example, Fig. 10-19(a) shows the control word and port

494 Input/Output Interface Circuits and LSI Peripheral Devices Chap. l0

MODE 2 AND MODE O ( INPUT)

PC:

PA7-PAo

PC-r

PCo

PC,

0a, - 5

Pc2 'o

P87 - PBo

DoD7

CONTROL WORD

D6 Ds D4 03 D2 D1

PCz'o

oBFA

ACKA

5i€-o

IBFA

VOI = INPUT0 = OUTPUT

D7

R D

WR

coNTRO|'.WORD

D6 D5 D4 D3 D2

RD

WR

INTRA

d6Fo

AeKA

mA

IBFA

O_E'FB

TER,

INTRB

(b)

Figure 10-19 (a) Combined mode 2 and mode 0 (input) contro-l word T{I/gco"nfiguration. (Reprinted by permission of Intel Corporation. Copyright/IntelCorpl tlSOl (b) Combined mode 2 and mode 1 (output) control word *9-I/gconhguration. (Reprinted by permission of Intel Corporation. Copyright/IntelCorp. 1980)

MODE 2 AND MODE 1 (OUTPUT)

PCg

PA7 - PAo

PC,

PCe

PCq

PCs

PB7 - PBo

PCr

PCz

PCo

I o l

495

configuration of an 82C55A set up for bidirectional mode 2 operation of port A and inputmode 0 operation of port B. It should also be noted that in all modes, unused pins of portC are still available as general-purpose inputs or outputs.

EXAMPLE I O.I O

What control word must be written into the control register of the 82C55A such that portA is configured for bidirectional operation and port B is set up with mode I outputs?

Solution

To configure the operating mode of the ports of the 82C55A, D7 must be 1:

D z : 1

Port A is set up for bidirectional operation by making D6 logic 1. In this case, D5 throughD3 are don't-care states:

l

D o : 1

D5D4D3 : XXX

Mode I is selected for port B by logic 1 in bit D2 and output operation by logic 0 in D1.Since mode I operation has been selected, Ds is a don't-care state:

D z : -

D r : 0

D o : X

This gives the control word

D7D6D5D4D3D2D1D9 : I 1XXX1OXz

Assuming logic 0 for the don't-care states, we get

DzD6D5D4D3D2D1Dq : 110001002: C46

This configuration is shown in Fig. 10-19(b).

EAMPLE I O.I I

Write the sequence of instructions needed to load the control register of an 82C55A withthe control word formed in Example 10.10. Assume that the control register of the82C55A resides at address 0F16 of the I/O address space.

496 Input/output Interface circuits and LSt peripherat Devices chap. l0

Solution

First we must load AL with C416. This is the value of the control word that is to be wdt-ten to the control register at address 0F16. The move instruction used to load AL is

MOV AL, OC4H

These data are output to the control register with the OUT instruction

OUT OFH, AL

Because the I/O address of the control register is less than FF16, this instruction usesdirect I/O.

In our descriptions of mode 1 and mode 2 operations, we found that when the82C55A is configured for either of these modes, most of the pins of port C perform I/Ocontrol functions. For instance, Fig. 10-12 shows that in mode I PC3 works as the INTR4output. The MPU can be programmed to read the control information from port C throughsoftware. This is known as reading the status of port C. The format of the status informa-tion input by reading port C of an 82C55A operating in mode 1 is shown in Fig. I0-20(a).Note that if the ports are configured for input operation, the status byte contains the val-ues of the IBF and INTR outputs and the INTE flag for both ports. Once read by theMPU, these bits can be tested with other software to control the flow of the program.

lnput configuration

D7 D6 D5 D4 D3 D2 D1 Do

Group A Group B

,.. Output contigurations

D6 D5 D4 D3 D2 D1

Group A Group B

DoD7

(a)

DoDlD2D3D,D5D6D7

OBFI INTEl tBFAtNTE2 NTRA

Group A Group B

(Defined by mode 0 or mode 1 selection)

(b)

Figure 10-20 (a) Mode I statusinformation foi port C. (Reprinted bypermission of Intel Corporation.Copyright/Intel Corp. 1980) (b) Mode2 status information for port C.(Reprinted by permission of IntelCorporation. Copyright/Intel Corp.1980)

vo vo IBFA INTEA INTRA INTEB IBFB INTRB

oBFoINTEAvo VO INTRA INTEB5-er,INTRB

Sec. 10.5 82C55A Programmable Peripheral lnterface 497

By using a software handshake sequence that tests the status bits to change the pro-

gram sequence, hardware signals such as intemrpts can be saved. For instance, if port A

is used as an input in mode 1, the processor can read (poll) the status register and:check

bit D3 for INTRA. If D3 is 1, INTRA is active and the processor is signaled to read the data

from port A of the 82C55A. In this way, the INTRA output may not be connected to the

processor and one intemrpt request input is saved.

If the ports are configured as outputs, the status byte contains the values of outputs

OBF and INTR and the INTE flag for each port. Figure 10-20(b) shows the status byte

format for an 82C55A configured for mode 2 operation.

A 10.6 82C55A IMPLEMENTAIION OF PARALLELINPUT/OUTPUT PORTS

In Sections lO.2 and 10.3, we showed how parallel input and output ports can be imple-

mented for the 8088- and 8086-microcomputer systems using logic devices such as the

74F244 octal buffer and 74F373 octal latch, respectively. Even though logic ICs can be

used to implement parallel input and output ports, the 82C55A PPI can be used to design

a more versatile parallel I/O interface. This is because its ports can be configured either

as inputs or outputs under software control. Here we will show how the 82C55A is used

to design isolated parallel I/O interfaces for 8088- and 8086-based mibrocomputers.

The circuit in Fig. 10-21 shows how PPI devices can be connected to the bus of the

8088 to implement parallel input/output ports. This circuit configuration is for a minimum-

mode 8088 microcomputer. Here we find a group of eight 82C55A dpvices connected to

the data bus. A 74FI38 address decoder is used to sdlect one.of the devices at a time for

input and output data transfers. The ports are located at even-address boundaries. Each of

these PPI devices provides up to fhree byte-wide ports. In the circuit, they are labeled port

A, port B, and port C. These ports can be individually configured as inputs or outputs

through software. Therefore, this circuit is capable of implementing up to 192 I/O lines.

Let us look more closely at the connection of the 82C55As. Starting with the

inputs qlllk 74FI38 address decoder, we see that its enable inputs are G2s :Ae and

Gzl : IO/M. A0 is logic 0 whenever the 8088 outputs an even address on the bus' More-

over, IO/I4 is switched to logic 1 whenever an I/O bus cycle is in progress. This logic

level is inverted and applies logic 0 to the G2a input. For this reason, the decoder is

enabled for all I/O bus cycles to an even address.

When the 74FI38 decoder is enabled, the code at its Aq through ,{2 inputs causes

one of the eight 82C55A PPIS attached to its outputs to get enabled for operation. Bits ,{5

through 43 of the I/O address are applied to these inputs of the decoder. It responds by

switching the output corresponding to this 3-bit code to the 0 logic level. Decoder outputs

Oe through 07 are applied to the chip select (CS) inputs of the PPIs. For instance,

A5A4A3 : 000 switches output Oe to logic 0. This enables the first 82C55A, numbered 0

in Fig. I0-2LAt the same time a PPI chip is selected, the 2-bit code A2A1 at its inputs AlAs selects

the port for which data are mput or output. For example, AzAr : 00 indicates that port A

is to be accessed. Input/output data transfers take place over data bus linelPo through D7.

The timine of these read/write transfers is controlled by signals RD and WR.

498 Input/Output Interface Circuits and LSl Peripheral Devices Chap. l0

?

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!

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A5

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cs

Do-Dr

82C55A

4!RD\\R-

: r"nA

iiiit_i

IiB re 10-21 82C55A parallel I/O ports jn an 8088-barcd microcomputer

EXAMPLE 10.12

ftat must be the ad&ess bus inputs of the circuit in Fig. 10-21 if port C of PPI 14 is to

SolutionTo enable PPI 14, the 74F138 must be enabled for opemtion and its O? output switchedto logic 0. This requires enable input GrB = 0 and chip select code CBA : 111. This irtum rcquires ftom the bus that

An = 0to enable 74F138

AsAaA3 = 111to select PPI 14

sec. lU.6 a2c55A lmprememation or Pararlel Input/Output Pors 499

Port C of PPI 14 is selected with ArAo : 10' which from the bus requires that

A'?Ar = 10

The rest of the address bits are don't-care states

EXAMPLE I O.I3

Assume thal. in Fig. 10-21, PPt 14 is configured so that pon A is an output pof' botb ports

B and C are input ports, and all three ports are set up for mode 0 oPeration write a pro'glam that will input the data at polts B and C, fnd the difference (po.t C) - (port B)' and

output this difference to port A.

SolutionFrom the ctcuit diagam in Fie. 10 21, we find that the addrcsses of the thee I/O ports

of PPI 14 are

Port A address : 00111000, = 3816

Port B address = 00111010,:3A16

PotC addrcss = 00111100, = 3Cr6

The data at ports B and C can be input with the instruciion sequence

IN AI,, 3Alj ;REAd POI! B

. MOv BL/ al, ;Save data from Polt B

rN AL, 3Cl{ ;Read Port c

Now the data from po{ B are subtracted from ihe data from port C with the instuction

SUB al,, Bi, ;Sllrtract B flon C

Finallt tk; difference is output to port A with the instruction

Ot'! 38H, Al, ;wrile to Port A

Figue 10-22 gives a similar circuit that implements Parallel input/output ports fora minimurn mode 8086-based microcomputer system. l€t us now look at the differencesbetween this circuit and the 8088 ,microcomputer circuit shown in Fig. 10-21. In Fig.10-22, we find that the l/O circuit has two gmups of eight 82C55A devices; one connected to the lower eight daia bus lines, and the other to the upper eight data bus lines.Each of these groups is capable of implementing up io i92 I/o lines to dive a total I/ocapabiliry of 384 I/O lines.

5OO lnput/Outpr.t Interlace circuits and tsl Peripheral Devices ChaP l0

6

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DrDz

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ilr-Figm l{L22 82C55A paralel l/O pons at sen- and odd-aoldrelJ bounduies in anE086-ba*d microcomDDter.

501

Each of the groups of 82C55As has its own 74F138 I/O address ilecoder As ithe 8088 microcomputer circuil, the address decoder is used to select devices in a grqt

on€ at a time. The porc in the uppe. group are connect€d at odd-address boundaries dthose in the lower group aie at even-address boundaries. Let us iirst look more closely athe connection of the upper goup of the 82c55As. starting with lhe inp{s of the 74F13decodet we see that its G2B input is al ven by control signal BHE, the GzA input is s{Fplied by connol signal M{O, and the Gr input is pemanently enabled by fixing it ar dE1 logic level. BHE is logic 0 whenever fte 8086 outputs an odd ad&ess on the bus MorE-over M,{O is switched to logic 0 whenever an I/O bus cycle is in plogress. In this way,we see that the upper decoder is enabled for I/O bus cycles that access a b'te of dara ian odd I/O address. Actualt it is also enabled during all word-wide I/O data accesses

The code or address lines,Ae ttuough A5 selects one of the eight 82C55As lbr oP€f,-ation. Wlten the upper 74F138 is enabled, the address code applied at the CBA inPubcauses the corresponding output lo switch to logic 0. This ouiput is used as a chip sel€ct(CS) input to one of the 82C55As and embles it for inpuvoutput operation. The port thaiis accessed in the enabled PPI is selected by the code on lines Ar and A, of the UOaddrcss. Finally, the I/O data transfer takes place over data bus lines Ds through Drs.

The connection of the lower goup of PPIS in Fig. 10 22 is similar to that shown inFigl0 2i. The onry difference is that no invefter is rcquired in the connection of lheM O signal to the G,A input of the ?4F138 decoder This bank is enabted for a b)tewide data accesses to an even address as well as for all word wide data accesses.

iO,7 MEMORY-MAPPED INPUT/OUTPUT PORTS

T\e nemory-mapped I/O intedace ol a nirnmu]J.-mode 8088 system is essentially thesame as that employed in tbe accumulator I/O circuir of Fig. 10 21 . Figue 10 23 showsrhe equivalent memory-mapped circuit. Ports are siill selected by decoding an address onthe address bus, and data are tEnsferred between the 8088 and I/O device over the databus. One difference is that now the tull 20-bit address is available for addressing VO.Therefore, memory mapped I/O devices can reside anywhere in the lMbyte memoryaddress space of the 8088.

Another difference is thai du.ing UO operations memory read and write bus cyclesare initiated iNtead of I/O bus cycles. This is because memory instructions, not inpuvoutput instructions, are used to perform the data transfers. Furlhemore, IO,IM stays at the0 logic level thmughout ihe bus cycle. This indicates that a memory opemtion, rot an I/Ooperation, is in Progress-

Since memory-mapped I/O devices rcside in the memory address space and areacc€ssed wirh read and wnre clcles. addjrional I/O addre.. larch. address buffer. data bu.transceiver, and ad&ess decoder circuitry are not needed. The circuitry govided for thememory interface can be used 1o access memo.y-mapped polts.

The key difference betwe€n the cncuits in Figs. 10-21 and 10-23 is that IO,4\4 is nolonge. inverted. Instead, it is applied direcrly to the G,A inpul of the decoder. Another dif-ference is that the Gr input of the decoder is not fred at the I logic levelinstcad, it issupplied by address line Ar0. The I/O circuits are accessed whenever IO/M is equal tologic 0, Ar0 is-equal to togic 1 , and A0 equals 0.

5|)2 lnput/Output Interface ClrcujB and LSI Peripheral Oevices Chap. l0

+4

ac- 74t138

G^Gr

Do_Dz

82C55A

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HrT#-" Menorv-mapped 82c55A paraltel I/o ports in e 8088 ba$d micfo-

EXAMPLE IO.I +

Wlich l/O port in Fig. t0 2j r. letected for operalion $hen rhe memory addre(s ourpuron the bus is 00a02,6?

SolutionWe begin by converting rhe address ro binary form. This gives

Ale. . . A,A0 = 00000000010000000010,

In this address, bits Ar0: landA,{:0. Thereforc. the 74F138 address decoder isenabled whenever IOd = 0, which is the case during memory operations.

sef. 10.7 Memory.Mdpped Inout/Ourput pons 503

A memor'/-mapped I/O operation takes place at ihe port selected by &A4A3 : 000'

This input code switches decoder output O0 to logic 0 and chip sele€ts PPI 0 for opera-

tion. That is,

and selects PPI 0.The address bits applied to the port select inputs of the PPI aft ArAr = 0t These

inputs cause polt B to be accessed. Thus, the adalress 00{0216 selects port B on PPI 0 for

memory-mapped I/o.

EMMPLE IO. I5

I-ower half of port C as inPut

Port B as input

Mode 0

Upper half of port C as input

Port A as oulput

Mode 0

Mode setflag active

From the circuit diagram, the memory address of the control register for PPI 0 is foundto be 00000000010000000110, = 0040616. since PPI 0 is memory mapped' the follow-ing move instructions can be used to initialize the control register:

oo=o

Write the s€quence of instructions needed to initialize the control register of PPl0 in the

circuit of Fig. 10-23 so that port A is an output port, ports B and C are input ports, and

all tbree ports are configlred for mode 0 operation

SolutionRefening to Fig. l0 9, we find that the contol byte required to provide this conligu-

MOV AL, 0MOV DS, AX

MOV t 40 6!al , Ar

;Create data seqnenl a! 00000H

;Load AL with control bytej h l i E e c o n - r o l o r , c e E o D D 0 c o n L t o l r e g i s - e -

10001011 r : 88 ,6

504 lnput/Output Interface Circuits and Lsl PeriPheral Devices chap. lo

EXAMPLE IO.I6

Assume that PPI 0 in Fig. 10-23 is configued as descdbed in Example 10.15. wdte aprcgram tbat will input the contents of ports B and C, AND them togethe! and output the

SolutionFrom the circuit diaglam, we find that the addresdes of the tbree I/O ports on PPl0 are

PoIt A address = 0040016

PortB addrcss = 0040216

Port C address:00404,6

Now we set up a dara segment at 0000016 and input the data from ports B and C:

MOv BL, [402H] ;Read por ! BMOv Ar, [404H] ;Read por t C

Next, the contents of AL and BL must be ANDed and the result output to port A. This isdone with the instructions

MOV AX, 0MOV DS, AX

AND AII, BLMOV l400Hl , A !

;create data seqnent at 00000H

;aND data at ports B dd c

;W!i!e to Port A

Figure l0 24 shows a memory-mapped palallel I/O inteface circuit for an 8086-based misocomputer system. Just like the accumulator mapped circuit in Fig. 10-22, thiscircuit is capable of implementing up to 384 palalel l/O lines.

A IO.8 82C54 PROGMMMABLE INTERVAL TIMER

'The 82C51 is an LSI peripheral deslFed to permit easy implementation of ttmrr andcounter functions in a mlqocomputer system. Il contains tbree independent 16-bit coun-ters that can be pograrDmed to operate in a variety of ways to implement tining func-tions. For instance, they can be set up to work as a one-shot pulse generator, square-wavegenerato! or rale genefator

Block Diaqram of the 82C54

Let us begin our study of the 82C54 by looking at the signal interfaces shown in itsblock diagam of Fig. 10-25(a). The actual pin location for each of these signals is given

Sec. 10.8 82C54 Drogranmabre lntervdl llmer 505

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FiSur€ 10-24 Memory malped 82C55A pala el I/O pons in an 8086-based nicro'

506

risure 10-25 (a) Bl@k diagan ofrhe 82C54 inteNal rimei (b) Pinlayou!. (Repiinted by permission ofIntel Corporatio!. cop)right/Intelcorp. 1987)

in Fig. 10-25(b). In a nicrocomputer system, the 82C54 is treated as a peripheral deviceMoreover, it can be memory-mapped into the memory adakess space or l/O-rnapped intothe I/O address space. The microprocessor interface of the 82C54 allows the MPU to readfrom or wriae into its intemal .egisters. In this way, it can be configwed in various modes

Now we wil look at lhe signals of ihe miooFocessor inteface. The microproces-sor inierface includes an 8-bit bidirectionat dala bus, D0 ilrough DT It is over these linesthat data are transfened between the MPU and 82C54. Register address inputs Ao and A1are used to select the register to be accessed, and control signals read (RD) and wriG (WR)

indicate whether it is to be read from or wdtten into, respectively A chip-select (CS)

inpui is also Fovided to enable the 82C54\ mic.oprocessor interface. This input allowsthe designer to locate the device at a specific memory or I/O ad&ess.

sec. lo.8 82C54 Programmable IntervalTlmef so,

At the other side of the block in Fig. 10-25(a), we find rhrce signals for eachcounter. For instance. counter 0 has two inputs that are labeled CLK! and GATE0. Pulsesapplied to the clock input are used to decrement counter 0. The gate input is used toenable o. disable the counter GAIEo must be switched to logic I to enable counter 0 foropemtion. For example, in the sq\rare wave mode of operation, the counter is to run con-tinuously; therefore, GAIEo is fixed at the 1 logic level, and a continuous clock signal isappliert to CLKo. The 82C54 is rated for a maximum clock fieqrency of 10 MHZCounter 0 also has an outpur line lhat is labeled OUTo. The counter produces either aclock or a pulse at OUTo, dep€nding on the mode of operation selected. For instance.when configured for lhe square wave mode of operation, fiis outrut is a ciock signal.

Architecture of the 82c54

Figure 10-26 shows dre intemal architecture of the 82C54. Here we find the dardbus buffe. read/it rite logic, contrcl ||ord rcgister, ar,d th-ree courtrru. The data bus bufferand read/write control logtc reFesent the microprocessor interface we just described.

The control word register section actually coniains ibIee 8-bit registeN used to con-figure the operation of counten 0, I , and 2. The formai of a cdt zl d/ is shown in Fig.10-27. Here we find that the two most significant bits are a code ihat assigns the conilolwod to a counter. For instance, making fhese bits 01 selects counter 1. Bits Dr tkoughD1 are a 3-bit mode-select code, M,MrMo, which selects one of six nodes of counteroperaLjon. The leair . ipni f icdnr bi l D0 i . labeled BCD and.eleLrs e| |her brna4 or BCDmode of counting. For instance, if this bii is set ro logic 0, rhe counter acts as a 16-bir

Figure 10'26 Intemal dchitecture ofrhe 82C54. (Relrilred by lemisionof Intel Corporation. Co!]righvlntelCorp. 1987)

504 Input/Ourpur Inrerrace CrrLurts .ind L.)l Peflpherdl Devrces Chap. i0

BCD

D, D6 D5 DI D3 D2 DI DO

01

1

Blnary cod.d d@imal (BCO) counier

Flgurc 10-27 Contiol word fomatof tle 82c54. Geprinred bypermission of Intel Corporadon.Cop)'righ/Intel Coip. 1987)

binary counter. Finaly, the 2-bit code Rw,ryr'r RWwo is used to set the sequence in whichbytes are read fton or loaded into the 16 bit count registers.

EMMPLE I0.17

An 82C54 receives the control word 10010000r. mat configuration is set up for the timer?

SolutionSince the SC bits are 10, the rest of the bits are for setting up the configuration ofcounter 2. FollownE the fonnat in Fig. 10 27, we find ihat 01 in the RW/W bits setscounter 2 for the read/write sequence identified as the least signiicanr byte only. This

00 Read/w.ite mon sisnifi@d by@ only

R@d/wrhB le.d liqniJic.nt bvte 6n y

Read/wrie lern dqnilic.nt bvbli.n,then mct siqn ifioan t byis

sec. 10.8 82C54 Progrdmmable Interval llmer JO9

means that the next wrjte opemtion perfomed to counter 2 will load the data into the leasrsignificant byte of its count register Next the mode code is 000, and rhis selects mode 0operation for this counter. The last bit, BCD, is also ser ro 0 and selects binary counring.

The three counteN shown in Fig. 10 26 are each 16 birs in length a.nd operare as dolrncor,?t?,'s. That is, when enabled by an active gate input, r}le clock de.rements the count. Eachcounter contains a 16-bit cdrn r€gtrr€r that must be loaded as part of tlle initiatization cycle.The value held in the count register can be read at any time tkough softwarc.

To read from or write to the counlers of the 82C54 or load its conrol word registetthe micmproc€ssor needs to execute instructions. Fig e i0-28 shows the bus-conlrolinformation needed to access each register For example, ro write to the control rcgistetfie register addre" line' mu\r be A An = l dnd rhe conlrol LiDe. mu.l be wR = 0.R D : 1 . a n d C S = 0 .

EXAMPLE IO. I8

W.ite an instruction sequence to set up the tbree counren of rhe 82C54 in Fig. 10 29 asfollows:

Counter 0: Binary counter operating in mode 0 with an initial value of 1234H.

Counter 1: BCD counter operating in mode 2 with an initiai value of 0100H.

Counter 2: Binary counter operating in mode 4 with an initial value of IFFFH.

SolutionFirst, we need ro derermine the base address of the 82C54. The base address. which isalso the address of counrer 0, is deremired with ArA0 set to 00. In Fig. 10-29 we findthat to setect the 82C54, aS nust be iogic 0. This requires thai

ArrA,4. . . A7A6L5. A, : 00000000010000,

cg F wF-0 0 00 o o0 0 1 o0 0 10 0 1 0 00 0 I 00 0 1

0 0 I Nlop€Etion (s€rare)1 x x No.Op€r6tion (3-Sbl€)0 x

Figure 10-24 Accessing thereSlsteB of the 82c54. (Reprinted bypermission of Intel corporation.Copyri8hvlnrel Corp. 1987)

5to lnput,/Output Interlace Circuits and Lsl Peripheral Devices Chap. lO

rigure lo-29 Microprocessor interface for th€ 82C54.

Combitring this part of rlle address with the 00 at ArAo, gives the base address as

0000000001000000: = 40H

Since the base address of the 82C54 is 40H, and to select the mode register requiresArAo = 11, i1r **""" s 43H. Similarly, the tbree counten 0, I, and 2 are at addresses40H, 4lH, and 42H, respectively. Let us first determine the mode words foi the threecounters. Following the bit defniiions in Fig. lo-n, we get

TOFiow

Mode word for count€r 0 = 00110000, : 3016

Mode word for counter I : 01010101, : 5516

Mode word for counter 2 : 10111000, = 8816

82C54 Programmable Interual Timersec. l0.a 5 t I

The following instruction sequence can be used to set up the 82C54 with the desiredmode words and counts:

MOV AI], 3OEOUT 43H, ATMOV AL, 55Houl 43H, Ar-MOV A!, OBSHOUT 43H, AI]MOV AI,, 1234HOIJT 4OH, 'I,MOV Ar-, 12HouT 40H/ AI!MOV AL, 0100ItOUT 41H, ALMOV AI,, O1HouT 41t{, ALMOV AIJ, 1FFFHoIlT 4214, 4!MOV AIJ, lFHOUT 42H, AI-

;Set up coute! 0 mode

;set up counlet 1 node

;set up counte! 2 node

;h i l ia1 lze couter 0 v i rh 1234r{

; I4 i t ia l i ze coun le ! l w i th 0100H

; In l l ia l i ze coEtse ! 2 s i th 1FFFH

Earlier we pointed out that the contents of a counr register could be read at anytime. Lei us now look at how this is done in software. One apFoach is simply to read theconients of the corresponding register with an iryur instruction. Figure 10-28 shows thatro read the conlenre ofcounr register0.lhe conrot inpuL. musr be -S = 0. RD - 0,andWR : 1, and the register address code must be ArA0 : 00. To ensure thar a vatid countis read out of count register 0, the counter must be itrhibited b€fore the read operationtakes place. The easiest way to do this is ro switch the cAIEo input to logic 0 before per-lbming the read opemtion. The counr is rcad as two separate bytes, low blre fo owed bythe high byte.

The contents of the count registers can also be read without first inhibiting thecounter That is, the count can be read on the ffy. To do this in software, a command mustfirst be issued to the mode register to captue the current value of the counter into a tem-porary lntemal storage register Figure 10-27 shows that sening bits D5 and D4 of themode byte to 00 specifies the latch mode of operation. Once this mode byte has been \rdr-ten to the 82C54. the contents of the remporarl, storage register for the counter can beread just as before.

EMMPLE IO, I9

Write an inshuction sequence to read the contents of counrer 2 on the fly. The counris to be loaded inro the AX register. Assume that rhe 82C54 is located at I/O address40H.

512 Input/Output lnterface Circuits and tst Peripheral Devices Chap. lO

SolutionFist, we lalch the contents of counter 2 and fhen read this value from the temporary stor-age register. Tlis is done with the following sequence of instructions:

MOV 4I, lOOOXI)CXB ;Latch counler 2,;xlxx must be as per the node and

;Read lhe Low byte

;Read rhe hlgh byte

lA-1a) = counter 2 value

OUT 43!{, ALIN AL, 42H

IN AL, 42H

MOV AL, BL

AnoilH mode of operation, rcan-back mode, penajis a Fogrammer to captue thecurrent count values and status infomation of all three counters with a single cornmand.In Fig. 10-27 we see that a rcad-back comnand \gs bits D6 and D7 both set to 1. Theread back comrnand format is shown in more detail in Fie. 10 30. Note rhat bits Dr (CNT0), D, (CNT 1). and D3 (CNT 2) are made logic 1 to select the counters, logic 0 in bit D1means rhat status infomation wil be latched, and logic 0 in Dj means that the counts willbe latched. For instance, to capture the values in all three counte , the read-back com-mand is I 1011 I 10, : DEr6. This command must be *ritten into the contol word rcgis=ter of the 82C54. Figure 10 3l shows some other examples of read-back commands.Note that both count and status information can be latched with a single command.

Our read-back cornmand example, DEr6, only latches the values of tbe three coun-ters. The programmer mrrst next rcad these values by issuing read cornmands for the indi-vidual counters. Once the value of a counter or status is latched, it must be read before anew value can be captured.

Figure 10 3 I gives'an example of a cor@and that latches only the status for coun-ters I and 2. This conmand is coded as

11101100, = ECr6

Figure 10-32 shows the format of the status idormation latched with this command.Here we find that bits Do tbrough D5 contain the mode-control information that was wrilren imo lhe coumer These bils are idenrical lo lhe six leasr .ienificanr bit' of lhe conbol

A O , A 1 = i i G = O F 5 = r f f i = O

D5:0 - Llrch.oud ol s€l€ct€d @unl.(s)o4: 0 - L{ch 4dtu. or so|.cr€d @uni6r(e)

Oo: Fe.N6d tcr luluro €xp.mioni hu61 b€ 0

Figur€ l0J0 Read-back conmandfomar. (Reprinted bi pemission ofIntel CorpomtioD. CopyrightlrtelCorp. 1990)

5 t3sec. 10.8 82C54 Programmable lnterval llmer

1 0 B.ad back court and status

0 Read back frarusof Couder 1 sr4us laiched for count$ l1 1 0 Fead back statui ol Counr.tr Sd$ ldchedlorCounted

1 0 Read bacr @unror Counter 2 Count btch€d fof Count& 2

1 0 Read bEck coufrsnd sratus Count and .ial$ latched for

Re.d ba.k srarus or CouGr0 srdus l.tch6d lor counter 0

Figure 10-31 Read-bek coMd exanples. (Relrinred by lemission ofIntel Corporalion. Copyright/Inrel Corp. 1990)

word in Fig. 10-27. In addirion to this information, rhe status byre contains the logic stateof the counter\ output pin in bit position D? and the value of the null count flip-flop inbit position D6. The programmer rcads latched status information by issuing a read-counter conrrlland to the 82C54.

The first command in Fig. 10-31, 11000010, = C2r6, captu.es borh the counr andstatus information for counter 0. When both count and sraos information is captrred witha read back command, two read counter commands lre required to rctum the informationto the MPU. Duing the fint read operation, the value of the count is read, and the sratusinformation is transfened during the second read opemtion.

Operating Modes of 82C54 Counters

As indicated earliet each of the 82C54's counrers can be configured to operate inone of six modes. Figue 10-33 shows wavefoms rhar surffnarize operarion for eachmode. Note that mode 0 opemtion is kiown as inrerupi on termjnal count and mode 1 iscalled programmable one-shot. Tbe GATE inpur of a counrer takes on diffe.ent tuncrions,depending on lvhich mode of operation is selected. Figure 10-34 sumnarizes the effecrof the gate input. For instance, in mode 0, GATE disables counting when ser ro logic 0and enables counting when set io I . Let us now discuss each of these modes of operationin more detail.

T\e intemet on temial cornr mode of operarion is used to generate an inrerruptto the microFocessor after a certain interval of time has elapsed. As shown in fte wave-forms for mode 0 operation in Fig. 10-33, a counr of = 4 is wrinen inro rhe count reg-ister synclronously with the pulse at WR. Afte. the wrire operation is complere, the coutr

Figure 10-32 Status byte fomat.(Reprinted by pemission of InletCorporation. Copyright/Intel Corp.r990)

0 - colnt.v.it.bt. tor 66dinsD$Oo Coulnor troO€frhod Mod€

5 t4 lnput/Output Interface Circuits and LSI Peripherat Devices Chap. lO

h-. +,_-! l

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-1______l-

IODE 0: WTEAAUPT ON TEAUNAI COU|T IODE 3: aOUABE WAVE OENEnATOF4q -.rrnffLrl-frffLnnruul-

@uft .4 J'--1___Ji-I-I-L--J@86.4 J----1_r-r_t-

r|OOE a: aOFTWAnE TBIaGEREO ATFOBE

4dIfl-rl-rlNIJ1rIJIJI-rlJtrL*r-Lg4-

oufr r - - - . - - - . - - - - - - - l -

6s,-_-1J.:.gf-

-*---ffio @ w - - - - - . - - - - - - - - - r _

I|ODE 5: HAFDTXARE TRIOOEFED ATROBEc(dffuuuul-ll-fii**---{;1-

_..-.------r-I-XOD€ A RATE GEI{ERAIOA

c@r J-u1J-u1rur,ru'u'lJlJ.U'1J.lJ-UiLrf , :-1r-:f--r:-]r-:- --J,ffi

-.--------------

ffi h.$ il:!-------l-rij=ir-L

Figure 10-33 Operating modes of lhe 82C54- (RePrinted by permission of Intel Corloration. Coly.ight/Intel Corp- 1987)

is loaded into the counter on the next clock pulse and the count is decremented bv I foieach clock pulse that follows. When the count rcaches 0, the terminal couna, a 0-lo- I tran-sition occurs at OUTPUT. This occurs after r + I (five) clock pulses. This signal can beused as the interrupt input to the microFocessor

Earlier we found in Fig. 10 34 that GATE must be at logic I to enable the counterfor inierrupt on teminal count mode of operation. Figure 10-33 also shows waveformsfor the case in which GATE is switched to logic 0. Here we see lhat the value of the countis 4 when GATE is switched to logic 0. It holds at dris value until GATE relums lo 1.

EMMPLE I O.2O

The counter of Fig. 10 35 is pmgrammed to operate in mode 0. Assuming thai the deci-mal value 100 is written inio the countet compute the time delay (TD) that occurs unnlthe positive transition takes place at the counter 0 output. The counter is configured lbrBCD counting. Assume the relationship between the GAIEo and the CLK! signal asshown in the figure.

Sec. 10.8 82C54 Proqrammable lnterval llmer 5 t5

9lgnrlStrlurtod..

LowOrGolng

LowRLlng Hlgh

0 Disabl€Ecountino

Enablescounlino

1 1) Initiat€scountitE

2) Res€ts outpulatt€r neritclock

2 1) Dbablescounung

2) S€ts outputimm€diat€lyhidh

lnitiatescounting

Enabl€gcounung

3 1) Disabloscounting

2) Setsouhutimmedialelyhidh

lnruatescounting

Enabl€scounting

1 Diseble3cilnlim

Enables6uniim

5 Initiat€scounfno

Dz-Do

Figure 10-34 Effect of the GAIEinput for each mode. (Reprinted bypermission of Intel Corporation.Copyright/Intel Corp. 1987)

1 . 1 9 3 1 8 M H z

oUrs I l-- l r , l

F__ro________+j

Figure 10-35 Mode 0 configuration.

CLK6

WR GATEO

ouTo

82C54

5r6

Solution

Once loaded. counter 0 needs to count down for 100 pulses at the clock input' During this

period, the counter is disabled by logic 0 at the GAIEO input for two clock periods.

Therefore, the time delay is calculated as

To:(n + 1+ d)(Tct-ro)

: (100 + 1 + 2X1l1.19318) Ps: 86.3 p.s

Mode 1 operation implements what is known as a progr&mmable one-shol. As Fig.

10-33 shows, when set for this mode of operation, the counter produces a single pulse at

its output. The waveforms show that an initial count, which infhis example is the num-

ber 4, is written into the counter synchronous with a pulse at WR. When GATE, called

TRIGGER in the waveshapes, switches from logic 0 to 1, OUTPUT switches to logic 0

on the next pulse at CLOCK and the count begins to decrement with each successive

clock pulse. The pulse is completed as OUTPUT returns to logic 1 when the terminal

count, 0, is reached. In this rway, we see that the duration of the pulse is determined by

the value loaded into the counter.The pulse generator produced with an 82C54 counter is what is called a

retriggerable one-shot. By retriggerable we mean that if, after an output pulse has been

staft;;, another rising edge is experienced at TRIGGER, the count is reloaded and restart-

ing the count operation extends the pulse width. The lower one-shot waveform in Fig'

10--33 shows ttri. typ" of operation. Note that after the count is decremented to 2, a sec-

ond rising edge occurs at TRIGGER. On the next clock pulse, the value 4 is reloaded into

the counter to extend the pulse width to 7 clock cycles'

EXAMPLE IO.2I

Counter 1 of an 82C54 is programmed to operate in mode 1 and is loaded with the deci

mal value 10. The gate and clock inputs are as shown in Fig. 10-36. How long is the out-

put pulse? Assume that the counter is configured for BCD counting'

Solution

The GAIEI input in Fig. 10-36 shows that the counter is operated as a nonretriggerable

one-shot. Therefore, the pulse width is given by

1 : (counter contents) (clock period)

: (10X1/1.19318) MHz

: 8.38 p,s

Sec. | 0.8 82C54 Programmable Interval Timer 5r7

c L K l

r d A I E l

ouTr

82C54

1 .19318 MHz

Figure 10-36 Mode 1 configuration.

When set for mode 2, rate generator operation, the counter within the 82C54 is setto operate as a divide-by-N counter. Here N stands for the value of the count loaded intothe counter. Figure 10-37 shows counter 1 of an 82C54 set up in this way. Note that thegate input is fixed at the 1 logic level. As the table in Fig. 10-34 showso this enablesthe counting operation. Looking at the waveforms for mode 2 operation in Fig. 10-33, wesee that OUTPUT is at logic 1 until the count decrements to 1. Then OUTPUT switchesto the active 0 logic level for just one clock pulse width. In this way, we see that there isone clock pulse at the output for every N clock pulses at the input. This is why it is calleda divide-by-N counter.

EXAMPLE 10.22

counter 1 of the 82c54, shown in Fig. 10-37, is programmed to operate in mode 2 andis loaded with decimal number 18. Describe the signal produced at OUT1. Assume thatthe counter is configured for BCD counting.

Solution

In mode 2 the output goes low for one period of the input clock after the counter contentsdecrement to 0. Therefore,

t7_-

i-:-l - l

f+- | ---

and

Tz: l /1.19318 MHz : 838 ns

T : 18 X T2 : 15.094 ps

c L K l

GATE l

ouTr

82C54

1 . 1 9 3 1 8 M H z

+ 5 V

Figure 10-37 Mode 2 configuration.

Input,/Output Interface Circuits and LSI peripheral Devices

T2

F-r---*]

5 t8 Chap. l0

Mode 3 sets the counter of the 82C54 to operate as a square-wave rate generator.In this mode, the output of the counter is a square wave with 50 percent duty cycle when-ever the counter is loaded with an even number. That is, the ouput is at the 1 logic levelfor exact$ the same amount of time that it is at the 0 logic level. As shown in Fig. 10-33,the count decrements by two with each pulse at the clock input. When the count reaches0, the output switches logic levels, the original count (n : 4) is reloaded, and the countsequence repeats. Transitions of the output take place with respect to the negative edge ofthe input clock. The period of the symmetrical square wave at the output equals the num-ber loaded into the counter multiplied by the period of the input clock.

If an odd number (A/) is loaded into the counter instead of an even number, the timefor which the output is high depends on (N * 1)/2, and the time for which the output islow depends on (N - l)/2.

EXAMPLE 10.23

The counter in Fig. 10-38 is programmed to operate in mode 3 and is loaded with thedecimal value 15. Determine the characteristics of the square wave at OUTI. Assume thatthe counter is configured for BCD counting.

Solution

Tcr-rr : 1/1.19318 MHz : 838 ns

T1 : Tc1K1(N + I)/2: 838 ns x [(15 + I)/2]

: 6.704 p.s

T2 : Tq1K1(N - I)/2: 838 ns x [(15 - l)/2]

: 5.g66 p,s

T : Tr + Tz: 6.704 p"s + 5.866 ps

: 12.5i p"s

Selecting mode 4 operation for a counter configures the counter to work as asofaaare-triggered strobed counter. When in this mode, the counter automatically beginsto decrement one clock pulse after it is loaded with the initial value through software.Again, it decrements at a rate set by the clock input signal. At the moment the terminal

1 .19318 MHz

+ 5 V

WF--r----

Figure 10-38 Mode 3 configuration.

cLKl

GATEI

ouTl

82C54

Sec. 10.8 82C5+ Programmable Interval Timer 5r9

count is reached, the counter generates a single strobe pulse with duration equal to oneclock pulse at its output. That is, a strobe pulse is produced at the output aftet n * 1 clockpulses. Here n again stands for the value of the count loaded into the counter. This outputpulse can be used to perform a timed operation. Figure 10-33 shows waveforms illustrat-ing this mode of operation initiated by writing the value 4 into a counter. For instance, ifCLOCK is 1.19318 MHz, the strobe occurs 4.19 ps after the count 4 is written into thecounter. In the table ofFig. IO-34, we find that the gate input needs to be at logic 1 forthe counter to operate.

This mode of operation can be used to implement a long-duration interval timer ora free-running timer. In either application, the strobe at the output can be used as an inter-rupt input to a microprocessor. In response to this pulse, an interrupt service routine canbe used to reload the timer and restart the timing cycle. Frequently, the service routinealso counts the strobes as they come in by decrementing the contents of a register. Soft-ware can test the value in this register to determine if the timer has timed out a certainnumber of times; for instance, to determine if the contents of the register have decre-mented to 0. When it reaches 0, a specific operation, such as a jump or call, can be initi-ated. In this way, we see that software has been used to extend the interval of time atwhich a function occurs beyond the maximum duration of the 16-bit counter within the82C54.

EXAMPLE 10.24

Counter 1 of Fig. 10-39 is programmed to operate in mode 4. What value must be loadedinto the counter to produce a strobe signal 10 ps after the counter is loaded?

1 .19318 MHz

+ 5 V

- - rw R l J l

II

ou r , f f i l - ' t-l

F_r___}J

at*,

Figure 10-39 Mode 4 configuration

Du-Do CLKr

WR GATE1

ouTl

82c54

520 Input/Output Interface Circuits and LSl Peripheral Devices Chap. | 0

Solution

The strobe pulse occurs after counting down the counter to zero. The number of input

clock periods required for a period of 10 ps is given by

N: T/T616

: 10 pus/(1/1.19318 MHz)

: 12rc: Cro : 000011002

Thus, the counter should be loaded with the number n : 086 to produoe a strobe pulse

10 ps after loading.

The last mode of 82C54 counter operation, mode 5, is called the hardware-

triggered strobe. This mode is similar to mode 4 except that now counting is initiated by

a signal at the gate input-that is, it is hardware triggered instead of software triggered.

As shown in the waveforms of Fig. 10-33 and the table in Fig. 10'34, a rising edge at

GAIE starts the countdown process. Just as for software-triggered strobed operation, the

strobe pulse is output after the count is decremented to 0. But in this case, OUTPUT

switches to logic 0 N clock pulses after GAIE becomes active.

A IO,9 82C37A PROGRAMMABLE DIRECT MEMORYACCESS CONTROLLER

The 82C37A is the LSI controller IC that is widely used to implement the direct rnemory

access (DMA) function in 8088- and 8086-based microcomputer systems. DMA capabil-

ity permits devices, such as peripherals, to perform high-speed data transfers between

either two sections of memory or between memory and an I/O device. In a microcom-

puter system, the memory or I/O bus cycles initiated as part of a DMA transfer are not

performed by the MPU; instead, they are performed by a device known as a DMA con-

troller, such as the 82C3lA. The DMA mode of operation is frequently used when blocks

or packets of data are to be transferred. For instance, disk controllers, local area network

controllers, and communication controllers are devices that normally process data as

blocks or packets. A single 82C37 A, supports up to four peripheral devices for DMA

operation.

Microprocessor Interface of the 82C374

A block diagram that shows the interface signals of the 82C3'7A DMA controller isgiven in Fig. 10-40(a). The pin layout in Fig. 10-40(b) identifies the pins at which these

signals are available. Let us now look briefly at the operation ofthe microprocessor inter-

face of the 82C374.In a microcomputer system, the 82C37 A acts as a peripheral controller device, and

its operation must be initialized through software. This is done by reading from or writ-

Sec. 10.9 82C37A Programmable Direct MemoryAccess Controller 521

DMA handshakesignals

DREQ0-DREQ3

DACK0-DACK3

roRtow

MEMR

MEMW

(Note 1)

READY

HLDA

ADSTB

AEN

HRQ

cSCLK

RESET

DACK2

DACK3

DREQ3

DREQ2

DREQ1

DREQO

(GND)Vss

A7

A6

A5

A"

EOP

A3

A2

A1

Ao

V6e (+5 V)

DBo

DBr

DBz

DBg

DBa

DACKo

DACKl

DBs

DBo

DBt

(b)

Figure 10-40 (a) Block diagram of the 82C37A DMA controller. (b) pin layour.(Reprinted by permission oflntel Corporation. Copyright/Intel Corp. 1987)

ing into the bits ofits internal registers. These data transfers take place through its micro-processor interface. Figure 10-41 shows how the 8088 connects to the 82C37Ns micro-processor interface.

Whenever the 82C37 A is not in use by a peripheral device for DMA operation, it isin a state known as the idle state.When in this state, the microprocessor can issue com-mands to the DMA controller and read from or write to its internal registers. Data buslines DBs through DB7 form the path over which these data transfers take place. Whichregister is accessed is determined by a 4-bit register address that is applied to addressinputs ,{6 through ,{3. As Fig. 10-41 shows, address lines A6 through ,{3 of the micro-processor directly supply these inputs.

During the data-transfer bus cycle, other bits of the address are decoded in exter-nal circuitry to produce a chip-select (CS) input for the 82C37A.Wheri in the idle state,the 82C37A continuously samples this input, waiting for it to becbme active. Logic 0 atthis input enables the microprocessor interface. The microprocessor tells the 82C37Awhether an input or output bus cycle is in progress with the signal IoR or IOW, respec-tively. In this way, we see that the 82C37A maps into the I/O address space of the 8088microcomputer.

4

b

t'

I

to ,rcaro tt11 30

522 lnput,/Output lnterface Circuits and LSI Feripheral Devices Chap. | 0

es82C37A

DBl) DB?

IORRD

WRr0,6r-

Figure 10-41 Micropruessor interlace of 82C37A to the E088

DMA lnterface of the 82C374

Now that we have described how a mjcroprocessor tatks lo the registers of the

82C3?A, let us contjnue by looking at how peripheml devices initiate DMA service. The82C37A contains four independent DMA channels, channels 0 rb.ough 3. T}?ically, each ofthese cha.nels is dedicated to a specific peripheral device Figue 10 42 shows lhat thedevice has fom DMA rcquest inputs, denoted as DREQo througl DREQ3 These DREQinputs conespond to channels 0 through 3, respe.tively ln the idie stare. the 82C37Acontinuously tests these inputs to see if one is active. Wllen a peripheral device wants toperform DMA operations, it makes a request for seNice ai ils DREQ input by switching itto logic 1.

In response to the active DN4,A rcquest, the DMA contsoller switches the hold request(HRQ) output lo logic 1. Normally, this output is supplied to ihe HOLD input of the 8088and signals the microprocessor tllat the DMA controller ne€ds to take conhol of the systembus. When the 8088 is ready to give up conool of dre bus, lt puts its bus signals into thehigh-impedance state and signals this fact to the 82C37A by swiichlng the HLDA (hold-

acknowledge) output to logic 1 HLDA of lhe 8088 is applied to the HLDA input of the82C3?A and siglals that ttte system bus is now available for use by the DMA conlroller.

wnen rhe 82C37A has control of the system bus, it lels the requesting peripheral

device that il is rcady by outputting a DMA-acknowledge (DACK) signai Note inFig. 10-42 that each of the four DMA request inputs, DREQo through DREQ]' has a

corresponding DMA-acknowledge output, DACK! through DACK3 Once fiis DMA-rcquest/acknowledge handshake sequence is complete, the peripheral device gets directaccess to the system bus and memory under control of $e 82C37A

During DMA bus cycles, the DMA controtlet rot the MPU, ddves the svstem busThe 82C3?A generates the addrcss and all control signals needed to perfbrm the memoryor I/O data transfers. Al the beginning of all DMA bus cycles, a 16-bit address is outpu!on lines A.0 ttrough A? and DBo through DB?. The upper 8 bits of the address, available

Sec. 10.9 82c37A Programmable Direct MemoryAccess controller t23

3't

o

I

L

F.

^x

I>9e , .:EE6

f?

?

? "r3 3 F E sa

424

on the daia bus lines, appear at the same time that address sFobe (ADSTB) becomesactive- Thus, ADSTB is intended to be used to stobe the most significant byie of theaddrcss into an extemal address latch. This 16-bir address gives the 82C37A the ability todirecdy address up to 64Kbytes of storage locations. The address enable (AEN) ouQutsignal is active during the complete DMA bus cycle and can be used to both enable theaddrcss latch and disable other devices connected to the bus.

Irt us assume for now that an I/O peripheral device is to transler data to memory-that is, the I/O device wants to write data to memory ln this case, fie 82C37A uses theIOR output to signal the I/O device to put the data onto data bus lines DBo through DB7.At the same time, it assefs MEMW to signal that the data available on the bus are to be$Tinen into memory In this case, the dara are transfered directly from the I/O device iomemory and do not go through the 82c37A.

In a similar way, DMA transfers of data can take place from memory to an I/Odevice. In * s case, the I/O device reads data from memory and outputs it to the periph-eral. For this data transfer, the 82C37A activates ihe MEMR and IOW contol signals.

The 82C37A perfoms both the memory-to-I/O and l/O-to-nemory DMA buscycles in just four clock periods. The duration of these clock periods is detemined by theftequency of the ciock si$al applied to the CLOCK inpDt. For instance. at 5 MHz theclock period is 200 ns and the bus cycle takes 800 ns.

The 82C37A is also capable of perfoming memory-to-memo.y DMA transfers.In such a data transfer, both the MEMR and MEMW signals are urilized. Unlite ihe I/O-to-memory operation, this memory-to-memorf data tr'ansfer tates eight clock cycles.This is because it is actuaily performed as a separate fouFclock read bus cycle from thesowce memory location lo a temporary rgister within the 82C37A and then another four-clock write bus cycle from the temporary regisier to the des.ination menory location. At5 MHz, a memory-to memory DMA cycle takes 1.6 Us.

The READY input is used to accommodate slow memory or I/O devices. READYmust go active, logic 1, before fte 82C37A will complete a memory or I/O bus cycle. Aslong as READY is at logic 0, wait states are inseded to extend the dwation of the currentbus cycle.

lnternal Architecture of the B2C37A

Figue i0-43 is a block diagram of dre intemal architectue of the 82C37A DMAcontroler Here we lind the following tunctional blocksi the timing and control. the pri-ority encoder and rotating priodty logic, the command contol, and 12 differeni iypes ofregisters. Let us now look briefly at the functions perfomed by each of these secrions ofcircuitry and registers.

The timing and control part of the 82C37A generates the timing and control signalsne€ded by the extemal bus interface. For inst?nce, it accepts as inputs the READY andCS signals and produces output signals such as ADSTB and AEN. These signals are synchronized to the clock signal rhat is inpu! to the controller. The highest speed version ofthe 82C3?A availabie today operates at a ma{imum clock raie of 5 MHz.

ff multiple requests for DNtrA service are received by the 82C37A. they areaccepted on a priority basis. One of two priority schemes can be selected for the 82C37A

Sec. 10.9 82C37A PfogrammabJe Direct MemoryAccess Contrcller t25

too

I

e

(ti

o

>'

e. F

q

t,'-caOc.l@

C)

. N

o o oO *

t o8b

. F v

c d =

e . : i= k* >

CQ L)t

d . 9

9 X

a 0 xh O

js-f rxaz

a

o

=o

H *J ? l=13 Et= '* -E?

f

F

@

GUu4

UIrf

99

G

E

L=uF

cuLq

co

U

@(t

-sat',

2 3 ,; E @

6 <

EuIIl

UF

=

U

Eur oA F

d l 9^ U

= GUF

FzU

U

U

C)z

U=CE=

u

EuILf

u=G=

o sE , ^

=Hr r= zP :r o

EUL

r

!oouE

if

FqU

U

=z o E

1 4 =F E

t r2tg?FF

526

under software control: fixed priority and rotating priority. The flxed-priority modeassigns priority to the channels in descending numeric order. That is, channel 0 has thehighest priority and channel 3 the lowest priority. Rotating priority starts with the prior-ity levels initially the same way as in fixed priority. However, after a DMA request for aspecific level gets serviced, priority is rotated such that the previously active channel isreassigned to the lowest priority level. For instance, assuming that channel 1, which wasinitially at priority level 1, was just serviced, then DREQ2 is now at the highest prioritylevel and DREQr rotates to the lowest level. The priority logic circuitry shown in Fig.10-43 resolves priority for simultaneous DMA requests from peripheral devices based onthe programmed priority scheme.

The command control circuit decodes the register commands applied to the82C37 A through the microprocessor interface. In this way it determines which register isto be accessed and what type of operation is to be performed. Moreover, it is used todecode the programmed operating modes of the device during DMA operation.

Looking at the block diagram in Fig. 10-43, we find that the 82C3'7A^ has 12 dif-ferent types of internal registers. Some examples are the current address register, currentcount register, command register, mask register, and status register. Figure 10-44 lists thenames for all the internal registers, along with their size and how many are provided inthe 82C31 A. Note that there are actually four current address registers and they are all 16bits long. That is, there is one current address register for each of the four DMA channels.We will now describe the function served by each of these registers in terms of overalloperation of the 82C3'7A DMA controller. Figure 10-45 summarizes the address infor-mation for the internal registers.

Each DMA channel has two address registers: the base address register and thecurrent address register. The base address register holds the starting address for the DMAoperation, and the current address register contains the address of the next storage loca-tion to be accessed. Writing a value to the base address register automatically loads thesame value into the current address register. In this way, we see that initially the currentaddress register points to the starting I/O or memory address.

These registers must be loaded with appropriate values prior to initiating a DMAcycle. To load a new 16-bit address into the base register, we must write two separatebytes, one after the other, to the address of the register.The 82C31A has an internal flip-flop called the first/last flip-flop.This flip-flop identifies which byte of the address isbeing written into the register. As the table in Fig. 10-45 shows, if the beginning state ofthe internal flip-flop (FF) is logic 0, then software must write the low byte of the addressword to the register. On the other hand, if it is logic 1, the high byte must be written to

ilrm SEe Nunbcr

Bese Addra$ FegistsrsBase Wofd Count Regist€rgCurent Addrg33 R€gisbBCunent Word Count FogistsrsTemporary Addr€os RsgistefTomporary Word Count B€gbterStatus RegbtsrCommand RegbtorTemporary RegisterMod€ RogisteBMask RegistetRequest Rogister

'16 bitg16 bits16 bits10 bits16 bits16 bits8 bits8 bitsI bits6 bitg4 bits4 bits

4*-

44I'|1114'|'I

Figure 10-44 Internal registers ofthe 82C37A. (Reprinted by permissionof Intel Corporation. Copyright/IntelConr .1987)

Sec . 10 .9 82C37A Proorammable Direct Memorv Access Controller 527

2

3

0

10

0

0

0

0

010

0

X

524

Iigu.€ 1{L45 Accessing the registers of the 82C37A.

the register. For example, to w.ite the address 123416 into the base address register andthe cunent address rcgister for channel 0 of a DMA controller located at base I/O adchessD\4A (\Lhere DVA i' < FoH and ir is decided b) how $e CS ior lhe 82C37A musr begenerated), the following instnrctions may be executed:

MOv aL, 34H ,iirite lov byteOUT DMA+o, AI,MOV AL, 12H ,Wr i te h igh by le

OUT DMA+O, AL

This rouiine assumes that the intemal flip-flop was inilially set to 0. Looking at Fig.10 45, we lind that a corDmand can be issued to the 82C37A ro clear the intemal flip-flop. This is done by initiating an output bus cycle to addless DMA + C16.

If we read lhe conients of the register at address DMA + 016. the value obtained isthe contents of the curent address register for channel 0. Once loaded, the value in thebase adahess register cannot be read out of the device.

The 82C37A also has iwo word count registers for each of its DMA channels: thebase count rcRister aJ'd the cuftent count rcgister. ln Fig. l0 44, we find that these .eg-isters are also 16 birs in length, and Fig. l0 45 identifies their address as 116, relative tothe base address DMA for channel 0. The number of bltes of data to be Bansferred dur-ing a DMA opemtion is specified by the value in the base word-count register' Actually,the number of bytes transfened is aiways one more than the value Fogrammed into thisregister. This is because the end of a DMA cycle is detected by the rollover of the curredtword count ftom 000016 to FFFFL6. At any time during the DMA cycle, the value in thecurent word-count register tells how many bytes tmain to be transferred.

The count registers are programmed in the same way as just described for theaddress registers. For instance. to proFam a count of 0FFFI6 i+to the base and currentcount regjsters for channel 1 of a DMA contro er located at ad&ess DMA (where DMA< F0H), the following inshuctions can be executed:

Mov AL, oFFH ;wrile lov byteOUT DI[A+3, A.I]MOV AL, OFH ;W.ite hiqh byle

OIIT DMA+3, AL

Again we have assomed that the intemal flip:ffop was initially cleared.Figwe 10-44 shows that the 82C37A has a single 8-bit command register The bils

in this rcgister are used to contrcl operating modes that apply to all channeis of the DMAcontroler Figrre 10-46 identifies the tunction of each of its control bits. Note that theseitings of the bits are used to select or deselebt operating lbatures such as memory-tomemory DMA transfer aJ}d the pdodty scheme. For instance, when bit 0 is set to logic I,the memo.y-to-memory mode of DMA tansfer is enabled, and when it is logic 0, DMAtransfers take place betwe€n I/O and memory, Moreovet setting bil 4 to logic 0 selectslhe fixed pdoriry schene for aI four channeis or logic 1 in this location selects rotatingpriority. Looking at Fig. 10-45. we see tbat lhe command rcgister is loaded by outputtingthe command code io the regisler at address 816. relative to the base address for the82c3',7 A.

sec. 10.9 A2c3T\Prcgatnable Direct Memory Access Contrcller 529)

0 chd0.ddr{dd4r.

I'tgure 10-46 comd Egisterformat. (Reprinted by pemi$ion ofInt€l Corpomtion. Copyright/IntelCorp. 1987)

EXAMPLE I0.25

If the corDmand register of an 82C37A is loaded with 0116, how does the controler operate?

SolutionReFesenting the command word as a binary number, we get

01" = 6666600t'

RefemDg ro Fig. l0-46, we find thal Lie DMA op€.ation can be described as foilows:

Bit0: I - Memorylo-memory transfers are disabled

Bit 1 = 0 = Channel 0 address increments/decrements normally

Bit2:0 = 82C37A is enabled

Bit 3 = 0 = 82C37A operates with normal timing

Bit 4 : 0 = Channels have fixed priority, channel0 having the highestpdodty and chaDnel 3 rhe lowest pdodty

Bit 5 = 0 : Write operation occurs late in ihe DMA bus cycle

Bit 6 = 0 = DREQ is an active high (togic 1) signal

Bit 7 = 0 = DACK is an active low (logic 0) signal

Ttl€ ntode rcgisters arc also used to conligure opentional feahres of theFigurE 10-44 shows that there is a sepamte mode rcgister for each of the four DMAnels and that each is six bits in length. Their bits are used to selecr various opelalionaltures lor the individual DMA chamels. A mode register corffnand, shown in Fig. 1

530 Input/Output lnterla.e CircLriB and LSl Peripheral Devices Chap.

Figun 10-47 Mode ftgister [orma!.(Reprinted by pemission of IntelCoQoralion. Cop)'right/lntel Cor?.1987)

has two least significant bits that are a 2-bit code, which identifies the chamel to which inemode command b)'te applies. For instance, in a node rcgister cornnand written for channelI, these bits must be made 01. Bits 2 and 3 specily whether the chamel is to p€rform datawrite, data read, or vedfy bus cycles. For example, if these bits are set io 01, the channelwill only perform write-dafa transfen (DMA data transfe$ ftom an UO devic€ to memory).

The next two bits of the mode register atrect how the values in the curent adciressand cLffenr counr regrsrers aJe upddreo dr rhe end oi a bl\44 qcle dnd DMA drrr rany1b., respectively. Bit 4 enables or disables the autoinitialization function. When auto-initialization is enabled. the cunent add.ess and current count registe$ arc automaticallyreloaded ftom tbe base address and base count registers, respectively. at the end of aDMA operation. In this wat fte channel is Fepared for the next DMA tansfer The set-ting of bit 5 deiermines whether the value in the curent adahess register is automaticallyinffemented or deremented at completion of each DMA data transfer

The two most significant bits of the mode register select one of four possible modesof DMA operation for the cha[\el: denand node, singte made, block mode, ar.d cascaderrod€. These modes alow for either one byte of data to be tansfe.red at a time or a blockof bytes. For example, when in the demand Eansfer mode, once the DMA cycle is initi-ated, bytes arc continuously tansferred as long as the DREQ signal renains aciive andthe teminal count (TC) is not reached. By reaching the terminal count, we mean that thevalue in the crment word-count register wlrich automatically decrements a{ter each datatransfer, rolls over from 000016 to FFFFr6.

Block-tansfer mode is similar to demand-transfer mode ]n that once the DMA cycleis initiaaed, data are continuously hansfened uniil the terminal count is rca.hed. Howevetthey differ in that when in the demand mode, tbe retum of DREQ to its inactive state haltsthe data aansfer sequence. But when in block-transfer mode, DREQ can be released at anytime after the DMA cycle begins, and the block transfer will still run to completion.

ln the single-hansfer mode, the channel is set up such that it performs just one datairanstbr al a time. At the completion of the transfer the curent word count is decrementedand the curent address ei.her incremented or dedenented (based on dre selected option).Moreover an autoinitializaiion, if enabled, will noi occur unless the terminal count hasbeen reached at the completion of the current daia tansfer. lf ihe DREQ input becomes

Sec. 10.? 82C37A Programmable Direct Memory Access Controller 531

inactive before the completion of the current data tansfer, anoiher data transfer will nottake place until DREQ once more becomes active. On the other hand, if DREQ remainsactive duling the complete data tansfer cycle, the HRQ output of the 82C37A is switchedto ;ts inactive 0 logic level tb allow the microprocessor to gain control of the system busfor one bus cycie before another single transfer tahes place This mode of operation isqpically used when it is necessary to not lock the microprocessor off the bus for the com-Dlete duration of the DMA operation.

EXAMPLE I0.26

Specily the rnode blae for DMA channel 2 if it is to transfer data from an input periph-

eral device to a memory buffer starting at adahess A00016 and ending at AFFF]6 Ensurethat the microFocessor is not completely locked off the bus during the DMA cycle.Moreovet at the end of each DMA cycle, the channel is to be reinitialized so that thesame buffer is lilled when the next DMA operation is initiated.

Solution

For DMA channel 2. bit I and bit 0 must be loaded with 10r:

BlBo : 10

Tmnsfer of data from an I/O device to memory represents a wite bus cycle. Thercfore,bit 3 and bit 2 must be set to 01:

B3B, : 91

Selecting autoinitialization will set up the chamel lo automatically reset so that it points

io the beginning of the memory buffer at completion of the curent DMA cycle Mfingbii 4 equal to 1 enables ihis featue:

B + = t

The aaldress that points to the memory buffer must inoement after each data fansfetTherefore, bit 5 must be set to 0l

Bs=o

Finally, to ensure 6at the 8088 is not locked off the bus during the complete DMA cycte,we will select the single-tmnsfer mode of operation. Making bits B7 and 86 equal to 01does dis:

8786 : 0 l

Tbus, the node register byte js

8?868584838rBrBo = 01010110' : 56'6

t t2 Input/Output lnterface Circuits and LSI Peripheral Oevices Chap l0

0

s.r*r ch.n.€r 2 liaF 10_48 Reoue.r reaisrer lur-er. (RepruLed by pemi\siod ol lnrel

F...r Gqu..r btl corloration. coP]tiShvlntei corp.s.r rcq!..r bI 1987)

Up to noq we have discussed how DMA cycles can be initiated by a hardwarerequest at a DREQ input. However, the 82C37A is also able to respond to software-initiatedrequests for DMA service . The requesr rcgister has be€n provided for this purpose. Figue10-44 shows that the request rcgister has just four bits, one for each of the DMA channels.Wlen the request bia for a channel is set. DMA operation is started, and when reset. theDMA cycle is stopped. Any channel used for software-hitiated DMA rnust be progranmedfor block-transfer mode of operation.

The bits in the request register can be set or reset by issuing software commands tothe 82C37A. The format of a request regrster command is shown in Fig. 10 48. Forinstance, if a conmand is issued to the addrcss of the rcquest register with bits 0 and Iequal to 0l and with bit 2 at logic 1, a block-mode DMA cycle is initiated for channel 1.Ficure 10-45 shows lllat the request register is located at register ad&ess 916, relative tothe base addrcss for the 82C37A.

A 4+it mo,sk reqister is also provided within the 82C37A. One bit is provided inthis register for each of the DMA channels. When a nask bit is set, the DREQ input forthe corresponding channel is disabled. Therefore, hardware requests to the channel areignored. That is, the channel is masked out. On ihe other hand, il the nask bir is cleared,the DREQ input is enabled and an extemal device can activate its channel.

The format of a software command that can be used to set or reset a single bit inthe mask register is shown in Fig. 10-49(a). For example, to enable the DREQ input fo.channel 2, the comrnand is issued with bits 1 and 0 set to 10 to select channel 2, and withbit 2 equal to 0 to clear the rnask bit. Thereforc, the so{tware command byte would be0216. The table in Fig. 10 45 shows that this command blte must be issued to the82C37A with register address A16, relative to the base address for the 82C37A.

n sd..r cion l s Nr !n

Figure 10-49 (a) Slngle'chdnel msk-register commd format. (Reprintedby lemisio! of Intel Coipomtion. Copyri8lthtel Corp. 1987) (b) Four-cbannel maskjeSister coMd fomar. (Reprinted by pemi$ion of Intel CoFporalion. Copltighvlntel Corp. 1987)

Sec. lO.9 82C374 Ptogftnmable Direct I/emory Access Controller 533

Figur€ 10-50 Status register(Reprinted by pennission of IntelCorloratior. CoD,right/Intel Corp.1987)

A second mask register command is shown in Fig. 10 49(b). This command can beused to load all4 bits of lhe register at once. ln Fig. 10-45. we find that this colnnland isissu€d to relative rcgister address Fr6 instead of A.16. For instance, to mask out channel 2while enabling channels 0, 1, and 3, the conmand code is 0416. Either of these two meth-ods can be used 10 mask or enable the DREQ input for a channel.

At system initialization, it is a common Factice to clear the mask register. Lookirgal Fig. 10-45, we see that a special command is provided to perfom this operation. Exe-cuting an output cycle to the register with relative address Er6 clears the nask register'

The 82C37A has a status register that contains information about the operatingstate of its four DMA channels. Figue 10-50 shows the bits of the status register anddefines their functions. Here we find lhat the four least significant bits identify whelher ornot channels 0 tlrough 3 have reached their terminal count. Wlrcn the DMA cycle lbr achannel reaches lhe terminal count, this fact is rccorded by setting the corresponding TCbit to ihe 1 logic level. The four most significant bits of the r€ister te1l if a request ispending for the coresponding chaDnel. For instance, if a DMA request has been issuedfor channel 0 either through hardwaft or softwarc, bit 4 is set to I . The 8088 can read thecontents of the status register through sofrware. This is done by initiating an input buscycle for rcgister address 816, relative to the base address for the 82C37A.

Ea ier we pointed out thar duriry memory-to memory DMA tansfers, the dataread from the souce address are held in a register krrc''tn as the tempomry reqiste\ anihen a write cycle is initiated to write f]le data to ihe destination address. Al ihe comple-tion of the DMA cycle, this regisier contains the last byte that was transfered. The valuein this register can be read by the microFocessor

EXAI\4IPLE 1O.27

write an instruction sequence !o issue a master clear to the 82C3?A and then enable allits DMA channels. Assume that the device is located at base I/O address DMA < FoH.

SolutionFigure 10-45 shows thal a special software conlllland is provided to pertbrm a masterreser of the 82c37A s registers. Since the contenrs of the data bus are a don'l-care statewhen executing the master clear command, it ls pedonned by simply writing into the rcg-ister at relative address Dr6. For instance, the instruction

OIIT DMA+ODI{, AL

Input/Output lnterface Circuits and Lsl Peripheral Devices534 Chap. l0

can be used. To enable the DMA request inpuls, all 4 bits of the mask regisrer musr becleared. The clear-mrsk register command is issued by perfomring a write to the regisrerat .elanve ad&ess Er6. Agaiq the data pur on the bus duriry rhe wrile cycle are a don'tcarc staie. Therefore, the command crn be perforned wirh rhe inshuction

OUT DT4A+OE}I, AI-

DMA Interface for the 8088-Based MicrocomDuterUsing the B2C37A

Figure 10 51 shows how the 82C37A is coDnecred to rhe 8088 microprocessor tofolm a simplilied DMA interface. Here we see that borh the 8088 MPU and the 82C37ADMA controller drive the same three sysren buses- address bus, dara bus. and confol busLei us now look at how each of these devices aftaches ro ihe sysrem bus. The 8088.s mul-npbxed address/data bus is denultiplexed using rbrce 74F373 latches lo fo.m indepen-dent system address and data buses. The addrcss bus is 20 biis in length, and these linesare identified as Ao thrcugh Are. On the otber hdnd. the dara bus is byte wide. wirh linesD0 through D7. Nore thar thc ALE outpur of the 80tt8 is trs€d as rhe CLK i.put to the

Looking at fte 82C37A, we find that the lower blre of irs address, identified by Aothrough Ar and Aa through A7. is supplied directly to the sysrem address bus. On rhe otherhand, the most significant b}1e of ils address, As rbrough Aij, is demulriplexed horn databus lines DBo through DB7 by ,nother 74F373 larch. This latch ;s enabled by thc AENoutput of the DMA controller. and rhe addrss is loaded into rhe larch wirh rhe signalADSTB- DBo tbrough DB7 are also direcrly anached b the sysrem daia bus.

Final l ) . er u. l , ,ok a, how rbe.ysrcm conlrol bu, s igml. de deri \ed. Ihe tOA4.RD, 441ryE cj!q9\,u!p!!s of fte rnicruprocessor are sated rogelher to produce rhe signals MEMR, MEMW. IOR, ,nd IOW. These signals are combined to form rhe systemcontol bus- Note that these same four signals are generated as outputs of ihe 82C37A andare also supplied to tbe cotrEol bus.

Now fiat we have shown how the independenr address, data, and conrol signals ofihe 8088 and 82C37A are combircd ro form rhe sysrem address. data, and control buses.let us continue by lookine ar how the DMA requesr/acknowledge interface is implernented. l/O devices requesr DMA service by activaring one of rhe 82C37As DMArequesr inputs. DREQo through DREQ. wlen lhe 82c37A re.eives a val;d DMA requeston one of dese lines, n sends a hold rcquesr ro the HOLD inpur of the 8088. Ir does thisby setting rhe HRQ ourput to logic 1 . After the 8088 gives up cotrtrol of the system bnses,it acknowledges this facr |o the 82C37A by swirching irs HLDA ourpur ro the 1 logiclcvel. This signal is rcceived by ihe DMA controler ar irs HLDA jnpu. ad tetis it thar t1lesystem buses are available. The 82C37A ;s now ready to aal€ over control of the sysiembuses, and it signals rhis facr ro rhe device thar is requesting seflice by aclivating itsDMA acknowledge (DACK) Iine.

Dudng the DMA operarion, the 82C37A genentes aI of the bus signats rhat areneeded to access I/O devices and the memory h also gercrares l})e AEN signal, which is

sec 10.9 82C37A ProqEmmabte Dted Memory Access Conirolter 535

frEla rllw- 6i i6tcs

used to disable the miffoprocessor's connection to the system bus AEN does this by dis-

abling the controt bus decoder and the latches for the adilrcss bus The microprocessor's

conn;ction to the alata bus is also disabled in response to the hold request received on its

HOLD input. Remember that logic I at HOLD puts the data bus lines in the high-Z state'

Thus, dwing a DMA operation, the 82C37A is in complete control of the ad'lrcss bus'

contol bus, and data bus.

I O.IO SERIAL COMMUNICATIONS INTERFACE

Another lype of I/O interface that is widely us€d in rnicrocomputer systems is knosn as

^ seial conanunication pot This is the type of interface that is cornmonly used to con'

Figure 10-51 8088-bas€d micrccomluter with 82C37A DMA interface'

5 t6 lnDut/Outout tnterlace Cjrcuits and tsl Perjpheral Devices Chap l0

nect peripheral units, such as CRT teminals, modems, and pdnters, to a mibrocomputer.It permits data to be transfened between two units usingjusi two data lines. One line isused for transmitting data and the oiher for receiving data. For instance, data input at rhekeyboaxd of a terrninal are passed to the MPU part of the microcomputer through thistype of intedace. Let us row look into the two different types of serial iDterfaces that areimplemented in microcomputer systems.

Synchronous and Asynchronous Data Communications

lworype,ot 'eial 4s n , onnunica t iot5 are $ ide b u\ed in rnicrocompurer ') s-trms: asynchrohous communications and synchmnous connunications. By synctnolo]us,we mean that ahe receiver and transmifter sections of the two pieces of equipment communicating with each other must rlrn synchronously. For this reason, as shown in Fig.10-52(a), the interface includes a Clock line as well as Transmit data, Receive data, andSignal common lines. It is the clock signal that synchronizes both the transmission andreception of data.

The fomat used for synctuonous comrnunication of data is shown in Fig. 10-52(b).To initiate syncbronous transmission, rhe tansmitter firct sends oui synchronization char-acters to the receiver. The receiver reads the synchrcnization bit pattem and compares itto a known sync pattem. Once drcy are identified as being the same, the receiver beginsto .ead character data off the data line. Transfer of data continues dhtil dre complete blockof data is received. ff large biocks of data are being sent, ihe synchronization characters

SYN

(b)

Figur€ 10-52 (a) sylchronous comunicatioDs jnted:re. (b) synchrcnousdata'transmission fomat.

Sec. 10.10 Sefial Communications lnterface 5t7

mry be penodically rcsen! to rlsure that synchronization is maintained. The synchronoustype of communications is typicalLy used in applications where high speed data trrnsferis required.

The asynclronous nethod of commxnications eliminates the need for the Clocksignll. As shown in Fig. 10 53(a), the sinplcsL fblm ol an asynchronous communicationinterface could consist of a Receive data, Transmit data. and Signal cornrnon cornmuni-cation lines. In this case, the data to be transmitted are sent out one characier at a lime,and at the receiver examining synchronizarion birs that are included at the beginning andend of each character perfbrms end ol thc conrmunication line synchronization.

The fbrmal of a typical asynchronous character js shown in Fig. I 0 5 3(b). Here wesee tbal Lhe synchronization bit at the beginning of the character is called the,ltdrr bir, andlhat d! the end of the character the rrop br. Depending on lhe communications scherne, l.l7r, or 2 stop blts can be used. The bits of thc character are embedded belween ihe startand stop bils. Nolice that the start bil is eilher input or outpu! first. The LSB of the char-acte! the rest of the characreis bi!s, a p,trity bit, and the stop birs follow il in the serialbit stream. For inslance, 7-bit ASCII can be used and parity added as an eighth bitfor higher reliability in transmission. The duradon of each bit in the format is called a

The fact that a 0 or I logic level is being trensferred over the communication line isidenlified by whether the vohage level on the line comesponds to that of a spdc€ or amal., respectively, The stan bit is always to the malk level. It synchronizes the receiverto the transmilter and signals that lhe unit receiving dah should (art assembling lhe char-

tt"fi'

(MARK)

l'igure 10-53 (a)AsyDch.onons comnu.icationr inlerface. (b) Asynchronousdata-t.0smi$ioD fb.nat.

-1

(SPACE)

534 Input/Output interface Circuits and LSI Pefjpheral Devices Chap. l0

acter. Stop bits are to the space level. The nontransmitting line is always at the space logiclevel. This scheme assures that the receiving unit sees a transition of logic level at the startbit of the next character

Simplex, Half-Duplex, and Full-Duplex Communication Links

Applications rcquire different b?es of asynckonous links to be implemented. Forinstance, the communication lint needed to connect a pdnter to a mioocomputer just

needs lo support communications in one direction. That is, the printer is an output-onlydevice: therefore, the MPU ne€ds ody to transmit data to the printer. Data are not trans-mitted back. In this case, as shown in Fig. l0-54(a), a single unidirectioml communi-cation line can be used to connecl the printer and microcomputer together' This rype ofconnection is knou'n as a sinpl?r com,nuntuation link

Other devices, such as the CRT terminal widr keyboard shown in Fig. 10 54(b),need to both transmit data to and receive ddt4 ftom the MPU. That is, they must bothinput and output data. Setting up a half-duplex communication linL can also satisfy thisrequirenent with a single communication line. In a half-duplex tinl, daia are transmittedand received over the same line; therefore, tansmission and reception of data cannot takeplace at the same tiriF.

lf higher-perfomance communication is required, separate transmit and receivelines can be used to connect the peripheral and microcomputer When this is doDe. datacan be transferred in both directions at lhe same time. This rype of link, illustrated in Fig10 54(c), is called arll-duplpi connunicdtion link.

FisN 10-54 (a) Sinplexcomunication link. (b) Half duplexcomunication link- (c) FnI duplex

Sec. 10.l0 Serial Communications lnteface 53q

Baud Rate and the Baud-Rate Generator

The rate at which data aansfers ral.e place over the receive and transmit lines iskl],o\vn as the baud nte. By baud rare we mean the number of bits of daia transferred persecond. For instance, some of the common data rransfer rates are 300 baud. 1200 baud.4ld 9600 baud. They correspond to 300 bits^econd (bps), 1200 bps. and 9600 bps,respectively. Baud rate is set by a part of ihe serial commuDication interface caled rhebawlrate generutor

The baud Iate at which dara are transfered detemines the bit time that is. theamount of time each bit of data is on the communicarion line. Ai 300 baud, rhe bit rimeis found to be

tlr : 1/300bps : 3.33 ms

EMMPLE I 0.28

The data transfer acruss an asyncbronous serial dara comrnunications ljne is obsened andthe bit time is measured as 0.833 ms. Whar is rhe baud rare?

SolutionBaud rate is calculated fron rhe bit time as

Baud mre : l/rBr : I /0.833 ms : 1200 bps

The RS-232C Interface

Tne RS-232C intetac€ is a standard hardware inrerface for imDlemenrins as!n,chronous cerial dala conmunicarion pon\ on oevicei.uch as printer,. Cnr reritnis.keyboards, and modems. The Elecrronic Indusrries Association (EIA) defines the Dindefiiirions and elecrical chardcrerinic. ol rn. inrerface. the arm behind Dubti.h;ne\randards. ,uch d, lhe RS-2J2C. is ro a..ure comparibitiD berkeen equipmenr .na,ie Ujdiff erent manufacturers-

Periphemls that connecr ro a microcomputer can be located within the sysr€ms oranywhere hom several feet to many feet way. For instmce, jn large systems ir is commonto have the mjcrocomputer part of ihe system in a separare room from the teminals andpdniels. This leads us to the main advantage of using a serial inredace to connect peri-pherals to a miclocomputer, which is that as few as three signal lines can be used to con-nect the peripheral to the MPU: a receive-data line, a transmir-data line. and sisnal common.This result" In J large sar ing, in qir ing .o,r( , and rhe .mrl number ot t rne. rnor need .obe put in place also leads to higher reliabitit

The RS-232C standard defines a 25-pin intedace. Figure t0 55 lists each pin andiis tunction. Note that the tfue€ signals thar we menrioned eartier, transmit dara (TxD),receive data (RxD), and signal ground, are tocated ar pins 2, 3, and 7. rcspecrivety. pinsale also provided for addirional control functions. For instance. pins 4 and 5 are therequest-to-send and clear-to-send conrrol signals.

J40 Input./Output lnterface Circufis and LSt pefipheral Devices Chap. lO

Pin Signal

1 | Protective Ground2 | Tr€osd' €d Dsis3 | Fec€ived Data4 | Fequest ro send5 | Cleat to Send6 | Dara set Re.dy7 | Si9n6l Ground (Common Rerurnl8 | A€csived lin€ Sisnsl D€tector

9 | R€5.tusd lo, Data Set Testins

10 | F.sorved lor D.r. S€r Testinsl1 | Un..signed12 | Second.ry Rec€ived Line Siqn.l Oerector

13 | secondary clear to se.d14 | Seconddry Tr€nsmitr€d Data15 | T.ansmission Signal Element TinihgrO I S€cond..y R€@ived Oata11 | Roceiv€r Signal Element Timing18 | Uoassisnedl9 | S6cond.'y Fsqlest to Send20 | O.t6 T..minal Feady21 | Sign.l Oualiry Oetsctot22 | Bins Indacaiot23 | 0616 Sienal Fare Selecto,24 | T.ansmit Sagnal €lenenr Timing25 | Udassisned

rigult 10-55 RS-232C interface pins md tunctions.

How the signals of the RS-232C interface are used in a device depends on whetherit is configured as what is knc' n as a Data Teminal Eqaipnent (DTE) ot a Data Con-munications Equipnent (DCE). An example of a DTE is a PC, and that of a DCE is amodem. The direction for signals in a DTE and a DCE device are revelsed. That is, sig-nal Lines that are outputs on a DTE device are inputs on a DCE and vic€ velsa. Thisenables one to use a cable that makes dir€ct connections between the pins of the DTE anda DCE. For instance, if pin 2 on a DTE is an output, it connects direcdy to pin 2 on theDCE, which acts as an input.

To make a DTE device €ommudcate to a DTE device requires a cable that makesthe pin-to-pin connections shown in Fig. 10-56. Note that wh€n both devices are config-ured as DTES, the dao transmitted by one is received by the other and vice versa. It there-fore rcquires a special cable in which tbe TxD pin of one is connected to the furD pin olrbe orber device and vice versa.

The control pins are provided to set up a handshake sequence for idtiating com-munication between serial devices. These signals have the neanings expressed ir theirnames; for instance, request to send (RTS) is used to send a request from a DTB device

Sec. 10.10 Serial Communications lnterface t4r

RxD

TxD

DTR

DSR

RTS

cTs

GND

TxD

DSR

cTs

GND

Flgu.e 10-56 A DTE-Io,DTE serial communicatiotr comection.

to a DCE or another DTE device to ger ctearance to send data. In many sysrems onlythree signals TxD, RxD. and common are used to provide serial cornmunicarion. In such aset up no handshake sequence is used ro initiate communication.

The RS-232C interface is specified to opemte correcrly over a distance of up ro100 feet. To satisfy this distance specificarion, a bus dn,ver is used on the rmnsmir tine anda bus receiver is used on the receive line. RS-232C drivers and receivers are available 6srandad ICs. These buffers do botb the volragelevel rranslarion needed to converr the TIL,compatible si$als to tlle mark oogic 1) and space (logic 0) voltage levets defined for rheRS-232C interface. The voltage level for a mark can range from -5V ro -15V at the rrans-mitting end and -3V or less ar the receiving end. Similarly, a voltage level jlom +5V to+15V ar rhe transmining end and +3V or more ar the rcceiving end is consialered a space.

The RS-232C data communication rate is sDecified as baud rate. Earlier we Doinredout that this is a measure of the bits transfened tfuougb rle communicatioD inrerface persecond (bps). For example, a common rare of C600 baud neans 9600 birs are nansminedor received in one second. In general, rhe receive and rransmit baud rates do not need tobe the same; however, in most simpler systems they aft set to the same value.

l. IO. i I PROGMMMABLE COMMUNICATIONINTERFACE CONTROLLERS

Berause 5erial Loomunicadon rorerface. are so $jdet) used in modem eted.o c equrpment, special LSl peipheral devices have been developed to permir easy implementationof these t'?es of intedaces_ For instance, an RS-232C port is the type of inreface needed

542 Input/Output lnterface Circuits and LSI peripherat Devices Chap_ tO

to connect a CRT terminal or a modem to a miuocompuler To supPort connection ofthese two peripheral devices, the microcomputer would need two independent RS-232CI/O pots. This function is normally implemenled with a prcgranmable conmunicationcontrolei known as a &niversal anchrcnous/asJnchrcnous rcceirer tratLsmiher (US/-IT)

As the name implies, a USART is capable of implementing either an asyncbrcnous orsynchronous communicatlon interface. Here we will concentrate on its use in implemenling an asynchronous communication interface.

The progammability of the USART provides for a very flexible asynchronous com-munication interface. Tlpicaly. it contains a ful1-duplex receiver and transmitlet whichcan be configured tlmugh software for communication of data using formats with charac_tef lengths between 5 and 8 bits, with even or odd paity. and with 1, 17r, or 2 stop bits.

A USART has the ability to auromatically check characte$ during data r€ception todetect the occurrence of pariry, framing, and overrun errors. A framing error means thalafter the delection of ihe beginning of a character with a sta( bii the appropriate numberof stop bits were not deiected. This means that the character that was tansmitted was notreceived conectly and should be rcsent. An overun error means that the pfor characterthat was received was not read out of the USART'S receive data register by the miffo-

Focessor before another chatacter was received. Thercfore, the first character was lostand should be retansmitted.

825l/q USART

A block diagam showing the intemal architecture of the 8251A is shown in Fig.10-57(a) and irs pin layout in Fig. 10-57(b). From this diagam we find that it includesfour key sections: the bus interface section, which consists of the data bus buffer andread/write conaol logic blocks; the transmit section, which consisls of the transmit bufferand transmit control blocks; the receive section, which consists of the receive buffer andrcceive-contol blocks; and the modem-control section. L€t us now look at each of theseseclions in more detail.

A UART cannot stand alone in a cornmunication system: its operation must t)?i-cally be controlled by a miffoFocessor The bus interface section is used to connect the82514 to a miuoprocessor such as the 8086. Note that the interface includes an 8-bitbidirectional dala bus D0 tlrough D7 driven by the data bus buffer It is over these linesthat the microprccessor transfers cornmands to the 8251A. reads ils status register. andinpuL. or outpuls characrer drr,i.

Data transfers over the bus are controlled by lhe signals C,D (control/data), P.D(read), WR (write), and C.s (chip select), a[ inputs to the read/write control logic section.'Ihically, the 8251A is located at a specific address in the microcomPutert I/O or memory address space. \\&en the miffoprocessor is to access registers within lie 8251A, itputs this addrcss on ihe address bus. The ad&ess is decoded by extemal circuitry andmust Foduce logic 0 at lhe CS input for a rcad or write bus cycle to take place to the8251A.

The orher duee conrol ..goals. CD. RD. dnd wR. rell dle 825 | A whar Dpe of datatransfer is to take place over the bus. Figure 10 58 shows the various types of read/writeoperations that can occur For example, the first siate in the table, C'D = 0, RD = 0, andwR = 1, coresponds to a character data transfer from lhe 8251A to the microprocessor

Sec. 10.I I Programmable Communjcation Interface Controilers 543

srE3'

v . . t r p E t ' r a A q 2 2d o '> " r i rE tE tE p d i E rE ; ;

iE

c *

: . 5

o€B3FF* r'd

o 6 S

. sE 5

s a ; " I o- d o ' 6 1*" 15 r3,oQ le, i

h

_ e : r - 4 > v" s i ! - t3 lE ErE

544

c/D RD

0

I I ;I

0

0

0

0

0

I

Figure 10-5E Read/rrile operations.(Relrinled by permission of IntelCorpodiotr. Copyright/Intel Corp.19871

Note that in genenl RD : 0 signals that the microprocessor is reading data from the8251A, WR : 0 indicates that data are being written into the 8251A, and the logic levelof C/D indicates whether chancter data, control information, or status info.mation is onthe data bus.

EX,\l\ttPLE 1O.29

w1lat type of datariansfer is taking place over the bus if fte control signals are atCS = 0, C/D : 1,RD : 0,andWR : 1?

SolutionI ooLrng ar lhe rable in Pig. 10-58. $e .ee rbal -S -0 means lhal lhe 825 | c s daLa bushas been enapled for operatlon. Since C./D is 1 and RD is 0, status infomalion is beingread from the 8251A.

The receiver section is responsible for reading the serial bit stream of data at theRxD (receive data) input and cqnverung it to parallel form. When a mark voltage level isdetecGd on lhis line, inaicating a start bit, the rcceiver enables a counter As the counterincrements to a value equal to one-half a bit time, ihe logic level at the RxD line is sam-pled again. ff it is still at the mark level, a ralid start pulse has been detect€d Then R{Dis examined every tine the counter increments tfuough another bit time. Tbis continuesuntil a complete chamcter is assembled an4 the stop bit is .ead. AJter this' the completecharacter is transferred into the receive-data register.

During reception of a character, the receiver automaiically checks ihe character datafor parity, ftaning, or overun errors. If one of these conditions occurs, it is flagged bysetling a bit in the status register Then the RxRDy (receiver ready) output is switched tothe 1 logic level. This signal is sent to fhe micropocessor to tell it that a characier is available and should be read from the receive-data registex RxRDy is automaticaly reset tologic 0 when the MPU reads ihe contents of the rcceive_data register.

The 8251A does not have a builli, baud-rate generator For tbis reason, the clocksignal that is used to set the baud rate must be extemally generated and appiied to the Rxcinput of the rcceiver. Tkough software the 8251A can be set up to intemally divide theclock signal input at Rxc by 1, 16, or 64 to obtain the desired baud rate

sec. l0.l I Programmable Communication lnterface Controllers 545

The traffmitter does the opposite of the receiver section. Ir receives parallel char_acter data from the MPU over the data bus. The character is rhen automaricalty fiamedwith the saart bit, appropdate parfty bi! and the conecr number of stoD bits and Dut intoIhe ratrsmr dara buffer regisrer. Finalty, il is shified our ot rhis regisle; ro produ;e a biFsenal ouipul on the TxD line. wlen rhe rransmit alata buffer regisrer is empty, rhe TxRryoutput switches ro logic l This signal can be retumed to the MpU to tell ii rhar anothercharacte. should be ourpui ro ihe rransmitter section. When rhe MpU writes another char_acter out ro ihe transmitrer buffer r€ister. the TxRDy outpur resets.

Daia are outpur on the transrnir line ar rhe baud mte set by rhe extemal tansmitterclock signal that is input ar Txc. In mosr appticarions, the transminer and receiver oper-ate aa the same baud mte. Therefore, the same baud-rate generaror supplies both Rxc andTxc- The circuit in Fig. 10-59 shows rhis fype of sysrem conigumtion.

The 8251A UART, just like the orher peripheral lcs discussed eadier in the chaDter,can be coofrgurcd for various modes ot operarion tbrougb softua_re. trs operarion r. con-rolled though lhe sening of biB in rfirce inLernal connot regislers: Lle moae controt reg-ister. commrnd regisrer and the status regisier_ For instance, the way in which the 825ltsreceiver and rraffmitrer worh is determined by rhe contents ol rhe mode conrol reaister.

Figure 10. 60 shows |le organLarion ot rhe node conrrot regLrer and fie tu;cdoDof each of its bits. Nore that the rwo leasr significad bitl Br and B, aleremine whether tbedevrce operates as an asyncbronous or synchromus corDmunication conroller and inasyncbronous mode how rhe extemal baud rate clock is divided within rhe B25tA. Forexample, if .hese two bits are I I , ir is set for asynckonou operatjon wirh divi{te bv_64lor d|e baud-mre inpur. fte rwo bils $ar toUow dese. Lr anl L..er tbe tengrtr oi Llechamcter. For instance, when infomarion is being ransmitred and received as ?_bitASCI characteN, rhese bits should be toaded wirh 10.

The next rwo bits, PEN and EP, determine whether pariry is in use and, if so,whethe. it is even pnity or odd pariry. I_ooking at Fig. 10_60, we see rhai pEN enablesor drsables parity. To enable pariry, ir is s€t .o 1. Furrhemore, when pari4, is enabled.

Figur€ 10-59 Receiver andtmsmilter driven ar the same baudrate. (Relrinted by pqmission of InteiCorporation- Copylight/Inrel Corp.1987)

546 Input./Output Interface Circu'ts and LSI perjpherat Devices Chap. tO

Iigure 10-60 Mode instructiotrfomat. (Repnnted by pemi$ion ofInrel Corpontion. Co?yright/IntelCorp. 1987)

logic 0 in EP selects odd pariry, or logic I in this position selects even parity. To disableparity, all we need to do is reset PEN.

We wi]l assume that the 8251A is workiry in the asynchronous mode; therefore,bits Sr and S, determine the number of stop bits. Note that if l1 is loaded into these bitpositions, the character is fansmitted with 2 stop bits.

EXAMPLE iO.30

Wlat value must be written into the mode control register in order to contrgure the 8251Asuch that it works as an asyncbronous communications controller with the baud rate clockintemally divided by 16? Chancter size is to be 8 bits; parity is odd; and one stop hitis used.

Solution

From Fig. 10-60, we find ahat B2Br must be set to 10 in order to select asynchronousop€ration with divide-by-16 for the extemar baud clock input.

BrBr : 10

To select a chamcter length of 8 bits. dle next 2 bits are both made logic 1. This gives

' . - 1 1

To set up odd paritt EP and PEN must be made equal to 0 and 1, respeclively-

E P P E N : 0 1

Finaly, SrSr are set to 01 for one stop bit.

s,sr : 01

Programmable communication Int€rface conttolle6Sec. 10.I l 54'

Therefore, the cornplete control word is

DrDe . . Do : 01011110,

Once the conli$mtion for asynchronous communications has been set up in themode control registet the microprocessor controls the operation of the serial inrerface byissuing conmands to the cornmand register wirhin rhe 8251A. The fomar of the command instruction byte and the function of each of its bits is shown in Fig. 10 61. Let uslook at the tunction of just a few of its bits.

TXEN and R\EN are enable bits ldr the transmitter and rcceiver. Since borh thereceiver and transmitter can operatb simultaneously, rhese rwo bits can borh be set. RXENis actually an enable signal to the RxRDy signal. It does not rum the receiver section onand off The receiver runs at all times, but if RXEN is sei ro 0, rhe 8251A does not signalthe MPU that a character has been received by swirching Rxmy to logjc L The same istrue lbr Txd. It enables the TxiDy signal.

The 8251A USART has a status rcgisrer rhat contains information related to irs cur-rent state. The status register of the 825 1 A is shown in Fig. 10 62. Birs panty enor (PE),overflow error (OE), and frane enor (FE) are eror flags for the receiver. If rhe incomingcharacter is found to have a parity enor the PE (parity enor) bit gets set. On the oiherhand, if an overrun or framing eror condition occurs, the OE (overrun error) or FE (frarn-

Figure 10-61 Comand instructionlbmat. (Retrilted by pemisiod ofInlel Corporanor CopyrightlrtelCorp. 1987)

548 Input/Output Interface Circuirs and Lst Periphefat Devices Chap. 10

I I I

FiguE 10-62 Status register(RepriDied by pemission of Int€lCorporation. Copyright/Intel Corp.1987)

ing enor) flag is se! respectively. Before reading a character from the receive data regis-

tei the MPU should always veriry that valid data has been received by examining these

ellor bits. If an error is identified, a command can be issued to the command register to

write a 1 into ihe ER bit. This causes all thiee of the eror flags in the status register to be

reset. Then a software routine can be initiated to cause the character to be retransmitted

Let us took at just one more bit of the comrund register. The IR bit' which stands

for inte al rcset, allows the 8251A to be initializ€d under software control To iniiialize

the device, the MPU simply writes a I into fte IR bit.Before ille 8251A can be used to receive or transmit characten, its mode control and

commanai registers must be inidalized. The flowchart in Fig. l0 63 shows the sequence

that must be followed when initiatizing ttte devic€ l-€t us just briefly trace thmugh the

sequence of evenls needed to set up the controller for asynchonous oPelatlon'

As $e microcomputer powers up, it should issue a hardwarc reset to the 8251A'

Switching its RESET input to logic I does this. AfGr this' a load-mode instruction must

be issui to write the new configuration b)4e into the mode-control regrster Assuming

rhat the 8251A is in the l/O adthess space of the 8088, the comrnand b)te formed in

Example 10.30 can be written to the command register with the instruction sequence

MOV DX, MODE REG_ADDR

MOV AI,, 5EHOUT DX, AI,

where MODE-REG-ADDR is a Yadable equal to the address of the mode jegister of the

8251A.

Sec, IO.l I Programmable Communication Interface controllers 54.t

Flgur€ 10-63 8251A injtializationflowchari (Relrilted by permjssion ofIfltel Cor?oration. Copyright/IntelCorp. 1987)

Since bits BrBl of this register are not 00, asynchronous mode of operation is'elerred. Therefore. ue go do$n rhe brancn n rhe floucban to rhe toad comm;d in.nuc-tion. Execution of another OUT instruction can toad tlle comrnand rcgister widr irs initialvdiue. For rn,tance. lhi5 conr,.nand coulo erable +e nansmirer and rccerrer b) .erring rheT{ .\ and R\r\ bill. re5pelri\el). Durijg |l. ope'rdtior rl-e .ralu, regLler can be rea.t bythe nxffoprocessor to detemine if ihe device has received the next byte, if ir is read)r tosend the next byte, or if any problem occured in the Aansmission such as a parity elTo.

EMMPLE IO.3I

The circuii in Fig. 10-64(a) irnplements serial I/O for rhe 8088 microprocessor using an8251A. !\nre a program rha, conrinuou.t) reads cer aJ characrers hom rhe RS 232Cinterface, complements the received characters with software. and sends them backthrough the RS,232C interface. Each character is received and ransmined as an 8_bircharacter using 2 stop bits and no parify.

Solution

We must llrst detemine ihe addresses for the regisrers in the 8251A rhar can be accessedI-om lhe microprccesor Interface. Ctup relecL rCSr i, enabled ior 1/O read or q rile oper-atrons to addresses for which

ATA6A5A4A3ArAr = 1000000

lnput,/Output Interface Circuts and LSt P€ripheral Devices Chap. i0550

D o - D z

RD

WF

clo

Microproc€ssor Signals

Do Dz

idF

iow

BaudClock = 19.2kHz

BS232Signals+12V

Data

A15Al4Al341rAr1AioAeAaA7A6AA&Ar&&

x x x 1 0 0 0 0 0 0 1 = x x 8 1 Hx x x 1 0 0 0 0 0 0 0 = x x 8 0 H

sz sr

1 1

I Bald Rars Facror = 16

EP PEN I4 LT 82 81

1__ 9 Lr L-9No. ol slop bits = 2

= EEH

Charact€rleieth=8bit(c)

nsur€ 10-64 (a) Inplementation of senal I/O using the 8251A. (b) Addr:sl.fol.the8251A registers. (c) Mode word. (d) conrnand word. (e) Flowchart for initialization'@€iv€ operatioa, md trmnit opstion. (I) Progran for tle implementedoD of initl€l-ization. receive operation. and transmit oFmtiotr

551

EH IR RTS

0 0 0

ER SBNK

1 0

RXEN DTR TXEN

1 0 1

Figu.e 10-64 (contjnued)

Bit Ao of rhe address bus is used to select between rhe data and control (or status) regis-ters. As shown in Fig. 10-€4(b), the addrcsses for rhe daia:nd the control (or status) reg-ister are XX80H and XX81H, respecrively

Next we must detemine the mode word ro select an 8,bit character with 2 srop birsand no parity. As shown in Fie. l0 64(c), the mode word is EEH. Here we have used abaud rate factor of 16, which means thai the baud rate is given as

Baud rate = Baud-mte clock/16 : 19,200/16 : 1200 bps

To enable lhe transmitter as well as receiver operation of rhe 8251A, the requiredcommand word as shown in Fig. 10-64(d) is equal io 15H. Note lhat error reset has alsobeen inplemented by making the ER bit equal 1.

The ffowchat ofFig. 10 64(e) shows how we can write software ro implemenr ini-tialization, the receive operation, and iransmir operation. The Fogram wdnen to performtbis sequence is shown in Fig. l0-64(f).

Initializaiion involves witing the mode word followed by lhe command word to thecontrol register of the 825 1A. It is important to rote rhai rhis is done afler the device hasbe€n reset. Since the contol register's I/O address is 8 lH, rhe rwo words are output to thisad&ess using appopriate inslructions.

The receive opemtion starls by reading the conrents of the status regisrer ar adahess81H and checking if the LSB, RriDy, is at logic 1. ff it is not l, the routine keeps read-ing and checking until ir does become L Next we read the data register at 80H for rhereceive data. The byre of data rcceived is complemented and then saved for transmission.

The tsansmi! opemtion also srarrs by reading the starus rcgister ar address 81H andchecking if bit 1, TxRry, is logic 1. ff it is not, we again keep reading and checking untit irbe.omes L Next, the byte of daia that w2s saved for rransmission is written ro the data rcgis-ter at address 8lH. This causes it to be transmitted at the serial interface. The rcc€ive atrd irans-mit opemtions are repeated by jumping back to the poinr wherc rhe receive opemtion begins.

4250/16450 UART

The 8250 and 16450 are pin-for-pin and tunctionally equivalent universal asyncbro-nous rcceiver tralsmitter ICs. These devices are newer rhan the 825 I A UART and implemenr

552 Input/Output Inteface Cjrcuirs and LSt Peripherat Devices Chap. I0

II1II

TI

II

Fieu.e 10-64 (continued)

a more versatile serial I/O operalion. For instance, they have a built-in prcgranmable baud-rate generator, double bufiering on communication data rcgisters, and enhanced status andintenupt signaling. The common pin layoxt for these devices is shown in Fig 1H5(a).

The connection of the 8250/16450 to inplement a simple RS-232C seriat colnmu-

nications interface is shown in Fig. 10 65(b). Looking at the microprocessor interface, we

Sec. Programmable Communicatioh Interface Controller 553

Fisrre 10-65 (a) Pin layout of the8250/16450 UART. (Counesy ofNational Semiconductor Corporation)(b) 8250/16450 RS-232C interfac€.(Coullesy of Nalional Seniconductor

find chip-select inpuls CSo, CSr, and CS,. To enable the inGrface, rhese inpnts must be atlogic 1, 1, and 0, respectively, at the same time that address strobe (ADS) is logic 0.Iheretore. rhe inrenace in l-i8. l0 h5rb, i\ enable.d whenever logrc 0 n applied ro -5.hom the MPU'S bus.

Let us next look at how data are read ftom or wrinen inro ihe regisrers of the8250/16450. Data transfers between the MPU and comnunicarion conrrolter rale placeover daia bus lines Do through D?. The MPU signals rhe peripheral wherher a data inputor outpur oper:r ion i \ lo occur s ih rhe logic le\el dt rne aau-inpur .rrobe TDISIR ' anddaia-ouQut strobe (DOSTR) inpuis. Note that when data are output during a memorywnre or ourpu' bu. clcle. rhe \4PU noiifie, rhe 8250/10450 uirh logic 0 on rhe MEMW-or vOW signal line, which is applied to the DOSTR input.

554 lnput,/Output Interlace Circuitr and LSI Peripherat Devices Chap. l0

During the read or write bus cycle, the register that is accessed is detemined by thecode at rcgister select inputs A,o, Ar, and Ar. Figwe 10 65(b) shows ihal these inputs areattached to address lines A0 through Ar, respectively. The registers selected by the variousregister-select codes are shown in Fig. 10-66. Note that the setting of the divisor lalch bit(DLAB), which is in the line-control rcgister is also involved in the selection of the register. For example, to write to lhe line conaol register the code at ArA1A.0 must be 01lr'Morcover, to read the receive buffer regjstet the DLAB bit in the line-contol rcgister musttust be set to 0 and then a rcad perforned wifi register-select code A2ArAo equal to 000r'

The firnction of the various bits of the 8250/16450's registers is summarized in thetable of Fig. 10-67(a). Note that the receive buffer register (RBR) and transmitter holdrcgister (THR) conespond to the read and wriie tunctions of regisler 0 However, as mentioned earlier to perfom these read or write operations the divisor latch bit (DLAB), whichis bit 7 of ille line coDtrol register (LCR), must have aheady been set to 0. From the lable,we find that other bits of LCR are used io define the serial character data structure. Forinstance, Fig. 10-67(b) shows how the ilord-length sekct bits, bit 0 (WLS and bit 1(WLS j) of LCR, select the number of bits in the serial ch?.l?.cter Bit2, number ol stop bits(STB), selects the number of stop biis. If it is set to logic 0, one stop bit is generated forall transmitied data. On the other hand, if bit 2 is set to 1, one and a half stop bits are pro-duced if charact€r length is set to 5 bits and 2 stop bits are supPlied if character length is6 or more bi!s. The next 2 birs, bit 3 pait! enable (PEN) ^ld bn 4 eren paritr select(EPS). are used io select parity. First parity is enabled by making bit 3 logic I and theneven or odd parity is selected by maLing bit 4 logic I or 0, respectively. The LCR can beloaded with the appropdate configuration infomation under soltware control.

Figure i0 65(b) shows that the baud-raie generator is operated off a 3 0?2-MHzcrystal. This crystal ftequency can be divided within $e 8250/16450 to Foduce a varieiyof data conmunication baud rates. The divisor values lhat produce standard baud rates areshown in Fig. 10-68. For example, to sel lhe asynchronous data communication rate to300 baud, a divisor equal to 640 rnust be used. The 16 bit divider must be loaded undersoftware contrdl into fie divisor latch registers, DLL and DLM. Figure 10-67(a) showsthat the eight least significant bits of the divisor are in DLL and the elght most significantbits in DLM.

0

11

0

00

10

0

0

0

0

I0

Rdivd Buftor (6ad),

Figm 10-66 RegisteHelert codes.(Courtesy of National Seniconductor

S e c . l 0 . l I Programmabre Con"-unrcation lnrerface ControllFrs 555

Et!0 otAt- o ODL B-O i DLAB=O 0 DLAB= i i DLAB= I

E!|l.r

Only)

Holdlnt ltoDEll

Gl)(r*t)

FBF THF IEF F L5h 3Ch DLL

o Dat Bilo.

IEFBF1I

(DTR) (DO[S)

Bho Bho Elt S

1ID

Bn (0)Blt 1

(RTS) (o9

{0DsF)

B h 1 Bir 1 Ett I

2 Data Bn 2 D!t! Btt 2

IELSl)

IDBfi (1)

Slop 8ll!(sTB)

our 1Eror(PE)

TIrlllngEdge Flnt

fiEFD

Blt 2 Btt2 B h l o

3 0.!a Blt I o.ll Elt3MOOEM

{EDSSD

o(PEN)

Oul2 o.lL

(DDC0)

8h9 Eir 3 Blr 11

IEPSI(8D

tcTsl

Bh4 Bir 4 gft12

flHFA (DSF)

Bit 5 Bir 13

Dard Bir 6 o

OEMT) (FD

Bit 6 Blt6 Bi t14

o

BN(DLAB)

0

(DCD)

Bit T Bh7 Bi t15

.Bn 0 b b. hlt .ledieir bt r rr b. iEr bh Eddt @{nnrd d @Md

h )

{b)

t h 1 dlt 0

11

oI

5 BltB6 Bh!

Figure 10-67 (a) Regisler bit tucnons. (Courtesy of National Semiconductor Corporation) (b) Wordlength selecl bils. (Cou.tesy of National Semiconductor Corporatio!)

556

5o

1to

150

12001300200024oO960O

7200

1E200la4oo

25€O17r(tt2a1230

320

taao5t

201 0

o.izs':'

_0.623

Figure 10-68 Baud rates mdcorcsponding .!viso6. (courtesy ofNational Semiconductor Corporation)

EMMPLE I0.32

Wlai count must be loaded into the divisor latch regisrers to set the data communicationrate to 2400 baud? What register-select code must be applied to the 8250/16450 whenwdting the bytes of the divider count inio the DLL and DLM registers?

Solution

Looking at Fig. 10-68. we find that the divisor for 2400 baud is 80. wlen writing theb)'te into DLL, the ad&ess must make

ArArAo : 000, with DLAB = I

and the value that is written is

D L L : 8 0 : 5 O H

For DLM, the address must make

ArAlA{ = 001, with DLAB = I

and the value is

D L M : O : O O H

l,et us now tum our attention to the righl side of the 8250/1&150 in Fig. 10-65(b).Here the RS-232C serial communication inteface is implemented. We find that the trans-mit data are outpur in serial folm over the serial output (Sou.r) line. and receive data areinpot over the serial input (SN) line. Handshaking for the asyncfuonous serial interface is

sec. 10.11 ProgrammableCommunicationlnterraceContrcllers 557

implernented with the request to send 6-TD and data terninal readv (DTR) outputs and

th; data set ready G)SR), daia carder detect (DCD), clear to send (CTS-), and riry indi-

cator (RD inputs.The serial interface input/output signals are buffered by EIA ddven for compari-

bility with RS-232C voltage levels and drive cunents. For example, a MC1488 driver IC

can be used to buffer the output lines. It contains four Tn- level to RS-232C drivers' each

of which is actually a NAND gate. The MC1488 requircs + 12V 12V, and gound sup-ply connections to provide the mark and space transmission-voltage levels The gates of

a MCl489 RS-232C to TTL level ddver can buffer the input lines of the interface TbisIC contains four inverting buffers with tristate ouQuls and is operated from a single +5v

supply. Figure 10 69 shows an RS-232C tuerface including the EIA airiver circuitry.

IO.i2 KEYBOARD AND DISPIAY INTERFACE

The keyboard and display are impofant input and oulput devices in microcomputer sys-

tems such as the PC. Different types of keyboards and displays are used in many other

-t072 MHz

CONNECTOB

rigurc 10-69 RS-232C ilterfa@ wift EIA driv6

Input/Output Interface Circuits and LSI Peripheral Devices chap. l0

GND(vss)

BAIDOUi

33r Sun outz

sour6lsiF srN

rsrR csollr

558

types of digital electronic systems. For insiance, all calculators and hand-held computershave both a keyboard and a display; also many electonic tesl instruments have a display.

The circuit diagram in Fig. i0 70 shows how a keyboard is most frequently inter,faced to a microcomputer. Note that the switches in the keyboard are aranged in an dndlThe size of the array is described in terms of fie nunber of rows and fte number ofcolumrs. In our example. the keyboard array has four fows, labeled I{n through Rr, andlbur columns, labeled Co thrcugh C3. A row and a column uniquely define the location ofthe switch for any key in the array. For instance, the 0 key js localed at the junction of R0and C0. whereas the 1 key is located at Ro and Cr.

Now that we know how the keys ol the keyboard are arranged, let us look at howthe microcomputer seflices them. In mosl applications, the microcomputer scans the key,board araay. That is. it strobes one row of the keyboard after the other by sending out ashort-duration pulse. to the 0logic level, on fte row line. During each row strobe, all colulnn lines are examined by reading thern in parallel ])rpically, ihe column lines are pulledup to the 1 logic level; therefore, if a switch is closed. a logic 0 will be read on the cor,responding column line. If no switches are closed, ali ls will be read wher the column

For instance, ifthe 2 key is depressed when the micrccomputer is scanning Ro, thecolumn code read-back wil be CaCrCrCo = 1011. Since dre microcomputer knowswhich row it is scanning (Ro) and which column the strobe was retumed on (C,). it candetemine thai the number 2 key was depressed. The microcomputer does not necessarilystore the row and column codes in the folm that we have shown. It is more conmon lojust maintain the binary equivalent of the row or column. In our example, the microcomputer would inremally store the row number as R0 : 00 and lhe colxmn number asC, = 10. This is a more compac! representation of the row and column information.

Several other issues arise when design g keybofids for micrccomputer systems.One is that when a key in the keyboard is depressed. its contacts bounce for a short periodof time. Depending on the keyboard sampling me$od. this could result in inconect read-ing of the keyboard input. This problem is overcone by a technique known as lelroarddebouncing. Debo.ulr,cine is achieved by resampling the column lines a second tlme, aboutl0 ms later, to assure that rhe same column line is at the 0logic level. If so. it is thenaccepcd as a valid input. This technique can be implemented either in hardware or

Another Foblem occurs in keyboaJd sampling when more than one key isdepressed at a rime. In this case, the column code rcad by the microcomputer would havemore than 1 bit that is logic 0. For instance, if ihe 0 and 2 keys werc depressed, lhe col-umn code read back during the scan of & would be CaCrClCo = 1010. Typically, twokeys are not actually deFessed at the same time. It is more common that the second keyis depressed while the first one is still being held down and lbat the column code show-ing two key closures would show up in fie second test thar is made for debouncing-

Several different reclniques are used to overcome this problem. One is called ,wo-n") lock &r With ihis rnethod, the occurrence of a second key dudng the debounce scancauses both keys to be locked out, and neither is accepled by the micrccomputer. ff rhesecond key that was depressed is released before the first key is released. the fiffr keyeniry is accepted and the second key is ignored. On the other hand, if the lirst key isreleased before the second key, only the second key is accepted.

sec. 10.12 Keyboard and Display lnterface 55t

t gte

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A second method of solving this problem is that known as N-fO ,?llover In thlscase. nore fian one key can be depressed at a lme and be accepted by the micmcom-purer. The microcomputer keeps track of the order in which they are depressed and aslong as rhe switch closures are slill prcsent at anotber keyboard scan 10 ms late! they areaccepted. That is, in the case of multiple key depressions. tbe key entries afe accepted inthe order in which their switches are closed.

Fieure 10-? I shows a display interface used in many microcomputer systerns. Herewe are using a four-digit, seven segment nuneric display. Note that segment lines athrough g of a digits of the display are driven in parallel by outputs of tbe microcom-puter It is over these lines that the miffocomputer outputs sjgrals to tell the displaywhich segments are to be lighted to form numbers in its digits. The way in which the seg-ments of a seven-segment display digit are labeled is shown in Fig. 10-72. For instance,to form the number 1, a code is output to light only segments b and c.

The other set of lines in the display interface conespond to the digits of the display.These lines, labeled D0 through D1, correspond to digits 0, 1, 2, and 3, respectively. It iswith these signals that the microcomputer rells the display in which digit lhe number cor-responding to the code on lines a through g should be displayed.

The way in which the display is driven by lhe microcomputer is said to benultiplexed. That is, dara are not permanently displayed; instead, ihey are output to onedigit after the other in tirne. This scanning sequence is repeated frequently so the usercannot recognize the fact that the display is not pemranendy Lighted.

The scanning of the digits of the display is similar io the scanning we have justdescribed for fie rows of the keyboard. A digit drive signal is output to one digit of thedisplay after fte orher in time and dwing each digit-ddve pulse the seven-segment codefor the number to be displayed in that digit is output on segment lines a through g. In fact,in most systems the digit drive signals for ihe display and row-drive signals of the key-board are supplied by the same set of outputs.

A IO.I3 8279 PROGMMMABLEKEYBOARD/DISPLAY CONTROLLER

Here we will introduce an LSI de\ice, the 8279 proqrannable kzyboard/displal inteF/dca which can be used to implement ketboard and display interlaces similar to thosedescribed in the previous secdon. Use of the 8279 nakes the design of a keyboard/displayinterface circuit quite simple. This device can drive an 8 x 8 keyboard swiich aray anda 16 digit, eight segment display. Moreovet it can be conligured through software to sup-port key debouncing, two-key lockout, or N key rollover modes of operatio[ and eitherlelt or dght data entry to the display.

A block diasram of the device is shown in Fig. 10 73(a) and its pin layout in Fig.10 73(b). FIom this diagram we see that there are four signal sections: the MPU inter-face. the key data inputs, the display data outputs, and the scan lines used by both ihe key-board and display. Let us first look at the function of each of these inlefaces.

The bus interface of the 8279 is similar to tbat found on the other peripherals wehave considered up to this point. It consists of ihe eight data bus lines DBo through DB7.These are the lines over which fie MPU outputs data to dre display, inputs key codes.issues commands to the controller and rcads status information from the controller Othcr

Sec. 10.13 8279 Programmable Keyboard/DisplayConlrolJer J6l

iE

EE

-

B*

+>: . gP? e=

552

Figure 10-72 Seven-segmen!displaylabeling.

signals found at the intedace are the read (RD), write (wR), chip-select (CS), and addressbuffer (Ad control signals. They are the signals that control the data bus transfeff takingplace between the microprocessor and 8279.

A new signal introduced with this interface is inte upt rcquest (lRQ), an ontputthat gets .etumed to an interrupt input of the microcomputer This signal is provided sothat the 8279 can tell rlle MPU i! contains key codes that should be read.

The scan Lines are used as low-drive signals for the keyboard and digit-drive signalsfor the dispiay. There are just four of these Lines, Sh drough SL3. However they can beconfigued for two different modes of operation through software. In applications tharrequire a small keyboard and display (four or less rows and digits), they can be used inwhat is known as the d€coded mode. Scan ontp\tt \\avefon$ for this mode of operationare shown in Fig. 10 74(a). Note that a pulse to the 0 logic level is produced at one output afler the other in time.

The second mode of opemtion, called encoded mofu, allows use of a keyboaxdmatrix witlr up to eight rows and a display with up to 16 digits. When this node of oper-ation is enabled tkough software, the binary-coded waveforms shown in Fig. 10 74(b)are output on the SL lines. These signais nust be decoded wiih an extemal decoder cir-cuit to produce the digit and column ddve signals.

Even though 16 digitdrive signals are produced, otrly 8 row-drive signals can beused fbr the keyboard because the key code that is stored when a key depression has be€nsensed has just 3 bits allocated io identify the row. Figure 10 75 shows this kind of cir-cuit configuation.

The key data lines include the eight retum tines. RLo ttuough RIr. These linesrcceive inputs from the colulnn outputs of the keyboald array. They are not tesied all atorce as we described earlier Looking at the waveforms in Fig. 10 76, we see that the RLlines are examined one after the other during each 640-ps row pulse.

If logic 0 is detected at a return line, the number of the column is coded as a 3-bitbinary number and combined with the 3-bit rcw number to make a 6-bit key code. Thiskey code input is first debounced and then loaded into an 8 x 8 key code FIFO within the8279. Once the FIFO contains a key code, the IRQ output is automatically set to logic 1.This signal can b€ used io tell the MPU that a keyboard input should be read ftom the8279. There are two other signal inputs in this section: shift (SHIFD and control/strobed

Sec. 10.l3 A279 Prcgtammable KeyboardlDisptay Conrrolter 563

FD

WR

E-D

Flsule 10-73 (a) Block diasim of the 8279. (Reprinted by pmission of Intel Corpo-ration. Colyright/Iltel Corp. i987) (b) Pin layout. (Reprinted by pemi$ion of IntelCorpoiation. Copyrightlnt€l Corp. 1987)

(CNTL/STB). The logic levels at these two inputs are also stored as part of the key codewhe! a switeh chsure is detected. The fornat of the complete key code byte storcd inFIFO is:hosn io Fie. 10-77.

A status regjster is pmvided within the 8279 ihat contains flags indicating the sta-t.d:s of the Lzt code FIFO. The bits of the status register and their meadngs are shown inFig. 10-78. Note that the three least signifiaant bils, labeled NNN, identify the nlmber of

v " 6

3a

27

3

554 Input/Output lnterfac€ Circuits and Lsl Peripheral Devic€s chap. I0

)!i [_l u tJ u

,arffi

"'ffitarffi

- l r -

Itsule 10-74 (a) Daoded modescan line sienals. (Reprinted bypermi$io! of Iltel Cor?oratio!.Copldeht^ntel Cor!. i987)(b) Encoded'mode sce line sisnats.(Reprinted by lemision of IntelCorporation. Copltighvtnt€l Corp.1987)

'hm

",ffisL, r------ l-]sL, l----------l

key codes currently held in the FIFO. The next bit, F, indicates whether or nol the FIFOis full. The two bits that lollow it, U aDd O, reFesent lwo FIFO erlor conditions. O,which stands for overrun, indicates thai an attempt was made to enter another key codeinto the FIFO, but it was already full. This condition could occur if the microprocessordoes not respond quickly enough to the IRQ signal by rcading key codes out of the FIFO.The other eror condition, underun CJ), means that drc microprocessor attempted to readthe contents of the FIFO when it was ernpty. The microprocessor can read tbe contentsof the status register under software control,

The display data Lines include rwo 4-bit output pofts, Aqr through A3 and B0 ttrough

&, that are used as display segment drive lines. Segment data that are output on lheselines are held in a dedicated display RAM area within the 8279. This RAM is organized16 x 8 and must be loaded with segment data by the microprocessor Figure 10-76shows that during each 640-FS scan time the segment data for one of the digits are outputat the A and B pofis.

The opemtion of the 8279 must be configued through software. Eight corDmandwords are provided for this purlose. These control words are loaded into lhe device by per-forming wdte (output) operations to the device with buffer address bit A0 set to logic 1Let us now look briefly at the function of each of these control words.

fte first command (command ward 0) is ]used to set the mode of operation for thekeyboard and display. the general format of this word is shown in Fig. 10 79(a). Here wesee that the tnrce mosi significant bits ale always reset. These 3 bits are a code by whichthe 82?9 identifies which command is being issued by the miooprocessor. The next 2 bits,labeled DD, are used to set the mode of operation for the display. The table in Fig.10-79(b) shows the options available. After power-up rcset, these bits are set to 01. From

Sec. I 0. I 3 82 7 9 Progfammable Keyboard/Display Controller 565

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566

Preler prosnmmed for int m.l

SD

lEq*ncy = r(r0kHzb rc, - t0/s

FT ^. h--;=rL -i_( :t:1:I

r-shFBtot Bt

30 80

60 Il, - I F-co.dhio.d wne to FIFo

40$ - l<- RLo s.r6Ed. raehedR.tom li* ae smpled on.d a !d ar iho*n

Note: Shom G encoded *an Ieft enrys?- q .re rct shoM but rh€v areiimp'y q divided bv 2 and 4

figu.e 10-76 Keyboard md display signai riming. (R€prified by lemission of IntelCoryoEtion. Coplright[ntel Corp. 1987)

the table we see that this confgures the display for 16 digits wirh left enrry. By left enrrywe mean that characters are entered into the display starriDg from the left.

The three least significant birs of lhe command wod (KKK) ser rhe scan mode ofthe keyboard and display. They arc used to configue the operarion of rhe keyboardaccording to the table in Fig. r0 79(c). The defauh code ar power up is 000 and sele.rsencoded scan opemtion wiih rwo key lockour.

EMMPLE I0.33

What should be the value ofcornmand word 0 ifrhe display is to be set for eighr S-segnentdigits with righr efty and the keyboard for decoded scan with N,key rolover?

Figure 10-77 Key code byte forut.(Repri ed by lemission of lntelCorporation. Copyright,alntel Corp.r9E7)

sec . t o . l 3 8279 Proqrammable Keybodrd/DEplay Controllel 567

Iiglre 10-7E Status €glsier{tepnnted by_pemission of lrelcorporadon. LoPlngnv Lnr I L orp1987)

I'tgure 10-79 (a) CoImad word 0forna!. (Reprinted by pemissioD ofIntel corporation. copyright/ItrtelCor!. 1987) (b) Dis?lay mode selectcodes. (Repnnted by pernission ofIntel Corporatior. Coplright/IntelCorp. 1987) (c) Keyboed select codes.(Repri ed by Fmission of IntelCorporation. CopltiSht/Itrlel Corp.1987)

o l o l r l P l P l P l P l P

Figue 10-E0 Conrnand word Ifomar (Reprinted by permlssio! ofIniel Corpomtion. Copynght/Iltelcorp. 1987)

0 D D K K K

D D

0 l

l 0

8 &bit chancr.r dkpl.y - llfi.nrry

l6 &bn chrncr.rdjrpby - L.ft enrry

3 3-bit chancr.r dktlay - Righr.nky

l6 3+n ch.r..tc!dilpby.. Risht.nty

K K K0 0 0

0 l l

1 0 0

t l r

E dd.d Scrn K.ybo.rd l-Key t ckolr

D.cod.d Scar K.ybo.d 2-K.y Lo.kou!

Encod.d Sc.n kyboard N-(.y Roltov.r

D.@d.d Sdn K.ybo.rd - N-Kcy Rollov.r

En.od.d Son SensrM.tlx

D4oded S.2n s.isrMstir

Stob.d I'put, Encod.d DisDlay Scrn

Slrob.d lnplt, D.cod.d Dilplay Scrn

564

1 Co Co

1 0

AllZ.ro! lX - Oonl clrrl

AA = H.r 20 10010 0OO0r

En.bl.cl... displ.v wh.n = I lor bv CA = ll

Fig@ 10-81 (a) Cormand word 6 forlnai. (Replinted by permission of I elcoryoration. Co!,rishtlntel Corp. 1987) (b) CD coding. (Repnnt€d by permisiotr of Intel Corporution. Copyright/Intel Colp. 1987)

Solution

The tbree MSBS of the conmand word are always 0. The rcxt 2 bits, DD, must be set to10 for eight 8 segmeni digits with.ight enty. Finaly, the tbr€e LSBS are set to 011 fordecoded keyboard scan with ff-kq rolover. This gives

Cornmand word 0 = 000DDKKK

= 00010011,

Command i'ord 1 is used to set the frequency of operation of the 8279. It isdesigned to run at 100 kHz; however, in most applications a nuch higher ftequency sig-nal is available to supply its CLK input. For this reaso\ a s-bit proqwvnabk prcscalcris provided within ttte 8279 to divide down the input frequency. The fomat of this com-mand wod is shown in Fig. 10-80 (p. 568).

For instance, iD a 5-MHz 8086-based microcomputer system, the PCLK ourput ofthe 8284 clock ddver IC can be used for the 82791 clock input. PCLK is one-half the fre-quency of the oscillator or 2.5 MHz ln this case *Ie divider P must be

P : 2.5 MHz/100 kHz : 25

tuenl)-6ve expres.ed a. a 5-brt brna4 number is

P : 1 1 0 0 1 2

Figur€ 10-82 comard wdd 7fbrmat. (ReprinM by lemisior ofhtel Comoralion. CoovrishvlnFl

x . oon r ca.e co|! 1987)1 L 1 l r l E l x l x l x l x

s e c . l O . l 3 4279 Ptogtammable KeyboardlDisplay Controller 569

0 t l t 0 t a r t x t A t a t A

Figure 10-83 Co,r'mand word 2forDat. (Reprinted by pemission of

r=o".',c*" 8j1:i#iation copvrishu er

Therefore, tbe value of command word 1 written to the 8279 is

Command word 1 : 001PPPPP, : 00111001,: 3 9 ' o

Let us skip now to crnrna"rd vr'ord 6 beca'rse ]t is also used for initialization of the8279. li is used to iniiiaUze the complere display memory, the FIFO status, and the inter-rupi-rcquesi ouQur 1ine. The fomat of fiis word is given in Fig. 10-81(a) (p. 569). Thethree CD bits are used to control initialization of the display RAM. Fig$e 10 81(b)shows whal values can be used in these localions. The CF bit is Fovided for clearing theFIFO status and resetting the IRQ line. To perform the resel operation, a I must be writ-ten to CF. The last bit, clear a1l (CA). can be used to initiate both the CD and CF tunctions.

EXAMPLE ]0,34

What clear operations are pedorned if the value of conmand word 6 wrilten lo the 8279is D216?

SolutionFirst, we exFess the command word in binary form. This gives

Commandword6: D2r6 = 11010010,

Note ihat the 6ree CD birs are i00. This combinadon causes display memory to becleared. The CF bit is also set, and this causes the FIFO shius and IRQ output to be reset.

As Fig. 10 82 (p. 569) shows, only one bit of con'n zd word 7 is funciional. Thisbit is labeled E and is an enable signal for \yhat is called the special-error mode. Whenthis mode is enabled and the keyboard has N-key rollover selected, a multiple-key depres-sion causes the S/E flag of the FIFO status register to be sei- This flag caD be read by themicroprocessor though software.

Figurc 10-84 CoImDd word 4fonnal. (Reprinted by penision ofhlel Corporadon. Copyriglt/IltelCorp. 1987)l l 0 l 0 l a r l a l A l a l A

570 Input/Output lnteface Circuits and LSI Peripheral Devices Chap. lo

The rest of the command codes are related lo accessing the key code FIFO and dis-play RAM. The key code FIFO is read only. However, before the microProcessor canaccess it. a read FIFO command must be issued to the 82'79.This is conmand wo 2 andhas ihe fomat shown in Fig. 10-83. When the 8279 is se. up for keyboard scanning, theAI and AAA birs are donl-care states. Tben all that needs to be done is to issue the com-mand 01000000, : 4016 to the 8279 and initiate rcad (input) cycles lo the ad&ess of lhe8279. For each read bus cycle, the key code at the top of the FIFO is read into the MPU.

The display RAM can be either read from or written into by the MPU. Just like forthe FIFO. a cornmand must be sent to the 8279 before reading or writing can be initialed.For instance, when the microprocessor wants 10 send new data to the display, it must firstlssne command word 4. This cornmand has tbe formai shown in Fig. l0 84. Here theAAAA in the four least significant bit locations is the address of the first location to beaccessed. For instance, if 0000, is put into these biis of the command, the first write oper-ation will be to the first location in display RAM. Moreover if the AI bi! is set in the com-mand, autoincrement addressing is enabled. In ihis way, the display RAM address pointeris automatically incremented after the write opemtion is complete and a write cycle canbe initiated to address 0001, of display RAM without first issuing another write

The MPU can also read the conients of the display RAM in a similar way. Thisregrrjles $at cotn'Mnd wor.d J be issued to the 8279. Figurc l0 85 shows the fbmat ofthis read disDlav RAM corffnand.

REVIE! ( / PROBLEMS

Sect ion 10 . Il. Give three examples of the special-purpose input/output interfaces of a micro-

2. List tfue€ core input/output intedaces commonly used in microcomputer systems.

Section 10.23. What is the ad&ess ofpod 7 in the circuit shown in Fig. 10 1(a)?

4. what are the inputs of ihe I/O address decoder in Fig. 10-1(a) when the I/O addresson the bus is 8004.16? Which output is active? Which output port does rhis enable?

5. What operation does the instruction sequence that follows perfom for the circuit inFis. 10-1(a)?

M O V D X , 8 0 O 4 HOUT DX, AI!

Figurc 10-85 Command woid 3fomat. (Reprinled by pemlssion ofIntel Coryoration. copynelt/InielCorp. 1987)

5 t l

6. Write a sequence of itrstructions lo outf,ur the word contenrs of the memory locationcaled DATA to output ports 0 and 1 in the circuit shown in Fig. 10 1(a).

Section lO.37. Wlich input port in the circuit shown in Fig. l0-3 is selecred for operation if the I/O

address output on the bus is 8008t6 ?8, What operation is peformed to the circuit in Fig. 10 3 when the instrucrion sequence

that follows is executed?

MOV DX, 8000tlIN AI-, DXAND AIT, OFIi!4OV ILOW NIBBLE], AIJ

9. Wfte a sequence of instructions io lead in rhe conrents of ports I and 2 in the circuitshown in Fig. 10-3 and save them ar consecurive memory addresses .4000016 andA0001,6 in memory.

10, Write an insaucdon sequence that polls input 163 in the circuit shown in Fig. 10-3,checking for it to switch to logic 0.

Section 10.411. Name a method that can be used to syncbroniz€ the input or output of informaiion ro

a peripheral device.12. List the control signals itr the parallel prinrer incrface cncui( shown in Fig. 10 5(a).

Identify whether they are an input or outpur of the printer and briefly describe theirtunctions.

13. Wllat type of device provides ihe data tines for the pdnrer interface circuit shown inFig. 10 6(d)?

14. cive an overvieq, of what happens in dre circuit shown in Fig. 10 6(d) when a writebus cycle of blte-wide data is performed ro I/O address 800016.

15. Show what push and pop instructions are needed in th€ program wdrten in Exam-ple 10.6 to prese e the contents of r€isters used by it so that it car be used as asubroutirc-

Section 10.5f6. W}}at kind of itrput/oulput interfac€ does a PPI imptement?17. How many I/O tines are available on the 82C55A?1E. Wllat arc drc signal namer of ihe I/O porr lines of rhe 82C55A?19. Describe the mode 0, mode 1, and rnode 2 I/O operarions of rne 82C55A.20. w}lat tunctiou do the lines ofport B ofthe 82C55A serve when port A is configured

for mode 2 opeEtiotr?21. How is an 82C55A configwed if irs control regisier conrains gBH?

.\ 22. ff the value A416 is wrinen ro the contol rcgisrer of an 82C55A, what is the modeand I/O configuratiotr of po{ A? Port B?

Ar2 lnput/OLrtput Interra.e Circuits anct 6t Peripherat Devices Chap. l0

23, Il ports A, B, and C of an 82C55A are to be configured for mode 0 operation, wherethe A and B ports are inputs and C is an output port, what is the conlrol word?

24. \Yhat value must be wniten to the control register of rhe 82C55A to configlre thedevice such fhat both port A and Port B are configured for mode I input operation?

25. ffthe control register ofthe 82C55A in problem 23 is atI/O address 1000ft, \t iE an

instruction sequence that will load the control word

26. Assume thal the cont ol register of an 82C55A resides al memory ad&ess 0010016.Write an instruction sequence to load it with the control word fomed in problem 23

27, What control word must be wriften to the controt rcgister of an 82C55A shown inFig. 10-15(a) to enable the INTRB output? INTEB corresponds to bit PCl of port C.

28. Ifthe value 0316 is written to the control reglster of an 82C55A set for mode 2 oper-ation, what bit at pofi C is affected by the bit set/reset operation? Is it set to I or

cleared lo 0?29. Assume that the control register of an 82C55A is at UO address 010016. Write an

instuction sequence to load it with the bit set/reset value given in problem 28.

Section 10.630. If I/O address 003Er 6 is applied to the circuit in Fig. 10-21 during a bvte-write cycle

and the data output on the bus is 9816, which 82C55A is being accessed? Are databeing written into port A. pon B, port C, or ihe control register of this device?

31. If the instruction thal follows is executed, what opemtion to the l/O interface circuit

in Fig. 10-21 is perfomed?

IN 4I,, O8H

32. Wtat are the addresses of the A, B, and C ports of PPI 2 in the circuit shown inFig. 10-222

33. Assume lhat PPI 2 in Fig. 10-22 is conigured as defined in problem 23. Write a pro-gram that wil input the data at Ports A and B. add these values together' and outputthe sum to port C.

Section 10.734. Distinguish beween memory-mapped I/O and isolated I/O.

35. Wllat address inputs must be applied to the circuii in Fig l0 23 in order to accessport B of device 4? Assuming that all unused bits are 0, what would be the memoryad&ess?

36. Write an instruction that will load the control register of the polt identified in plob-

lem 35 with the value 98!6.

37. Repeat problem 33 for the cncuit in Fig. 10 24.

Section 10.838. wlat are the inputs and outputs of counter 2 of an 82C54?

39. Write a control word for counter I that selects ihe following options: load least sig-nificant b]te only, mode 5 of operation, and binary counting.

5r3

40. What are the logic levels of inputs CS, RD, WR, Ar, and A0 when rhe byte in plob-lem 39 is written to an 82C54?

41, Write an instruction sequence that loads the coDtrol word in problem 39 into an82C54, starting at address 0100016 of the memory address space. ArA0 of the nicro-Focessor are directly connected to ArA0 of rhe 82c54.

42. Write an instruction sequence lhat loads the value 1216 into rhe least significant byteof the count regisier for counter 2 of an 82C54, starting at nemory address 0100016.ArA0 of ihe midoprocessor are directly connecred to ArA0 of rhe 82C54.

43. Repeat Example 10.19 for the 82C54 located at memory addrcss 0100016, but thistirne just read the least significant byte of the counter. ArAqr of dre miuoprocessor aredirectly connecred ro A1A0 oftbe 82C54.

44. Wlrat is the maximum time delay that can be generated wifi the timer in Fig. 10-35?Wlat would be the na.ximum time delay if the clock ftequency were indeased to2 MHz? Assume thar it is configured for binary counting.

,t5. Wtai is the resolution of pulses generat€d wirh rhe 82C54 in Fig. 10 35? Wlar wiltbe the resolution if the clock fuequency is increased to 2 MHz?

46. Find the pulse width of the one-shot in Fig. 10-36 if the counter is loaded with thevalue 100016. Assume that the counter is configured for binary count operation.

47. Wlat count must be loaded into the square,wave generator in Fig. 10-38 in order roproduce a 25-KHz output?

48. If rhe counter in Fig. 10-39 is loaded wirh rhe value 12016, how long of a delayoccurs befoE the sirobe pulse is ouiput?

Section i0.949. Are signal lines MEMR and MEMW of the 82C37A used in the miqoprocessor

50. Summadze the 82C37As DMA requestacknowledge handshake sequence.51. What is the total number of user accessible registen in the 82C37A?52. Write an instruction sequence that reads the value of the address from the cunent

address register for channel 0 inlo the AX register. Assume that the 82C37A has thebase address l0H.

53. Assuming that an 82C37A is located at UO addrcss 1000H, write an instuctiorsequence to perlbrm a master clear operation.

54. Write an instruction sequence that writes the command word 0016 into the cornmandregister of an 82C3?A located at address 2000H in tbe I/O address space.

55. Write an instruction sequence that loads the mode regisier for channel 2 with illemode byte obtained in Example 10.26. Assume that the 82C37A is located at I/Oadairess FoH.

56. What must be output lo th€ mask register in order to disable all of the DRQ inputs?57, Write an instruction sequence that reads the contents of the status register into the AL

rcgister Assume the 82C37A is locaied at I/O address 5000H.

574 lnput/Output lnterface Circuits and Lsl Peripheral Devices Chap. l0

Sect ion 10.1058, Narr?e a sigal fine ttat disfitgrishes an asyncnronous comtllunicafion jnterface fton

that of a slDchronous conmunicatiotr int€dace.

59. Define a simplex, a ha]f-duplex, and a tull-duplex communication lint

60. For an RS-232C hterface, wbat roltage range d€fines a mark at the transmit end ofa serial commudcatiotr line?

Sect ion l0 . l I61, To wdte a b}'te of data qlhe 8251A" what logic levels must ihe microprocessor apply

to contol inputs C/D, RD, W& and CS?

62. The mode-control reglster of an 8251A contains 11111111r. What are the asyncbro-nous chancter lengtl\ typ€ of Parity, and the number of srop bias?

63, Write an instruction sequence to load the control wod obtained in problem 62 into amemory mapped 8251A wi$ the control register located at addfss MODE.

64. Descdbe the difference betwefl a mode instfllction and a command instruction usedin 825 1A itritialization.

Sec t ion 10 . l265. Refening to Fig. 10_70, what ;s $e maximum number of keys that can be supported

using a]l 24 UO lircs of an apFopriately contrgwed 82C55A?

66. In the circuit shown in Fig. l0 70, what rcw and column code wodd identi{y the9 key?

67. wlat codes would need to be output on the digital and segmenl lines of the circuit inFig. l0 71 to display lhe rumb€r 7 h digit l?

sect ion 10.1368. Specily lhe node of operaiion for the keyboard and display when an 8279 is config-

ured with commalld word 0 equal to 3Fr6.

69. Deternine the clock ftequency applied to the input of an 8279 if it ne€ds conmandword 1 equal to lEr6 to oPerate.

70. Swimarize the finction of each command word of the 8279.

575