improving the performance per area factor of risc-v based ... · improving the performance per area...
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Improving the Performance Per Area Factor ofRISC-V Based Multi-Core Systems
Tobias StrauchR&D, EDAptix, Munich, Germany
[email protected]—————————–
4th RISC-V Workshop at MIT, Boston, USA
July 13, 2016
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Agenda
I C-Slow RetimingI System Hyper Pipelining
I Basic IdeaI Performance BalancingI Deep PipeliningI Extended PipeliningI Performance per Area Factor
I microRISC Project
I miniRISC Project
I Miscellaneous
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
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C-Slow Retiming
I Known since the 60’s, Barrel processors
I Leiserson [1]
I Berkeley summer class in 2001
I CSR on FPGAs (LUT level) by Weaver et al. [2]
I Millions of engineers
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C-Slow Retiming (Personal Work)
I Diploma Thesis in 1998 on CSR of FSM
I LSI Logic (Milpitas, CA), RISC Processor, CSR on gate level
I 2001: Timing estimation on RTL, RTL code modification, ...
I 2010: Automatically apply CSR on RTL
I 2010: AVR Core (VHDL) on opencores.org
I 2010: OpenRISC Core (Verilog) on opencores.org
I Papers on CSR on RTL, CSR in safety critical designs, ...
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
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System Hyper Pipelining
I Based on CSR
I Replaces original registers with memories (D).
I Adds thread stalling and therefore thread bypassing features.
I Cycle accurate performance balancing
I Late read / early write [3]
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SHP, Performance Balancing
I Predictive runtime of specific threads
I Sync. start/execution, ”Dynamic Length Instruction Words”
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SHP, Deep Pipelining, T0 in “Beast Mode“
I Detect instruction dependency, LSB RISC-V ISA
I 1) Instruction LSB-sniffing
I 2) Enhanced PM read
I 3) Consider stall/flush signal
I No back-to-back, turned on/off on the fly
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SHP, Extended Pipelining, “Frequency-Over-Scaling“
I Less registers per path than necessary
I Multi-cycle path for example in datapath section
I Re-execution of thread with valid multi-cycle path
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SHP, Performance per Area Factor
I CHStone
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SHP, System Level
I Performance (frequency) over area curve
I System level performance improvements !!!
I microRISC (Vscale), microcontroller, virtual peripherals, ...
I miniRISC (lowRISC, Rocket), SoC, OS, FPU, accelerators, ...
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microRISC
I Vscale @80MHz async DDR3, SHP-ed @250MHz synchron
I Based on RV32IM subset (no FENCE and no SI, ”RV32B”)
I Individual threads handle interrupts (less stack activity).
I Main focus on virtual peripherals
I TC with event handler (complex timer)
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microRISC
I UARTs
I PWMs
I ...
I Standard toolchain compatible (C++, ...)I Demo: How to run timing critical software peripherals based
on a highly dynamic SHP-ed core.
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lowRISC / University of Cambridge
I Diagram: Wei Song, lowRISC / University of Cambridge
I Wei: ”personal view”
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miniRISC (based on lowRISC)
I Minions part of Rocket core, heterogeneous multi-core
I SHP impact on performance per area and SoC architecture
I Arbiter/multiplexer: blocking
I Multilayer: complex
I SHP: time sliced usage at higher speed
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Miscellaneous
I Simple programming model
I Fork-join operations, OpenMP
I Estimated ASIC numbers in paper [3]
I Altera Hyper Pipelining technology looks promising
I More on-FPGA memory (memory wall)
I Power consumption (work ongoing)
I Source code of projects in PDVL (VHDL, Verilog)
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References
[1] C. Leiserson and J. Saxe, “Retiming Synchronous Circuitry“,Algorithmica, vol. 6, no. 1, pp. 5-35, 1991.
[2] N. Weaver, Y. Markovskiy, Y. Patel and J. Wawrzynek,“Post-Placement C-slow Retiming for the Xilinx Virtex FPGA,“FPGA 2003, February 23-25, 2003, Monterey, CA, USA.
[3] T. Strauch, “The Effects of System Hyper Pipelining on ThreeComputational Benchmarks Using FPGAs“, 11th InternationalSymposium in Applied Reconfigurable Computing, ARC 2015,13-17 April 2015, Bochum, Germany, pp. 280-290.
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You made it !!!
I Thank you
I @arduissimo
I www.cloudx.cc
I Call for cooperation: SHP-ed CPU in an ASIC technology