A Novel Low Power 8T-cell Sub-threshold SRAM with Improved Read-SNM

Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi and Roghayeh Saeidi Department of Electrical Engineering, SharifUniversity of Technology, Tehran, Iran

S_hassanzadeh@ee.sharif.edu, Miladzamani@ee.sharif.edu, Ksadeghi@sharif.edu, rosaeidi@ee.sharif.edu

Abstract-The fast growth of battery-operated portable applieations has eompelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the subthreshold regime many structures has been proposed adding extra transistors to the conventional 6T -cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is simple. The new structure uses fewer controlling signal in comparison to the conventional 8T-cell SRAM. Thus, the proposed 32k SRAM consumes 25% lower power consumption in the read operation for 0.3V sub-threshold SRAM in 90nm TSMC CMOS model.

Keywords-component; Sub-threshold; SRAM; Stability; Static Noise Margin.

I. INTRODUCTION

Sub-threshold circuit design has emerged as a vital and low energy solution for low power application with strict energy constraint. Memory circuits such as SRAM occupy a significant amount of any digital Ie S's area. Sub-threshold possibility has led to further research of SRAM design. However, memory circuits operating successfully at such low voltage is more challenging since SRAM yield decreases considerably at these low voltages [1]. In addition, the counteracting threshold voltage variation and process variation challenge the correct operation of SRAMs in nanometer technologies. Taking bitline leakage current and device variation into account, designing a robust SRAM cell plays a key role in practical sub-threshold design [2].

In sub-threshold regime, conventional 6T-cell SRAM experiences poor read and write ability. The threshold voltage fluctuation contributes a large reduction in static noise margin (SNM). Noise margin becomes worse at the time of read and write operation compared to hold operation which the internal feedback operates independent of other transistors [3]. Fig. 1 shows the conventional 6T -cell SRAM and the butterfly curve for hold and read SNM. 6T-cell shows poor stability even in hold SNM. High variation of internal nodes during read operation and internal feedback effect during write operation lead to weak stability of 6T cell. To achieve higher stability,

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designers manipulate the cell and add extra transistor. 7T, ST, 9T and lOT are the different configurations to improve the stability [4-6]. These structures use separate read mechanism, feedback cutting, asymmetric theme and one side access to augment the performance and stability of the cell and hence the functionality of SRAM and the peripheral circuits. However, designing a fully differential scheme that provides differential outputs for sense amplifier and improving the stability during the hold and read phase is the necessity of a practical and high performance sub-threshold SRAM [7].

BL

(a)

(b)

III o

WL

Q(V)

Figure I. a) conventional 6T cell SRAM and b) butterfly curve for hold and read SNM.

RDWL

WL

Buffer Foot

BLB BL RDBL

Figure 2. Conventional 8T cell SRAM. The conventional uses read buffer to separate the read operation process from i ntemal nodes.

In this paper we present a new design of 8T cell SRAM that provides differential outputs with increasing hold and read noise margin and also ensures reliable write operation. Using two extra NMOS transistors stacked to the each side of latch, we can control the internal feedback during the read and write operation to achieve higher hold and read SNM. The read and write operations are differential to maintain the interleaving characteristic of SRAM and simple design of sense amplifier.

The paper is organized as follows: section II explains the challenge faced by the conventional 6T and 8T cell SRAM for operation in sub-threshold region. Section III presents the new 8T cell structure and its functionality. Section IV shows the different simulation confirms the proper operation of the proposed structure and section V is the conclusion of the paper.

II. SUBTHRESHOLD SRAM DESIGN CHALLENGES

A. 6T cell SRAMfailure The 6T cell shown in Fig. 1 fails to operate in sub

threshold because of process variation and reduced signal level. Proper read and write operation depends on the strength of devices. For example, the read SNM requires that the ratio MIIM4 be stronger than access transistors ration M2IM6 and at sub-threshold region SNM becomes negative that means the SRAM fails to work properly. In addition it shows that the hold SNM is acceptable but is marginal. Similarly, write SNM shows the ability of access transistors to be written and hence M3!M5 ratio is important. This shows that 6T cell SRAM fails in sub-threshold as the read SNM isn't better than hold SNM.

B. Conventional 8T cell SRAM Fig. 2 shows the conventional 8T cell SRAM [5]. The main

idea of this topology is to separate the read operation from internal node of latch. By using the read buffer, from one side during the read operation the internal node change the semi output node without any voltage change. Thus, the read SNM limitation of pervious part is eliminated. The buffer ground is attached to the other voltage to minimize the leakage current.

Using this scheme improves the read SNM and decreases the bitline leakage effect. However, the asymmetric design of the

BL

EN 1 Ms

BLB

WL -+--r-----+----+---r-;-

IQ IQB Ms

Figure 3. proposed 8T cell SRAM. Two transistors M5 and M6 can be inactive by EN signal.

300

i 200 Z LLJ

100

1 300 :;; > 200

100

300

i 290 -' 280 co

270

260

250

300

>' 250 .s co -' co 200

150 0 50 100 150 200

Time (ns) Figure 4. Proposed 8Tcell read operation simulation results.

cell can deteriorate the process variation effect. Moreover, the single side read operation of the conventional 8T needs the perfect design of sense amplifier and also precise timing control. Furthermore, this structure has the write SNM problem only improves the read SNM. Using charge-pump circuit for altering the ground of buffer transistors, we use extra power consumption wasted during read operation.

36 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTlS)

I \

! 2001

lOL o l ... V-. '", r----(-r 200 J 100 1 0 v 300

1

I 300 j \ :;- 200 I .s cJ 1:0 I \ \ r 300 ....----- -_.---

:;-.s 200

cJ 100

o 10 20 30 40 50

Time (ns) Figure 5. Proposed 8Tcell write operation simulation results.

III. PROPOSED 8T CELL SRAM

Fig. 3 shows the proposed 8T cell structure. In conventional 8T cell, the read and write operation perform from different paths. In this novel structure we use the same differential paths similar to the 6T cell for both read and write operation. Similar to conventional 6T cell SRAM the data recovered from latch consists of two inverters. The transistors M7 and M8 attached through M6 and M5 to the nodes Q and QB. During the read operation, two signals, EN and WL are active. EN controls two transistors M6 and M5 placed between pull up and pull down transistors. During the write operation, active EN changes our proposed structure to the conventional 6T topology which is only two inverters attached to each other. In the read operation phase EN signal will be low and the node which we read from will be separated from the internal node. The hold phase is similar to the 6T cell one and the SNM is about equal.

! ____ B_L=\ =-_EN._ Ir--D-. ._ ___ :

!

GN

! :

::II

'4------,.....,......,-::::--.....1 1 __________ !.-___________ L __ -__ -__ -__ -__ -__ -__ -" ________________ 3:..5!_u_'"-___ .t

(b) ON ....

2.7um

Figure 6. Layout of a) proposed 8T cell and b) conventional 6T cell. The proposed 8T cell consume 55% more area than conventional 6T cell.

A. Read operation Fig. 4 shows read operation waveform simulation results.

In the read operation WL is active and EN is inactive. By cutting off the M5 and M6 using inactive EN, the storage data in the internal nodes will be separated from reading path. Although the nodes Q and QB are separated from reading paths, the read operation will be done indirectly from M2 and M l. By cut-off mode of the M5 and M6, manipulating the internal nodes, IQ and IQB, has a small effect on the internal nodes Q and QB. This separation improves the read SNM. During the time of read operation the internal node Q and QB can be altered through internal noise. Using differential read operation, the time of it is as small that the noise has small effect to these nodes and after reading the closed loop of the inverters recovers the data. Decreasing WL of other cells which are inactive, the bitline leakage will decrease. The voltage of other WLs can be negative through a charge-pump and improve the reading speed and power consumption [5].

B. Write operation Fig. 5 shows the write operation simulation results in the

proposed scheme. Supposing writing 1 and to the nodes BL and BLB respectively, the write operation is similar to the 6T cell write operation with some negligible reduction due to the stacked transistors M5 and M6. BL and BLB access to the Q and QB through M5, M7 and M6!M8 respectively. The EN signal is high throughout write operation.

Fig. 6 shows the layout of 6T and proposed 8T cell. The proposed 8T cell consumes 55% more area than conventional 6T cell.

IV. SIMULA nON RESUL TS & COMP ARISION

At this section we show different simulations and comparison to confirm the functionality of our proposed structure. All simulations are done for 90nm TSMC CMOS technology. The default V DD for cell is 0,3 at the room temperature.

2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTlS) 37

HoIdSNM

.7-, ---;C;;:----;C;-:;:_______;;.T, ---;C;;:----;C;-.________; VDD(V)

(a) ReadSNM

4\.7-, ---;C;;:----;;;-----.';;,--------;C; . ,----;;';:;:------;;;------;e;;:------; VDD(V)

(b) WriteSNM

. ' .'o-, --,---------;eo--_____,.C:, -,---------7C-------;;,O------,l VDD(V)

(c)

Figure 7. Various SNM for different VDD and temperature. a) Hold SNM. b) Read SNM. c) Write SNM.

Fig. 7(a) shows hold SNM for various VDD and temperatures. The hold SNM changes with V DD reduction significantly. Operating around 0.3V, temperature variation has a small effect on hold SNM. Fig. 7(b) shows read SNM for various V DD and temperatures. For normal variation of temperature, read SNM is acceptable. Fig. 7(c) shows the write SNM for various VDD and temperatures. Again the write SNM around 0.3V is acceptable for proper functionality of cell. Table I shows the various comparison of different structures. The read SNM of the proposed structure shows 90% improvement in comparison to the conventional 6T and small reduction due to feedback cutoff in comparison to the conventional 8T. Using fewer controlling signals, proposed 8T shows lower power consumption in comparison to the conventional 8T. The most important characteristic of our proposed scheme is the differential operation of the cell. This helps the other peripherals to be simple and low power. Moreover, differential output and symmetric layout improve the total performance of proposed structure.

TABLE L

Operation

Read SNM (mV)

Write SNM (mv)

Hold SNM (mv)

Write Energy for one cell (fi) Write time (ns)

# of control signal

Read method

Area

COMPARISION WITH OTHER STRUCTURES

Different Structures COllvellliollal COllvellliollal8T

6T {51 45 92

90 93

92 91

33 50

4.5 3. S

2 3

differential single

A 1.6A

V. CONCLUSION

New8T

S7

S9

90

39

4.1

2

differential

1.55A

In this paper we propose a new robust 8T-cell structure that shows 90% improvement in read SNM in comparison to 6T cell while write and hold SNM reduction can be ignored. Using two transistors as the controlling elements to manipulate the latch during the read and write operation, the proposed structure improve the total stability in different V DD. Benefiting differential output voltage in the read operation, sense amplifier design is simple. The new structure uses fewer controlling signal in comparison to the conventional 8T-cell SRAM. Thus, the proposed 32k SRAM consumes 25% lower power consumption in the read operation for 0.3V sub-threshold SRAM in 90nm TSMC CMOS model. The proposed cell uses 55% more area than conventional since using more transistors for SNM improvement need extra area consumption .

REFERENCES

[I] Raychowdhury, A. ; Mukhopadhyay, S. ; Roy, K. ; , "A feasibility study of subthreshold SRAM across technology generations," Computer Design: VLSI in Computers and Processors. 2005. ICCD 2005. Proceedings. 2005 IEEE Illternational Coriferellce all , vol. , no., pp. 417- 422, 2-5 Oct. 2005.

[2] Tae-Hyoung Kim; Liu, l; Keane, J. ; Kim, C.H. ; , "A 0. 2 V, 4S0 kb Subthreshold SRAM With I k Cells Per Bitline for Ultra-Low-Voltage Computing," Solid-State Circuits, IEEE Journal 0/ , vo1.43, no.2, pp.5IS-529, Feb. 200S.

[3] Calhoun, B.H. ; Chandrakasan, A.P. ; , "Static noise margin variation for sub-threshold SRAM in 65-mn CMOS," Solid-State Circuits, IEEE Journal 0/, vo1.41, no.7, pp.1673-1679, July 2006.

[4] Ebrahimi, Behzad; Afzali-Kusha, Hassan; Afzali-Kusha, Ali; , "Low power and robust STIJ OT subthreshold SRAM cells," Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 Internatiollal Con/erellce all, vol. , no. , pp.141-144,19-21 Sept. 2012.

[5] Venna, N ; Chandrakasan, A.P. ; , "A 256 kb 65 nm ST Subthreshold SRAM Employing Sense-Amplifier Redundancy," Solid-State Circuits. IEEE Journal 0/, volA3, no I, pp. 141-149, Jan. 200S.

[6] Aly, RE. ; Bayoumi, M. A. ; , "Low-Power Cache Design Using 7T SRAM Cell," Circuits and Systems 11: Express Brie/s, IEEE Transactions on , vo1.54, noA, pp.31S-322, April 2007.

[7] Bo Zhai; Hanson, S. ; Blaauw, D. ; Sylvester, D. ; , "A Variation-Tolerant Sub-200 m V 6-T Subthreshold SRAM," Solid-State Circuits, IEEE Journal 0/, vo1.43, no. I 0, pp. 233S-234S, Oct. 200S.

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