Implementation of a Stored Program

Computer

ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides2.ppt Modification date: Oct 16, 2014 1

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Component Parts of a Stored Program Computer

Consists of:

• Processor• Memory• Input circuits and devices• Output circuits and devices

Input devices (such as a keyboard) used to enter information.

Output devices (such as a printer) used to obtain results from the computer.

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Internal Structure of Computer

Convenient to connect the processor, main memory and I/O connect through a set of common wires called a “bus”:

Bus

(set of wires)

Input device(s) Output devices

Input Main

Processor

Outputinterface(s) memory interface(s)

Instructionsand data

Note: Recent computers use more than one bus – separate buses for memory etc.

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Processor fetches binary encoded machine instructions from memory and performs actions defined, for example, add two numbers together and put result back in memory.

Data needed for the calculation also stored in memory.

Main Memory

Holds list of executablemachine instructions, and data(as binary patterns)

Processor

Main memory• Set of storage locations holding binary patterns.

• Used to hold both machine instructions and data

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Memory Addressing

2n locations requiren-bit address

01234

2n 1

Address Memory

Memorylocation

• Each location given a unique address (a binary number starting from zero).

• Each “addressable” location holds a fixed number of bits.

• Any location can be accessed at high speed in any order (random access memory).

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Size of memory locations

In the early days of computers (and perhaps up to 1970), each manufacturer decided on how many bits would be in each memory location. Various sizes existed e.g. 24 bits, 36 bits, 40 bits, etc.

Usually dictated by the number of bits in the instruction.

Also defined the number of bits in numbers stored in memory.

Currently (and for last 30 years at least), each addressable memory location holds 8 bits (a byte)

Originally convenient for holding ASCII (American Standard Code for Information Interchange) code that represented alphanumeric characters (letters, digits, symbols as found on a keyboard).

More recently Unicode/UTF-8 variable width encoding (1 - 4 bytes) encoding mostly used - Encodes most of characters used in world (ASCII a subset). See www.unicode.org/ , en.wikipedia.org/wiki/UTF-8

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Size of memory locations continued

Eight bits is not large enough for encoding machine instructions or most numbers.

For more than eight bits, consecutive locations used. Address given by address of first location.

Example

32-bit integer variables a, b, c, and d might be located at addresses 0, 4, 8, 12.

• Little Endian - Least significant byte stored in first location (little end) or

• Big Endian - Most significant byte stored first location, (big end)

depending upon convention of processor:

Big endian – early common approach Found in some current processors Used in network protocols

Intel uses little endian (a little easier logic) a

b

c

00..00000

00..00100

00..01000

00..01100

d

Address(in binary)

Memory

Little endian/big endian from Gulliver’s Travels

0

4

8

12

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Little endian (little end first)

nn+1n+2n+3

Memory

031

Most Leastsignificant

bytesignificant

byte

32-bit word

Address

Addressof 32-bit word

Memory physically organized so that all32 bit transferred simultaneously along bus

nn+1n+2n+3

Memory

031

Most Leastsignificant

bytesignificant

byte

32-bit word

Address

Addressof 32-bit word

Memory physically organized so that all32 bit transferred simultaneously along bus

Big endian (big end first)

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Question

Suppose a compiler uses the memory locations starting from location zero to hold the variable x using big endian representation. Specify what would be in these memory locations (in binary) if the program has the statement:

int x = 17;

The memory is byte-addressable (each location holding a byte) and x is a 32-bit number.

Answer

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Follow-on question

Suppose x is then read from memory by a processor using little endian representation. What value would it get?

Answer

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Bytes, half word, words, double words and all that

Many processors support multiple data sizes:

High level languagedeclaration of variable x

• 8 bits byte byte x; (Java ) char x; (C)• 16 bits half words• 32 bits words int x;• 64 bits double words long int x;

Other formats also (floating point).

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Machine Instructions

The operation of an instruction reduced to a very simple form.

Consider a calculation one might write in a high level language:

x = (y + z) / (a - b);

where a, b, x, y, and z are declared as integers.

Unreasonable to provide a specific machine instruction just for this calculation.

Need to break down calculation into a series of simple arithmetic operations.

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Suppose the variables a, b, x, y, and z are stored by the compiler in memory locations 100, 104, 108, 112, and 116:

100104108112116

xyzab

temp1

x = (y + z) /(a - b);

temp2

+

-/

Memory

Address

temp1 = y + ztemp2 = a - bx = temp1/temp2

temp1, temp2 could be memory locations but better to use fast internal register storage, see later. Note: integers are stored in registers by the compiler if possible

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Machine Instructions

Each of the steps in the previous example:

temp1 = y + z

temp2 = a - b

x = temp1/temp2

might be encoded into one machine instruction.

Each machine instruction usually only has one operation (+, - etc), possibly two source operands, and a single result.

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Machine Instruction Encoding

A binary pattern that specifies one operation (usually), the operands used for the operation and where the result should be placed if any.

Specifies location of source operands

Operation

Opcodeand where to put result

(various methods - see next)

Addition, subtraction, etc .

Number bits may be fixed or may be variabledepending upon design of processor

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Op-code Encoding

Suppose there were 60 different operations, add subtract, multiply, divide, etc. Six bits would be sufficient (25 <= 60 < 26). Could allocate one pattern for each operation:

Exampleop-code

ADD (“ADD”) 000001SUBTRACT (“SUB”) 000010MULTIPLY (“MUL”) 000011DIVIDE (“DIV”) 000100

etc. . .

Sometimes more complex encoding used. Many possibilities.Pattern of all zeros often reserved for no operation (“no-op”)

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Specifying the Locations of Operands

First let us assume operands and results in main memory:

Three-Address Format

Memory Addresses

Operation Result 1st operand 2nd operand

Three-address format

Opcode

NoteOrder of operands here is with destination first but it could be different depending upon processor.

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Example:

Addition

+100

200

300

Memory ADD 300 200 100

Processor

Instruction

Address

Op-code pattern for ADD here

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Machine Instruction

The processor executes machine instructions which are binary patterns. The previous machine instruction might be encoded as:

ADD 300 200 100

Machine

000001 000...00100101100 000...00011001000 000...00001100100

32 32 326

instruction

where in this case, 6 bits in opcode and 32 bits for each address.

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Assembly Language and Machine Instructions

Much more convenient to use an “assembly language” notation to describe machine instruction rather than actual binary patterns.

Previous machine instruction might be written in assembly language as:

ADD [300], [200], [100]

where [ ] means “contents of memory”, a common notation. ADD is the op-code mnemonic.

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The 3-(memory) address format has the disadvantages:

• Long instruction length• Three memory accesses

and rarely used.

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Two-Address Format

Operands and results in memory. One operand and result same location

Operation1st operand

2nd operand

Two-address format

and result

AddressesOpcode

Eliminates one address

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Example:

ADD [200], [100]

+100

200

Memory Processor

ADD 200 100

Instruction

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Disadvantages:

• One operand overwritten• Still needs three memory accesses

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One-Address Format

Only one location allowed for one operand and result, a location within the processor, called an accumulator historically.

Other operand still in main memory, and its address given in instruction:

AddressesOpcode

Operation

One-address format

2nd operand

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Example

ADD [100]

+100

Memory

Processor

ADD 100

AccumulatorInstruction

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Advantages:

• Shorter instruction• Eliminates two memory accesses• Faster accessing location inside processor than memory

Disadvantages:

• Only one location for one operand and result• Still needs one memory access

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Register Format

Have more than one location within processor - set of registers.

Operation Register 2nd operand

Register-memory format

AddressesOpcode

If there were 32 registers, say R0 to R31, 5 bits are required in each field to specify the register.

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Example

ADD R1, [100]

100

Memory

Processor

ADD 100

Instruction

+

R4R3R2R1R0

Registers

R311

Refers to register R1

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Register-Register Formats

With registers, can now hold all operands in registers and operate on registers only:

Operation Register

Opcode

Register

1st operand/result 2nd operand

Operation Register

Opcode

Register

Result 2nd operand

Register

1st operand

If 2 registers specified

If 3 registers specified

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Example

ADD R3,R1,R2

+

Processor

ADD 3 1 2

R4R3R2R1R0

Registers Instruction

R31

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Zero-Address Format

Possible to eliminate all addresses by using specific locations.Then only the operation need be specified in the instruction

Usually locations for operands/result are top two locations of a stack (a last-in first-out queue) in memory or implemented with registers within processor.

Stack pointer - a register within processor used to hold the address of the top location.

Operation

Opcode

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Example

ADD

+

Stack

Processor

100100

Stack pointer

ADD

Could be insideprocessor, but usually in memory

Instruction

Zero-address format useful to compilers for producing code for arithmetic expressions (using reverse Polish notation)Used by Burroughs in their computers in the 1960’s and not widely since (but re-introduced in SUN Java chip).

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We have outlined several instruction format possibilities:

• 3-address• 2-address• 1-address• register formats (3 register or 2 register)• zero-address

A particular processor will not use all formats.

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Examples

Intel 64/IA-32 instruction set processors (continuing early 8086 processor designs)

• From an external perspective, 2-address formats with one operand in a register, the other in a register or memory.

IBM PowerPC, SUN Sparc processor and other so-called reduced instruction set computers

• 3-register format for arithmetic and register-memory format for accessing memory operands. More details later.

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Questions