IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 4, APRIL 2014 431

Impact of Stress Mode on Stochastic BTIin Scaled MG/HK CMOS Devices

Andreas Kerber, Senior Member IEEE, Purushothaman Srinivasan, Senior Member IEEE

Abstract— Stochastic bias temperature instability (BTI) mod-eling has gained importance for scaled metal gate/high-k CMOSdevices to ensure SRAM circuit functionality. In this letter, wediscuss the impact of the BTI stress mode on the �VT distributionand the time evolution of VT in small and large area CMOSdevices. It is shown that the stress mode has strong impacton the evolution of the threshold voltage distribution in smallarea devices leading to an increase in the σ -value for constantoverdrive stress, whereas no change is observed for constantvoltage stress. Since CMOS circuits share the supply voltage,the constant voltage stress σ -values are relevant and thus, thereliability guidance for future CMOS design should be based onconstant voltage stress.

Index Terms— Bias temperature instability, variability, metalgate, high-k dielectrics, CMOS devices.

I. INTRODUCTION

T IME dependent variability modeling is emerging as acritical input for CMOS circuit design of future tech-

nology nodes. Bias temperature instability (BTI) is one of themost critical device reliability mechanism and a major sourcefor time-dependent variability. To model the stochastic BTIprocess in CMOS devices different stochastic models havebeen proposed in the literature [1] and [2] explaining observeddeviations from normal statistics. Besides the differences in themodeling approach, the employed stress modes also differedwhich may affect the stochastic behavior. In reference [1] thematched pairs of pFET devices were subjected to equivalentstress voltages whereas in reference [2] the stress voltage forindividual devices was adjusted for the time-zero VT variation.In this letter we discuss the implication of the constantvoltage stress (CVS) [1], [3] and the constant overdrive stress(COS) [2] on the stochastic BTI and the time evolution of theVT distribution.

II. EXPERIMENTAL SETUP

N- and pFET MG/HK devices used in this letter werefabricated on bulk substrates utilizing a conventional CMOSprocess flow [4]. Two sets of short channel devices were testedreferred to as “small FETs” with sub-100nm gate width and“large FETs” with a gate width of >1μm. To enhance the

Manuscript received January 21, 2014; accepted February 1, 2014. Date ofpublication February 24, 2014; date of current version March 20, 2014. Thereview of this letter was arranged by Editor S. Hall.

A. Kerber is with Globalfoundries, Inc., Yorktown Heights, NY 10598 USA(e-mail: andreas.kerber@globalfoundries.com).

P. Srinivasan is with Globalfoundries, Inc., Malta, NY 12020 USA.Color versions of one or more of the figures in this letter are available

online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2014.2304532

statistical significance, a novel shared gate device configura-tion giving access to 64 FETs per site in a 8 × 8 matrixconfiguration with short sense delays as required for BTIcharacterization is used. The BTI test followed the sequenceoutlined in [5] where a transistor characteristic is measured inthe linear regime followed by BTI stress in inversion modeexecuted at 125 °C. A total of 10 drain sense current readoutsper decade with equal spacing on a logarithmic time scalewere used. The threshold voltage shift (�VT) is determined bylinear interpolation between the drain sense current readout ata specified gate sense bias and its corresponding pre-stressedtransfer characteristic. In this letter the gate sense bias wasfixed at +0.5V for nFET and at −0.5V for pFET devicesfor a |VDS| = 0.05V. In the case of CVS the BTI stressvoltage, VCVS, is predetermined for all tested devices and waschosen to yield a significant voltage shift within the 100s stressduration. For the COS test, first the threshold voltage of theindividual device, VT(i), was determined and then the BTIstress voltage calculated as:

VC OS(i) = VT (i) + Vod,

with Vod being the overdrive voltage determined byVod = VCVS–VT50, where VT50 is the average thresholdvoltage of the COS population. Since the stress voltage is setindividually for each device a shared gate testing concept isnot applicable for the COS test method. As a result the samplesize in this letter for the COS tests is typically ∼4 times lowercompared to the CVS tests. Overall 250 small FETs weretested for COS and 1000 small FETs for CVS. Since largerFETs were formed by connecting the various gate columnsof the matrix structure the sample size is further reduced andonly about 35 and 140 large FETs were tested for COS andCVS, respectively.

An illustration of the differences between CVS and the COStest method in scaled MOS devices is given in Fig. 1. Sincetime-zero VT distributions typically follow normal distribu-tions [6] for a sample size as used in this letter the stressvoltage distribution for COS is expected to follow a normaldistribution with a targeted mean value close to the CVS testvoltage. Thus it is expected that the mean degradation for CVSand COS testing will be similar.

III. RESULTS AND DISCUSSION

To discuss the impact of the stress mode on the cumulativedistributions for �VT and VT the measured BTI degradationtraces were analyzed at various stress times and cumulativedistributions were plotted on a normal scale.

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432 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 4, APRIL 2014

Fig. 1. Schematics illustrating the difference between the CVS (left) andCOS (right) stress mode for BTI testing in scaled MOS devices. For CVStesting the stress voltage is predetermined whereas for COS testing the stressvoltage for individual devices is derived based on the time-zero VT.

Fig. 2. �VT distribution versus stress time (left side) for CVS (upper panel)and COS (lower panel) test for small area nFET devices assuming normaldistribution. Evolution of VT distribution during stress normalized to time-zero mean value (right side) for CVS (upper panel) and COS (lower panel)test. Correlation plots for �VT versus VT normalized to time-zero meanvalues are shown in the inset. Note the significant increase in the spread ofthe normal VT distribution for the COS test.

In Fig. 2 the data for small area nFET devices are summa-rized. As can be seen, with increasing stress times the mean�VT increases along with the σ -values which is consistentwith literature reports [1], [3], [7]. It is interesting to notethat the experimental results of the CVS and COS followthe theoretical predictions for mean degradation and moreoverboth test methods yield similar σ -values when fitted to a nor-mal distribution. In contrast, the cumulative VT distributionsshow significant differences between the two test methods.For the CVS test <1mV change in σ -value is observedwhereas the σ -values for the COS test shows an increase by∼9mV for ∼70mV mean shift. As a result, the normalizedVT distribution for the CVS test show a parallel shift tohigher VT values whereas the normalized VT distributionsfor the COS test are shifted to higher values with reducedslope equivalent to higher σ -values. This is not expected sincebasic stochastic models for uncorrelated processes predict thesame time evolution for the VT distributions independentof stress mode when time-zero VT and �VT distributionsare equivalent. Therefore the data in Fig. 2 suggests that�VT is not uncorrelated to time-zero VT as shown by theinset [3]. This finding differs from data presented in [7]

Fig. 3. �VT distribution versus stress time (left side) for CVS (upperpanel) and COS (lower panel) using large area nFET devices assuming normaldistribution. Evolution of VT distribution during stress normalized to time-zero mean value (right side) for CVS (upper panel) and COS (lower panel).Correlation plots for �VT versus VT normalized to time-zero mean valuesare shown in the inset. Note the decrease in the spread of the normal VTdistribution for the CVS test.

where absence of correlation is stated. The time-zero VTand �VT correlation is responsible for the observed dis-crepancy in σ -value for the time evolution of VT betweenCVS and COS. Adverse contributions of gate electrode work-function or oxide charge and substrate doping to oxide fieldare likely responsible for this correlation [8]. For bulk pla-nar technologies the most dominant contributor to time-zeroVT variation is the random dopant fluctuation [9] supportingthe applicability of CVS for stochastic BTI characterization.

In large area nFET devices, the difference between the CVSand COS test is reduced compared to small area devices. Thisis because the time-zero VT range is reduced by more than3×, which is consistent with device width scaling and thusthe modulation in overdrive voltage is reduced by the sameamount. Again, the mean value of �VT and the correspondingσ -value are very comparable between CVS and COS as shownby the data in Fig. 3 but in this case the VT distribution forthe COS test show a parallel shift with no significant changein σ -value whereas the CVS test actually shows a reductionor improvement in the σ -value, as indicated by the arrows inFig. 3. This again can be explained by correlation of �VTwith time-zero VT (shown in the inset of Fig. 3) where higherVT devices experience less degradation compared to lower VTdevices.

The results for small and large area pFET devices aresummarized in Fig. 4. Here also, for small area devices,the CVS test results in a parallel shift of VT distributionwith increasing stress time whereas for the COS test the VTdistribution shifts with a reducing slope consistent with anincrease in σ -value. Large area devices show minor changesin σ -value and minor differences between CVS and COS.

The change in sigma values with increasing thresholdvoltage shift for the various devices is summarized in Fig. 5.As can be seen, CVS shows no change in σ -value forsmall area devices whereas for COS a significant increase inσ -value is noticed even at technology relevant degradationlevels of ∼50mV. In large area devices, both improvementand degradation in σ -value can be observed. But at high

KERBER AND SRINIVASAN: IMPACT OF STRESS MODE ON STOCHASTIC BTI 433

Fig. 4. VT distribution during stress normalized to the time-zero mean valuefor small area pFET devices (upper panel) and large area pFET devices (lowerpanel) for CVS (left) and COS (right). Note the significant increase in thespread of the normal VT distribution for the small area COS test.

Fig. 5. Change in σ -value for the cumulative VT distribution during CVSand COS BTI test in small FETs (upper panel) and large FETs (lower panel)derived from data shown in Figs. 2–4. Note the systematic impact of thestress mode on the change in σ -value for small FETs while for large FETsthe changes are smaller and more complex.

threshold shifts the σ -value typically increases due to increaseof �VT σ -value with increasing voltage shift [1], [3], [7].To account for correlation effects, the threshold voltage timeevolution can be written as:

VT (t, V ) = VT (0, VT 50, σV T ) + �VT (�VT 50(t, V ),

σ�V T (t, V ), VT (0, VT 50, σV T ))

where VT (0, VT 50, σV T ) is the time-zero VT with mean value,VT50, and standard deviation, σVT. The second term is relatedto the BTI induced threshold voltage shift and given by:

�VT (i) = �VT 50 + X · (VT (i) − VT 50) + σ�V T · �−1 (F)

with mean shift, �VT50, standard deviation, σ�VT,F the cumulative failure fraction frequently written as

F = (i-0.3)/(N + 0.4) where N is the total number of samples.The term X·(VT(i)–VT50) describes the first order linear corre-lation. Both σ�VT and correlation factor X vary with �VT50.For small area devices, shown in Fig. 2, a correlation factorof X = −0.086 is extracted for CVS and X = 0.164 forCOS while for large area devices shown in Fig. 3 the factor isX = −0.255 for CVS and X = −0.124 for COS. Note thelarger uncertainty in the correlation factor for the large areaCOS test is due to small sample size.

IV. CONCLUSION

Correlation of time-zero VT and BTI induced thresholdvoltage shift in MG/HK technologies has significant impacton the modeling of the time evolution of VT for scaleddevices. For the CVS stress mode, no degradation in σ -valueis observed whereas COS shows a significant σ -value degrada-tion. Since CMOS devices share the supply voltage, reliabilityguidance needs to be based on the circuit constraint which isa constant supply voltage and thus the CVS test is the relevantstress mode.

ACKNOWLEDGMENT

The authors would like to acknowledge the stimulatingdiscussions with T. Nigam, S. Mahapatra and E. Cartier andwould like to thank W. McMahon and S. Richter for teststructure layout support.

REFERENCES

[1] S. E. Rauch, “The statistics of NBTI-induced VT and β mismatchshifts in pMOSFETs,” IEEE Trans. Device Mater. Rel., vol. 2, no. 4,pp. 89–93, Dec. 2002.

[2] B. Kaczer, T. Grasser, P. J. Roussel, et al., “Origin of NBTI vari-ability in deeply scaled pFETs,” in Proc. IEEE IRPS, May 2010,pp. 26–32.

[3] A. Kerber and T. Nigam, “Challenges in the characterization and model-ing of BTI induced variability in metal gate/high-k CMOS technologies,”in Proc. IEEE IRPS, Apr. 2013, pp. 1–6.

[4] H. Shang, S. Jain, E. Josse, et al., “High performance bulk planar 20 nmCMOS technology for low power mobile applications,” in Proc. Symp.VLSI Technol., Jun. 2012, pp. 129–130.

[5] A. Kerber, K. Maitra, A. Majumdar, et al., “Characterization of fastrelaxation during BTI stress in conventional and advanced CMOSdevices with HfO2/TiN gate stacks,” IEEE Trans. Electron Devices,vol. 55, no. 11, pp. 3175–3183, Nov. 2008.

[6] A. Asenov, “Random dopant induced threshold voltage lowering andfluctuations in sub-0.1 μm MOSFET’s: A 3-D ‘atomistic’ simulationstudy,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505–2513,Dec. 1998.

[7] D. Angot, V. Huard, L. Rahhal, et al., “BTI variability: Fundamentalunderstandings and impact on digital logic by the use of extensivedataset,” in Proc. IEDM, Dec. 2013, pp. 405–408.

[8] M. Wang, R. Muralidhar, J. H. Stathis, et al., “Superior PBTI reli-ability for SOI FinFET technologies and its physical understand-ing,” IEEE Electron Device Lett., vol. 34, no. 7, pp. 837–839,Jul. 2013.

[9] X. Wang, G. Roy, O. Saxod, et al., “Simulation study of dom-inant statistical variability sources in 32-nm high-k/metal gateCMOS,” IEEE Electron Device Lett., vol. 33, no. 5, pp. 643–645,May 2012.