ihs 3: test of digital systems...integrated hw/sw-systems andreas mitschele-thiel 19-feb-14 16...

Integrierte Hard- und Softwaresysteme

IHS 3: Test of Digital Systems

R.Ubar, A. Jutman, H-D. Wuttke

Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar

2

Overview

1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test

Integrated HW/SW-Systems 3Andreas Mitschele-Thiel 19-Feb-14

Logic Synthesis

structural domainbehavioral domain

physical domain (layout)

transistor layout

cells

chips

boards

CFG, algorithmsregister transfers

Boolean expressionstransistor functionstransistors

registers, ALUs, MUXs

processors, memories, buses

gates, flip-flops

translation of Boolean expressions into a netlist of components from a given library of logic gates such as NAND, NOR, EXOR, etc.

-> see logic synthesis section for details


Register-transfer Synthesis



transistor layout

cells

chips

boards



gates, flip-flops

start with a set of states and a set of register-transfers in each state one state typically corresponds to a clock cycle (clock-accurate description) register-transfer synthesis generates the corresponding structures

in two parts



(a) a data path which is a structure of storage elements and functional units that perform the given register transfers, and

(b) a control unit that controls the sequencing of the states in the register-transfer description


5

BDDs and DDs

SSBDD

mlm

lm,1

m1

m0mT,1

mT,0

lm,0

Root node DD

m

lmlm,1m1

mT,1

Root node

lm,2m2

mT,2

lm,nmn

mT,n

DD

m

lmlm,1m1

mT,1

Root node

lm,2m2

mT,2

lm,nmn

mT,n

Test generation at logic level (BDD)

Test generation at higher levels (DD)


6

Fault Modeling on High Level DDsHigh-level DDs (RT-level):

Terminal nodes represent:RTL-statement faults: data storage, data transfer, data manipulation faults

Nonterminal nodesrepresent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding,control faults

SSBDDs (Gate-level):Terminal nodes represent:Path value faults {0,1}Stuck at 1Stuck at 0

Nonterminal nodesrepresent: Path signal faults:

All stuck at faults along a correspondingsignal path


7

RT-Level Design

• data path and control path on RT-level

• RT level simulation

• Functional units (F1,..,F4)

• Register

• Multiplexer / Demultiplexer


8

Register Level Fault Models

K: (If T,C) RD F(RS1, RS2, … RSm), NRTL statement:

K - labelT - timing conditionC - logical conditionRD - destination registerRS - source registerF - operation (microoperation) - data transfer N - jump to the next statement

Components (variables) of the statement:

RT level faults:K K’ - label faultsT T’ - timing faultsC C’ - logical condition faultsRD RD’ - register decoding faultsRS RS’ - data storage faultsF F’ - operation decoding faults - data transfer faults N’ - control faults(F) (F)’ - data manipulation faults


9

Register Level Fault Models

K - label: -T - timing condition: -C - logical condition: y1 y2 y3 y4RD - destination register: R2RS - source register: R1 , INF - operation: +, * - data transfer: N - jump to the next statement: -

Components (variables) :

R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4


10


R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1 + R2

IN + R2

R1* R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

2

M1

y1 Function0 M1 = R1

1 M1 = INM2

y2 Function0 M2 = R1

1 M2 = INM3

y3 Function0 M3 = M1+ R2

1 M3 = IN2 M3 = R1

3 M3= M2* R2

R2

y4 Operation Function0 Reset R2 = 01 Hold R2 = R’2

Load R2 = M3


11


R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1 + R 2 IN + R 2

R1 * R 2 IN* R 2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

Terminal nodes represent:RTL-statement faults: data storage, (e.g. #0)data transfer, (e.g. IN)data manipulation faults (e.g. R1*R2)

Nonterminal nodesrepresent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding,control faults


12

High-Level Decision Diagrams

R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

Superposition of High-Level DDs:A single DD for a subcircuit

Instead of simulating all the components in the circuit, only a single path in the DD should be traced

y4

y3 y1 R1 + R2

IN + R2

R1* R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

R2

R2 + M3

M1+ M3

M2+ M3


13

Decision Diagrams for Microprocessors

I1: MVI A,D A INI2: MOV R,A R AI3: MOV M,R OUT RI4: MOV M,A OUT AI5: MOV R,M R INI6: MOV A,M A INI7: ADD R A A + RI8: ORA R A A RI9: ANA R A A RI10: CMA A A A

High-Level DDs for a microprocessor (example):

Instruction set:

3I R

A

OUT4

I A2R

IN5

R1,3,4,6-10

I IN1,6

A

A2,3,4,5

A + R7

A R8

A R9

A10

DD-model of themicroprocessor:


14

Decision Diagrams for MicroprocessorsHigh-Level DD-based structure of the microprocessor (example):

I R3

A

OUT4

I A2R

IN5

R1,3,4,6-10

I IN1,6

A

A2,3,4,5

A + R7

A R8

A R9

A10

DD-model of themicroprocessor:

OUT

R

A

IN

I


15

Hierarchical Modelling on DDs

M=A.B.C.q

1

1

q

xA

0qA

i B’ + C’

#1

qB

i#2

0qA

i A’ + 1

#4

2

1

xB

qC

i C’#3

0qC

i A’ + B’

#5

3

1

xC

qA

i B’ + C’

#5

0qC

i A’ + B’

#5

41

xC

qC

i C’#5

0

B

Ai A’ + B’+C’xA

0

q#5

B’

qB

i B’#5

x1

x2 x3

x4 x5

x6 x7

0

11

0

C

Component:Binary Decision Diagram

System:High-level decision diagram

A small part is simulated at the higher level: to increase the speed of analysis

A small part is simulated at the lower level

Cause-effect analysis well formalized

B’ + C’


Circuit Synthesis

generates a transistor schematic from a set of input-output current, voltage and frequency characteristics or equations

transistor schematic contains transistor types, parameters and sizes



transistor layout

cells

chips

boards





gates, flip-flops


17

Mapping Transistor Faults to Logic Level

Shortx1

x2

x3

x4

x5

y54321 xxxxxy

)()(* dydyy d Generic function with defect:

Function:

))(( 53241 xxxxxyd Faulty function:

A transistor fault causes a change in a logic function not representable by SAF model

Defect variable: d =0 – defect d is missing

1 – defect d is present

Mapping the physical defect onto the logic level by solving the equation: 1*

dy


18

Mapping Transistor Faults to Logic Level

Shortx1

x2

x3

x4

x5

y )()(* dydyy d

))(( 53241 xxxxxyd 54321 xxxxxy

Test calculation by Boolean derivative:

1

))(()(*

5432154315421

5324154321

xxxxxxxxxxxxxd

dxxxxxdxxxxxdy

Generic function with defect:

Function:

Faulty function:


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Component level

dy

Mapping of defects

Uniform Fault Model

x1

x2

x3

x4

x5

System level

Wd

dn dFFddxxFy ),,...,(** 1

Logic levelError

Defect

1*

dyW d

{Wd} dyFault model:

Hierarchical diagnostics

y*


20

Componentlevel

dy

Defect mapping

Hierarchical Test Generation

System level

Wd

Logic levelError

Hierarchical test (fault propagation)

y*

&

&

&

1

&

&

&

Logic level

R2M3

+M1

*M2

R1

IN

RT Level

x1

x2

x3

x4

x5

Defect

Transistor level


21

Overview

1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling

5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test


22

High-Level Decision Diagrams Applet

• Design of data path and a micro-program (control path) on the RT-level

• RT level simulation

• Fault simulation and test coverage evaluation

• Test generation

• Design for testability and BIST


23

Applets for Learning RT- Level Test

Functional Test mode:The test vectors are operands results can be observed at the output, no extra test parts

Deterministic Test mode:Gate level test for each FU separatly, generate test vectors, local test panel, cumulative FC calculation

BIST mode:Functional-, Logical- Circular Built In Self Test via extra test part: Test Pattern Generator and Signature analyzer

Because of interaction the learning process becomes more efficient

The game-like character should raise the students' curiosity


24

Functional Test

• The test vectors areoperands, results can be observed at the output,

• no extra test parts needed


25

Deterministic Test

• Adder (F2)– Schematic level– Gate level test– Boolean derivation– SSBDDs– Path activation– Fault propagation– Fault observation


26

Deterministic Test

• Fault coverage of the vector (FC vec) and • Fault coverage of the sequence (FC)


27

Deterministic Test

• Insert test vectors manually

• simulate the fault coverage of the vector (FC vec) and the sequence (FC)


28

Built In Self Test (BIST)

• Functional– No additional part

• Logical– Additional TPG

• Test Pattern Generator

• Circular– Additional TPG/SA

• Test Pattern Generator• Signature Analyzer


29

Functional BIST

• Find a configuration of the LFSR – (Linear Feedback

Shift Register) that generates optimal operands (= test vectors) (TPG/SA)

• Parameters: – Initial State S0

– Feedback polynom P


30

Logical BIST

• Find a configuration (S0, P) of the LFSR (Linear Feedback Shift Register) that generates optimal operands (= test vektors)

• LFSR is generator andanalyzer in one


31

Test Pattern Generation

• LFSR generator


32


• Micro operation: MUX, F1,…• Control signal: micro operation• Cost: number of gates that

implement a micro operation• Choose between high speed

and low cost

• Implementing an algorithm• F can be transparent / disabled

– Only F2 M-Automaton– F1, F2, F3 sequence– F1, F2, F3; F4 parallel


33


• Algorithm: average• (A+B)/2

• a) high speed– Max resources– Max parallel

• b) low cost– Min resources– Sequential


34


• Algorithm: high speed average• (A+B)/2 (4 steps Cost: 83)

• Simulation– Load from Input Reg1– Load from Input Reg2– Add, Div and store in 1 clock cycle– Output and End


35



• a) high speed– 2 operation units (F2, F3)– Add and Div in in 1 clock cycle– 4 steps– Cost: 83


36



• Test


37



• To continue the test

• Follow the example at

• http://www.pld.ttu.ee/applets/rtl/rtl_exercises.html


38



• b) low cost– Only 1 Unit (F4)– 2 clock cycles for operation– 5 clocks – Cost: 73

ihs 3: test of digital systems...integrated hw/sw-systems andreas mitschele-thiel 19-feb-14 16...

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