IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011 1295

Steady-State Stability of Current-ModeActive-Clamp ZVS DCDC Converters

N. Lakshminarasamma, Md. Masihuzzaman, and V. Ramanarayanan

AbstractActive-clamp dcdc converters are pulsewidth-modulated converters having two switches featuring zero-voltageswitching at frequencies beyond 100 kHz. Generalized equivalentcircuits valid for steady-state and dynamic performance have beenproposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under cur-rent control in this paper. The steady-state stability analysis ispresented. On account of the lossless damping inherent in theactive-clamp converters, it appears that the stability region in thecurrent-controlled active-clamp converters get extended for dutyratios, a little greater than 0.5 unlike in conventional hard-switchedconverters. The conventional graphical approach fails to assess thestability of current-controlled active-clamp converters, due to thecoupling between the filter inductor current and resonant induc-tor current. An analysis that takes into account the presence of theresonant elements is presented to establish the condition for sta-bility. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for themaximum duty cycle for subharmonic-free operation is obtained.The results are verified experimentally.

Index TermsActive-clamp converter, current-programmedcontrol, equivalent circuit model, stability, subharmonic oscilla-tions, zero-voltage switching (ZVS).

NOMENCLATURECc Clamp capacitor.Cr Resonant capacitor.D Main diode.Dc Clamping diode.fr Resonant frequency.fs Switching frequency.iLr (t) Resonant inductor current.IL (t) Steady-state inductor current.IP Peak of inductor current.Lr Resonant inductor.Po Output power.S1 Main switch.S2 Auxiliary switch.vC (t) Resonant capacitor voltage.Vo Output voltage.Vg Input voltage.

Manuscript received September 30, 2008; revised December 1, 2008;accepted April 17, 2009. Date of current version June 22, 2011. Recommendedfor publication by Associate Editor J. A. Pomilio.

N. Lakshminarasamma is with the Department of Electrical Engineering, In-dian Institute of Technology, Madras Chennai Science, Bengaluru 600036 India(e-mail: lakshmin@ee.iitm.ac.in).

M. Masihuzzaman is with the Department of Electrical, Bharath Heavy Elec-tricals Ltd., Bengaluru 560 012, India (e-mail: masih_9296@yahoo.co.in).

V. Ramanarayanan is with the Department of Electrical Engineering, IndianInstitute of Science, Bengaluru 560 012, India (e-mail: vram@ee.iisc.ernet.in).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2022827

Vgs1 Gate voltage for the main switch.Vgs2 Gate voltage for the auxiliary switch.

I. INTRODUCTION

S INGLE-ended active-clamp converters are becoming pop-ular for compact dcdc converters with switching fre-quencies beyond 100 kHz. They belong to the family of two-switch pulsewidth-modulated (PWM) converters featuring zero-voltage switching (ZVS).

A converter circuit proposed to reset the flux in the isola-tion transformer of a flyback converter developed into a newfamily of soft transition converters [1], [2]. Such converters arenamed active-clamp converters. The analysis of active-clampconverters has been presented with different topologies and dif-ferent levels of approximation [3]. The realization of ZVS activeclamp variation for many of the dcdc converter topologies hasalso been presented [4], [5]. These converters have the advan-tages of constant frequency PWM, soft-switching transitions,and low device voltage stress due to clamping action. Steady-state models for active-clamp converters have been proposedin [6].

The hard-switching converters are fully evolved in terms ofanalysis, modeling, design methodologies, covering both thesteady-state and dynamic performance. The modeling methodsare still evolving for soft-switching converters. Small signalmodels have been developed for the resonant load convertersin [7]. Topological constraints were derived for the family ofquasi-resonant converters in [8]. A unified approach for thesteady-state analysis of the quasi-resonant converters has beenpresented in [9]. The conversion ratio and the equivalent circuitmodels for quasi-resonant converters have also been presented.Small signal models have been reported as well.

Such a unified steady-state analysis for the whole familyof constant frequency active-clamp converters has been pre-sented [10]. The circuit equations governing the subintervals areexpressed in terms of pole current and throw voltage. With such adefinition, circuit intervals and the design equations are identicalto the whole family of active-clamp dcdc converters. Identify-ing a unified performance for the ZVS active-clamp convertersresulted in generalized steady-state equivalent circuits valid forsteady-state and dynamic performance as well [11]. It is inter-esting to note that the output voltage in these converters exhibitsa load-dependent drop. This load-dependent drop is a functionof resonant inductor and switching period. Active-clamp con-verters exhibit lossless damping in the equivalent circuit.

ZVS converters with active clamp retain the simple featuresof the hard-switched counterparts. In addition, ZVS converterswith active clamp exhibit lossless damping in their dynamic

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1296 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

performance. This may be seen by the presence of the losslessresistance in the equivalent circuit [11]. The damping resis-tance is a function of resonant inductor and switching period. Inconverters, where the damping is quite substantial, the naturalfrequencies of the output filter are real; closed-loop compen-sator is easier to design. It is worth checking, if this dampingleads to better performance for these converters under currentcontrol.

Hard-switched current-programmed converters exhibit sub-harmonic switching at D 0.5. This is referred as subhar-monic instability in literature [12]. Nonlinear dynamics andthe instability modes have been studied in detail for the current-controlled hard-switched dcdc converters [13][20]. Severalmethods have been suggested in the investigation of the nonlin-ear behavior of switched-mode dcdc converters [14], [15].

The stability criterion for soft-switched active-clamp con-verters under current programming is investigated in this paper.Steady-state stability analysis of the current-controlled active-clamp converters shows that their stability region may get ex-tended to duty ratio greater than 0.5, unlike in the case of conven-tional hard-switched converters. However, experiments showthat the subharmonic instability boundary is at 0.5 for active-clamp converters as well. To correctly predict the stability ofactive-clamp converters, it is necessary to take into accountthe presence of the resonant inductor in the analysis. Such ananalysis is presented in this paper. The same is validated on acurrent-programmed active-clamp converter prototype [21].

This paper is organized as follows. The steady-state analysisof the active-clamp converter is presented in Section II. Therequirement of the current-programmed analysis in the active-clamp converters and the stability analysis are presented inSection III. The design methodology, implementation of thecontroller, and experimental verification of the stability analy-sis are presented in Section IV. Conclusions and references arepresented in Section V.

II. ACTIVE-CLAMP CONVERTERS: STEADY-STATE ANALYSISSoft transition active-clamp converters combine low-

switching-loss characteristics of the resonant converters withconstant-frequency characteristics of conventional PWM con-verters. They are essentially square-wave converters for the mostpart, except during the resonant transitions. Active-clamp con-verters have the advantages of constant-frequency PWM, softcommutation (ZVS), and low voltage stress due to clampingaction. The switching transitions of main switch are lossless,whereas the turn-OFF transition of the auxiliary switch is lossy.

The ZVS buck converter with active clamp, which is illus-trated for analysis, is presented in Fig. 1. The operation of thecircuit follows sequentially the intervals shown in Fig. 2.

The main active switch S1 is turned on at t = 0, following thefreewheeling state. The resonant inductor current ILr (t) raiseslinearly with a slope Vg/Lr (0 t t1). This is followed bythe turn-OFF of the freewheeling diode D at t1 . Following t1 ,the inductor Lr resonates with the capacitor Cr . At the end ofthe resonant interval, the voltage across Cr reduces to zero at t2 ;current through the switch S1 is clamped to (I + Vg

Cr/Lr ).

After t2 , the resonant inductor freewheels through the diode Dc .

Fig. 1. ZVS active-clamp buck converter.

Fig. 2. Idealized waveforms of ZVS active-clamp buck converter.

At t3 , the main active switch S1 is turned off. During turn-OFF,the rate of rise of the voltage across the switch S1 is limitedby the capacitor Cs1 . Thus, the turn-OFF loss of the switch S1is substantially less. Following the turn-OFF of S1 , the switchvoltage is clamped to (V + Vg ). The antiparallel diode of S2is conducting. S2 can now be turned on with ZVS. The ILr (t)ramps down and reaches the input current at which point thediode Dc stops conducting. There is a short resonant intervalfollowing t4 , which ends at t5 . The diode D becomes forwardbiased at t5 , following the resonant interval, when the voltageacross Cr reaches Vo . ILr (t) current now ramps down with aslope V/Lr . This interval ends when the auxiliary switch S2is turned off at t6 . The antiparallel diode of switch S1 startsconducting. Turn-ON of the switch between t6 and Ts resultsin ZVS of the main switch. The idealized waveforms of ILr (t),Vc(t), and the pole voltage Vp (t) waveforms are shown in Fig. 2.

The stability analysis of the active-clamp converters undercurrent-programmed control is presented in the sections below.

LAKSHMINARASAMMA et al.: STEADY-STATE STABILITY OF CURRENT-MODE ACTIVE-CLAMP ZVS DCDC CONVERTERS 1297

Fig. 3. Steady-state filter inductor current waveform of ZVS active-clampconverter.

III. CURRENT-CONTROLLED ACTIVE-CLAMP CONVERTERS:OPERATION

Current-programmed control is preferred to duty ratio controlin power converters because of several advantages, which are asfollows.

1) Parallel operation: Several converters can be operated inparallel without load-sharing problem.

2) Closer protection: The switch is turned off when its currentreaches a set level. Failure to excessive switch current isprevented by limiting the maximum value of the controlsignal.

3) Simple control: Current-programmed control effectivelyeliminates the inductor current as a state variable of theconverter. The overall order of the converter then reducesby 1, resulting in a simpler gain function.

However, such converters exhibit subharmonic oscillations,when operated at duty ratios D 0.5. This is referred as sub-harmonic instability in literature [12]. Ramp compensation is astandard remedy to overcome the subharmonic instability [12].Active-clamp converters exhibit lossless damping in the equiv-alent circuit [10]. It is worth checking, if this damping leads tobetter performance under current control [21].

Fig. 3 illustrates a steady-state inductor current iL (t) wave-form of the active-clamp ZVS converter operating in continuousconduction mode. It is observed that, during the interval T1 inthe ON-time DTs , both the main switch S1 and the freewheelingdiode D are conducting. During the overlap interval T1 in theON-time DTs , the inductor current iL (t) falls with a slope m2unlike in conventional hard-switched converters [10].

With the knowledge of the slopes m1 and m2 , we can de-termine general relationships between iL (0), ic , iL (Ts), andDc

iL (dcTs) = ic = iL (0) + m1(dTs T1). (1)After turn-OFF of the main switch, the filter inductor currentincreases for a small time T4 with the same slope. Thus, thepeak of the inductor current is given as

Ip = ic + m1T4 = iL (0) + m1(dTs + T4 T1). (2)In a similar manner, for the subintervals S2 , Dc ON, and S2 , DON, we can write

iL (Ts) = Ip + m2(dTs T4 + T1). (3)

Under steady-state conditions

iL (0) = iL (Ts), dTs T1 + T4 = DTs T1 + T4 = DcTs,m1 = M1 , m2 = M2 . (4)

From (2) to (4), we haveM2M1

=DTs + T4 T1DTs T4 + T1 =

DcTsDcTs

(5)

where Dc is the effective duty ratio and is given by DcTs =DTs + T4 T1 .

From (5), it appears that the stability region for the current-controlled active-clamp converters may get extended to [0.5 +(T1 T4)/Ts ] unlike conventional hard-switched converters.However, experiments show that the subharmonic instabilityboundary is at 0.5 for active-clamp converters as well. To cor-rectly predict the stability of active-clamp converters, it is nec-essary to take into account the presence of the resonant inductorin the analysis. Such an analysis is presented in the next section.

A. Current-Controlled Active-Clamp Converters: AnalysisThe steady-state and the perturbed waveforms of iL (t) and

iLr (t) are illustrated in Fig. 4. The resonant intervals are as-sumed to be negligibly small compared to the switching period.It is assumed that the converter operates near steady state suchthat the slopes m1 , m2 , mr1 , and mr2 remains unchanged,where

m1 =Vg Vo

L, m2 =

VoL

, mr1 =VgLr

, mr2 =VcLr(6)

Vg is the input voltage, and Vo is the output voltage of the buckconverter with active clamp.

The effect of coupling between iL (t) and iLr (t) is seen byconsidering a small time error t(0), as shown in Fig. 4. Thecurrent-controlled active-clamp converters will be stable, if thiserror t(0) eventually decays to zero. To do so, the propaga-tion of error is evaluated after n switching periods t(nTs) todetermine whether t(nTs) tends to zero for large n. In steadystate, starting from iL (T4), on equating iL (t) and iLr (t) att = Ts + T1 , we get

iL (T4) + m2(dTs T4 + T1) = iLr (T4) + mr2(dTs T4)+ mr1T1 . (7)

Since iL (T4) = iLr (T4), on simplifying, we get

T1 =mr2 m2m2 mr1 (d

Ts T4). (8)

Similarly for perturbed waveform, again starting from iL (T4),on equating iL (t) and iLr (t) at t = Ts + T 1 , we get

T 1 =mr2 m2m2 mr1 (d

Ts T4 + t(0)). (9)

From (8) and (9), we have

T1 = T 1 T1 =mr2 m2m2 mr1 t(0). (10)

1298 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 4. Steady-state and perturbed waveforms of filter inductor current iL (t) and resonant inductor current iL r (t).

The steady-state and the perturbed filter inductor has the sameinitial condition iL (T4) and both reached the reference at t =Ts + T1 + T2 and t = Ts + T 1 + T 2 , respectively. Thus, fromthe previous condition, we get

iL (T4) + m2(dTs T4 + T1) + m1T2= iL (T4) + m2(dTs T4 + t(0)) + m1T 2 . (11)

From (11), we have

T2 = T 2 T2 =m2m1

[(mr2 m2)(m2 mr1) + 1

]t(0). (12)

The time error after one switching period is given as

t(Ts) = T 2 T2 + T1 . (13)From (11)(13), we have an expression for t(Ts), and is givenby

t(Ts) =[m2

m1+

mr2 m2m2 mr1

(1 m2

m1

)]t(0). (14)

Voltseconds balance across resonant inductor Lr givesmr2mr1

=T1

DTs. (15)

Under the assumption mr1 >> m2 and mr2 >> m2 , we have

t(Ts) =[DcDc

+(

1 +DcDc

)(T1

DTs

)]t(0). (16)

After n switching periods, the time error t(Ts) is given by

t(nTs) =[DcDc

+(

1 +DcDc

)(T1

DTs

)]nt(0)

= ()nt(0). (17)

The evolution of time error is determined by the characteristicvalue

=[DcDc

+(

1 +DcDc

) (T1

DTs

)]. (18)

As n tends to infinity, the time error t(Ts) tends to zero pro-vided the characteristic value has value less than 1

|t(nTs)| 0, when || < 1 (19)|t(nTs)| , when || > 1. (20)

By simplifying the previous equation, we get the condition D > m2 , we get

t(Ts) =[(m2 mc)

m1 mc +(mr2

mr1

) (m1 m2m1 mc

)]t(0).

(27)After n switching periods, the time error becomes

t(nTs) =[(m2 mc)

m1 mc +(mr2

mr1

)(m1 m2m1 mc

)]nt(0)

(28)t(nTs) = ()nt(0). (29)

The evolution of time error is determined by the characteristicvalue

=[(m2 mc)

m1 mc +(mr2

mr1

)(m1 m2m1 mc

)]. (30)

As n tends to infinity, the time error t(Ts) tends to zeroprovided the characteristic value has value less than 1

|t(nTs)| 0, when || < 1|t(nTs)| , when || > 1.

Therefore, for stable operation, we need to choose the arti-ficial ramp slope mc such that the characteristic value hasmagnitude less than 1. Hence, proper artificial ramp slope maybe chosen to stabilize the system for duty cycle greater than0.5 [12].

1300 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 6. Implementation of current controller for the active-clamp buck converter. (a) Active-clamp ZVS buck converter. (b) Current-programmed controller.

IV. STABILITY ANALYSIS OF A CURRENT-CONTROLLEDACTIVE-CLAMP CONVERTERS: VALIDATION

As a means of verifying the steady-state performance andthe stability analysis, the current-controlled active-clamp buckconverter is simulated and a prototype is implemented. The sim-ulation and experimental results turn out to be in good agreementwith the mathematical analysis. The design methodology, sim-ulation and experimental results are presented in the sectionsshortly.

A. Current-Controlled Active-Clamp Converters: DesignMethodology

The design methodology of the active-clamp converters hasbeen presented in [10]. The design constraints in order to achieveZVS transitions are the following.

1) fr >> fs, where fr is the resonant frequency and fs is theswitching frequency.

2) V

CrLr

> Imin .

A spreadsheet design procedure for the active-clamp con-verters has been presented in [10]. Following that, the current-controlled active-clamp converter is designed for the followingspecifications.

Output power Po = 33 W.Output voltage Vo = 15 V.Input voltage Vg = 68 72 V.Switching frequency fs = 300 kHz.Output current ripple = 10%.Output voltage ripple = 1%.Control scheme: Current-programmed control.

B. Implementation of the ControllerSimple current-programmed control is implemented for the

active-clamp converters. The converter output is controlled bythe choice of the peak switch current is(t) [12]. The control inputsignal is a current ic(t) and a simple control network switchesthe MOSFET ON or OFF such that the peak switch current followsic(t), as shown in Fig. 6.

The circuit parameters and specifications of the implementedcurrent-controlled active-clamp buck converter is summarizedin Table I.

TABLE 1UTILIZED COMPONENTS AND PARAMETERS IN THE BUCK

CONVERTER PROTOTYPE

Fig. 7. Simulated active-clamp buck converter: Vo = 15 V, Po = 33 W,fs = 300 kHz.

C. Current-Controlled Active-Clamp Converters: SimulationResults

The 33-W, 300-kHz buck converter with active clamp shownin Fig. 7 is simulated and the results are presented in Fig. 8.

1) Steady-State Performance (Simulation Results of BuckConverter With Active Clamp):

1) Vgs1 and Vgs2 are the gate pulses driving the main switchS1 and the auxiliary switch S2 . The switching transitionsof the switch S1 and S2 are with turn-ON and turn-OFFdelay.

LAKSHMINARASAMMA et al.: STEADY-STATE STABILITY OF CURRENT-MODE ACTIVE-CLAMP ZVS DCDC CONVERTERS 1301

Fig. 8. Steady-state simulation results of active-clamp buck converter: Vo =15 V, Po = 33 W, fs = 300 kHz.

2) iLr (t) is the resonant inductor current waveform, which issimilar to the main switch S1 current during the ON-timeDTS . It is observed that, the main switch S1 is turned on,when the current through it is negative. This indicates thezero-voltage turn-ON of the main switch S1 .

3) Vp(t) is the pole voltage of the converter. It is observedthat, the pole voltage is similar to the input voltage duringthe ON-time of the main switch except during the resonantintervals.

4) iC c(t) is the current through the clamp capacitor Cc .2) Stability Analysis (Simulation Results of Buck Converter

With Active Clamp): Fig. 9(a) shows the filter and resonantinductor current for duty cycle less than 0.5. It can be seenthat there is no subharmonic oscillation for duty cycle less than0.5. Therefore, current-programmed active-clamp converters arestable for D < 0.5.

Fig. 9(b) shows the filter and resonant inductor current forduty cycle greater than 0.5. It is clear that for D > 0.5 thereis subharmonic oscillation in the current-programmed active-clamp converter. From the simulation results, it is clear thatcurrent-controlled active-clamp converters also exhibit subhar-monic oscillations for D > 0.5. To validate the mathematicalanalysis and simulation results, the current-controlled active-clamp buck converter is implemented, and experimental resultsfor the same are presented in the next section.

Fig. 9. Filter and resonant inductor current waveforms of the current-controlled active-clamp buck converter for D < 0.5 and D > 0.5. (a) Filterinductor current (indicating equal valleys ia and ib) and resonant inductor cur-rent (indicating equal valleys ic and id) waveforms of the current-controlledactive-clamp buck converter for D < 0.5. (b) Filter inductor current (indicatingunequal valleys ia and ib) and resonant inductor current (indicating unequal val-leys ic and id) waveforms of the current-controlled active-clamp buck converterfor D > 0.5 indicating subharmonic oscillations.

D. Current-Controlled Active-Clamp Converters:Experimental Verification

To verify the stability condition, a current-controlled active-clamp buck converter is built and tested with the followingspecifications.

Output power Po = 33 W.Output voltage Vo = 15 V.Switching frequency fs = 300 kHz.Input voltage Vg = 6872 V.The experimental results for the previously designed proto-

type are presented in this section. The experimental results arein good agreement with the mathematical analysis.

1) Steady-State Performance (Experimental Results of BuckConverter With Active Clamp): The 33-W, 500-kHz buck con-verter with active-clamp prototype is built and tested. Experi-mental results are presented shortly.

1302 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 10. Experimental waveforms of 33-W, 300-kHz active-clamp buck converter prototype. (a) Ch1: Vg s1 (20 V/division) and Ch2 Vg s2 (20 V/division); timescale 0.5 s/division; gating pulses for S1 and S2 . (b) Ch1: Vds1 (50 V/division) and Ch2 iL r (t) (1 A/division); time scale 0.5 s/division; drain-to-sourcevoltage of switch S1 and resonant inductor current.

Fig. 11. Experimental waveforms of 33-W, 300-kHz active-clamp buck converter prototype. (a) Ch1: Vg s1 (10 V/division) and Ch2 Vds1 (50 V/division);time scale 1 s/division; gate pulses of S1 and drain-to-source voltage of switch S1 . (b) Ch1: Vg s2 (10 V/division) and Ch2 Vds2 (50 V/division); time scale1 s/division; gate pulses of S2 and drain-to-source voltage of switch S2 . (c) Ch1: Vds2 (50 V/division) and Ch2: iC c (1 A/division); time scale 0.5 s/division;drain-to-source voltage of switch S2 and clamp capacitor current iC c (t). (d) Ch1: Vp (50 V/division) and Ch2: iL r (t) (1 A/division); time scale 0.5 s/division;pole voltage and resonant inductor current.

Fig. 10(a) shows the gate pulses driving the switches S1 andS2 . Vgs1 and Vgs2 are complementary. The switching transi-tions of the switches S1 and S2 are with turn-ON and turn-OFFdelay.

The drain-to-source voltage of the main switch S1 andthe resonant inductor current iLr (t) waveforms are shown inFig. 10(b). It is observed that the main switch current (whichis similar to iLr (t) during the ON-time) is negative at the turn-ON of the switch S1 . This indicates zero-voltage turn-ON of theswitch S1 .

Fig. 11(a) shows the gate pulses and the drainsource voltageof the main switch S1 . It is observed that the gate pulses aredriving the switch S1 , only after the drainsource voltage ofthe switch S1 has reached zero. This indicates the zero-voltage

turn-ON of the switch S1 . Similarly, switch S2 is turned on atzero voltage, as shown in Fig. 11(b).

Fig. 11(c) shows the clamp capacitor Cc current and the drainsource voltage of the switch S2 . The pole voltage Vp waveformis shown in Fig. 11(d). It is observed that the pole voltage issimilar to the input voltage during the ON-time of the mainswitch except during the resonant intervals.

2) Stability Analysis (Experimental Results of Buck Con-verter With Active Clamp): A 33-W current-controlled active-clamp buck converter is fabricated and tested.

Fig. 12(a) and (b) shows the resonant inductor current, filterinductor current, and gate pulse for D < 0.5. Fig. 12(c) and (d)shows the resonant inductor current, filter inductor current, andgate pulse forD > 0.5. It is clear that, for D > 0.5, subharmonic

LAKSHMINARASAMMA et al.: STEADY-STATE STABILITY OF CURRENT-MODE ACTIVE-CLAMP ZVS DCDC CONVERTERS 1303

Fig. 12. Experimental waveforms of current-programmed active-clamp converter operating with duty ratio D < 0.5 indicating [(a) and (b)] stable waveformsand operating with duty ratio D > 0.5 indicating [(c) and (d)] subharmonic oscillations without slope compensation. (a) Ch1: 10 V/division, Ch2: 2 A/division,resonant inductor current iL r (t) (indicating equal valleys ia and ib), and the main active switch gate voltage Vg s1 for duty ratio D < 0.5 and switching frequencyfs = 300 kHz. (b) Ch1: 10 V/division, Ch2: 500 mA/division, filter inductor current iL (t) (indicating equal valleys ic and id) and the main active switch gatevoltage Vg s1 for duty ratio D < 0.5, and switching frequency fs = 300 kHz. (c) Ch1: 10 V/division, Ch2: 2 A/division, resonant inductor current iL r (t)(indicating unequal valleys ia and ib) and the main active switch gate voltage Vg s1 for duty ratio D > 0.5 indicating subharmonic oscillations. (d) Ch1: 10V/division, Ch2: 500 mA/division, filter inductor current iL (t) (indicating unequal valleys ic and id), and the main active switch gate voltage Vg s1 for duty ratioD > 0.5 indicating subharmonic oscillations.

Fig. 13. Ch1: 5 V/division, Ch2: 5 A/division, Main active switch gate voltageVg s1 and resonant inductor current iL r (t) for duty ratio D > 0.5, i.e., D =0.64 with slope compensation (stable operation).

oscillations are observed in the waveforms [see Fig. 12(c) and(d)]. Experimental results show that current-controlled active-clamp converters exhibit subharmonic oscillations for D > 0.5,identical to hard-switched converters. The current-programmedactive-clamp converters can be rendered stable for D > 0.5,by slope compensation [12]. Fig. 13 shows resonant inductorcurrent and control pulse for D = 0.65. Stable waveforms areobserved for duty ratio D > 0.5 with slope compensation.

V. CONCLUSIONThe active-clamp converters are analyzed for its dynamic be-

havior under current control in this paper. The steady-state sta-

bility analysis of current-controlled active-clamp converters ispresented. Hard-switched current-programmed converters suf-fer from subharmonic instability at D 0.5. The stability crite-rion for the active-clamp converters under current programmingis analytically proved to occur at the same boundary of D 0.5as in hard-switched converters.

An approach to investigate the subharmonic oscillations incurrent-programmed active-clamp converters has been proposedin this paper. The steady-state stability analysis, taking into ac-count, the effect of the resonant elements, is presented. Thiscorrectly predicts the condition for subharmonic-free operationof current-controlled active-clamp converters. It is observed thatthe family of active-clamp converters also exhibits instabilityfor D 0.5 like hard-switched converters. A simple expressionfor the maximum duty cycle for subharmonic-free operationis obtained. This condition is not obvious from the conven-tional graphical approach. Experimental results are presentedfor the ZVS active-clamp buck converter to demonstrate current-programmed control and validate steady-state stability analysisof active-clamp converters under current control.

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1304 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

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N. Lakshminarasamma received the B.E. degreein electrical engineering and the Masters degree inpower electronics from Bangalore University, Ben-galuru, India, in 1994 and 1997, respectively, and thePh.D. degree from the Indian Institute of Science,Bengaluru, India, in 2007.

During 19971998, she was a Faculty Memberat BMS College of Engineering, Bengaluru. During19992002, she was a Software Engineer with I2Technologies India Pvt. Ltd. During 20022003, shewas a Faculty Member in the Department of Electri-

cal Engineering, Nitte Institute of Technology, Bengaluru. She worked for GEHealthcare India Pvt. Ltd., Bengaluru, during 20082009, and currently she iswith the Department of Electrical Engineering, Indian Institute of TechnologyMadras, Chennai, India. Her current research interests include power electronicsand switched-mode power conversion.

Md. Masihuzzaman, photograph and biography not available at the time ofpublication.

V. Ramanarayanan received the B.E. degree fromthe the University of Madras, Chennai, India, in 1970,the M.E. degree from the Indian Institute of Science,Bengaluru, in 1975, and the Ph.D. degree from theCalifornia Institute of Technology, Pasadena, in 1986.

He was a Senior Design Engineer and the Chief ofR&D with M/s Larsen and Turbo Ltd., during 19701979, and NGEF Ltd., during 19791982. He is cur-rently a Professor of the Department of ElectricalEngineering, Indian Institute of Science. His currentresearch interests include power electronics, indus-

trial drives, switched-mode power conversion, and power quality issues. He isa consultant to several industries in related areas.