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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 7, JULY 2014 1463

A Sub-nW 2.4 GHz Transmitter for LowData-Rate Sensing Applications

Patrick P. Mercier, Member, IEEE, Saurav Bandyopadhyay, Member, IEEE, Andrew C. Lysaght,Konstantina M. Stankovic, and Anantha P. Chandrakasan, Fellow, IEEE

Abstract—This paper presents the design of a narrowband trans-mitter and antenna system that achieves an average power con-sumption of 78 pW when operating at a duty-cycled data rate of1 bps. Fabricated in a 0.18 µm CMOS process, the transmitteremploys a direct-RF power oscillator topology where a loop an-tenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggres-sive power gating techniques and sizing optimizations, limited thestandby power of the transmitter to only 39.7 pW at 0.8 V. Sup-porting both OOK and FSK modulations at 2.4 GHz, the trans-mitter consumed as low as 38 pJ/bit at an active-mode data rate of5 Mbps. The loop antenna and integrated diodes were also used aspart of a wireless power transfer receiver in order to kick-start thesystem power supply prior to energy harvesting operation.

Index Terms—Body-sensor networks, energy harvesting, lowpower electronics, power amplifiers, radio frequency integratedcircuits, voltage-controlled oscillators, zero-power electronics.

I. INTRODUCTION

T HE ongoing miniaturization of electronics, as modeledby Bell’s law [1], has taken solid-state computing plat-

forms from stationary room-sized mainframes to portable plat-forms such as laptops, smartphones, and smart watches. Al-though the power consumption and computational performanceof such electronic devices have also scaled with Moore’s law,the battery technology necessary to power portable devices has

Manuscript received November 28, 2013; revised February 06, 2014 andMarch 28, 2014; accepted March 28, 2014. Date of publication April 21, 2014;date of current version June 23, 2014. This paper was approved by Guest Ed-itor Stefan Rusu. This work was supported by the C2S2 Focus Center and theInterconnect Focus Center, two of six research centers funded under the FocusCenter Research Program (FCRP), a Semiconductor Research Corporation en-tity. This work was also supported by U.S. National Institutes of Health grantsK08 DC010419 and T32 DC00038, and the Bertarelli Foundation .P. P. Mercier is with the Department of Electrical and Computer Engi-

neering, University of California at San Diego, La Jolla, CA 92093 USA(e-mail: [email protected]).S. Bandyopadhyay is with Texas Instruments, Dallas, TX 75243 USA.A. C. Lysaght is with the Massachusetts Eye and Ear Infirmary, Boston, MA

02114 USA, and the Harvard/MIT Joint Division of Health Sciences and Tech-nology, Cambridge, MA 02139 USA.K. M. Stankovic is with the Massachusetts Eye and Ear Infirmary, Boston,

MA 02114 USA, and the Harvard/MIT Joint Division of Health Sciences andTechnology, Cambridge, MA 02139 USA. He is also with the Department ofOtology and Laryngology, Harvard Medical School, Boston, MA 02114 USA.A. P. Chandrakasan is with the Department of Electrical Engineering and

Computer Science, Massachusetts Institute of Technology (MIT), Cambridge,MA 02139 USA.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2014.2316237

not scaled nearly as rapidly. Thus, as Bell’s law continues tomarch on and device sizes continue to scale, it will become nec-essary to create advances in energy harvesting and near-zero-power electronics in order to overcome limited battery capaci-ties to push into the next generation of ubiquitous sensors and“internet of everything” devices.Many emerging sensing applications have underlying phys-

ical properties that do not vary rapidly with time. For example,sensing of temperature, metabolites, and air quality are buta few examples of applications where sensing front-ends donot require rapid sampling, and therefore can be aggressivelyduty-cycled into ultra-low-power sleep states. If the majorityof the active elements in such a sensing system can follow thisduty-cycling paradigm, then the average power consumptionof the system is not set primarily by the active-mode power, butrather from a combination of active-mode and standby-modepower, with a large percentage coming from standby-modeduring deeply duty-cycled operation. Thus, minimizing thestandby-mode power is the key to enabling near-zero-powersensing nodes at ultra-low data rates.In general, miniaturized sensing systems communicate their

measured information wirelessly over a short distance (e.g.,often only a few meters) in order to minimize the active-modepower of the constituent Radio Frequency (RF) Power Am-plifier (PA). Thus, local base stations are typically employedin locations where energy is more abundant—a smartphonewithin a Body-Area Network (BAN), for example. However,even under low path-loss constraints, RF circuits still oftendominate the power consumption of sensor nodes [2], [3].Thus, there is considerable interest in minimizing the powerconsumption of RF circuits in such sensing nodes. Many recentpublications in the area of energy-efficient RF circuits havedescribed receivers, transmitters, and transceivers with excel-lent RF performance at efficiencies down to tens-to-hundredsof picojoules per bit [4]–[6]. However, such architectures aretypically demonstrated and optimized for efficient performanceat data rates exceeding 100 kbps. At such average data rates,leakage and standby power are not critical, and therefore notaggressively optimized. As a result, the average power of suchradios do not necessarily scale well down to ultra-low datarates.In order to enable next generation sensor nodes with near-

zero-power for energy-autonomous operation in combinationwith energy harvesting, this paper presents a 2.4 GHz trans-mitter that is specifically optimized for standby power in thepicowatt regime [7]. To achieve this, a low-complexity, single-stage direct-RF architecture is employed, featuring significant

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1464 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 7, JULY 2014

Fig. 1. Architecture of the endocochlear potential harvesting, sensing, andcommunicating system.

power gating and sizing optimizations for minimized leakagepower.To validate the design, the transmitter is integrated into

a system that harvests energy from the Endocochlear Po-tential (EP)—an electrochemical gradient found naturally inthe inner-ear of mammals—which can only sustain energyextraction of approximately 1 nW [8], [9]. A figure of the EPharvesting system is shown in Fig. 1. Since the EP voltage islow (typically between 70–100 mV), a boost converter is usedto process the energy up to a higher voltage (typically between0.8–1.0 V), which is directly dumped onto capacitor . Asmore energy is extracted from the cochlea, it is continuallybuffered onto , forcing its voltage, , and as a result itsstored energy, to rise. When sufficient energy has been storedon , the 2.4 GHz radio is enabled to quickly transmit apacket, then return to an ultra-low-power standby mode.In this system, the boost converter requires 544 pW of quies-

cent power [10]; leaving approximately 250 pW of transmitterpower budget after taking into account the overhead of other pe-ripheral circuits and adding some power budget safety margin.Given the extreme power budget limit, the transmitter is de-signed and optimized to operate over short transmission dis-tances (1 m) in order to limit the requisite output power. In ad-dition, the transmitter is deeply duty-cycled, for example downto a duty-ratio of 0.00002% by transmitting 64-bit packets onceevery 80 seconds, with an instantaneous data rate of 5 Mbps, foran average data rate of 1 bps in this example (though this canbe programmable).Since the EP in this case is too low to directly start-up CMOS

electronics (in particular, the boost converter control circuitry),the transmitter’s antenna is shared with a kick-start rectifier [11],used to initialize the charge on at system start-up with littleoverhead. As an implanted system, kick-starting is performedby placing an external antenna, driven by an RF source, nearthe surface of the skin just above the implant for transcutaneouswireless energy delivery, similar to traditional inductively-cou-pled or mid-field powered systems [12], [13].This paper describe the details of the transmitter, antenna,

and kick-start rectifier, while details of the biology and overall

system operation can be found in [8], and details of the boostconverter can be found in [10].

II. TRANSMITTER ARCHITECTURE

A. Motivation and Prior Work

The application use-case for this design is to use the endo-cochlear potential as an energy source to autonomously powera wireless implant. In this case it is not desired (or required) tohave a semi-permanent external wireless source powering andinterrogating the implant, as is typically done for implantablesystems such as cochlear implants. Instead, information can betransmitted directly from the implant to an external device ap-proximately one meter away (e.g., a cell phone or smart watch).This setup permits the design of a functionally autonomoussystem, with zero patient involvement required (other thana wireless kick-start for system initialization). In addition, itexploits the benefits of a body-area network, where commu-nication complexity is pushed away from the energy-starvedimplant and towards the energy-rich base station platform.Since the transmitter will be deeply duty-cycled, its average

power consumption is not determined solely by its active orleakage performance, but by a combination of both [14]. Moreprecisely, the average power consumption can be predicted by(1):

(1)

Here, is the transmitter leakage power, is theenergy required to transmit a single bit, is the number of bitsper packet (programmable from 8–128 bits based on a binarycounter), and is the time interval between packets (pro-grammable from 40–360 s based on a counter that is driven bythe 12.8 Hz on-chip oscillator found in the boost converter con-trol circuitry [10]). Based on this equation, the transmitter mustnot only have extremely low leakage power, it also must be veryenergy efficient during active-mode in order to achieve the nec-essary overall power goal, otherwise the effective bit rate (i.e.,

) will be forced to be extremely low.There are many examples of very energy efficient transmitter

designs in the literature. Previous narrowband transmitters haveattained energy efficiencies on the order of 140–2900 pJ/bit foroutput power ranging from 16 dBm to 0 dBm at instantaneousdata rates under 5 Mbps [4]. [15]–[20]. However, none of thesesystems are optimized for ultra-low standby power. On the otherhand, narrowband work in references [21], [22] were indeedoptimized for low leakage power, consuming 675 pW and 3.3nW in standby power modes, respectively. However, neither ofthese results meet the 250 pW power budget required in thiswork, particularly when their actives transmission modes aretaken into account. For example, the two separate chips require29 nJ/bit and 4.7 nJ/bit, resulting in an average powers of 46 nWand 11 nW, respectively.1

Pulse-based Ultra-Wideband (UWB) radios, which com-municate using very short duration impulses at RF, also offerpromising results in terms of energy efficiency. In particular, the

1This is calculated using each radio’s nominal instantaneous data rate scaledto 1 bps.

MERCIER et al.: A SUB-nW 2.4 GHz TRANSMITTER FOR LOW DATA-RATE SENSING APPLICATIONS 1465

TABLE IPERFORMANCE OF A mm LOOP ANTENNA IN FREE SPACE AND BIOLOGICAL TISSUE ENVIRONMENTS AT VARIOUS ISM BANDS

Fig. 2. Simplified block diagram of the direct-RF power oscillator transmitter.

energy efficiency of UWB transmitters using non-coherent sig-naling can be much lower than their narrowband counterparts,due in part to relaxed frequency tolerances and internationallyregulated output power limits [23]–[28]. Although potentiallyappealing, such efficiency is generally achieved not throughactive-mode power reduction, but instead through increasedinstantaneous data rates. In fact, many UWB transmitter im-plementations require multiple RF stages (even “all-digital”implementations, which often use many cascaded RF invertersas a PA), all of which generally require low- transistorsin order to switch sufficiently fast to generate power in the3.1–10.6 GHz UWB bands. Thus, the high active-mode power,distributed low- blocks can be difficult to effectively powergate down to the requisite levels in this particular application,especially if the ratio of power gating switches is lim-ited. Additionally, the high frequencies employed in standardUWB bands suffer from increased losses when transmittingthrough biological tissue, due primarily to larger conductivityat higher frequencies [29], which would reduce the overallsystem radiation efficiency compared to lower-frequencyIndustrial, Scientific, and Medical (ISM) bands, and wouldthereby require increased active-mode power, increasing thedifficulty of effective power gating.

B. Architecture Overview

For the reasons outlined in the preceding section, it is nec-essary to reduce the overall transmitter complexity by limitingthe number of RF blocks while pushing all possible communi-cation complexity to the energy-abundant external base stationreceiver. Taking the simplified architecture concept to a logicalextreme, the transmitter presented in this work radiates informa-tion through the use of a direct-RF power oscillator (PO) design,inspired by the early days of single-transistor radios and morerecent work presented in [15]. A simplified block diagram of thetransmitter is shown in Fig. 2.The transmitter generates RF at a frequency of 2.4 GHz as a

compromise between tissue losses, antenna efficiency, and cir-cuit power consumption. A more thorough discussion of thistrade-off is found in Section III. A loop antenna is chosen asthe radiative element, as it offers sufficient radiation conver-sion efficiency, has a high quality factor, and is naturally well

suited to receive wireless power for system initialization. Dueto anatomical size constraints, the physical size of the antennawill be much smaller than its radiating wavelength, resultingin an electrically small design. An electrically small magneticloop antenna can be modeled as an inductor in series with a re-sistor, which is well suited to serve as part of the resonant net-work of the power oscillator. The oscillator itself performs auto-matic impedance matching, resulting in a very low-complexity,low-area, and energy efficient design. Data modulation can beachieved by turning on or off the entire oscillator for on-offkeying (OOK) modulation, or the resonant capacitors can bedynamically switched for frequency-shift keying (FSK) mod-ulation.

III. ANTENNA DESIGN

The design of antennas for implantable applications usu-ally involves a trade-off between radiation efficiency (whichincreases with antenna size and/or carrier frequency as thewavelength approaches the physical antenna size) and tissuelosses (which increase with frequency as the conductivity oftissue increases). In this application, the antenna size is limitedto a few millimeters in diameter due to anatomical constraints.At 5 GHz and below, a loop antenna of this size would beconsidered electrically small, and can thus be modeling as aninductor, , in series with a resistor, . Equationspredicting the performance of the antenna can be found the inAppendix.Table I shows simulated results for radiation efficiency,

quality factor, and inductance of a representative mmantenna in free-space, using 0.2 mm, 2-oz copper traces on a1.6 mm FR-4 printed circuit board (PCB) substrate in air atvarious ISM band frequencies. For completeness, the sameantenna is additionally simulated in a realistic implanted envi-ronment using both FR-4 and Rogers substrates, while coatedwith 0.1 mm of bio-compatible parylene and being surroundedon the underside by bone and brain, and on the top side by 3mm of fat tissue and 2 mm of skin. Antenna electromagneticsimulations were performed in IE3D, a fully 3D method-of-mo-ments simulator [30].Although the Medical Implant Communication Service

(MICS) specification at 402–405 MHz is specifically des-ignated for medical implant communications, the radiationefficiencies are simply too low to be useful for implants withlimited antenna sizes. To put this in perspective, a transmitterconsuming 1 mW of power could, at its theoretically optimalpoint, only radiate 44 dBm in air or 64 dBm in an im-planted environment at 400 MHz. In contrast, the same antennaoperating at 2.4 GHz would ideally radiate 21 dBm in airor 33 dBm in an implanted environment. While operatingat an even higher frequencies may be beneficial for many


applications with small implanted antennas, the non-inductiveantenna reactance may require large (or small and lossy) in-ductive-based tuning circuits. Additionally, because the lossresistances of the antenna are higher, such an approach maypreclude the design of a single-stage power oscillator archi-tecture, as the oscillator load would be substantial, therebyrequiring either a separate driver or significantly more staticpower consumption. On the other hand, Table I indicates thatpeaks at 900 MHz, not 2.4 GHz. However, extremely high

is not necessarily desirable in this case: a very high impliesthat radiation efficiency is low. What we desire here is finite,positive , with maximum radiation efficiency, and a positivereactance for ease of on-chip matching. As a result of theseconsiderations, a frequency of 2.4 GHz was chosen to complywith the simplified architecture philosophy and extreme powergating possibilities. Additionally, this provides an opportunityto communicate in the uncrowdedMedical Body-Area Network(MBAN) band at 2360–2395 MHz recently allocated by theUnited States Federal Communications Commission (FCC)and supported by the recently passed IEEE 802.15.6 standard[31].In terms of sizing optimization, the antenna has restrictions

not only from anatomy, but also from a resonant frequencyperspective. It is known that the radiation resistance of anelectrically-small loop antenna increases with the square ofthe area of the antenna (see (4) in the Appendix), while theloss resistance only increases linearly with area. It would thenbe beneficial to size the antenna as large as possible givenanatomical constraints for maximum radiation efficiency.However, increasing the antenna size also increases its in-ductance (2). Since the antenna-chip interface contains fixedparasitic capacitance (bond pads, electrostatic discharge (ESD)protection diodes, etc.), the maximum resonant frequency willin fact decrease with increasing antenna size. Fig. 3 presentselectromagnetic simulation of a rectangular antenna where theantenna height is swept from 2 mm to 7 mm, for a fixed widthof 3 mm at 2.45 GHz in air with an FR-4 substrate. The max-imum center frequency was calculated based on the simulatedinductance, and a layout-extracted parasitic capacitance of 300fF. As predicted, radiation efficiency does indeed increase withantenna size. However, the maximum parasitic-limited reso-nant frequency decreases; 2.4GHz resonance is not achievablebeyond an antenna height of 4.5 mm. This places a functionalupper bound on the antenna size given the requirement toradiate in the 2.4 GHz ISM band. Based on the precedinganalysis, an antenna size of mm with an inductance of9.5 nH in air is chosen for this design in order to maximizeradiation efficiency given both the anatomical and resonantfrequency size constraints.In the above analysis, the loop antenna was optimized for

maximum radiation efficiency. However, it still must also actas a receiver of wireless power for system initialization, thoughsince kick-starting only happens once, its efficiency is not ex-tremely important. Interestingly, the simulated wireless powertransfer gain through 13 mm of tissue was found to be 15.5 dBat an optimal frequency of 1.45 GHz, which is in line withprevious work in this area [13]. At 2.4 GHz, the gain falls to17.5 dB, an acceptable trade-off for not requiring re-tuning.

Fig. 3. Electromagnetic simulation results for varying the antenna height for afixed, 3 mm antenna width.

Fig. 4. Detailed circuit schematic of the 2.4 GHz radio transmitter with in-tegrated wireless energy receiver. High- switches are shown in green, andsignals operating from the charge pump supply are shown in red with dash-dotlines.

IV. CIRCUIT DESIGN

A transistor-level schematic of the transmitter and wirelessenergy receiver architecture is shown in Fig. 4. The followingsubsections describe the system operation, including details ofeach individual block.


A. Power Management

The transmitter receives its supply voltage, , from anon-chip boost converter whose details are discussed in [10].The value of is set by a balance between the amount ofenergy extracted from the EP and the power of the load circuits.Though no explicit regulation is performed in this initial proto-type, the load circuit power consumption increases with ,thereby producing a quasi-regulation effect. Future revisionscould explicitly introduce feedback regulation by sensingand dynamically modulating the activation frequency, outputpower, or other load circuit characteristics. During clinicalmeasurements of this prototype, has been shown to varybetween 0.8–1.0 V [8], which is where the transmitter wasoptimized to operate. Diode-clamp circuits are employed toensure does not exceed process safety standards. Theboost converter also supplies a boosted power supply voltage,

, generated by an on-chip charge-pump. Ideally,, though in practice is slightly lower

than this as current is drawn from this supply. The dynamicsof start-up enable a simple Power-On-Reset (POR)scheme, which is discussed, along with the wireless kick-startparadigm, in Section IV-D.

B. Power Oscillator

The core of the transmitter is the power-oscillator, com-prising the cross-coupled pair of transistors (M1 and M2),footer power-gating/biasing transistors Mf[5:0], a capacitivetuning DAC (comprising eight parallel instances of transistorsMs1-3), and the loop antenna. OOK modulation is achievedby dynamically activating footer transistors Mf[5:0], therebyturning on or off the oscillator at the OOK modulation fre-quency. Similarly, FSK modulation is achieved by dynamicallyre-configuring the 8-bit capacitive DAC between differentcenter frequency settings. The power-oscillator is biased viaa center-tap in the loop antenna that is directly connected tothe system power supply, , through an on-board via thatconnects to a plane below (as shown in Fig. 1).Since the transmitter draws significant amounts of active-

mode power, it is not suited to operate from the on-chip decou-pled charge pump supply, . As a result, the cross-cou-pled devices M1 and M2 are implemented using low- devicesin order to reduce parasitic drain capacitance by comparedto high- devices sized for equivalent on-conduction (from2.8 pF to 280 fF) at . The reduced capacitance permits asignificantly larger antenna as discussed in Section III than ifhigh- devices were instead used. During OOK modulation,the capacitance at the source terminals of the cross-coupledM1 and M2 devices only switches at the data rate frequencyand not at RF. Consequently, the power oscillator can be bi-ased using high- NMOS transistors without any recourse tooperational speed. This permits standby-mode leakage currentsthat are lower for equivalent on-conduction. To further re-duce active energy consumed per transmitted bit, the high-NMOS devices are enabled by full-swing signals operating at

, which decreases the associated gate capacitance (andtherefore active OOK switching energy) by for equiva-lent on-conduction. The biasing circuit specifically consists ofsix binary weighted devices (Mf[5:0]) with ratios ranging

Fig. 5. Simulated capacitor quality factor versus parasitic switch capacitancefor single-ended and differential switches.

from 16 m/0.35 m to 0.5 m/0.35 m in order to controlthe amount of on-current for output amplitude swing control, ordynamic pulse shaping in a future implementation. To reiterate,the biasing transistor gates are not driven by an intermediatevoltage as set by a current reference, but rather they are drivenby full-swing digital signals at in order to maximize

to ratios.Resonant tuning of the antenna inductance within the

power oscillator is implemented primarily using a 5-bit bi-nary-weighted Metal-Insulator-Metal (MIM) capacitive DAC,totaling approximately 300 fF. The DAC is dynamically ac-tivated using differential switches, which according to thesimulation result shown in Fig. 5, reduces the parasitic switchcapacitance by for a capacitor quality factor of approxi-mately 50 (or up to for lower quality factors). A separate3-bit sub-ranging DAC is implemented using custom-designedMetal-Oxide-Metal (MOM) capacitors, where a 3 fF unit-sizedMOM cap is placed in series between the main DAC andsub-DAC. Although parasitics can be larger than the sub-DACunit capacitors, the sub-DAC can still be employed to providefine frequency control, with 0.25 fF switchable at the (LSB)using differential smaller-than unit 0.6 fF MOM capacitors inseries with the 3 fF splitting capacitors [32]. The sub-DACis specifically used to achieve minimal bandwidth FSK mod-ulation. For example, Minimum-Shift Keying (MSK), whichuses the theoretically smallest amount of FSK bandwidth fora given data rate, requires approximately 0.5 fF of switchablecapacitance at 2.4 GHz when communicating at an instanta-neous data rate of 5 Mbps. Although non-linear, the sub-DACis monotonic, which is sufficient for FSK/MSK purposes.Including the DAC, the resonant circuit achieves a tuningrange from 2.1–2.6 GHz, simulated in Cadence using extractedantenna s-parameters from IE3D and extracted circuit modelsfrom layout.

C. Ring Oscillator, Modulator, and Control

For this particular prototype, transmitted data comes fromoff-chip (for example, from a digital sensor interface) or on-chipmemory. The modulating frequency that clocks-in this data isgenerated by an on-chip ring oscillator, shown in Fig. 6. Theoscillator is a five-stage current-starved inverter-based design.To minimize active switching power, the inverter devicesuse low- transistors. However, overall current is dictated by6 bits of NMOS and PMOS degeneration devices, separated


Fig. 6. Current-starved ring oscillator schematic. High- devices are shownin green.

into two groups of control: coarse and fine. Since generatingan on-chip current reference would consume excessive staticpower, current starving devices are instead sized to operate asresistive elements (i.e., in the triode regime) when driven byfull-swing input signals (i.e., at ). For manufacturing andoperational reliability, the ring oscillator is designed to operatefrom 100 kHz to 10 MHz across process corners and vari-ation. To achieve the high-end frequencies in slow process cor-ners, low- devices are used for the coarse [2] control signal.To achieve low-end frequencies at fast process corners, two-bitsof capacitive tuning are included in each inverter delay element.To minimize active energy consumption, these extra ca-pacitors should not be activated unless it is necessary to achievethe desired operational frequency. During standby mode, the os-cillator is put into a low-leakage state by gating the output andgating all current starving elements.The data modulator consists of digital logic that is manually

designed primarily using low- -based standard cells in orderto minimize switching power losses that occur at thedata modulation frequency. A schematic of the main data path isshown in Fig. 7. It accepts a digital clock from the ring oscillator(labeled as in Fig. 7) for simple fully-integrated testing, orcan accept externally driven serial data (labeled as data in Fig. 7)for benchtop testing or eventual system integration with a sep-arate sensor. Depending on if OOK or FSK modulation modesare enabled (via enOOK and enFSK signals, respectively), ei-ther the power-oscillator biasing transistors (Mf[5:0] in Fig. 4),or the capacitive DAC transistors (Ms1-3) are activated, re-spectively. FSK is achieved by switching between two differentprogramming codes (i.e., frequencies), set by [7:0] and

[7:0]. A inverter-transmission gate circuit [6] is used tocreate phase-matched differential signals to drive a multiplexorselecting one of or at a time.To decrease the standby current of the power oscillator bi-

asing devices (Mf[5:0]) for a given on-current, the modulatoroutput signals are driven from the supply. A similareffect is arranged for the capacitive DAC to increase its qualityfactor. Level-conversion to the higher voltage is achieved usinga standard cross-coupled level shifter circuit. Since the outputis single-ended, a dummy driver load is installed for edge tran-sition matching purposes. The entire modulator is power gated

Fig. 7. Main data path of the modulator.

by PMOS devices MP1 and MP2 whose inputs are driven byenPGATE—a signal driven from the supply. Powergating saves upwards of 4,000 in leakage power from thesupply (MP1), and from the supply (MP2). Thesavings are larger from MP1 since the device enters the supercut-off regime upon application of to its gate. The sizeof power gating devices are annotated in Fig. 7, with MP1 andMP2 having on-resistances of approximately 1.8 and 600at 15 and 35 , respectively. The area overhead of powergating here is minimal, occupying the area of approximately sixNAND gates in this design.The output of the ring oscillator also clocks a counter and

comparator that are used to set the number of bits transmittedin a single packet. The counter, whose schematic is shown inFig. 8, uses a ripple-carry frequency divider for the first tworegisters. The final two counter stages use a synchronous de-sign that is pre-scaled to reduce the critical path, enabling suffi-ciently fast operation at low voltages using low-leakage devices[33], [34]. Although the counter itself is a 7 bit design, onlythe final 5 bits are applied to the comparator, as the utility oftransmitting 1–4 bit packets is limited. Furthermore, rather thandesigning a full 5 bit adder to count to arbitrary 5 bit packetlengths, a simple 5 bit power-of-two comparator is used, en-abling counting intervals ranging between 8 and 128 in powersof two only. This reduces the gate count by , resulting ina low-complexity, low-leakage design. The counter is powergated by a single PMOS device (size: 6 m/0.18 m, or an ap-proximate overhead of 3%), nominally saving in standbypower. Since the circuit operates using the supply, it is pos-sible to gate the PMOS device with the supply, forcingthe transistor into super cut-off, and saving an additionalin leakage, or in total. The on-resistance of the PMOS isapproximately 1.2 k at 10 .A start-up logic block is designed to receive an activation

signal, nominally generated by the boost converter, which dis-ables the appropriate power gating devices and initializes thering oscillator and modulator. Since the start-up block itselfcannot be power gated, it is designed using almost exclusivelyhigh- devices for minimal leakage power consumption.


Fig. 8. Circuit schematic of the 7-bit (5-bit output) counter, with the 5-bit com-parator used to set the transmitted packet length.

D. Wireless Energy Receiver and Power-on Reset

The wireless energy receiver circuit design is already in-cluded in Fig. 4. In fact, since the antenna can be modeled asan inductor that has a center tap, creating a full bridge rectifieris as simple as placing two diodes between the two ends of theinductor, connected to ground (diodes D1 and D2 in Fig. 4).Interestingly, these diodes are in fact already required for ESDprotection. Thus, adding wireless power transfer functionalitydoes not add any additional complexity and, more importantly,does not add any additional parasitic capacitance on the sen-sitive antenna interface nodes. As described in Section III,reduced parasitics on these nodes permit the design of a larger,more efficient antenna given a resonant frequency requirementof 2.4 GHz. Naturally, diodes D1 and D2 only protect theground supply; additional diodes are required to protect thepositive (i.e., ) supply. However, since the antenna iscenter-tapped and biased at , the power oscillator outputRF signals naturally swing symmetrically above and below

. If only a single set of diodes were placed to protect ,these RF voltage swings would be limited to a single diodedrop. The solution here is to instead stack three diodes in series.Following wireless energy delivery for the purpose of ini-

tializing , it is of critical importance to ensure the chip isreset to a known-good state. If, for example, the power oscil-lator gating switches were somehow enabled after the externalwireless energy source was removed, the on-current would belarge enough to catastrophically collapse the supply. Toavoid such an event, a reliable POR is required. Fortunately, cre-ating a POR signal can be achieved in a very low-complexity,low-leakage manner. Since the charge pump supply, ,requires 600 ms to initialize following initialization [9],[10], a simple inverter structure can be used to generate the req-uisite POR signal, as illustrated in Fig. 4. Specifically, an in-verter powered from the supply with at the inputwill nominally output a logic high value until crossesthe inverter threshold (nominally several hundred millisecondsafter initialization). The inverter is designed with high-transistors, since there is no opportunity to power-gate the ini-tialization logic. The leakage impact of this inverter is negli-gible, however, since after the reset signal has been deactivated,the leakage of the inverter is set by the PMOS device which inthis case is biased in super cut-off due to the presence ofas its input.

Fig. 9. Die photograph.

Fig. 10. Photograph of the chip-on-board package (the protective epoxy cov-ering the chip is not shown for clarity).

TABLE IISUMMARY OF CHIP RESULTS

While the circuit is implanted it is not possible to directlymeasure kick-start and POR success with immediate feedback.Instead, successful start-up can be confirmed when the radiotransmits its first packet.

V. MEASUREMENT RESULTS

The transmitter was fabricated in a 0.18 m process and oc-cupies a core area of 0.035 mm . The overall die size ismm including the DC/DC converter, as shown in Fig. 9; the

design is thus severely pad-limited (future revisions can reducethe pad count substantially by providing programming, testing,and calibration functionality through a scan-chain). To mini-mize packaging parasitics and size, the chip was directly wire-bonded to a PCB using chip-on-board packaging technology.Exposed copper pads on the PCB were finished with 2 m ofsoft gold over 6.4 m of nickel for wirebonding compatibility.The chip was directly bonded to an on-board mm an-tenna. A photograph of the board is shown in Fig. 10. Table IIsummarizes the transmitter results.

A. RF Performance

Since the antenna is part of the resonant network of thepower oscillator, it was not possible to directly test or probe the


Fig. 11. Active-mode output power of the radio transmitter measured from ap-proximately 5 mm from the on-board loop antenna, plotted versus power oscil-lator current configuration settings.

Fig. 12. Measured active-mode power consumption of the transmitter plottedversus power oscillator current configuration settings.

output power of the transmitter. Instead, wireless testing wasperformed, unless otherwise specified, by placing the centerconductor of a 2.4 GHz, whip antenna approximately5 mm from the loop antenna. Testing the radio transmitterwith this setup revealed that the maximum wirelessly receivedpower was 21.9 dBm when operating with andthe maximum current setting in the power oscillator. Fig. 11reveals measurements for additional supply voltages across allpower oscillator tuning bits. When placing the whip antennaat a distance of 1 m from the loop antenna, the maximumwirelessly received power was measured to be approximately60 dBm. These measurements suggest that the maximum

output power of the transmitter is approximately 20 dBm.Fig. 12 shows the consumed power of the transmitter when inactive mode under the same conditions. The power oscillatorachieved a phase noise of 105 dBc/Hz at 1 MHz offset.Fig. 13(a) shows measured OOK spectral results modulated

by random externally derived bits at data rates of 1 Mbps and10 Mbps. Achieved 3 dB bandwidths and energy per bits for 1Mbps and 10 Mbps data rates are 620 kHz and 2 MHz, and 191pJ/bit and 19 pJ/bit, respectively. No explicit filtering is per-formed here; the attenuated side-lobes may be attributed to an-tenna filtering and oscillator start-up transient effects. Interest-ingly, there is no apparent feed-through component found in thespectrum, which is typical for non-phase scrambled OOK trans-mitters. This implies that the PO start-up is not coherent, and has

a certain amount of randomness in its phase. Fortunately, this re-sults in a more desirable spectrum, as OOK is normally usedin non-coherent communication systems anyways. Fig. 13(b)shows measured spectra using FSK and near-MSK modulation.The power oscillator achieves a frequency tuning range from2.1 GHz to 2.54 GHz across the 8-bit capacitive DAC when res-onating with the on-board mm inductive loop antenna,matching simulated results well.The transmitter is capable of starting-up in 180 ns, as shown

in Fig. 14, enabling rapid and aggressive duty-cycling into low-power sleep states. The start-up time is dictated primarily bythe slow, high- logic in the start-up block, which in simula-tions requires approximately 120 ns to propagate the initializa-tion signal through a D flip-flop and a small number of logicgates. Note that during this period the PO is not activated, andthe overall transmitter power consumption is still dominated byleakage.

B. Ring Oscillator

By tuning the current starving and capacitive loading bits,the ring oscillator was measured to generate clock frequenciesfrom below 100 kHz to at least 100 MHz while consumingbetween 14 nW and 19 W across supply voltages rangingfrom 0.7 V to 1.0 V. This large amount of configurability wasrequired to be able to generate the requisite frequencies acrosssevere PVT variation. To show the effects of current starvingversus capacitive tuning, the measured energy required peroutput cycle, plotted versus achievable frequencies, is illus-trated Fig. 15. Here, it is clear to see four distinct zones ofenergy consumption—a result of the four capacitive loadingoptions, [1:0]. Although the ring oscillator consumes asmall fraction of the total transmitter active energy budget, itsenergy efficiency is clearly maximized at the lowest capacitiveloading setting.

C. Power Consumption

By implementing a low-complexity architecture togetherwith leakage-aware design considerations, the transmitterstandby power consumption was measured to be 39.7 pW ata supply voltage of 0.8 V. Table III summarizes the measuredtransmitter standby power at several different voltages andcompares the results to simulated results at 0.8 V. The simu-lated results matched the measured results with a reasonableamount of accuracy, landing somewhere in between the sim-ulated results in the TT and FF corners (with the exceptionof the digital supply, which resulted in higher power than theFF corner, though this was a minor component overall). Theleakage power from the and ring oscillator suppliesare the largest since they were not power gated by a transistorin super cut-off (it was simply not possible for , whilethe ring oscillator was designed before the charge pump andnot later modified during the design cycle). Total transmitterstandby power measured at various supply voltages are shownin Fig. 16. Low-current measurements were performed using aKeithley 6430 sourcemeter together with low-leakage tri-axialcables.To minimize the energy required to transmit a bit of informa-

tion during active mode, it is worthwhile to operate the PO at


Fig. 13. Measured spectra taken using a whip antenna a few centimeters from the on-board loop antenna. (a) OOK modulation at 1 Mb/s (dark) and 10 Mb/s(light). (b) FSK modulation at 1 Mb/s (dark) and near-MSK 2.5 Mb/s (light).

Fig. 14. Measured transient response, showing a 180 ns startup time betweenan enable signal and RF output.

Fig. 15. Measured energy required for every cycle of the ring oscillator at.

TABLE IIIMEASURED STANDBY-MODE POWER BREAKDOWN AT VARIOUS SUPPLY

VOLTAGES COMPARED TO SIMULATED RESULTS

an intermediate back-off point. For example, at ,a data rate of 5 Mbps, and a measured output power of at least26 dBm or 29 dBm, the transmitter consumed 374 W or

191 W for FSK and OOK modulations, respectively. This re-sults in a energy efficiency of 75 pJ/bit or 38 pJ/bit for FSK andOOK, respectively. A power breakdown of these two operatingpoints is shown in Table IV.

Fig. 16. Measured standby power of the radio transmitter plotted versus var-ious system supply voltages.

TABLE IVMEASURED ACTIVE-MODE POWER BREAKDOWN OF THE RADIO TRANSMITTER

OPERATING AT 0.8 V AND AT A FREQUENCY OF 2.48 GHZ

Combining this active-mode data point in OOK mode to-gether with leakage power as suggested by (1), results in thetotal average transmitter power consumption of

at an average data rate of 1 bps. In fact, the transmittercan achieve average data rates up to higher while main-taining an average power consumption below the 250 pW powerbudget specified by the endocochlear potential harvesting appli-cations. Table V summarizes the chip results compared to ex-isting state-of-the-art.

VI. CONCLUSIONS

This paper has presented the design of a radio transmitterthat was optimized for aggressive duty-cycling between anenergy-efficient active mode and an ultra-low-power standbymode for low data rate applications. By employing aggressivepower gating, sizing, and architectural strategies, the trans-mitter consumed 39.7 pW in standby mode. Integrated with anon-board antenna, and employing a direct-RF power oscillatorarchitecture with automatic impedance matching, the trans-mitter required 38 pJ to transmit a single bit of information.Operating at a duty ratio of 0.00002% and transmitting anaverage of 1 bps, the transmitter achieved an average power


TABLE VCOMPARISON OF PREVIOUSLY PUBLISHED ENERGY EFFICIENT

AND/OR LOW POWER TRANSMITTERS

Most transmitter publications do not report standby/leakage power.

consumption of 78 pW. The transmitter was then used withinan energy harvesting platform that extracted energy from theendocochlear potential within the inner-ear, demonstrated thefeasibility of sub-nW radio transmitter designs.

APPENDIX

ANTENNA CALCULATIONS

A circular loop antenna’s inductance can be approximated by(2):

(2)

Here, is the permeability of the surrounding environment, isthe diameter of the loop, and is the diameter of the constituentwire [35].The antenna’s series resistance, , is made up of a ra-

diation resistance, , and a loss resistance, . Theradiation efficiency, , can be calculated using:

(3)

The radiation resistance can be approximated by:

(4)

Here, is permittivity, is the antenna’s area in units of , andis the operational wavelength. The loss resistor, can becalculated in the usual way frommetallic conduction properties,taking into account the skin effect. The skin depth, , is givenby (5), and the associated loss resistance, , is given by(6):

(5)

(6)

Here, is the metallic conductance, while and are thelength and width of the PCB trace (an appropriate approxima-tion for flat PCB traces).

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Patrick P. Mercier (S’04–M’12) received the B.Sc.degree in electrical and computer engineering fromthe University of Alberta, Edmonton, AB, Canada,in 2006, and the S.M. and Ph.D. degrees in electricalengineering and computer science from the Massa-chusetts Institute of Technology (MIT), Cambridge,MA, USA, in 2008 and 2012, respectively.He is currently an Assistant Professor at the

University of California at San Diego (UCSD), LaJolla, CA, USA, in the Department of Electricaland Computer Engineering. His research interests

include the design of energy-efficient microsystems, focusing on the designof RF circuits, power converters, and sensor interfaces for biomedical andimplantable applications.Prof. Mercier was a co-recipient of the 2009 ISSCC Jack Kilby Award for

Outstanding Student Paper at ISSCC 2010. He also received a Natural Sciences

and Engineering Council of Canada (NSERC) Julie Payette fellowship in 2006,NSERC Postgraduate Scholarships in 2007 and 2009, an Intel Ph.D. Fellow-ship in 2009, and a Graduate Teaching Award in Electrical and Computer En-gineering at UCSD in 2013. He currently serves as an Associate Editor of theIEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS.

Saurav Bandyopadhyay (S’08–M’13) received theB.Tech. (Hons.) degree in electronics and electricalcommunication engineering and the M.Tech. degreein microelectronics and VLSI design from the IndianInstitute of Technology (IIT), Kharagpur, India, in2008, and the S.M. and Ph.D. degrees in electricalengineering and computer science from the Massa-chusetts Institute of Technology (MIT), Cambridge,MA, USA, in 2010 and 2013, respectively.He is currently a power management IC designer

in Texas Instruments Inc., Dallas, TX, USA. Hisresearch interests include power management and energy-efficient integratedmixed-signal integrated circuits and systems.Dr. Bandyopadhyay is the co-recipient of the Arun Kumar Choudhury Best

Paper Award at the 21st International Conference on VLSI Design, 2008.

Andrew C. Lysaght received the B.S. and M.S.degrees in mechanical engineering from the Uni-versity of Connecticut, Storrs, CT, USA, in 2006and 2008, respectively. He is currently completinghis Ph.D. thesis in the Joint Health Sciences andTechnology program at Harvard University andthe Massachusetts Institute of Technology (MIT),Cambridge, MA, USA.His thesis research applies next-generation

sequencing and proteomics techniques to the mam-malian auditory system to elucidate molecular

mechanisms of hearing decline and build insight towards useful diagnostictools.

Konstantina M. Stankovic received the B.Sc.degrees in physics and biology and the Ph.D. degreefrom Massachusetts Institute of Technology and theM.D. degree from Harvard Medical School with aresidency in otolaryngology, postdoctoral researchfellowship, and a clinical fellowship in neurotologyskull base surgery.She is currently an Assistant Professor of Otology

and Laryngology at Harvard Medical School and anAssociate Surgeon at Massachusetts Eye and Ear In-firmary in Boston. Her research program is cross-dis-

ciplinary and focused on hearing loss. She combines tools of systems neuro-science with electronics, optics and molecular studies to develop novel diag-nostics, prognostics and therapeutics for deafness. She serves on the EditorialBoard of Otology and Neurotology, and is President of the American AuditorySociety.

Anantha P. Chandrakasan (F’04) received theB.S., M.S., and Ph.D. degrees in electrical engi-neering and computer sciences from the Universityof California, Berkeley, CA, USA, in 1989, 1990,and 1994, respectively.Since September 1994, he has been with the Mass-

achusetts Institute of Technology, Cambridge, MA,USA, where he is currently the Joseph F. and NancyP. Keithley Professor of Electrical Engineering.He was the Director of the MIT MicrosystemsTechnology Laboratories from 2006 to 2011. Since

July 2011, he has been the Head of the MIT EECS Department.Dr. Chandrakasan was a co-recipient of several awards including the 1993

IEEE Communications Society’s Best Tutorial Paper Award, the IEEE Electron


Devices Society’s 1997 Paul Rappaport Award for the Best Paper in an EDSpublication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Awardfor Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Stu-dent Paper (2007, 2008, 2009). He received the 2009 Semiconductor IndustryAssociation (SIA) University Researcher Award. He was the recipient of the2013 IEEE Donald O. Pederson Award in Solid-State Circuits.His research interests include micro-power digital and mixed-signal inte-

grated circuit design, wireless microsensor system design, portable multimediadevices, energy efficient radios and emerging technologies. He is a co-authorof Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995),Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), andSub-threshold Design for Ultra-Low Power Systems (Springer 2006). He isalso a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of

High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakagein Nanometer CMOS Technologies (Springer, 2005).He has served as a technical program co-chair for the 1997 International Sym-

posium on Low Power Electronics and Design (ISLPED), VLSI Design ’98, andthe 1998 IEEEWorkshop on Signal Processing Systems. He was the Signal Pro-cessing Sub-committee Chair for ISSCC 1999–2001, the Program Vice-Chairfor ISSCC 2002, the Program Chair for ISSCC 2003, the Technology Direc-tions Sub-committee Chair for ISSCC 2004–2009, and the Conference Chairfor ISSCC 2010–2014. He is the Conference Chair for ISSCC 2015. He was anAssociate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1998to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meet-ings committee chair from 2004 to 2007.

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