Active-Feedback Frequency Compensation for Low-Power Multi-Stage Amplifiers

Hoi Lee and Philip K. T. Mok

Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology

Tel.: (852)2358-85 17, Fax: (852)2358-1485, Email: leehoi@ee.ust.hk, eemok@ee.ust.hk Clear Water Bay, Hong Kong

Abstract This paper describes a novel active-feedback frequency compensation (AFFC) technique for low-power multi-stage amplifiers. With a high-speed active feedback block, the proposed compensation technique significantly improves both the frequency and the transient responses of the amplifier. Implemented by a standard 0.8pm CMOS process, a three- stage AFFC amplifier achieves lOOdB gain, 4.5MHz gain- bandwidth product, 65" phase margin and 1.5V/ps slew rate with 0.4mW power consumption when driving a lOOpF capacitive load.

1. Introduction With the continuous decrease in the supply voltage of analog

circuits in advanced CMOS technologies, multi-stage amplifiers are becoming increasingly important since the single-stage cascode amplifier is not suitable for low-voltage designs. However, all multi-stage amplifiers suffer 60m closed-loop stability problems.

Different frequency compensation topologies for multi- stage amplifiers have been reported [ 1-51. Nested-Miller compensation (NMC) [1,2] is a well-known technique for compensating multi-stage amplifiers. However, as mentioned by Eschauzier er al. [l], NMC suffers from the bandwidth reduction. In particular, the bandwidth of a three-stage NMC amplifier is reduced to one quarter of that of a single-stage amplifier. Thus, based on NMC, multipath nested Miller compensation (MNMC) [ 1,2] and nested Gm-C compensation (NGCC) [3] are used to extend the bandwidth by approximately a factor of two when compared to NMC topology. Other non-standard NMC topologies such as embedded tracking compensation (ETC) [4] and damping- factor-control frequency compensation (DFCFC) [5] are proposed to significantly increase the bandwidth by reducing the output capacitive loading due to Miller capacitors. However, as all the published compensation topologies use passive capacitive feedback networks, the bandwidth is still limited for high-speed applications.

In order to firther improve the bandwidth, a novel active- feedback frequency compensation (AFFC) technique is proposed. In contrast to using passive capacitive feedback networks, AFFC proposes to use an active feedback mechanism, in which a gain stage is added in series with a compensation capacitor so that the required compensation capacitor in AFFC is reduced to smaller than that in other passive compensation topologies. As a result, the physical dimension of the amplifier is reduced and thus both the transient response and the bandwidth are improved. The comparison of bandwidth on three-stage amplifiers using different compensation topologies

This work, AFFC l l ( C 8 E )

DFCFC 151

NGCC [3]

0 . Passive Feedback

C . By Calculation

MNMC [1.2]

NMC 11.21

Single Stage [l]

0 2 4 6 8 10 12

Relative Bandwidth with 100pF Capacitive Load Figure 1 Comparison of bandwidth on different frequency compensation topologies (take NMC as the reference)

driving a IOOpF capacitive load, as shown in Figure 1, indicates that a three-stage AFFC amplifier achieves the largest reported bandwidth.

In the next section, the operation principle of the multi- stage AFFC amplifier is introduced. Then, different issues of a three-stage AFFC amplifier such as the structure, the transfer function, the stability criteria, the small-signal ac response, the transient response and the power optimization are discussed in Section 111. In Sections IV and V, implementation issues and experimental results are presented. Finally the paper concludes in Section VI.

11. Operation Principle of Multi-Stage AFFC Amplifier The structure of a multi-stage AFFC amplifier is shown in

Figure 2. The transconductance, the lumped resistance and the parasitic capacitance of the gain stages are notated by g,,,(i-

N), &?+I)) and C(l+-,)), respectively. Also, CL is the loading

High-Speed Block (HSB) Figure 2: Structure of a multi-stage AFFC amplifier

19-1 -1 0-7803-7250-6/02/$10.00 0 2002 IEEE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE

capacitor and RL is the loading resistor. It should be noted that AFFC amplifier consists of three main blocks. One is the input block, which is realized by a differential pair. The other is the high-gain block (HGB), which consists of N-l gain stages cascaded together in order to boost the DC gain of the AFFC amplifier. For the high-speed block (HSB), it consists of a feed-forward transconductance stage (FTS) with the transconductance g,f and a feedback transconductance stage (FBS) with the transconductance g,, connected in series with a compensation capacitor Ca. Figure 3 shows the equivalent small-signal circuit of the HSB in AFFC amplifier, in which the input resistance of the FBS is r, and the equivalent resistance and capacitance at node V2 due to the input block and the HSB are RI and CI, respectively. At high frequency, any output signal voltage change will be sensed through the input resistance of FBS such that the signal at V, is almost the same as the signal at V, given as

~ = ~ ~ I ( @ h i g h f r e q u e n c y ) ( I ) '0 ra+-

SCa

1

Then the signal at V, will be feed-backed to the output of the input block and amplified by the positive gain of the FBS. The amplified feedback signal at the output of the input block will then be feed-forwarded to the output again, through the FTS, in order to reduce the original output signal change. As the slow high-gain block is bypassed during the whole negative feedback action at high fiequency and as a smaller compensation capacitor C, is used due to the positive gain of the FBS, a significant bandwidth enhancement is achieved in the AFFC amplifier.

The FBS can also block the feed-forward capacitive path from the output of the input block to the output of the amplifier and thus the right-half-plane (RHP) zero is effectively removed. Moreover, the input resistance rs of the FBS and the compensation capacitor C, introduce a left half plane (LHP) zero to the amplifier, which helps to boost the 'phase margin and improves the stability of the AFFC amplifier. For the FTS, the value of gmf is chosen to equal to the transconductance of the output stage g" in order to implement a push-pull output stage for improving the slewing performance.

Figure 3: Equivalent small-signal circuit of the high-speed block in AFFC amplifier.

111. Design of Three-Stage AFFC Amplifier As three-stage amplifiers maintain a good compromise

between the voltage gain (-100dB) and the power consumption, a three-stage AFFC amplifier, which consists of a input block and a two-stage HGB, is used to demonstrate the effectiveness of the active-feedback frequency compensation technique. .A three-stage NMC amplifier is used as a reference for comparison as it is a well-accepted topology based on the passive feedback mechanism in multi-stage amplifiers.

The HGB in the three-stage AFFC amplifier can be implemented by using a two-stage Miller amplifier [6 ] to provide a sufficient DC voltage gain. As shown in Figure 4, the transconductances of the two gain stages are denoted as gmz and g,3, respectively, with a Miller compensation capacitor C,.

8- - - - - - - - - - - L------------------. - HOB using two-stage Mtllsr amplifier

Figure 4 Equivalent small-signal circuit of a three-stage AFFC amplifier

A Transfer Function To analyze the stability of the AFFC amp!ifier, the small-

signal transfer function of the amplifier shown in Figure 4 is investigated, with the following assumptions: (1) ra=l/gm; (2)

for simplicity. The transfer function is given as CL, Cm G>>CI, CZ; (3) ~ M ~ J & I , Z L ~ gmaRi>>1; and (4) Ca=Cm

Adc(l+S-) Ca gma (2) *v(AFFC)= CICL +s2-- C l C F (I+-)( 1 +s

~ - 3 d ~ C a b f - g m d gma(gmf-gm2) where %, = gmlgm~gm3RlR~R~ is the dc gain, and PJdB = (C&,,g,,,3RIR2R~)" is the dominant pole. In fact, the transfer function still holds true even if C,+C,,, and normally one can optimize the size of compensation capacitors by setting C,<C,.

Equation (2) shows that a LHP zero is created in the amplifier, which can increase the phase margin of the amplifier, and the gain-bandwidth product is controlled by the size of C, In fact, for a fixed C,, the Qvalue of the non-dominant complex poles, ~ 2 . 3 can be controlled by the transconduictance of FBS, g,, The Q-value of the non-dominant poles is given by

Moreover, the non-dominant poles locate at very high fiequency as the second order function depends on1 the parasitic capacitance CI instead of the compensation capacitor Cm? in the NMC amplifier.

B. Stabiliry Criteria, GB W and Phase Margin The stability of the AFFC topology can be achieved by

considering only the poles of the AFFC amplifier in unity-gain feedback configuration having third-order Butterworth response. Then the dimension conditions are given by

Ca(AFFC)'Cm(AFFC) and gma =4'gml

(4) =-- 4 g m i cL n gm3 1

= ; C m I m c )

where n = , / (8 .CLgml(gmf -gm2))/(cI .gm3) 2 . The dimension

condition of the compensation capacitors is less sensitive to

326 19-1 -2

the global variations of circuit parameters as it only depends on the ratios of transconductances and capacitances. As n>>l, the size of C, in AFFC is much smaller than that of C,, in NMC. In multi-stage amplifiers, most of the chip area will be occupied by the compensation capacitors especially when driving large capacitive loads. Thus, the area of the AFFC amplifier is significantly smaller than that of the NMC counterpart.

Applying (4) into (2), the GBW of the AFFC is given by gml

GBW(AFFC) = - c a

4CL = nGBWmMC)

From equation (9, the GBW is enhanced by n times compared to that of the NMC amplifier.

By taking left half plane zero ZLHp and the dimension conditions shown in equation (4) into considerations, the phase margin of AFFC is given by

C. Transient Response

stage is given by The slew rate of the AFFC amplifier with push-pull output

SR = mi"[ I, c a 'C" a) (7)

where I, and Iz is the amount of biasing current charging or discharging the compensation capacitors in the HSB and the HGB, respectively. Based on the dimension conditions stated in equation (4), the size of compensation capacitors in the AFFC amplifier is reduced by n times compared to that in the NMC amplifier and thus the slew rate of the AFFC amplifier improves by n times. Furthermore, n increases with the value of the loading capacitor, thus the slew rate enhancement of the AFFC amplifier is even better when driving large capacitive loads.

The settling time of the AFFC amplifier only depends on the phase margin as pole-zero doublet does not exist in the pass- band. From equation (6), the phase margin of AFFC amplifier is much larger than 60". Thus, the output voltage of the AFFC amplifier can settle within short duration,

D. Power Optimization The second-stage transconductance gm2 can be set to a small

value in the AFFC amplifier in order to have a larger n and thus a larger bandwidth. In addition, the stability condition for the NMC amplifier gm3 >> gml, g,,, which is difficult to achieve in low-power designs [7], is not required in AFFC amplifier. Thus AFFC is suitable for low-power designs.

IV. Circuit Implementations Circuit implementation of a three-stage AFFC amplifier is

shown in Figure 5 . Transistor M, is the common gate amplifier to implement the FBS while transistor M300 is the FTS. The amplifier is designed to drive a IOOpF capacitive

load. To optimize the size of compensation capacitors in the AFFC amplifier, both Ca and C,,, are fine-tuned based on the tradeoff of power consumption, bandwidth and phase margin. The final values of compensation capacitors, C, and C, are 7pF and 3pF, respectively. In order to minimize the systematic offset of the AFFC amplifier, replica biasing scheme is adopted to bias the transistors & I and Mc2 such that the biasing current in McI equals to that in W2 [8].

~

19-1 -3 327

Figure 5: Circuit diagram of a three-stage AFFC amplifier

V. Experimental Results To verify the functionality of the AFFC amplifier and

compare its performance with that of the NMC amplifier, both 2V three-stage AFFC and NMC amplifiers were fabricated with a standard 0.8-pm CMOS process with Vm=IV,l=0.8V and the micrograph is shown in Figure 6.

The measured frequency responses and the transient responses of both NMC and AFFC amplifiers are shown in Figures 7 and 8, respectively. The detailed performances are tabulated in Table 1.

By comparing the AFFC amplifier to the NMC counterpart as shown in Table 1, the AFFC amplifier improves the GBW by I 1 times, the slew rate by 9 times and the settling time by 8 times for a lOOpF capacitive load. In fact, the bandwidth improvement of AFFC over NMC is greater than that provided by single-stage amplifier, while the increase in the power consumption by the AFFC amplifier is negligible.

Figure 6: Micrograph ofthree-stage NMC and AFFC amplifiers.

Table 1 : Measured results of the NMC and AFFC amplifiers I I NMC I This work. AFFf 1

Power mW Vdd

CL(pF) FOM,

MHz’pF (- ) mW

FOML

76@8 16@8 1.4@2 6 . 9 g 3 0.42@2 0.4@

100 100 20 40 100 100

79 132 14 272 619 1125

3GHzf, 3GHzf, 2pm 0.6pm 0.8pm 0 . 8 ~ BJT BJT CMOS CMOS CMOS CMOS

To provide a clearer picture on the improvement by AFFC, a comparison table of some published compensation topologies is shown in Table 2. Two figures of merit, FOMs and FOML [ 5 ] , are defined for small-signal and large-signal performances.

(8)

(9)

A larger FOM implies a better fiequency compensation topology. From Table 2, AFFC achieves the largest FOMs with a comparable FOML.

GBW.CL FOMs = - power

S R . C FOML =L power

VI. Conclusion An active-feedback frequency compensation for multi-stage

amplifiers is introduced. Based on AFFC, a three-stage amplifier is designed, analyzed and verified in this paper. With a common gate amplifier in series with the compensation capacitor and a feedfonvard stage in the high-speed block, the negative feedback action is achieved through bypassing the intermediate high-gain stages. Thus the bandwidth is significantly enhanced. Also both the physical dimension and the transient response of AFFC amplifier are improved as smaller compensation capacitors are used. Moreover, AFFC amplifier can be used in low-power designs. Finally, comparison with other published passive feedback topologies is presented, and AFFC shows better small-signal performance than all existing topologies.

Acknowledgment This work was supported by Research Grant Council of

Hong Kong SAR Government, China (Project No. HKUST 602210 1 E).

120

100

c BO

P 60 - 3 40

if20

0

-20 1 0‘ 1 o3 10‘ 10’ 1 o6 10’

F I W U E ~ (e) Figure 7: Measured frequency responses of NMC and AFFC amplifiers driving lO@F capacitive load.

2 LJS t 1 1 2 . 4 ys 1 se mv AC i-i

Figure 8: Measured transient responses of NMC and AFFC amplifiers driving IOOpF capacitive load.

References [I] R.G.H. Eschauzier ahd J.H. Huijsing, Frequency Compensation

Techniques for Low-Power Operational AmpliJers, Boslon. MA: Kluwer. 1995.

[2] R.G.H. Eschauzier, L.P.T. Kerklaan and J.H. Huijsing, ‘“A 100-MHz 100- dB operational amplifier with multipath nested miller compensation structure,’’ /E€€ Journal of Solid-State Circuits. Vol. 27, pp 1709- 17 17. Dec. 1992. .

[3] F. You, S.H.K. Embabi and E. Sanchez-Sinencio, “Multistage amplifier topologies with nested Gm-C compensation,” /E€€ Journul ojSolid-State Circuits. Vol. 32, pp. 2000-201 I , Dec. 1997.

[4] H.T. Ng. R.M. Ziazadeh and D.J. Allstot, “A multistage amplifier technique with embedded frequency compensation,” I€€€ Journal of Solid-State Circuits, Vol. 34, pp. 339-347. March 1999.

[5] K.N. Leung, P.K.T. Mok. W.H. Ki and J.K.O. Sin. “Three-stage large capacitive load amplifier with damping-factor-control frequency compensation,” /E€€ Journal of Solid-Stufe Circuits. Vol. 35, pp. 221- 230, Feb. 2000.

[6] P.R. Gray and R.G. Meyer, Analysis and Desrgn of Analog lntegrated Circuits, 2“ edition, New York: Wiley, 1984.

[7] K.N. Leung and P.K.T. Mok, “Analysis of multistage amplifier-frequency compensation,” I€€€ Transaction on Circuits and Systems-I. Vol. 48. pp. 1041-1056, Sept. 2001.

[8] R. Reay and G. Kovacs, “An unconditionally stable two-stage CMOS amplifier,” /E€€ Journal of Solid-Stute Circuits. Vol. 30, pp. 591-194. May 1995.

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