A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS Image Sensor

for Ultra-Low-Power SoCs achieving 40-dB Dynamic Range

David Bol, Guerric de Streel, Fran90is Botman, Angelo Kuti Lusala and Numa Couniot ICTEAM Institute, Universite catholique de Louvain, Louvain-Ia-Neuve, Belgium

{david.bol,numa.couniot}@uclouvain.be

Abstract We propose a CMOS image sensor operating at ultra-low

voltage (UL V) in a 65-nm low-power (LP) CMOS logic

process for ultra-low-power SoC integration. Energy of

17-pJ/frame.pixel and 4x4-/Jm pixel size with 57-% fill factor

are achieved at 0.5 V with digital pixel sensor (DPS) and

time-based readout while reaching 40-dB dynamic range (DR)

despite high leakage currents and Vt variability, thanks to

delta-reset sampling (DRS) as well as gating and adaptive body

biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.

Introduction Wireless sensor nodes (WSNs) for the Internet-of-Things

(loT) require ultra-low-power consumption for energy­

harvesting compatibility, and low die area for cost and carbon

footprint reasons [1]. Microcontrollers (MCUs) and radio

digital baseband for WSNs benefit from SoC implementation at

UL V in nanometer CMOS to minimize power [2]. When vision

capability is required, a separate imager chip in an appropriate

CMOS image sensor (CIS) process can be integrated by die stacking [3] at the expense of low data throughput and high

energy/bit of the die-to-die communication. To avoid these

limitations, we propose a UL V CMOS imager design in

nanometer CMOS logic process for SoC integration.

CMOS image sensor design Fig. 1 shows the architecture of the imager, which is

integrated in a 65nm solar-powered video monitoring SoC codenamed SunPixer together with the MCU from [4]. The

imager uses a single external 32-kHz crystal clock and a 0.5-V

supply V ddL generated on-chip from the main I-V SoC supply

VddH. For low power, the architecture is digital with most of the

blocks synthesized from standard cells. Time-based readout (PWM) of the DPS [5] is performed in a rolling-shutter fashion.

Apart from the DPS pixel array, only a few analog peripherals

(clock, ABB and ramp generators) are custom laid out at the transistor level. Some blocks locally use the noisy V ddH supply

to alleviate UL V artefacts, on key noise-tolerant nodes.

The DPS array architecture (Fig. 2) is based on a 4x4-/Jm

pixel where the photosensitive voltage V pix is compared to a linear voltage ramp Vramp using a 2-T in-pixel comparator as the

gain stage to switch the pixel output bitline BL when the PMOS

IV gs l becomes smaller than the comparator threshold set by V pix' Such a comparator features a steeper voltage-transfer curve and

denser layout than its 5-T differential counterpart [5]. However,

it strongly suffers from NMOS/PMOS global mismatch at crossed SF and FS process comers, which complicates its

sizing and may even lead to pixels exhibiting "stuck-at" faults

on their output at UL V. As shown in Fig. 2, the reset/dark level

cannot be properly captured in these conditions, which severely

978-1-4799-3328-0114/$31.00 ©2014 IEEE

limits the DR. We propose an adaptive scheme with an ABB

voltage V ABB applied to the body of the comparator PMOS

through the pixel N-well to compensate such crossed comers.

V ABB is generated from a comparator replica outside the array,

thereby eliminating stuck-at faults (Fig. 2).

In 65nm CMOS, the relatively high gate leakage of the

NMOS comparator dominates the dark current. As the diodes

in logic CMOS process only generate low photocurrent levels,

this gate leakage limits the DR and its pixel-to-pixel mismatch

also introduces fixed-pattern noise (FPN). To limit the gate

impact of gate leakage, the comparator is gated during

exposure by an inverter shared by row. At readout time, the

comparator is enabled with a boosted V ddH input voltage for the

inverter to limit its series resistance and thus to keep maximum

V gs on the comparator NMOS. This gating scheme reduces dark

current by 10-15 x (Fig. 2) and saves static power as well.

Finally, to limit the impact of pixel-to-pixel Vt mismatch in

the comparator, a column-based DRS scheme is implemented.

Fig. 3 shows its implementation with clock-gating of the

generator, a UL V clock tree [2], and the readout HW

synthesized from HDL description. The readout features a multi-Vt asynchronous counter with the first stages low-Vt for

timing closure at UL V and the next stages std-Vt for low leakage. It is placed-and-routed automatically in a structured

datapath (SDP) fashion and features the test I1F scan logic.

Measurement results The SunPixer SoC is manufactured in a 65nm LP/GP mix

process [2] and contains a 128x 128-pixel imager prototype that

uses only LP transistors (Fig. 6). Imaging measurements show

in Fig. 4 that the DRS scheme reduces the FPN by 22 dB with a

small temporal noise increase. FPN is minimized at 0.5 V as a

lower V ddL increases the impact of Vt mismatch and a higher

V ddL increases gate leakage. With all analog peripherals

enabled, the FPN in dark conditions is 0.80%, with 40-dB DR

beyond the noisefloor set by FPN and temporal noise, resulting

in excellent image quality despite the 0.5V operation in 65nm.

Fig. 5 shows the power dependency on the frame rate and the

scene illumination, which is directly related to the switching

activity of the digital column readout circuitry. At the 32-fps

maximum frame rate an energy efficiency Epix of 15-20 pJ per

frame.pixel is achieved depending on the light intensity.

Without DRS, Epix drops to 10-15 pJ at the cost of degraded

image quality, offering a power/performance trade-off.

Conclusions We demonstrated the first 65nm CMOS imager operating at

0.5 V. Measurement results of the prototype integrated in a

solar-powered video monitoring SoC shows a competitive trade-off between energy efficiency and image quality while

enabling UL V SoC integration for loT applications.

2014 Symposium on VLSI Circuits Digest of Technical Papers

References [1] D. Bol et ai, "Green SoCs for a sustainable Internet-of-Things", in

Proc. iEEE FTFC, 2013.

[2] D. Bol et aI, ": A 2S-MHz O.4-V Sub-mm2 71l-W/MHz

Microcontroller in 6S-nm LP/GP CMOS for Low-Carbon

Wireless Sensor Nodes", in IEEE JSSC, pp. 20-32, vol. 48, 2013.

[3] Y. Lee et aI, "A modular 1 mm3 die-stacked sensing platform with

low power FC inter-die communication and multi-modal energy

harvesting", in IEEE JSSC, pp. 229-243, vol. 48, 2013.

[4] F. Botman et ai, "Bellevue: a SOMHz variable-width SIMD 32-bit

microcontroller at 0.37V for processing-intensive wireless sensor

nodes", in Proc. IEEE ISCAS, 2014.

[S] S. Hanson and D. Sylvester, "A O. 4S-0. 7V sub-microwatt CMOS image sensor for ultra-low power applications", in Proc. Symp. VLSi Circuits, pp. 176-177,2009.

Energy-harvesting power

management unit (PMU)

--------1:;;------

--------- -���--l:,

32·bit 50-MHz I

microcontroller

(MCU) (4)

32·kHz clock

Off-chip test Dual supply r-, setup (serial link) (Vddl + VddHl U

Fig. 1. Architecture of the O.SV CMOS imager inside the SunPixer SoC

600 SS ---

400 200

a

50 100 150 W/oABB TT SF

Comparator output stuck at 0 in FS corner

40 ,.----:-----,

20

WithABB TT SF

100'-:·'.,.., -'---...L...--........ -.....,., .. --'==-..,.. ..... ."L-�,,;-----' 0.50 a 50 100 150 10· Gate leakage dominates 1 0· Switching threshold

Total dark current on Vp• @reset level [A] on V"mp @reset [mY] Fig. 2. DPS array architecture and simulated impact of gate leakage on dark current and crossed process comers on failing pixels (post-layout

Monte-Carlo SPICE simulations of the 4x41lm pixel in 6Snm LP

CMOS, VddL = O.S V, VddH= 1 V, 2SoC, dark conditions).

(I�t�and freq. division)

Clock generator

tree

Control FSM mux ctrl

32·kHz clock Pixel value UJ Fig. 3. Low-power digital implementation of the column-based DRS

[6] J. Choi et aI, "A 1.361lW adaptive CMOS image sensor with

reconfigurable modes of operation from available

energy/illumination for distributed wireless sensor network", in Proc. iEEE iSSCC, pp. 112-113, 2012.

[7] M.-T. Chung and C.-c. Hsieh, "A O.SV 4.9SIlW 11.8fps PWM

CMOS imager with 82dB dynamic range and O.OSS% fixed-pattern noise", in Proc. iEEE iSSCC, pp. 114-11S, 2012.

0.4 0.5 0.6 10' 10 1 V ddl M Illumination level [a.u.]

Fig. 4. Measured image characteristics and sample pictures acquired

through the test I1F (typical die, VddH= 1 V, 2S°C). The test I1F fails

below O.S V, therefore only the supply voltage of the DPS array and

� 3, Q; � a a.

10

8

6

the analog peripherals is scaled below this point. 80r;::::;======;---,

� x 'n oj E '" � ...., EO

Vddl = 0.5 V Medium scene ,,-=-_-;,::---:::,::W_i t_h �D::,:R::-S...J 0 i I I u m i nation@32fps

1 0 20 30 0.5 0.55 0.6 0.65 Frame rate [Ipsl V ddl M periph.

Fig. S. Power measurement results (typical die, VddH= 1 V, 2SoC,

without regulator inefficiency)

TABLE I. COMPARISON WITH THE STATE OF THE ART

Hanson, S. VLSI, Choi, ISSCC, Chung, ISSCC, This work 2009 [S] 2012 [6] 2012 [7]

Technology O.13�m CMOS 0.18�m CIS 0.18�m CMOS 65nm LP CMOS

0.8V 0.5 V

Supply 0.5 V (monitoring O.S V (internal reg.

voltage mode)

from the 1V I/O supply)

Resolution 128 x 128 336 x 256 64 x40 128 x 128

Pixel pitch 5�m 5.6 �m 10 �m 4 �m

Fill factor 32% 46% 25.4% 57%

FPN (dark) 6.6% 1.35 %

0.055 % 0.80 % with DRS

(conditions NA) 11.8% w/o DRS

Temporal 5.4% NA

0.65 LSB 0.60 % with DRS

noise (dark) (conditions NA) -0.06% 0.42 % w/o DRS

Peak energy 8.5 pJ 15.4 pJ 147 pJ 17 pJ' with DRS efficiency 13 pJ' w/o DRS

IIframe.pixel) @8.5fps @15fps @78fps

@32fps

t From 0.5 V supply (excluding voltage regulator ineffiCiency), at medium scene Illumination.

E ::1. o '" ....

•

readout + test IfF

DPSarray (128xI28)

, 950 �m �

Analog

peripherals (voltage reg., ramp gen.,

ABB gen.,

clock gen.)

Fig. 6. Die microphotograph of the ULV CMOS image sensor

20[4 Symposium on VLS[ Circuits Digest of Technica] Papers