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S e p t e m b e r . 1 5 . 2 0 1 4

Doug Garrity, Ph.D. and Brandt Braswell

High-Performance Analog/Mixed-Signal Characterization Techniques

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

fundamental underlying principles:

first – high-precision/performance analog/mixed-signal IP must be proven/verified in silicon before being used in a product.

second – a high-precision/performance analog/mixed-signal circuit (like a 24-bit AFE) is very difficult to design, characterize and test and requires extreme attention to detail on all fronts.

third – the initial evaluation of high-precision/performance analog/mixed-signal IP must be done by the people that designed it.

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

IEC energy meters are typically quoted as n(m) @ p% • where n is the nominal current • m is the maximum current • p is the percent accuracy for the meter – i.e. 5(500) @ 0.1%

meters are required to meet the specified accuracy (p), from 5% of nominal (n) to maximum current (m)

meter dynamic range is defined as the ratio of the maximum current to the minimum current:

BUT, as stated above, the meter accuracy specification (p) applies over the entire meter dynamic range which leads to the following expression for the dynamic range of the meter’s analog-front-end (AFE):

background energy meter requirements*

!!!000,000,4)arg_(2000,000,2001.0

2000=•=== inmfor

pmic_rangemeter_dynac_rangeAFE_dynami

2000505.0

500050

=•

=•

=n.

mmic_rangemeter_dyna

* “IEC 62053 Standard”, IEC Commission, ©2003.

background energy meter requirements - continued

• so an AFE dynamic range of 4,000,000 or 21.93 bits is required for this example meter…does this mean that we have to have an ADC with 22 to 24-bit resolution and linearity?

• think about it…what are the resolution and linearity requirements for the meter? −0.1% accuracy is state of the art for nearly all conceivable meters (residential and industrial) −but 0.1% is less than 10-bits!!! so, the AFE needs 22 to 24-bit dynamic range at its input, but

the resolution and linearity requirements are much, much less

• so what can be done to meet this requirement?

• there are several (more or less) viable solutions:

1. a stand-alone ADC with 22 to 24-bit resolution

2. a programmable gain amplifier (PGA) with lots of gain followed by a 10 or 11-bit ADC

3. a PGA with moderate gain followed by a 17 to 18-bit ADC provides most efficient solution (see next slide)

AFE block diagram used as demonstration vehicle for High-Performance Analog/Mixed-Signal Characterization Techniques

• continuous-time (non-chopped) PGA for CT mode • chopper-stabilized PGA for shunt resistor mode • programmable gain settings: 1,2,4,8,16, 32, or 64 • fixed gain 32 or 64 for shunt resistor • over range detection for 4X maximum current

2nd Order discrete-time Σ∆ ADC (with correlated-double sampling)

either shunt

resistor or current

transformer (CT)

ADC sample rate > = 6.144MHz

programmable gain amplifier (PGA)

• input bandwidth = 1.5kHz (up to 21 harmonics of 60Hz)

• ADC dynamic range (PGA gain =1, 4x averaging) = 18 bit

• with PGA and averaging, analog front end dynamic range = 24 bits

• output data rate programmable from 3kHz to 24kHz

energy metering AFE – critical specifications to be measured: (temperature range: -40degC to +85degC)

• total AFE input dynamic range with NO averaging > 20 bits (23 bits with 64x averaging)

• PGA gain accuracy (all gain settings) = <0.5dB

• input referred noise floor with PGA gain set to 64 <~1µVrms

• input offset voltage with PGA gain set to 64 = < 50µV

• ADC (stand-alone) input dynamic range (NO averaging) > 17 bits

• ADC (stand-alone) peak SNR > 98dB

• ADC input referred noise floor < 10µVrms

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

IC design – best practices:

• interference from clocks and/or digital I/Os will limit performance − no cmos levels in to or out of test chip* − separate supplies for analog and digital portions of the test chip − separate padring sections (with associated supplies) for analog, digital, and I/O − use isolated wells if available

• noise (from anywhere) will limit performance − use differential signal routing (including parasitics) for analog (extreme attention to detail)* − add shielding all around critical signals (including references) throughout the signal path* − keep analog and digital and clock routing as separate as possible − use isolated wells if available − filter/bypass supplies and voltage references on-chip if there is extra room

• good grounding is critical − use package with exposed ground plane (e.g. QFN) and connect all (analog and digital) test chip grounds

to the package ground plane. − use extra ground pads in the pad ring to improve isolation.

• flexibility is good − provide ready access/adjustability to inputs, supplies, clocks, bias currents, etc.

* see upcoming slides

no CMOS levels in clock buffer to reduce voltage swings:

package Inductance

package and board

chip

ADC clock generator

package inductance

package and board

chip

PGA chopping clock generator

ADC clock in

PGA chopping clock in

no CMOS levels out digital output driver

buffer

data_in

gain control

package pin

board side

integrated circuit

v_driver

r_ext v_driver: adjusted to optimize logic analyzer data integrity r_ext: adjusted to reduce swing (and associated noise) while maintaining logic analyzer data integrity.

parasitics and matching

• parasitic capacitances and resistances due to interconnect also need to match.

A B B A

B A A B

metal crossover

good

A B B A

B A A B

bad

device and signal shielding

• the importance of the reference voltages in an ADC is equal to the importance of the input signal.

• common mistake is to focus only on the signal paths.

• references should be shielded and bypassed.

• fully-differential references must have equal parasitics.

• it is poor practice to route reference signals over active circuits. use area under reference routing for bypass caps.

REFP

REFM SHIELD

SHIELD

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

• KNOW your input!!! • measured results will never be better than the quality of the input signal - so make sure the signal

generator is better than the circuit to be measured over the desired frequency range! • just because the signal generator specifications are good enough doesn’t mean that the specific signal

generator being used is good enough measure it! • just because the output of the signal generator is good enough doesn’t mean that the signal at the input

to the part is good enough measure the input signal at the input pin!

• inductance is bad!!! • external power supplies connected to the part through 10-foot cables will limit performance – all testchip

power supplies should be built on the evaluation board and should be filtered/bypassed extensively* • an ADC will never be better than the reference voltage

• a high-quality internal reference with adequate filtering is best • a high-quality external on-the-board reference with adequate filtering is better • an external power supply used as a reference and connected through a 10-foot cable is worthless

• clock jitter is also bad!!! • a low-quality (jitter) clock will limit performance depending upon the signals being measured make

sure your clock is good enough*

• data has to be captured make sure there is adequate memory somewhere

* see upcoming slides

basic lab set up and equipment – best practices

signal source

logic analyzer

ADC clock

filter ADC interface s-e to diff

test board

voltage references power supplies

analysis software

low-jitter clock signal generator (better than ADC to be tested by 6-12dB)

basic lab set up and equipment – best practices

use a low (as possible) inductance socket

on-board (adjustable) power supply/reference voltage*

*for best results, a high-quality adjustable (i.e. trimmable) voltage reference should be integrated with the ADC

IC DESIGN RESEARCH LAB 18

the effects of clock jitter:

at higher sampling rates sampling jitter limits resolution regardless of signal power. …so how good does the clock need to be?

4

8

12

16

20

24

ENOB

100K

400K

1.6M

25.6

M

6.4M

1.64

G

6.5G

26.2

G

aperture jitter=0.5pS

Sampling Rate

*

14 Bit 2GSPS? Probably not gonna happen.

the effects of clock jitter continued:

clock jitter example (estimated assuming white-noise-based jitter)

so

example: to achieve SNR = 100dB, BW = 5MHz, Fs = 40MHz, OSR = 4 with fin = 2MHz, the allowable tjitter_rms = 1.6psrms or with fin = 25MHz, the allowable tjitter_rms = 127.3fsrms or with fin = 60MHz, the allowable tjitter_rms = 53.1fsrms evaluating a really good ADC requires an incredibly good clock

rmsjitter

jitter tfinOSR

SNR⋅⋅π

=2 where OSR = Fs/(2*BW)

20102snrrmsjitter

fin

OSRt⋅⋅π

=

the effects of clock jitter continued :

blue high phase noise/jitter clock red lower phase noise/jitter clock (measured SNR improved by ~7dB)

conclusion: a poor clock (of any kind) will limit measured ADC performance (even at very low input frequencies) (if you see something like the blue curve coming out of your ADC check the clock first)

what if the clock jitter isn’t just caused by white noise?

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

evaluation board – best practices

• inductance is still bad!!! • use a low-inductance package (with an exposed ground plane) if possible • use a low-inductance socket (or solder the part (or the bare die) down) • no external power supplies connected through long cables for testchip power/references

• grounding is still critical!!! • use one ground plane for the board * • isolators can be used to drive logic analyzer if needed (separate ground plane can be used for the logic

analyzer side in this situation)

• noise (from anywhere) will still limit performance!!! • use differential signal routing for analog signals (extreme attention to detail) • use as many board layers as needed to ensure signal integrity/isolation • arrange components on board to keep analog and digital signals separate from each other make the

board as big as it needs to be. • no CMOS levels on the board! • take measurements in a screen room if necessary (all AFE measurements were performed in a screen

room) • turn off all un-used equipment anywhere close by – turn off all near-by light bulbs as well

• universal evaluation boards are nice and convenient but almost never good enough for high-precision/performance analog mixed-signal characterization!

* see “Noise Reduction Techniques in Electronic Systems,” by Henry W. Ott, ISBN 0-471-85068-3

evaluation board

13 inches X 15 inches

Agenda

• fundamental underlying principles for successful high-precision mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

data analysis – best practices • know (intimately) the FFT routine being used*

− what is the format of the output? − are positive and negative frequencies produced? − are there (upper or lower) limits to the number of samples that can be processed?

• take enough samples − depending upon the frequency resolution needed (sample rate/number of samples), large numbers of

samples may be needed be sure there is sufficient memory − for some AFE measurements, 32 million samples were required

• know (intimately) the SNR/SINAD/THD/INL/DNL routines being used − is a window being used and if so which one? − how many FFT bins are allotted to signal power and harmonic power? does this number change as the

window is changed? − how many harmonics are included in the THD/SINAD calculations?

• use coherent sampling if possible (whole number of signal cycles sampled) − good ATE usually has coherent sampling capability (input signal, clock and data capture all phase locked) − coherent sampling is very difficult to set up in the lab use a good window

• use a good window if coherent sampling isn’t possible − the Blackman-Harris window is suitable for SNR/SINAD measurements of up to 95dB or so (signal

spreads into ~ 12 FFT bins or so) − the Kaiser window is well suited for SNR/SINAD measurements of > 100dB (signal spreads in to

additional FFT bins depending upon the window set up) * see “The FFT – Fundamentals and Concepts”, Robert Ramirez, ISBN #0-13-314386-4

FFT hints using a small number of samples makes it difficult to see what the ADC is really producing:

Where are the spurs located and how big are they?

128 samples

here’s the same ADC with 16384 samples

• note that the noise floor has been lowered by about 10dB and a number of spurs are now clearly visible.

• in practice in the lab, 213 to 216 samples are typically used since more samples better resolution.

• when simulating an entire ADC at transistor level with extracted parasitics, simulating 216 samples would probably take about one year so fewer samples have to be used.

28

another helpful fft hint…

ensure that the signal frequency and the sample rate have a non-integer multiple relationship with each other (especially in simulations)

Fs = 10MHz fin = 1.123542MHz

Note ‘white’ quantization noise

29

(otherwise energy piles up in just a few discrete bins making accurate measurements difficult to achieve):

Fs = 10MHz fin = 1.25MHz

30

this requirement extends to multiples of the sample rate as well:

Fs = 10MHz fin = 0.75MHz 3*Fs/fin = 40

16b ADC SINAD vs. input frequency from standard “canned” analysis routines

(correct) 16b ADC SINAD vs. input frequency from custom-hand-crafted analysis routines

coherent sampling*

• What is coherent sampling? − input signal frequency (fin) = integer*(sample rate(Fs))/(number of samples) which

means that fin is (completely) aligned with a specific FFT bin

• When is it possible to implement coherent sampling? − in simulations certainly − on high-end automated test equipment (ATE) in which the input signal and the ADC

sampling clock can be precisely phase locked − usually NOT in the lab since it is extremely difficult to phase lock the input signal

generator accurately enough with the ADC clock.

• What is to be done if coherent sampling cannot be implemented? − a non-rectangular window is applied to suppress the spectral leakage that results from

non-coherent sampling

*see “enpub.fulton.asu.edu/jalali/.../EEE%20598,%20Week%201,Lecture2.pdf,” B. Jalali, Arizona State University, 2007.

Rectangular window

The act of taking a finite number of samples of signal is in fact equivalent to multiplying the signal with a rectangular (uniform) window.

64-point rectangular window

In frequency domain, spectrum of the signal is convolved with the spectrum of this window. The FFT samples the convolved spectrum at intervals of Fs/N.

If the collected data includes an integer number of cycles of input signal, the FFT sampling of spectrum happens right at the main lobes – but if not…

The FFT does in effect create a sampled version of the continuous spectrum for what ever signal it operates on. The signal is assumed to be periodic by the FFT, so the new signal looks like this one repeated forever in both directions.

When a non-integer cycles of input signal are sampled during the time record, a discontinuity in the time domain is created which causes spectral leakage in the frequency domain (e.g. spectrum of the sin wave won’t look like a single pulse – rather the energy will be spread over a few frequency bins).

here’s what this looks like:

hopefully, if your ADC output looks like this, it’s just a sampling/FFT issue that you can fix with coherent sampling or windowing and not something worse…

General window

instead of a sharp-transition rectangular window, other types of windows with smoother on/off transitions can be used

which window should I use? this is a Hamming windowed FFT of a Σ∆ modulator output is the SNDR really only 47.8dB?

see “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform,” Fredric J. Harris, Proceedings of the IEEE, Vol. 66, No. 1, January 1978

40

which window should I use? this is a Hann windowed FFT of the same Σ∆ modulator output is the SNDR really only 79.1dB?

41

which window should I use? this is a Blackman-Harris windowed FFT of the same Σ∆ modulator output is the SNDR really only 108.2dB?

which window should I use? this is a Kaiser windowed FFT of the same Σ∆ modulator output this is the actual quantization-noise limited response of the modulator SNDR = 144dB

note the increased width of the fundamental signal due to the Kaiser window

here’s a zoom-in on the fundamental signal from a Kaiser windowed fft: note that the signal occupies nearly 30 fft bins (bin 835 +/- 15 bins) this ‘spreading’ must be taken into account in the SNR/SNDR calculations

now, how many samples will I need (worst case) for this metering application?

• target SNR > 100dB use Kaiser window (spreads signal and harmonics and DC into +/-15 FFT bins)

• for metering, the low end of bandwidth of interest is 10Hz and the signal frequency is 50Hz

• so if an interfering signal at 10Hz must be discerned from DC (spread by the window from bin 1 to bin 15) and from the signal of interest at 50Hz, 10Hz must fall into an FFT bin >> bin 15 and be << less than the 50Hz FFT bin

• choose 10Hz = FFT bin 50 to provide sufficient margin

• required FFT bin resolution = 10Hz/(50 bins) = 0.2Hz per bin

• then if the ADC sample rate = 6.144MHz, and the FFT bin resolution is defined as Fs/N where N is the number of samples then N = 6.144MHz/(0.2Hz per bin) = 30.72 million samples = 224.87

• FFT requires a power of 2 number of samples so round up to 225 = 33.554432 million samples!!!!

Agenda • fundamental underlying principles for successful high-precision

mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

energy metering AFE – measured performance at a glance

• total area = 0.23mm2 (PGA = 0.07mm2, ADC = 0.16mm2)

• total current = 4mA (PGA=2.6mA, ADC=1.4mA)

• temperature range = -40degC to 85degC

• total AFE input dynamic range with NO averaging = 20.2 bits (23.3 bits with 64x averaging)

• PGA gain accuracy (all gain settings) = <0.2dB

• input referred noise floor with PGA gain set to 64 ~600nVrms

• input offset voltage with PGA gain set to 64 = <20µV

• ADC (stand-alone) input dynamic range (NO averaging) = 17.1 bits

• ADC (stand-alone) peak SNR = 98dB

• ADC input referred noise floor = 6µVrms

lessons learned:

• sometimes even a high-quality on-the-board voltage reference with lots of filtering isn’t good enough - see blue curve with 1/f noise from reference causing ‘skirts’ around the input signal

• a 0.5Hz filter pole was added

to the voltage reference output - see red curve with 1/f noise ‘skirts’ removed.

• all subsequent measurements

were taken with 0.5Hz voltage reference filter in place

measured results – AFE input dynamic range

external reference filtered with 0.5Hz low-pass filter to remove 1/f noise

8x averaged data measured for 1µVrms – other 8x averaged data and all 64x averaged data is extrapolated

measured results – ADC input dynamic range

external reference filtered with 0.5Hz low-pass filter to remove 1/f noise

AFE measured results conditions: • input signal = 1µVrms sine wave • pga gain = 64 • chopping on • no averaging

Agenda • fundamental underlying principles for successful high-precision

mixed-signal/analog IP development

• 24-bit Analog Front End (AFE) – what is it and what does it do?

• IC design – best practices

• basic lab set up and equipment – best practices

• evaluation board – best practices

• data analysis – best practices

• measured results/lessons learned

• conclusions

conclusions

• high-precision/performance analog/mixed-signal IP must be proven in silicon before it is ever designed into a product.

• successful characterization of high-precision/performance analog/mixed-signal IP is hard and requires extreme attention to detail on all fronts.

• best practices in each of the following areas have been presented:

−test chip design

− lab set up and equipment

−evaluation board design

−data analysis

• measured data from a 24-bit AFE for power metering (using the presented techniques) was presented – measurements indicate >20-bit dynamic range (un-averaged) and > 23 bit dynamic range (with averaging)