Decoupling Control of Input Voltage Balance for Diode-clamped Dual Buck Three-level Inverter

Feng Hong College of Electronic

and Information Engineering

Nanjing University of Aeronautics and

Astronautics Nanjing, China

hongfeng@nuaa.edu.cn

Peipei Yin College of Electronic

and Information Engineering

Nanjing University of Aeronautics and

Astronautics Nanjing, China

ppyin0223@126.com

Baojian Ji College of

Automation and Electrical

Engineering Nanjing University

of Technology Nanjing, China

ji_baojian@126.com

Wei Yang College of Electronic

and Information Engineering

Nanjing University of Aeronautics and

Astronautics Nanjing, China

yangwei_nuaa@163.com

Chenghua Wang College of Electronic

and Information Engineering

Nanjing University of Aeronautics and

Astronautics Nanjing, China

chwang@nuaa.edu.cn

Abstract—In multilevel inverter, it is a key problem that how to balance voltages of input capacitors. Because of the coupling of multilevel modulation and input voltage balance, no matter hardware circuit or control method of multilevel inverters are always complex, and speed of voltage balance is low. Dual Buck circuit which composed by two Buck DC/DC converter bridges, works in current half-period mode. A novel diode-clamped multilevel dual Buck inverter is presented, which inherits those features. At any moment, one Buck bridge works for inverter, another works as a reverse Boost circuit and charges up input capacitors. So inverter and voltage balance control are completely decoupled. If multilevel number is not small, this method is conducive to reduce the number of devices and the system complexity, and improve reliability of the system. Simulation and experiment of a diode-clamped three-level inverter verifies these analyses.

I. INTRODUCTION Multilevel inverter[1] has obtained more and more

attention in high pressure and high-power converting fields since it is proposed by Nabae in the 1980s. One of the typical topologies is diode-clamped multilevel inverter. The key problem(voltage balancing problem[2]-[9]) is how to balance dc voltages of input capacitors dynamically with the multilevel modulation and inverter output, unless it will lead to the damage by overvoltage of some power components in series bridge.

There are two basic ways[2] to solve the voltage balancing problem: adjust control algorithm[3]-[6] and increase hardware circuit[7]-[9]. By studying the current control algorithm, circuit state can be divided into several sectors according to the output level. Every sector includes two modulating states and a variety of switching mode combinations. It means there are some redundant

switching states which have same contributions to output level but different influences to voltages of input capacitors. Even though the measures of control algorithm to balance voltage are different, the core is how to configurate the redundant switching states reasonably. But there are some difficulties in adjusting the control algorithm: 1) control complexity. Because of the coupling of multilevel modulation and voltage balance, output characteristics and performance of voltage balance cannot be optimized together. The control algorithm is complex[3]-[5]. 2) hardware complexity. Because of the complex structure of multilevel inverter, especially the diode-clamped inverter, it is necessary to take account of voltage balance with the simplification of circuit structure. But the control algorithm for voltage balance is based on the redundant switch states supported by the redundancy of the circuit. All of the above factors make the simplification more difficult[6]. 3) speed of voltage balance. The input circuit consists of many input capacitors. Although every sector includes many switching states available, every capacitors charge/discharge balance cannot be guaranteed in one sector. There are parts of the capacitors with their voltage decreasing or increasing in one sector, and the only way to solve this problem is to adjust in another sector. It is obviously that the speed of voltage balance is corresponding to power frequency period in magnitude, so input capacitances should be increased to reduce the voltage fluctuation.

In [7]-[9], an external balancing circuit is added to solve voltage balancing problem in diode-clamped multilevel inverter. Because the voltage balancing circuit is separated from original multilevel bridge, control algorithms are decoupled mutually which is helpful for reducing control complexity and optimizing individual performances. Meanwhile, as the voltage balancing circuit works in high frequency pulse width modulation(PWM), the speed of regulation is in the same order of switching frequency with no limit of sector mode. But the main problem is the further increase of hardware cost and complexity. In diode-clamped multilevel inverter, the quantity of clamping diode is linear to the square of output level. Meanwhile,

This work was supported by National Natural Science Foundation of

China (50907033), Specialized Research Fund for the Doctoral Program of Higher Education of China (20093218120023), Specialized Research Fund for NUAA (NS2010093), and Priority Academic Program Development of Jiangsu Higher Education Institutions.

978-1-4673-4355-8/13/$31.00 ©2013 IEEE 482

the number of active and passive components in the voltage balancing circuit increases with the output level at the same time.

According to the above problems, this paper proposes a new thought to realize the decoupling of input voltage balance and power conversion by the power bridge with the circuit structure of novel dual Buck multilevel inverter and its half-period working strategies. In the multilevel case, the control and hardware complexity have both been reduced, and the speed of voltage balance can be improved.

II. DERIVATION AND ANALYSIS OF DECOUPLING CONTROL OF INPUT VOLTAGE BALANCE FOR DUAL BUCK

INVERTER Traditional multilevel inverter is extended from

bridge circuit. Dual Buck inverter[10] exploited in the recent years is a new topology different from full-bridge or half-bridge. The multilevel inverter topologies derived from dual Buck inverter such as diode-clamped, flying- capacitor and cascade, have no shoot-through problem and can work in current half-period mode. The topology of diode-clamped three level dual Buck inverter(DCTLDBI) is shown in Fig.1. Decoupling method of DCTLDBI is proposed first, and then analysis of extended multilevel inverter is proposed.

DCTLDBI shown in Fig.1(a) is a parallel structure of Buck I and Buck II in output side. Buck I consists of S1, S3, D1, D3, L1, Cf, and Buck II consists of S2, S4, D2, D4, L2, Cf. Current passing through the inductance, which is iL1 in positive half period and iL2 in negative half period,

(a) Topology of DCTLDBI

tω

tω

tω

tω

tω0

0

0

0

0

(b) Working principle Fig.1 Diode-clamped three level dual Buck

inverter

is denoted by iL= iL1+ iL2. Neglecting the current passing through filter capacitor, load current is io= iL for a resistance load. It is assumed that the input voltage Ud is distributed on average by input capacitors C1, C2. Working area of DCTLDBI shown in Fig.1(b) is divided into four quadrants based on the polarity of inductor current iL and output voltage uo. The angle difference between iL and uo is called θ. DCTLDBI works in two half-period working mode without circular current. In the positive half-period, Buck I works and Buck II is suspended. During this period, the inductor current is iL= iL1>0, and the output of Buck I in bridge A is a three-level modulating waveform. In the negative half-period, Buck II works and Buck I is suspended. The inductor current is iL= iL2<0, and the output of Buck II in bridge B is a three-level modulating waveform. This topology has special characteristics of no shoot-through problem and no reverse-recovery of the body diode of the power switches and realizes high efficiency and high reliability[10]-[14].

To solve high voltage stress of some components and ensure normal output of the inverter, it is necessary to control the voltage balance of input capacitors. In the half-period working mode, there is one Buck suspended. Taking the first quadrant as an example, the inductor current is iL= iL1>0, the output voltage is uo>0, and the voltage of bridge A (uA) is 0 or + Ud/2. S3 works in PWM mode, and S1 is ON. The capacitor voltage uC1 declines linearly. Buck II works as a reverse Boost circuit. The side of Cf is input port. L2 is the inductance in Boost. S2 and S4 are the power switches, and D4 is the diode in Boost circuit. C1 is the output capacitor. When S2 and S4 work in PWM mode, the circuit charges up C1 and it is controlled independently. Meanwhile, Buck I works for multilevel modulation and inverter, Buck II for voltage balance. However, because the input of the reverse Boost circuit is the output of the inverter, which will influence the inverter output, this method cannot decouple inverter and voltage balance completely.

Based on DCTLDBI, a new topology shown in Fig.2 is presented, with S5, L5, D5andS6, L6, D6 attached to the circuit. When Buck I works, S2 in Buck II is turned OFF, and L2, D4, D2 do not work. So S6, S4, L6 and D6 can be considered as a reverse Boost circuit, which is named Boost II. Boost II independents from the output side of inverter completely. So Buck I and Boost II can works in parallel. In other words, the multilevel modulation and voltage balancing control are decoupled. Similarly, in the negative half-period, Buck II and Boost I (S3, S5, L5 and D5) are also mutually independent.

Fig.2 DCTLDBI with decoupling control

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There are many components in DCTLDBI with decoupling control. But the point needs to be emphasized is that the extended multilevel inverter has some advantage in the number of the components.

III. DECOUPLING OF INVERTER AND VOLTAGE BALANCE OF DCTLDBI

Working area of DCTLDBI with decoupling control shown in Fig.2 can be divided into four quadrants based on the polarity of inductor current iL and output voltage uo.

1) Quadrant I(iL=iL1>0,uo>0;+Ud/2,0 modulation): Buck I works in PWM mode. Circuit works in one of two

following modes: Inverter mode I: Shown in Fig.3 (a). S1 and S3 are ON.

The voltage of bridge A is +Ud/2. When capacitor C1 discharges, uC1 declines and uC2 rises. The relation between them is given as follows: uC2=Ud-uC1。

Inverter mode II: Shown in Fig.3 (b). S3 is turned OFF. S1 remains ON. The voltage of bridge A is 0. iL1 reflows from D1, S1. uC1 and uC2 do not change.

In this period, Boost II is composed of S6、S4、D6 and L6.

Voltage balancing mode I: Shown in Fig.3 (d). S4 and S6 are ON. The voltage on L6 is uL6=0-uC2=Ud/2. iL6 rises linearly, and the inductor stores energy.

Voltage balancing mode II: Shown in Fig.3 (e). S6 is turned OFF. iL6 reflows from D6.When capacitor C1 charges, uC1 rises and uC2 declines.

When the circuit works as inverter, Ud is the input, and the output is uo. But in voltage balancing mode, uC2 is the input, and the output is uC1. So inverter and voltage balancing control are completely decoupled, and the charge/discharge for C1 and C2 is opposite. Inverter Mode I,II and Voltage balancing Mode I,II can work at the same moment. Boost II works in high-frequency modulation separately, adding the energy for C1、C2 quickly.

2) Quadrant II(iL=iL1>0,uo<0;±Ud/2 modulation): Buck I works in PWM mode. Circuit works in one of

following modes: Inverter mode I: Shown in Fig.3 (a) (see above). Inverter mode III: Shown in Fig.3 (c). S1 is turned OFF.

iL1 reflows from D3. The voltage of bridge A is -Ud/2. uC1 declines and uC2 rises.

In this period, Boost II works in one of the Voltage balancing Mode I and II. Inverter and voltage balance control are completely decoupled, Inverter Mode I,III and Voltage balancing Mode I,II can work at the same moment. The charge/discharge for C1 and C2 is opposite.

In the negative half-period (quadrant III and IV), the working process is duality results to the above, with Buck II as inverter and Boost I for voltage balance. The two modes are also completely decoupled, and can work at the same moment. The charge/discharge for C1 and C2 is opposite. So it is unnecessary to give more details.

3) Quadrant Ш(iL=iL2<0,uo<0;-Ud/2,0 modulation): Inverter mode IV,V: Shown in Fig.3 (f),(g). Voltage balancing mode III,IV: Shown in Fig.3 (i),(j). 4) Quadrant IV(iL=iL2<0,uo>0;±Ud/2 modulation): Inverter mode IV,VI: Shown in Fig.3 (f),(h).

Voltage balancing mode III,IV: Shown in Fig.3 (i),(j). The block diagram of control strategy shown in Fig.4 can

divided into four parts, which consists of inverter control, voltage balancing control, interval judgment and logic circuit. Both the voltage outer-loop and current inner-loop are adopted in the inverter control. The modulation signal mI for sine pulse-width modulation(SPWM) is product by the comparison result between the triangular wave and the output of PI controller in inverter control. In voltage balancing control, the modulation signal mB for Boost circuit is created with the detected voltage error signal of capacitor ∆uC which is taken as the input signal of the PI controller. In the interval judgment, the reference voltage ur and the reference current ir are compared respectively with zero to produce the signal uP

and iP which can represent the polarity of output voltage uo and the inductor current iL. And the current working quadrant can be recognized from uP and iP. Six driven signals v1-v6 are acquired from analyzing mI, mB, uP, iP in the logic circuit. Obviously, the control method is easy to realize, and the inverter and voltage balance are worked in parallel.

IV. DECOUPLING CONTROL OF INPUT VOLTAGE BALANCE FOR DIODE-CLAMPED DUAL BUCK MULTILEVEL INVERTE The analysis above in three-level inverter can also be

extended to a multilevel inverter. The general topology of diode-clamped dual buck multilevel inverter with decoupling control is shown in Fig.5. C1~C2N are input capacitors which balance the input voltage Ui1、Ui2. The minimum level unit is Ui/N. Buck I consists of S0A~S2N-1A, D0A~D2NA, LA and Cf. In the positive half-period, S1A, S3A……S2N-1A are the switch bridge with D1A, D3A……D2N-1A as the clamp diodes. D2A, D4A……D2NA are the diode bridge with S2A, S4A……S2N-2A as the clamp switches. If S1A, S3A……S2i-1A(i=1,2……N) are all ON, the voltage of bridge A is +i state level. If S2iA(i=0、1、2……N)are ON only, the voltage of bridge A is -i state level. Buck II consists of S0B~S2N-1B, D0B~D2NB, LB and Cf. The working process in the negative half-period is similar to that of Buck I.

To achieve the decoupling control of input voltage balance, ScA, LcA, DcA and ScB, LcB, DcB are attached to the inverter topology. When Buck I works, S2B and S0B remain

OFF, and LfB, D0B, D1B do not work. Meanwhile, ScB, LcB, DcB and the rest components in Buck II compose Boost II. So, Boost II is separated from the output side of the inverter. And when S2i-1B are ON, Boost II can charge up C1~C2i-1by the D1B~D2i-1B,S2i-1B branch. Buck I and Boost II are mutually independent. The multilevel modulation and voltage balance can also work in parallel. Similarly, in the negative half-period, Buck II and Boost I are also mutually independent. The control strategy is similar to Fig.4. But the difference is that more working intervals should be divided(according to the voltage reference).

Obviously, the components used for voltage balance are always ScA, LcA, DcA and ScB, LcB, DcB, regardless of the number of the level. When the number of the level is increased, it is unnecessary to add any more clamped circuit. Then inverter and voltage balance decoupled completely by the original power bridge can work separately and in parallel. If the number of the level is M, the circuit shown in Fig.5 needs M-1 capacitors for voltage balance, 2M switches, 2M diodes

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(a) Inverter mode I (f) Inverter mode IV

(b) Inverter mode II (g) Inverter mode V

(c) Inverter mode III (h) Inverter mode VI

(d) Voltage balancing mode I (i) Voltage balancing mode III

(e) Voltage balancing mode II (j) Voltage balancing mode IV

Fig.3 Working modes

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Fig.4 Block diagram of control strategy

Fig.5 Diode-clamped dual buck multilevel inverter with decoupling control

and 4 inductances. Compared with the diode-clamped dual buck M-level inverter with decoupling control, the traditional diode-clamped M-level inverter which needs M-1 capacitors for voltage balance and 2M-2 switches, the number of clamped diode linearly increases with M2[15]. There are some methods to reduce the clamped diode number, such as complex clamped method by adding many active components[15]. And the traditional clamped circuit is coupled with the inverter. Besides, the control strategy should include both inverter output and voltage balance. All of these make the control complex. However, the diode-clamped dual buck multilevel inverter with decoupling control does not have those problems.

V. SIMULATIONS AND EXPERIMENTS The simulation of three-level close-loop system was

designed to verify the performance, whose parameters were: output capacitor, Cf ＝ 4.7µF; inductors, L1=L2 =L3=L4 =400µH; input voltage balancing capacitor, C1=C2=200µF; output voltage, uo=110VAC/400HZ; input voltage, Ud=400VDC. In steady state, when the switching frequency is 25kHz, uC1=uC2=200VDC.

The simulation is shown in Fig.6 where v1~v6 are the driven signals for switch S1~S6, uA and uB are the voltage for bridge A and B, uC1 and uC2 are the input voltage for C1、C2,

Fig.6 Simulation of three-level close-loop system

iL(=iL1+iL2) is inductor current, uo is the output voltage. Corresponding to the above, working quadrant can divide into I~IV. In the positive half-period(quadrant IV and I), Buck I works for the inverter, and uA is three-level modulation wave. With the modulation of S6 and S4, Boost II works for voltage balance, and the input balancing voltage is about 200VDC. S2 is OFF, and Buck II is separated from the output side of the inverter. iL2=0, uB=uo. In the negative half-period(quadrant II and III), Buck II works for the inverter, and uB is three-level modulation wave. With the modulation of S3 and S5, Boost I works for voltage balance, and the input balancing voltage is about 200VDC. S1 is OFF, and Buck I is separated from the output part of inverter. iL1=0, uA=uo. The inverter and voltage balancing control are decoupled in the close-loop system.

Based on the simulation, an experimental prototype was built in the laboratory to verify the actual performance further, whose parameters were similar to the parameters in the simulation. Power MOSFETs(IRFP460) were used as the controllable switches(S1~S6). DSEI60-06A power diodes were used for D1~ D6. Control algorithm is completed by DSP chip(TMS320F2812).

Experimental waveforms are shown in Fig.7. Waveforms in Fig.7(a) where uA is the output of bridge A, uB is the output of bridge B, uo is the output voltage and iL is the inductor current, represent that the multilevel modulation and the output of the inverter are decoupled in the diode-clamped

486

(a)

(b)

(c) Fig.7 Experiment waveforms

dual buck three-level inverter. The waveforms and phase relation of them agree well with the theoretical analysis. uA and uB realize the three-level modulation(±Ud/2,0). In Fig.7(b), the working quadrant can be judged from the waveform of uA: the modulation state(+Ud/2,0) corresponds to quadrant I, S1 is ON (v1), S3 is in PWM mode with the driven waveform corresponding to uA(v3 、 uA); the modulation state(±Ud/2) corresponds to quadrant IV, S1 and S3 are in PWM mode(v1、v3) ; In quadrant II and III, Buck I does not work, S1 is OFF (v1), iL1=0，uA approximates uo, S3 is in high frequency modulating mode(v3) corresponding to the voltage balancing process of Boost I. The waveform analyses are in a good accordance with the theory and simulation. In Fig.7(c), ch4 and ch2 are the waveforms for uC1 and uC2 respectively, which proves that the input balancing voltage is stable, and the effect is good.

VI. CONCLUSION The novel diode-clamped dual buck inverter proposed in

the paper provides an effective way to decouple the multilevel inverter and voltage balancing control. It is very important to reduce the system complexity and improve reliability. This inverter has the following features.

1) The circuit consists of two duality parts: Buck I and II working in two half-period according to the inductance

current polarity. When Buck I(II) works, Buck II(I) is controlled to work as a reverse Boost circuit, which realizes the voltage balancing control. So the Boost circuit is separated from the output of the inverter. The inverter and voltage balance are completely decoupled. It is helpful for reducing the system complexity.

2) The inverter has no shoot-through problem inherited from the dual Buck structure.

3) Because the inverter and voltage balance are independent, Boost circuit works in high frequency modulation with Buck as inverter in parallel. It contributes to increasing the speed of voltage balance and decreasing the input capacitance.

4) Except for LcA, LcB, ScA, ScB, DcA and DcB, voltage balance can be completed by the original power bridge without adding the clamping components. The circuit structure and the method for decoupling control can be extended to M-level. When the number of the level is increased to M, it is unnecessary to add any more clamped circuit with the power bridge instead. If the number of the level is M, the number of power components is 2M rather than M2 in traditional diode-clamped M-level inverter. So this method is useful to reduce the system complexity.

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