Nonlinear Analysis and Design of Frequency Selective Limiters Based on Parametric Circuits

F. Ramírez1, R. Melville2, A. Suárez1, and J. Stevenson Kenney3 1 DICOM, ETSIIT, University of Cantabria, 39005, Santander, Spain

2New Jersey Institute of Technology, Newark, NJ, USA 07102 3School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA 30332-0250

Abstract — A parametric circuit based on varactor-diodes is

presented for its application as a frequency-selective limiter. A simplified analytical model is initially derived for a general understanding of the circuit performance. The power limitation is due to the frequency division of above threshold signals, leading to a reduction of the output power. Next harmonic-balance simulation is applied to analyze the limiter behavior in the presence of a strong and a weak signal. A matching technique is derived to increase the input-power range with high limitation level. Cascaded detuned stages are used to limit multiple above threshold signals. An in-depth analysis of the behavior under two interferers is also presented, showing that each stage enables the frequency division of a different interferer. The techniques have been successfully applied to a frequency selective limiter in the 850 MHz band.

Index Terms — Frequency selective limiters, parametric circuits, harmonic balance.

I. INTRODUCTION

Frequency selective limiters (FSL) allow limiting or suppressing input signals above a given power threshold without affecting the output power of adjacent signals [1]-[3]. The frequency response of these circuits can be considered as a bandpass filter for every signal below the power threshold. When the power of any signal in the reception band becomes larger than the threshold, the frequency response of the circuit changes and a notch appears about the frequency of the above-threshold signal. Any signal within the notch is suppressed or limited, whereas the output power of any signal at different frequencies remains unaltered. The large-power signal will be considered here to be an interferer signal. FSL circuits can be obtained using the nonlinear properties of ferrite resonators, usually containing YIG spheres [1]-[2]. However, this technology is not suitable for integration. Alternatively, FSL based on varactor diodes have been reported [1],[3]. In both cases, the operation principle is based on the frequency division by 2 of signals above the power threshold. Provided a careful design is carried out, the generation of the subharmonic fin/2 gives rise to a significant reduction of the power at fin, which is due to the variation of the circuit input impedance at this frequency. In previous works, the design of these circuits was based on simplified analytical approaches. Here, an in-depth bifurcation analysis is presented. The conditions for optimum power limitation are investigated together with the limitation mechanism in the presence of

several above-threshold signals. An FSL operating at a central frequency of 850 MHz has been built for validation purposes, obtaining very good agreement with the simulation results.

II. FREQUENCY SELECTIVE LIMITER DESIGN

The considered reflection mode FSL is shown in Fig. 1a. Two identical parametric circuits [3]-[4] are connected to the outputs of a 90º-hybrid and the input source and load are connected at the IN and ISO ports, respectively. The circuit exhibits a flip bifurcation at the input power Pino, leading to the generation of the subharmonic component at in / 2ω . As long as the input power level is below Pino, the impedance seen by the input source is ideally reactive and thus all the power is reflected to the load. This is because the circuit does not contains any resistive elements, apart the series diode resistance Rd=0.15 Ω. Once the sub-harmonic component is triggered, part of the input power is absorbed, due to the real part of the voltage-to-current ratio between the diode terminals. The resonant circuit at the subharmonic component is constituted by the diode in series with an inductance, implemented on transmission line. The subharmonic voltage has 180º phase shift at the common node due to the balanced structure. Therefore, the middle node is a virtual ground at

in / 2ω . In turn, the two branches constituted by the series connection of the diode and the transmission line (LD branches, Fig. 1b) are in phase at the input frequency fin. Taking this into account and considering the input and subharmonic frequencies only, the circuit equations can be written in a simplified manner as:

d1/ 2 1/ 2

g d

*d1/2 o 1/ 2 1 1/ 2

2gT o 1 1/ 2

R jL 0V I0 2R R jL2V I

0R jL 0V jc V j2c VV 0E0 Z (2 )V 0 j2c V jc V

+ ω + = + + ω + ω ω + ω = + = ω ω + ω

(1)

where an ideal inductor L has been assumed and 1/ 2V ,V and

1/ 2I , I indicate the harmonic components of the diode voltage

and current at in / 2ω = ω and 2ω . For illustration, the case of

a linear capacitance o 1c(v) c c v= + has been considered. Note that the above system refers to any of the two hybrid ports (0º or 90º). The input signal from the hybrid connection port is represented as an equivalent generator Eg(t) in series with

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Rg=50 Ω. Equation (1) can be re-written in the following more explicit manner:

1/ 2

2g 1 T 1/ 2

o T

j( 2 )o 1

d

E jc Z (2 )VV (a)

1 j2c Z (2 )1 jc j2c V e 0 (b)

R jLφ− φ

− ω ω=

+ ω ω

+ ω + ω =+ ω

(2)

The notch about ω is due to the resonance at the subharmonic component, indicated by (2b). In practice, the resonance will have a certain quality factor, giving rise to a notch-filter behavior about the interferer. Although (2) is a nonlinear system of two complex equations, we can get some insight into the circuit behavior from the inspection of (2). Prior to the subharmonic generation (case 1/ 2V 0= , in (2a)), the voltage-current ratio exhibited by the LD branches will be mostly reactive. The Eg value for the flip bifurcation (Egb) is obtained combining system (2) with the condition 1/ 2V 0= . From the

flip bifurcation, the magnitude |V| takes a near constant value, in this simplified model, whereas the magnitude |V1/2| grows initially with high slope versus Eg, in order to fulfill the subharmonic-oscillation condition (2b). From equation (2a), this involves a significant variation of the two phase values φ and φ1/2, which gives rise to the real part in the voltage-current ratio observed from the input port. After this fast-growth stage, the sensitivity to Eg of the two phases decreases considerably. The magnitude |V1/2|

2 tends to evolve proportionally to Eg.

Fig. 1. Reflection-mode FSL. a) Block diagram. b) Schematic of the parametric subcircuit.

A. Harmonic balance analysis The circuit of Fig. 1 has been simulated with Agilent ADS

harmonic balance (HB), using an auxiliary generator (AG) both for analysis and design [5]. The circuit has been analyzed in the presence of two signals, at different frequencies f1 and f2. The interferer signal at f1 is above threshold whereas the desired signal at f2 is below threshold. The simulation has been carried out with two-tone harmonic balance, at f1/2 and f2, using an AG to obtain the subharmonic solution in the presence of the small signal at f2. The circuit has been analyzed versus increasing power of the interferer at f1. The

output-power variation at f1, f2 and the image frequency 2f1-f2 are shown in Fig. 3a. In agreement with the analytical model, there is an initial small input-power interval in which the circuit behaves in very nonlinear manner. This is due to quick growth of the subharmonic power versus Pin. In this interval there is high phase sensitivity to Pin. The nonlinear behavior gives rise to a fast power increase at the image frequency 2f1-f2. This behavior is inherent to FSL circuits and is equally obtained in YIG based FSL [6]. However, due the usually high quality factor of the subharmonic resonance, the image power will only get significant values at small frequency offset from the interferer, since the nearby frequencies will see reactive impedances from the hybrid ports. If Pin continues to be increased, the phase sensitivity decreases and so does the image power. Finally, for very high Pin, the power-transfer curve at the interferer tends to unit slope. Fig. 3b shows the measured variation of the image power for different values of the frequency spacing between the small signal at f2 and the interferer at f1.

b)

Out

put p

ower

0 2 4 6 8 10 12 14Input power (dBm)

-60

-55

-50-45

-40-35

-30-25

f=1MHzf=6MHzf=11MHzf=16MHzf=21MHzf=26MHz

Signal at f2

Signal at 2f1-f2

-5 0 5 10 15 20

-70-60-50-40-30-20-10

01020

Input power @ f1 (dBm)

Inpu

t pow

er @

f1 (d

Bm

)Output power @ f2 Pin2=-30 dBm

Output power @ 2f1-f2

SimulationsMeasurements

a)

Fig. 3 Variation of output power of the interferer and desired signals versus increasing power of the interferer signal. (a) Measurements and simulations. (b) Detailed experimental characterization versus the frequency spacing ∆f between f1 and f2, for Pin2= -30dBm.

B. Increase of the attenuation level Two main design objectives will be reduction of the input

power threshold for power limitation and the increase of the limitation level. The threshold can be easily reduced through flip bifurcation control. This is done by setting Pin to the desired value and optimizing the elements of ZT, so as to fulfill YAG=0 [5]. There is an obvious limit to this reduction, imposed by the device technology, since this device must be in nonlinear regime for the division to take place. To increase the limitation level, one of the sub-networks connected at the 0º/90º hybrid ports is going to be separately considered. The

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hybrid output is represented with an equivalent generator Eg in series with a 50Ω resistance. The capability to limit or suppress the interferer is directly related to the input matching at the interferer f1, once the division has taken place. In order to increase the attenuation level the objective will be to obtain a constant voltage/current ratio (V/I) at the input of the parametric circuit (Node 1 in Fig. 1b) when Pin increases. If this is achieved, it will be possible to obtain good matching at all the Pin values with a same linear network, connected between the hybrid output and the subcircuit composed by the two LD branches. Note that the ratio V/I naturally varies versus Pin, so, in order to maintain its value a nonlinear resistance Rb is introduced between the two branches (Fig. 1b). In the simplified model (1), the resistance will only be seen by the subharmonic frequency and will change the equation (2b), corresponding to the subharmonic resonance. This equation is coupled to (2a), so the resistance will also influence the conditions at 2ω . This resistance has the characteristic i(v)= a1v+a3v

3. Different discrete values of Pin are considered at each step. To determine the V/I ratio at f1, the circuit is analyzed in divided regime with an AG at the subharmonic frequency f1/2. The coefficients a1 and a3 of the nonlinear resistance are fitted so as to keep the real part of the (V/I)1 ratio at a constant value as Pin increases, here a 12 Ω value has been chosen. The next objective is to obtain a 50 Ω value from the hybrid port for all the power values Pin>Pth. A tapered transmission line is used to match it to the source impedance. The imaginary part of (V/I)H is also compensated with a reactive element at the input network. However, due to the nonlinearity of the circuit, it is not possible to obtain Imag(V/I)H=0 for all the input power values. The evolution of (V/I)H is illustrated in the Smith-chart representation of Fig. 3a. The effect of the resistance on the power-transfer curve at the interferer f1 is shown in Fig. 4b. Comparing the results of Fig. 3b with the one obtained with the original circuit, prior to the introduction of the nonlinear resistance, a power limitation increase of 30dB can be achieved. The nonlinear resistance is implemented using a network containing parallel reversed diodes and resistors. Measurements confirming the increase of the attenuation level are shown in Fig. 4, showing the power transfer curves at different input frequencies.

Fig. 3. Enhancement of the input matching at the interferer frequency with a nonlinear resistance. (a) Smith-chart representation of V/I at f1 in the presence of f1/2, obtained through a power sweep. (b) Power transfer at the interferer, resulting from the circuit modification.

Input power (dBm)0 5 10 15

850 MHz

860 MHz

840 MHz

-25-20-15-10-505

1015

Fig. 4. Measurements corresponding to the power limitation of the interferer for different input frequency values.

II. BEHAVIOR UNDER MULTIPLE INTERFERER SIGNALS

In similar manner to a YIG-based FSL, the dynamic range of the varactor-based FSL can be increased using two cascaded stages. Each stage will only give rise to the frequency division from a certain Pin value. As an example, two stages of the circuit in Fig. 1 have been cascaded and analyzed in the presence of an interferer at the frequency 1f , using, alternatively, one or two AGs at the subharmonic frequency (Fig. 5a). At the power threshold inbP a flip bifurcation occurs in the first stage, leading to the power limitation of the interferer at f1. If the input power is further increased, a second flip bifurcation takes place in the second stage at

inbP ' . Note that this bifurcation takes place in the presence of a subharmonic frequency in the first FSL stage. From the power value inbP ' , the two stages operate at the subharmonic frequency 1f / 2 . Fig. 5b shows the flip bifurcation locus of the two cascaded stages. The power limitation of the first stage gives rise to an increase of the input power required for the flip bifurcation in the second stage. The flip bifurcation locus of this stage is located inside of the one corresponding to the first stage.

By offset-tuning the two FSL stages it is possible to broaden the power limitation bandwidth. As has been verified here, assuming two interferers of different frequency f1, f1’, each stage will give rise to the frequency division by 2 of a different interferer. In case the signal at f1 has undergone the division at the first FSL stage, its power will be below threshold at the input of the second stage. Therefore, only the signal at f1’ is above threshold at the input of the second stage and can undergo the frequency division. As an example, the cascade connection of the two detuned FSL stages has been analyzed in the presence of two interferers at f1, f1’. To analyze the variation of power-limitation threshold versus the input frequency, the Flip bifurcation locus of the first stage is initially traced. This is done by connecting an AG at fin/2 to this circuit, with very small amplitude AAG=ε and imposing the condition: YAG(Pin,ωin,φAG)=0 [5]. This provides the locus indicated with (1) in Fig. 6. Next, the flip-bifurcation locus of the second stage is obtained, connecting the AG to this stage and imposing the same condition YAG(Pin,ωin,φAG)=0. The

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obtained locus is shown in Fig. 6. The result is qualitative, as in the presence of the two interferers the circuit will initially

operate in a quasi-periodic regime at '1 1f , f when any of the

two frequency divisions takes place. It is not possible to take this into account when tracing the flip locus because a different locus would be obtained for each power and frequency of the non-divided interferer. However, the curve in Fig. 6 clearly shows that the bandwidth broadens as two valleys are formed in the global flip-bifurcation locus, given by the envelope of the two loci. Although based on a different principle the broadening of the bandwidth of YIG based FSL is also carried out through the introduction of additional stages and the power-threshold characteristic also has a multi-valley shape.

b)

a)

0 2 4 6 8 10 12 14 16 18-2 20Input power (dBm)

-5

0

5

10

15

-10

20

Pinb Pinb´

835 840 845 850 855 860 865830 870Input frequency (MHz)

3

6

9

12

15

0

18

First-stageFlip locus

Second-stageFlip locus

SimulationMeasurements

Fig. 5 Extension of the dynamic range of the FSL through the cascade connection of two stages. (a) Power transfer curve. (b) Power threshold variation versus the input frequency.

Fig. 6 Bandwidth increase through the cascade connection of two offset-tuned FSL stages.

The behavior of the power limiter in the presence of two

interferers has been analyzed with envelope transient, using an AG at each of the stages to initialize the subharmonic oscillation. The power limitation threshold is 3 dBm. In the case of Fig. 7a, both signals are below threshold with

Pin1=Pin2=0 dBm. None is limited. In Fig. 7b, the signal power is Pin1=10 dBm, Pin2=0 dBm. Only the first signal is limited. In Fig. 7c, the input-power values are Pin1=0 dBm Pin2=10 dBm. Only the second signal is limited. Finally, in Fig. 7d, the input power is Pin1=Pin2=10 dBm. Both signals are limited. The unlimited signal, which still has relatively high power after the first stage, gets divided by the second stage.

Fig. 7 Envelope transient simulation of two cascaded FSL stages, in the presence of two interferers with different power values.

III. CONCLUSIONS

A parametric circuit for operation as a frequency selective limiter has been presented. An initial analytical study allows the understanding on the circuit behavior based on the frequency division by two of above-threshold signals. Next, a nonlinear design technique to increase the input power range with high limitation level. The operation of a two stage FSL in the presence of multiple interferers has been analyzed, obtaining that each stage gives rise to the frequency division of a different interferer.

REFERENCES

[1] A. Giarola, “ A review of theory, characteristics, and operation of frequency selective limiters,’ Proc. IEEE, vol. 67, no. 10, pp. 1380-1396, Oct. 1979.

[2] J.D. Adams, S.N. Stitzer, “Frequency selective limiters for high dynamic range microwave applications,” IEEE Trans. Theory and Techn., vol. 41, no. 12, pp. 2227-2231, Dec., 1993.

[3] D. Sychaleun, E.B. Felstead, G.A. Morin, “Progress on the frequency independent strong signal suppressor (FISSS),” MILCOM 97 Proc., vol. 1, pp. 69-73, Monterrey, CA.

[4] E. Goto, “The Parametron, a digital computing element which utilizes parametric oscillation,” Proc. of IRE, vol. 47, no. 8, pp. 1304-1316, Aug., 1959.

[5] A. Suárez, R, Melville, “Simulation-assisted design and analysis of varactor-based frequency multipliers and dividers,” IEEE Trans. Theory and Techn., vol. 54, no. 3, Mar. 2006.

[6] A.L. Berman, “Multiple-carrier behavior of a frequency-selective ferrite limiter,” IEEE Trans. Commun., vol. 12, no. 2, Jun., 1964.

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