A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs

Shaohua Wang, *Jinguo Quan, Rong Luo, **Hao Cheng, Huazhong Yang Dept. of Electronic Engineering, Tsinghua University, Beijing, 100084, China

wangsh02@mails.tsinghua.edu.cn; yanghz@tsinghua.edu.cn *Graduate School at Shenzhen, Shenzhen, 518055, China, quanjg@sz.tsinghua.edu.cn

**RF Integrated Corp., Beijing, China, hao.chen@rfintc.com Abstract—This paper presents a noise reduced Digitally Controlled Oscillator (DCO) using complementary varactor pairs for PHS transceivers. Due to some modifications on the varactors, reduced phase noise and increased frequency resolution are obtained for our DCO. The DCO is designed in a 0.18µm CMOS process with a central running frequency of 3.8GHz and over 1GHz tuning range. Simulation results show that the phase noise at 1.2MHz offset frequency is below -123dBc/Hz while drawing only 2.8mA of current from a 1.8V supply. It demonstrates that our DCO achieves improved phase noise and power consumption while its performance has no dependence on the feature size of the given process.

I. INTRODUCTION The explosive growth in the global cellular telephone market has

increased the need for communication systems to reduce their cost and power consumption. Personal Handy-Phone System (PHS), which can be used as a home cordless phone or a mobile phone, is developing quickly in China and other Asian countries. Current generation PHS transceivers are usually low-level integrated and relatively high cost. The demand for low cost and low power favors the implementation of high-level integrated and digitally intensive PHS transceivers [1].

Digitally Controlled Oscillator (DCO), which is proposed for wireless applications recently [2]~[4], generates a signal whose frequency can be directly controlled by its digital tuning words. It is regarded as one of the most critical blocks in All-Digital Phase-Locked Loops (ADPLL) [5]. Compared with traditional VCO (Voltage Controlled Oscillator), DCOs are much less sensitive to voltage headroom reduction as well as substrate noise coupling. Therefore it is considered to be a more appropriate selection for integrated RF transceivers than traditional LC VCOs and ring-oscillator-based DCOs.

The performance of DCOs in terms of frequency resolution and phase noise strongly depends on the minimum switched varactor capacitance, which is determined by the feature size of the given process. Specifically, the smaller the feature size, the better the performance. Therefore, in order to meet the stringent specifications of modern RF transceivers, DCOs have to be implemented in most advanced CMOS process, which is quite expensive. For example, the DCO in [3] is designed in a 90nm process and the DCO in [4] is 65nm. This becomes an effective deterrent against DCOs for current commercial low-cost RF transceivers. To solve this problem, some techniques such as inversion-mode MOS varactors and complementary varactor pairs are proposed and applied in this paper. Note that here the DCO is designed for PHS transceivers in a 0.18µm CMOS technology. Simulation results demonstrate that a very low phase noise is achieved with low power consumption over a large

frequency tuning range. This is superior to those DCOs proposed in [2]~[4], which can obtain comparable performance only when being implemented in more expensive CMOS processes.

II. OVERVIEW OF THE DCO The simplified schematic of our DCO is shown in Fig. 1. It is

similar to that in [6], except that it uses a digitally controlled varactor array rather than the single differential varactor pair. In order to avoid frequency pulling by the transmitter and to easily generate LO I/Q signals, the DCO is tuned to oscillate around 3.8GHz, which is twice the PHS RF signal frequency. A differential architecture is used to avoid supply and substrate noise coupling, which is serious in integrated conditions. An NMOS-PMOS cross-coupled structure is employed here, which is preferred in low power applications because it can produce large gm. The two cross-coupled transistor pairs, NM1~2 and PM1~2, produce a negative resistance to cancel the effective parasitic resistance of the LC tank. The inductor plays a critical role in the phase noise performance of the LC tank. A single completely symmetrical 1.15nH inductor with the quality factor (Q) higher than 14 around 3.8GHz is optimally designed, note that the simulated value of Q is illustrated in Fig. 2. A digitally controlled PMOS current source is exploited here in order to guarantee that the oscillator operates in the current-limited regime and to improve its Power Supply Rejection Ratio (PSRR).

The varactor array in Fig. 1 consists of four varactor banks, the arrangement of which is shown in TABLE I. The array is composed of weighted PMOS varactors, whose flat high-capacitance inversion region and low-capacitance depletion region (as involved in the two ovals in Fig. 3 and Fig. 4) are individually used. The selection between these two regions is controlled by the multi-bit digital Frequency Tuning Words (FTW) in the two-level buses. By setting the MOS varactors in the two flat regions rather than in the compressed linear region (as shown in Fig. 3), the capacitance sensitivity of the DCO due to noise and operating point shifts is lowest. The PMOS varactors are chosen here because of their well isolation properties.

There are four input FTW buses corresponding to the four varactor banks, respectively. Their bits individually set the capacitance of the varactors so as to establish the expected DCO frequency. As shown in TABLE I, the 6-bit binary-weighted PVT (Process-Voltage-Temperature) bank is activated during power-up and under the control of predetermined PVT FTW, in order to calibrate the large oscillating frequency uncertainty due to process, voltage and temperature variations. ACQ (Acquisition) bank is used to acquire the desired operational channel within the PHS frequency band (1884MHz-1930MHz). In order to achieve good frequency tuning linearity and to avoid binary switching noise, a 16×16 matrix composed of 256 unit-weighted MOS varactor cells is used in the

This work was supported in part by the NSFC under awards 90207001; in part by the 863 Program under award 2006AA01Z224.

9371-4244-0921-7/07 $25.00 © 2007 IEEE.

ACQ bank. The tracking banks (TIB and TFB in TABLE I) are activated during actual PLL tracking. The TIB (Integer Tracking) bank consists of small-size unit-weighted PMOS varactors and is clocked at a reference frequency (19.2MHz in our design). High-speed sigma-delta dithering at about 250MHz operates on TFB (Fractional Tracking) bank to enhance the frequency resolution of the DCO. Similar to the widely-used fractional-N dividers, PMOS varactors in TFB bank are controlled to switch alternately between the two flat capacitance regions many times during one reference cycle, due to which their time-averaged value is equal to TFB FTW. A third-order MASH 1-1-1 sigma-delta digital modulator is used to dither the TFB FTW. In this way, the DCO can be tuned with very fine frequency resolution.

Bias

VDD

•••

Varactor Array

1NM 2NM

2PM1PM

FTWoutP outN

Fig. 1 Schematic of the DCO core.

TABLE I VARACTOR ARRAY ARRANGEMENT

Bank Arrangement Varactor

Banks Weighting Frequency range Frequency

resolution(∆f)

PVT 6-bit

binary weighted 930MHz 14.5MHz

ACQ 8-bit unit weighted 160MHz 625kHz

TIB 6-bit unit weighted 1.28MHz 20kHz

TFB 8-bit unit weighted 20kHz 78Hz

Fig. 2 Simulated differential Q of the designed inductor.

III. THE PROPOSED INVERSION-MODE MOS VARACTOR AND ITS SIMULATION RESULTS

In [2], a PMOS transistor with its source, drain and bulk connected together is used as the varactor of the DCO. However, as shown in Fig. 3, due to the presence of the accumulation region, the low-capacitance depletion region used in the DCO is not as flat as expected, which can induce nonlinearity and impair phase noise performance.

To alleviate this problem, in our DCO we exploit an inversion-mode PMOS varactor [7], which does not enter the accumulation region for a wide range of gate voltage. Its bulk is connected to the power supply and its source and drain are tied together to the digital FTW bus. Moreover, the PPOLY/NWELL inversion-mode varactor features more distinctly defined operational regions than does the accumulation-mode varactor [2].

Simulation results illustrate that the low-capacitance region of the proposed inversion-mode varactor (Fig. 4) is much flatter than that used in [2] (Fig. 3). Its inversion region appears for lower value of Vg because of the substrate effect. Moreover, both the DCO using inversion-mode varactors and that using the varactors in [2] are simulated in Cadence SpectreRF. All the varactors are controlled by static digital signals. Their phase noise performances are compared in Fig. 5. Obviously, the phase noise of our DCO is from 6 to 9dB lower than that of the DCO using the varactors in [2].

Fig. 3 Gate capacitance versus gate voltage of a simulated PMOS varactor used in [2]. Its source, drain, and bulk are tied to ground, L=0.18µm, W=0.22µm.

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Fig. 4 Gate capacitance versus gate voltage of a simulated inversion-mode PMOS varactor proposed in this paper. Its bulk is connected to power supply and its source and drain are tied to ground, L=0.18µm, W=0.22µm.

Fig. 5 Simulated phase noise comparison between the DCO using the proposed varactors and the DCO using the varactors in [2]. All the design parameters are identical except for the varactors.

Fig. 6 Structure of the proposed complementary varactor pair.

IV. REDUCING DCO NOISE BY COMPLEMENTARY VARACTOR PAIRS

A. The Proposed Complementary Varactor Pairs In DCO, the achieved DCO frequency resolution △fres is a

function of the minimum switched varactor capacitance △Cmin[2], namely,

min

2,res

Cf f

C

∆∆ = ⋅ (1)

where f is the oscillating frequency and C is the total capacitance of the LC tank. Its single-sided power spectral density of the phase noise with sigma-delta dithering is [2]

221 1

{ } 2 sin12

,n

res

dth dth

f fL f

f f f

π∆ ∆∆ = ⋅ ⋅ ⋅

∆

(2)

where △f is the frequency offset, fdth is the dithering frequency of the sigma-delta modulator, and n is the order of the modulator. It can be seen from (1) and (2) that the frequency resolution and the phase noise of the DCO depend on △Cmin. The DCO with small △Cmin achieves fine △fres and low phase noise. Accordingly, to meet the demanding frequency resolution and phase noise specifications of modern wireless systems, △Cmin should be as small as possible. Note that △Cmin is usually determined by the minimum size of the MOS varactor in the given process. Denote the capacitance of the

minimum MOS varactor as high

minC when it is working in flat high-

capacitance inversion region, and as low

minC when in low-capacitance depletion region, then the achieved △Cmin in the given process is

high low

min min minC C C .∆ = − (3)

To obtain a small △Cmin on the order of tens of attofarads, previous DCOs have to be implemented in most advanced CMOS processes such as expensive 90nm and 65nm technology. This becomes a great impediment for the application of DCOs in low-cost commercial wireless transceivers nowadays. Moreover, although the frequency resolution of the DCO can be enhanced by sigma-delta dithering, a large △fres requires a high dithering frequency fdth of the modulator [2]. However, higher clock frequency of the modulator will consume much more power, which is not preferred from portability standpoint.

In our DCO, a novel complementary varactor pair is used in TIB and TFB banks to obtain a much smaller △Cmin in the given process. As shown in Fig. 6, the pair consists of two PMOS differential inversion-mode varactors (denoted as A and B). The size of varactor B is minimum and varactor A is slightly larger than B. Varactor A is controlled by its corresponding FTW, while varactor B is controlled by the inverted complementary signal FTW . Denote the capacitance of varactor A and B as CA

high and CBhigh when they work in high-

capacitance region and as CAlow and CB

low when in low-capacitance region, respectively. Then when FTW equals 1, the total capacitance

of the complementary varactor pair high

pairC is

high high low

pair A B A B A BC FTW C FTW C 1 C 0 C =C C .= ⋅ + ⋅ = ⋅ + ⋅ + (4)

When FTW equals 0, the capacitance of the pair low

pairC is

low low high

pair A B A B A BC FTW C FTW C 0 C 1 C =C C .= ⋅ + ⋅ = ⋅ + ⋅ + (5)

Accordingly, the total switched varactor capacitance of the complementary pair pairC∆ can be written as

high low low high

pair A B A B

high low high low

A A B B A B

A min

C (C C ) (C C )

(C C ) (C C ) C C

C C .

∆ = + − +

= − − − = ∆ − ∆

= ∆ − ∆

(6)

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Fig. 7 Simulated phase noise comparison between the DCO using the traditional minimum varactors and the DCO using the proposed complementary varactor pairs. All the design parameters are identical except for the varactors.

Based on (6), it can be seen that by properly choosing the size of varactor A, the proposed varactor pair can provide a much smaller switched capacitance than the traditional minimum size varactor. Therefore a very fine frequency resolution and low phase noise of the DCO can be achieved even in a large feather size CMOS process. Simulation results in a 0.18µm process show that by choosing the width of the varactor A to be 0.24µm and the length to be 0.18µm, simultaneously the width of the varactor B to be 0.22µm and the length to be 0.18µm, the switched capacitance of the proposed varactor pair equals 21aF. In contrast, without this technique, the achieved minimum switched capacitance △Cmin is 150aF in 0.18µm process and 55aF in 65nm process [4].

B. Simulation Method of the DCO and Simulation Results Due to the randomization effect of sigma-delta modulation, the DCO can not provide a quiescent operating point or a periodic steady state solution which is necessary for SPICE or SpectreRF. In this way, it is hard to predict the phase noise of the DCO in common circuit simulators. Consequently, based on the phase noise property extracted from transistor level simulation, a voltage-domain behavioral verilog-A model [8] is exploited by us to predict the phase noise of the DCO.

The phase noise performance of the DCO using the traditional minimum varactors and that using our proposed complementary inversion-mode varactor pairs are compared in Fig. 7. The humps in the data above 20MHz offset are due to the quantization effect of the finite DCO frequency resolution, which is pushed to high frequency offset by sigma-delta dithering. This quantization noise degrades the performance of the oscillator. As illustrated in Fig. 7, our DCO has a over 10dB lower phase noise performance than DCOs using traditional minimum varactors, and especially a 20dB lower noise at frequency offset around tens of megahertz. This improvement is just due to the proposed varactor pair, which provides a much smaller switched capacitance. TABLE II compares our work with other existing DCOs. Apparently, our DCO provides a significantly smaller △Cmin. The phase noise of the DCO is below −123dBc/Hz at 1.2MHz offset when oscillating at 3.8GHz. The frequency tuning range is over 1GHz. It easily meets the specifications of PHS transceivers. The DCO core consumes only 2.8mA current from a 1.8V power supply. However, other existing DCOs can achieve

comparable performance only when they are fabricated in most advanced processes.

V. CONCLUSION In this paper, a DCO is designed for PHS transceivers in a 0.18µm CMOS process. Different from existing DCOs, inversion-mode MOS varactors and novel complementary varactor pairs are proposed and exploited in our DCO. Simulation results show that highly improved phase noise and frequency resolution are achieved while very low power is consumed. Moreover, our DCO does not have to be fabricated in the expensive most advanced processes like other DCOs. The high performance achieved by our low cost and low power DCO makes it promising in facilitating the implementation of the All-Digital PLL in commercial CMOS integrated transceivers nowadays.

ACKNOWLEDGMENT The authors wish to thank R. B. Staszewski of Texas Instruments

Inc., Xiaojian Mao of RDA Corporation, Haibo Long of RF Integrated Corporation for the valuable discussions about sigma-delta modulator, phase noise and inductor design. The authors are also grateful to RF Integrated Corporation for their generous technical support.

REFERENCES [1] Mehta, S.; Si, W.W.; Samavati, H.; Terrovitis, M.; Mack, M.;

Onodera, K.; Jen, S.; Luschas, S.; Hwang, J.; Mendis, S.; Su, D.; Wooley, B., "A 1.9GHz Single-Chip CMOS PHS Cellphone," Solid-State Circuits, 2006 IEEE International Conference Digest of Technical Papers , vol., no.pp. 1952- 1961, Feb. 6-9, 2006.

[2] Staszewski, R.B.; Chih-Ming Hung; Leipold, D.; Balsara, P.T., "A first multigigahertz digitally controlled oscillator for wireless applications," Microwave Theory and Techniques, IEEE Transactions on , vol.51, no.11pp. 2154- 2164, Nov. 2003.

[3] Staszewski, R.B.; Chih-Ming Hung; Barton, N.; Meng-Chang Lee; Leipold, D., "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones," Solid-State Circuits, IEEE Journal of , vol.40, no.11pp. 2203- 2211, Nov. 2005.

[4] N. D. Dalt, C. Kropf, M. Burian, T. Hartig, H. Eul, “A 10b 10GHz digitally controlled LC oscillator in 65nm CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2006, pp. 188-189 and 647.

[5] Staszewski, R.B.; Wallberg, J.L.; Rezeq, S.; Chih-Ming Hung; Eliezer, O.E.; Vemulapalli, S.K.; Fernando, C.; Maggio, K.; Staszewski, R.; Barton, N.; Meng-Chang Lee; Cruise, P.; Entezari, M.; Muhammad, K.; Leipold, D., "All-digital PLL and transmitter for mobile phones," Solid-State Circuits, IEEE Journal of , vol.40, no.12pp. 2469- 2482, Dec. 2005.

[6] Craninckx and Steyaert, Wireless CMOS Frequency Synthesizer Design Norwell, MA: Kluwer, 1998, pp. 149-151.

[7] Andreani, P.; Mattisson, S., "On the use of MOS varactors in RF VCOs," Solid-State Circuits, IEEE Journal of , vol.35, no.6pp.905-910, Jun 2000.

[8] K. Kundert, “Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers,” Available from www.desingers-guide.com

TABLE II COMPARISON WITH THE STATE OF THE ART

DCO Tech [nm]

△Cmin

[aF] △fres [kHz]

Frequency [GHz]

Phase noise [dBc/Hz]

Current [mA]

[2] 130 38 23 2.4 -112@500kHz 2.3

[3] 90 50 24 0.9 -165@20MHz 18

[4] 65 55 1030 10.5 -102@1MHz 3

(Ours) 180 21 20 3.8 -123@1.2MHz 2.8

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