SINGLE-POINT-DETECTION SLEW-RATE ENHANCEMENT CIRCUITS FOR SINGLE-STAGE AMPLIFIERS

Hoi Lee and Philip K. T. Mok

Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology

Clear Water Bay, Hong Kong

Tel.: (852)2358-85 17, Fax: (852)2358-1485, Email: leehoi@ee.ust.hk, eemok@ee.ust.hk

Abstract

Most slew rate enhancement circuits can either be used in current-mirror amplifier or folded-cascode amplifier, but not in both amplifiers. In this paper, a new class of slew rate enhancement (SRE) circuit is proposed. By using a single-point detection (SPD) technique at the active load device of the core amplifier to sense the fast signal transient, the new SRE circuits can be used in both current-mirror amplifier and folded-cascode amplifier. In addition, the simple SRE circuits serve as a plug-in feature to the core amplifier and do not affect its original small- signal frequency response. Implemented by AMS 0.6pm CMOS process, the current-mirror amplifier with SRE circuit occupies the area of 0.027"' and achieves 1.5V/ps slew rate with 470pF capacitive load while only dissipating 90pA total static current. Similarly, the folded-cascode amplifier with SRE circuit occupies the area of 0.03mm2 and achieves 1.52V/ps slew rate with 470pF loading while only 84pA total static current is dissipated.

1. Introduction

For the applications of low-power high-speed switched- capacitor circuits, fast settling time of an operational amplifier is a common and critical requirement. The settling time of the amplifier can be divided into the slewing period and the quasi- linear period [ 13. In particular, the quasi-linear period depends on the small-signal behavior of the amplifier while the slewing period depends on the large-signal behavior. However, in switched-capacitor circuit, the amplifier needs to drive a large capacitive load (1100pF) so as to reduce the effects of thermal (kT/C) noise [2]. Thus the settling time of these amplifiers is dominated and restricted by its slewing period as the maximum available current I,, to charge up the loading capacitor is limited in low power condition. In fact, the slew rate (SR) of single-stage amplifiers is given by

S R = & (1) CL

In order to improve the slew rate, different methods on detecting the signal transient and supplying the dynamic current to charge and discharge the loading capacitor have been proposed [3-61. To detect the signal transient, one method uses another PMOS differential pair connected to NMOS differential pair of the core amplifier to sense the change in the signal during

0-7803-7448-7/02/$17.00 02002 IEEE I1 - 831

transient [4,5]. However, the existence of both PMOS and NMOS differential pairs at the same time not only limits the minimum supply voltage of the amplifier but also increases the noise and the input capacitance of the core amplifier. Other method detects signal change at the active load devices of the core amplifier [3,6]. This allows the amplifier to be able to operate under low voltage. However, this design requires detection of both the positive and the negative signal change simultaneously. As a result, this method can only apply to current-mirror amplifier. For the circuit providing the dynamic current, if the dynamic current is supplied to the main bias of the core amplifier [3,4] during the transient, then it places design constraint on the device size of the transistors in the core amplifier.

With respect to the above problems, a new class of SRE circuits is proposed in this paper. This class of SRE circuits contains two configurations and both of them only need to detect the positive signal change of the core amplifier in order to start- up the SRE circuit during transient. Thus the proposed class is called as Single-Point-Detection (SPD) SRE and can apply to both the current-mirror amplifier and the folded-cascode amplifier. Also our proposed class of circuits supplies the dynamic current directly to output of the core amplifier such that the design flexibility of the core amplifier is ensured. Furthermore, our proposed solution enables operation under low voltage and only dissipates a small static current.

Firstly, the operation principle of SPD SRE circuits for the current-mirror amplifier and the folded-cascode amplifier is discussed in Section 2. Then the detailed circuit implementations of both current-mirror amplifier with SPD SRE circuit 1 and folded-cascode amplifier with SPD SRE circuit 2 are shown and the measurement results of both amplifiers are depicted in Section 3 to verify the improvement in slew rate of single-stage amplifiers. Finally, a summary is given in Section 4.

2. Operation Principle of SPD SRE Circuits

Figure 1 shows the proposed SPD SRE circuit 1 for the current-mirror amplifier in which transistor M1 is the load device of the core amplifier while the slewing capability is provided by transistors M2-M8, Mp and Mn. In the SPD SRE circuit 1, the input step transition is detected by M2 connecting to a single point, that is the gate of M1, such that slew rate enhancement can be achieved during both positive and negative slewing. Current Ii, is a signal dependent quantity, which

increases when the voltage at the positive input of the core amplifier increases. Transistors M4 and M5 control the on and off of the transistor Mp, which provides the dynamic current to charge up the loading capacitor during positive slewing. Similarly, transistors M6-8 determine the on and off of the transistor Mn, which will discharge the loading capacitor during the negative slewing. In the quiescent state, the sizes of M4 and M5 are designed such that if they operate in saturation region, their drain currents equal to I4 and I,,, respectively. As the drains of M4 and M5 are tied together, the current flowing through these two transistors is 11, which is given by

I, = min{I4,IIn}= I,, (2) During the static state, transistor M5 operates in the saturation region while transistor M4 is forced to operate in the triode region. Thus, the voltage at node nl is pulled up to close to the positive supply voltage and the transistor Mp is off. Similarly, if transistors M6-8 operate in saturation region, their drain currents equal to b, I,, and Is, respectively. As the drains of these three transistors are tied together, a dc current I2 will flow through the branch, in particular 12 is given by

During the static state, transistor M6 will operate in the saturation region while both M7 and M8 are in triode region. Therefore, the voltage at n2 is close to negative supply voltage and the transistor Mn is off. As both Mp and Mn are in cut-off region, the SRE circuit does not affect the performance of the core amplifier during normal operation.

During the positive slewing, I,, increases and it equals to I,+ Then, the transistor M4 will go into the saturation region and M5 is in the triode region. The voltage at node nl is close to the negative supply voltage, which causes Mp to be heavily turned on. However, I2 will still be equal to I6 when I,, increases, then Mn is kept in the off-state. As a result, a huge current is generated to charge up the loading capacitor at the output. When the output voltage reaches the value close to the final value, I,, decreases back to its original value, which causes I1 to equal to I,, again. Thus the voltage at node nl will pull up to close to the positive supply voltage and the SRE circuit is shut down. Similarly, during the negative slewing, I,, decreases and I, equals to I, while 12 is the sum of I,, and Is. Then, transistors M4, M5 and Mp are in the same operation regions as they are in the static state. But, transistor M6 is forced to operate in triode region while both M7 and M8 are in saturation region. Thus, the voltage at n2 is close to the positive supply voltage, Mn is turned on and large current is sunk from the output to discharge the output capacitor. The operation of different transistors during different states is summarized in Table 1.

I~ =min(16,(1,, +r8))=r6 (3)

Table 1: Transistors’ operation regions of SRE circuit 1 for current-mirror amdifier

M5 I Saturation I Triode I Saturation MD I Off Off

Figure 1 : Proposed SRE circuit I for current-mirror amplifier

The proposed SPD SRE circuit 2 for the folded-cascode amplifier is similar to that for the current-mirror amplifier and is shown in Figure 2. In the circuit, transistor MI is the load device of the folded-cascode amplifier while the slewing capability is provided by other transistors. By detecting the change of the signal dependent current Ii,, transistors Mp and Mn will be switched on and off according to the voltages at nl and n2, respectively. Thus, the dynamic current is provided by either Mp or Mn to charge or discharge the loading capacitor. The detailed operation of different transistors in SRE circuit 2 during different states is summarized in! Table 2.

Figure 2: SRE circuit 2 for fo1de:d-cascode amplifier

Table 2: Transistors’ operation regions of SRE circuit for folded- cascode amplifier

W,--y!$W] Saturation

3. Implementatiions and Results

To verify the functionality of both SPD SRE circuit 1 and SPD SRE circuit 2, both circuits are incorporated into the

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current-mirror amplifier and the folded-cascode amplifier, respectively. Circuit diagrams of both the overall current-mirror amplifier and the overall folded-cascode amplifier shown in Figures 3 and 4 were fabricated with AMS 0.6pm CMOS process. The micrographs of the both amplifiers are shown in Figures 5 and 6, respectively. The area of the overall current- mirror amplifier is 0.027mm’ while that of the overall folded- cascode amplifier is 0.03”’. In particular, both SPD SRE circuit 1 and circuit 2 only occupy a small portion in the overall current-mirror amplifier and the overall folded-cascode amplifier, respectively.

The measurement results of small-signal performance of the overall amplifier such as the low frequency gain and the gain- bandwidth product GBW are almost the same as the simulated results and are presented in Table 3. The results verify that the proposed SRE circuits do not affect the small-signal performance of the current-mirror amplifier and folded-cascode amplifier under normal operation condition.

Figures 7 and 8 show the transient response measurements of the overall current-mirror amplifier and that of the overall folded-cascode amplifier, respectively, in unity-gain feedback configuration with 1V step input. The measured transient responses are also summarized in Table 3. Both Figures 7 and 8 show that the output voltage does not exhibit overshoot in the quasi-linear region of the transient response.

Figure 5: Micrograph of current-mirror amplifier with SRE circuit 1

, .................................... ............................................... ..................................... ,

Figure 6: Micrograph of folded-cascode amplifier with SRE circuit 2

0 ................................... J , .................................. .( ............................................... ULGa bu.u” W.ph P.UEblwsM

Figure 3: Circuit diagram of overall current-mirror amplifier ..........................................................................................................................

Figure 7: Transient response of current-mirror amplifier with SRE circuit 1 when driving 470pF capacitive load

I, : ........................................... ;! ...................................... / : .................................. ! CmlLD, =w- A.tJk~m

Figure 4: Circuit diagram of overall folded-cascode amplifier

To provide a clear picture on the improvements by the proposed slew rate enhancement circuits, a comparison of different single-stage amplifiers with different slew rate enhancement circuits is shown in Table 4. The large-signal

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figure of merit FOML [7] is defined for large-siJal performance.

(4) SR.CL

FOML =- power

The unit of FOM is (V/ps).pF/mW. An average slew rate SR, defined as the slope between 10% and 90% of the output voltage step level, is used in the calculation. In fact, the numerator implies the amount of the dynamic current charging or discharging the output capacitor while the denominator denotes the total static power consumption. Thus, FOML implies the current efficiency of the single-stage amplifiers and a larger figure of merit means a better slew rate enhancement circuit. In our proposed SPD SRE circuits, FOM, above 2600 V.pF/psmW can be achieved for 47OpF loading capacitors, which is an improvement to most S E circuits in previous work.

[31

141

[61 This work

SRE 1

the proposed SRE circuits were fabricated and characterized. Slew rates as high as 1.5V/ps with the capacitive load of 470pF in both amplifiers have been measured. Compared with other published SRE circuits, the proposed SRE circuit shows better large-signal performance with no overshoot in the transient response than most of the SRE circuits presented in previous work. A similar technique has been presented in [6]. The similarity is in the way of applying the dynamic current directly to the output. However, the circuits presented in this paper use a distinctive method to detect the fast signal transitions. This allows the SPD SRE circuits to be applied to all single-stage amplifiers.

78

747

2686

261 1

0.25

56

1.6

1.5

0*325@5 (CL470pF)

7.5 (C,=l OOpF)

0*28@3 (C 470pF)

0*27@3 (CL470pF)

Power (mW@Vdd)

This work: SRE 2

Figure 8: Transient response of folded-cascode amplifier with SRE circuit 2 when driving 47OpF capacitive load

2820 1.5 0*25@3 (CL47Q,F)

Table 3: Summary of the measurement results of both amplifiers I Current-Mirror I Folded-Cascode I

90P Static Current

Consumption (A)

I Amp.w/sRE I Amp. w/ SRE supply Voltage (v) I +/- 1.5 I +/- 1.5

84P ~~

GBW(MHz) I 0.057 0.05

89 Phase Margin (degree) 90

1.3(+)/1.73(-)

4. Summary

A new class of slew rate enhancement circuits, which is targeted for single-stage amplifiers driving large capacitive loads has been presented in this paper. By using single-point detection method, both candidates of the proposed class can be applied to both the current-mirror amplifier and the folded-cascode amplifier. To verify a significant improvement in the slew rate and 1% settling time using the proposed SRE circuits, both the current-mirror amplifier and the folded-cascode amplifier with

Acknowkdgements

This work was supported by Research Grant Council of Hong Kong SAR, China (Project No. HKUST 6022/01E).

References

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[2] A.E. Stevens and G.A. Miller, “A High-Slew Integrator for Switched-Capacitor Circuit$,” IEEE Journal of Solid-state Circuits, Vol. 29, pp. 1146-’I 149, Sept. 1994.

[3] M.G. Degrauwe, J. Rijmenamts, E.A. Vittoz and J.J.D. Man, “Adaptive Biasing CMOS Amplifiers,” IEEE Journal of Solid-state Circuits, Vol. SC-17, pp. 522-528, June 1982.

[4] R. Klinke, B.J. Hosticka and H.J. Pfleiderer, “A Very-High- Slew-Rate CMOS Operational Amplifier,” IEEE Joumal of Solid-state Circuits, Vol. 24, pp. 744-746, June 1989.

[5] K. Nagaraj, “CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique,” Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, pp. 11.6.1- 11.6.5, May 1990.

[6] H. Lee and P.K.T. Mok, “A CMOS Current-Mirror Amplifier with Compact Slew Rate Enhancement Circuit for Large Capacitive Load Applications,” Proceedings of the IEEE Intemational Symposium on Circuits and Systems, Vol. 1, pp. 220-223, May 2001.

[7] K.N. Leung, P.K.T. Mok, W.H. Ki and J.K.O. Sin, “Three- Stage Large Capacitive Load Amplifier with Damping- Factor-Control Frequency Compensation,” IEEE Journal of Solid-state Circuits, Vol. 35, pp. 221-230, Feb. 2000.

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