ic design of power management circuits (i)
DESCRIPTION
by Wing-Hung Ki Integrated Power Electronics Laboratory ECE Dept., HKUST Clear Water Bay, Hong Kong www.ee.ust.hk/~eeki International Symposium on Integrated Circuits Singapore, Dec. 14, 2009TRANSCRIPT
IC Design ofPower Management Circuits (I)
Wing-Hung KiIntegrated Power Electronics Laboratory
ECE Dept., HKUSTClear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated CircuitsSingapore, Dec. 14, 2009
Ki 2
1. Switching Converters: Fundamentals and Control
2. Switching Converters: IC Design
3. Switching Converters: Stability and Compensation
4. Fundamentals of Bandgap References
5. Development of Integrated Charge Pumps
6. Introduction to Low Dropout Regulators
Tutorial Content
Ki 3
Part I
Switching Converters:Fundamentals and Control
Ki 4
Steady State AnalysisLossless elementsBuck, boost, buck-boost power stagesVolt-second balanceContinuous conduction modeDiscontinuous conduction modeRinging suppressionPseudo-continuous conduction modeEfficiency
Performance Evaluation Parameters
Control TopologiesPWM voltage mode controlPWM current mode control
Single-Inductor Multi-Input Multi-Output Converters
Content
Ki 5
Linear Regulator has Low Efficiency
C LR
oV
1R
2R
obV
VREF
NM
EAddV
Q1I oIQ3IQ2I
ddI
Efficiency of linear regulator is not high:
η = = = < <+
o o o o o o
in dd dd dd o Q dd
P V I V I V1
P V I V I I V
Can one design a power converter with efficiency close to 1?
power converter
Ki 6
Switches as Lossless Components
A power converter with high efficiency needs lossless components.Reactive elements: capacitors, inductorsActive elements: switches
swI+
−swV
= Vsw ×Isw= Vsw ×0= 0
switch closed
Psw
swI+
−swV
store & relax
PC = 0
store & relax
PL = 0
switch open
Psw = Vsw ×Isw= 0×Isw= 0
CL
Ki 7
Switching Converter: Heuristic Development (1)
LR
oV
ddV
LR
oV
ddV
1SW
o ddV V=
t
No regulation
o ddV DV=
t
Load cannot accept a pulsating supply voltageduty ratio = D
ddV
Ki 8
C LR
oV
ddV
L1SW
C LR
oV
ddV
L1SW
2SW
xV
Add a lossless filter to achieve small ripple voltage, but …when switch is off, inductor current cannot change instantaneously and cause spark (volt-second balance).
Add a second switch that operates complementarily to arrive at a functional switching converter.
o ddV DV=
t
ddV
Switching Converter: Heuristic Development (2)
Ki 9
Buck, Boost and Buck-Boost Converters (1)
C LR
oV
ddVL
xV
C LR
oV
ddV
LxV
C LR
oV
ddV L
xV
One L and one C gives a second order switching converter.
C has to be in parallel with RL for filtering, leaving three ways to place L, SW1 and SW2 between Vdd and RL .
Three types of converters:Step-down: buckStep-up: boostStep-up/down: buck-boost
(Boost-buck, or Cuk, is a 4th order converter)
Buck
Boost
Buck-boost
1SW
2SW
1SW
2SW1SW
2SW
Ki 10
Buck, Boost and Buck-Boost Converters (2)
C LR
oV
ddV
LNM
1D
xV
C LR
oV
ddV
L xV
C LR
oV
ddVL
xV
SW1 is the controlling switch that determines the duty ratio D, while SW2 provides a path for the inductor current i to flow when SW1 is off.
SW1 can be a power NMOS (MN ). If power PMOS is used, the phase has to be reversed.
To prevent i from going negative, SW2
is usually implemented by a diode (D1), but the forward drop gives a low efficiency.
Note that Vo of buck-boost is negative.
Buck
Boost
Buck-Boost
i
state 1
state 2
NMstate 1
state 2state 1
NM
state 2
i
i
1D
1D
Ki 11
I-V Relations of C and L
The I-V characteristics of a capacitor and an inductor are described by
= cc
dvi C
dt=
div L
dt
Approximations are very useful in many calculations:
Δ=
Δc
cV
i Ct
Δ=
Δi
v Lt
ci +
−
cv
+
−
v
i
For sinusoidal steady state, the phasor relations are:
= =ω
cc
c
v 1zi j C
= = ωv
z j Li
CL
Ki 12
Volt-Second Balance
= ⇒ Δ = Δdi V
v L I tdt L
Switching actions cause ripples for both inductor current (i ) and capacitor voltage (vc). In the steady state, both quantities return to the same value after one cycle.
+ − v i
L
=11
V (S )m
L= −2
2V (S )
mL
1t(or DT)
2t(or D ' T)
Inductor current has to obey volt-second balance (VS balance):
V (S1)×t1 + V (S2)×t2 = 0
⇒
m1 t1 = m2 t2 or m1 D = m2 D’
It is used to compute the conversion ratio M = Vo /Vdd .
i
ΔII
0A
Ki 13
Inductor, Input, Switch, Diode and Tail Currents
Consider the buck converter:
C LR
oV
ddV
L
NM
1D
xVi
ddi
i
di
tisi
di
ti
si
ddici
Input current idd : current through Vdd
Switch current is : i in State 1
Diode current id : i in State 2; even if diode is implemented by NMOS switch
Tail current it : current through the combination of C and RL .
Capacitor current ic : ac part of tail current
Load current io : averaged tail current
oI
oI
Ki 14
Continuous Conduction Mode
The converter is operating in continuous conduction mode (CCM) if the inductor current is always larger than zero.
Buck converter(Step-down)
m1 D = m2 D’⇒
(Vdd -Vo )D = Vo D’
⇒ = =0
dd
V M D
V
Boost converter(Step-up)
m1 D = m2 D’⇒
Vdd D = (Vo -Vdd )D’
⇒ = =−
0
dd
V 1 MV 1 D
Buck-boost converter(Step-up/down)
m1 D = m2 D’⇒
Vdd D = -Vo D’
−⇒ = =
−0
dd
V D MV 1 D
oVddV oVddV oVddV
+
−V
1S 1S
1S2S2S 2S+ −V + −V
Ki 15
Discontinuous Conduction Mode
When the switching converter is operation in CCM, one switching cycle has two states S1 and S2 . When the load current becomes smaller and smaller, eventually the inductor current would fall to zero, and the converter then operates in discontinuous conduction mode (DCM) with a third state S3 . During D3 T, all switches are open.
=11
V (S )m
L= −2
2V (S )
mL
DT
i
ΔI
2D T 3D T
=3V (S )0
L
=i 0
VS balance becomes:
m1 D = m2 D2
Ki 16
C LR
oV
ddVL1SW
2SW
xV
xC
When both switches are open, L, C and the parasitic capacitor Cx at Vx form a resonance circuit that leads to serious ringing.
Ringing Suppression
We may add a small switch to short the inductor when SW1 and SW2 are both off [Jung 99].
xV
i
C LR
oV
ddVL1SW
2SW
xV
xC
3SW
xV
i
oVddV
Ki 17
Pseudo-Continuous Conduction Mode
C LR
oV
ddV
L
1SW
2SW
xV
FWSW
By increasing the size of the ringing suppression switch, a switching converter may work in pseudo-continuous mode (PCCM). It was first employed in a single-inductor dual-output (SI-DO) converter to increase the current handling capability [Ma 03b]. When both SW1 and SW2 are open, the freewheel switch SWFW is closed to allow free-wheeling of i at Ipccm.
i
pccmI
i
0
Ki 18
Efficiency of Buck Converter
C LR
oV
ddV
L1S
η = =o o o
dd dd dd
P V IP V I
For an ideal buck converter working in CCM, the conversion ratio M is Vo /Vdd = D, and Io :Idd = 1:D, giving η=1. If conduction loss is accounted for, then Io /Idd is still 1/D, but M is modified as M=ηD, with
η = =+ +
+
o
s ddd
L
P 1R DR D'RP 1
R
ddI
R
dR
sR
2S
oI
Ki 19
Efficiency of 2nd Order Converters
By accounting for conduction losses due to switch, diode and inductor series resistance (Rs , Rd and R , respectively), the efficiencies of buck, boost and buck-boost converters are computed as [Ki 98]
Buck:
Boost:
Buck-boost:
η =+ +
+buck
s d
L
1R DR D'R
1R
η =+ +
+boost
s d2
L
1R DR D'R11
RD'
−η =+ +
+buck boost
s d2
L
1R DR D'R11
RD'
Ki 20
Performance Evaluation Parameters
For a good voltage regulator, the output voltage should remain constant even the input voltage, load current or temperature changes.
Steady state parameters:Line regulationLoad regulationTemperature coefficient
Small signal parameters:Power supply rejectionOutput impedance
Transient parameters:Line transient (settling times)Load transient (settling times)Reference tracking time
Ki 21
Line Regulation
in mV / VΔ=
Δo
dd
Vline reg.
V
Line regulation is the change of Vo w.r.t. the change in Vdd :
Δ=
Δo o
dd
V / VV
in % / V
Switching converters are non-linear circuits for large signal changes, and hand analysis is impossible. It could be obtained by simulation. In datasheets, line regulation is usually measured.
Ki 22
Power Supply Rejection
Power supply rejection (PSR) is the small signal change of Vo w.r.t. the small signal change in Vdd .
In transfer function form:
In dB:
Usually |vo /vdd | < 1, but we customarily give a positive PSR in dB.
Note: Line reg. ≈
PSR × ΔVdd
= o
dd
vPSR
v
= × dd
o
vPSR 20 log
v
For a good switching converter (also for bandgap reference and linear regulator), the output voltage should be a weak function w.r.t. the supply voltage. Hence, a small signal parameter, the power supply rejection, gives good indication of line regulation.
Ki 23
Load Regulation and Output Impedance
in mV /mAΔ=
Δo
o
Vload reg.
I
Load regulation is the change of Vo w.r.t. the change in Io :
Δ=
Δo o
o
V / VI
in % /mA
In datasheets, load regulation is usually measured.
In the small signal limit, load regulation is the output impedance:
= oo
o
dVR
dIΩin
Ki 24
Temperature Coefficient
Temperature coefficient (TC) is the change of a parameter X w.r.t. the change in T, and is a large signal parameter:
−Δ= =
Δ −2 1
2 1
X(T ) X(T )XTC
T T T
TC could be positive or negative.
oin [X] / C
Δ=
ΔX / X
Toin ppm / C
Ki 25
PWM Voltage Mode Control (1)
S
RQ
Q
refVA(s)
EACMP
gV
oV
ckramp
L
CLR
1R
2R
obVav
av
PM
NM
A regulated switching converter consists of the power stage and the feedback circuit.
For a buck converter, if an on-chip charge pump is not available, then the NMOS power switch is replaced by a PMOS power switch.
avramp
ck
Q
Q
Ki 26
The output voltage Vo is scaled down by the resistor string R1 and R2 . The scale factor is b = R2 /(R1 +R2 ).
The scaled output voltage bVo is compared to the reference voltage Vref to generate a lowpass filtered voltage Va through the compensator A(s).
At the start of the clock, the SR latch is set and the switch MP is turned on, starting the duty cycle. A sawtooth waveform (ramp) synchronized with the clock ramps up.
When the ramp reaches the level of Va (trip point), the SR latch is reset, terminating the duty cycle.
When the SR latch is set, i ramps up. When the SR latch is reset, i ramps down. In the steady state, i returns to the same level at the start of every clock cycle.
PWM Voltage Mode Control (2)
Ki 27
PWM Feedback Action
For stability, the control loop has to have negative feedback.
Assume Vo drops suddenly due to change in load or disturbance⇒
error voltage Verr = (Vref –bVo ) becomes larger⇒
Va = A(f)(Vref –Vo ) also becomes larger⇒
with a higher Va , it takes the ramp longer to reach Va⇒
duty ratio D is temporarily increased⇒
more current is dumped into the load⇒
Vo rises accordingly and eventually settles to the original value
Note that A(s) is the frequency response of the compensator, not of the op amp Aop (s).
Ki 28
PWM Current Mode Control
S
RQ
Q
refVA(s)
EACMP
ddV
oV
ck
L
CLR
1R
2R
obVav
av
i
fi R
i /N
fNR
PM
NM
A current mode controlled switching converter is realized by replacing the fixed voltage ramp with the inductor current ramp.
ddVcurrentsensor
Ki 29
Sub-harmonic Oscillation and Slope Compensation
Output of EA Va cannot change in one cycle. If inductor current is perturbed by an amount of ΔI1 , oscillation occurs if
Δ −= > ⇔ >
Δ2 2
1 1
I m1 D 0.5
I m
=a a fI V /R
Δ 1IΔ 2I
=a a fI V /R
Δ 1I Δ 2I
1m − 2m1m − 2m
To prevent oscillation, employ slope compensation by adding a negative slope to Ia (i.e., Va ) to suppress the change in ΔI2 .
Δ 1I Δ 2I
1m − 2m
− cm
=a a fI V /R
<D 0.5 >D 0.5
−Δ= < ⇔ >
Δ +c 22 2
c1 c 1
m mI m1 m
I m m 2
Ki 30
Current Mode PWM with Compensation Ramp
S
RQ
Q
refVA(s)
EACMP
ddV
oV
ck
L
CLR
1R
2R
obVav
i
i /N
fNR
PM
NM
V2I
ramp from OSCav
DT
1 c f(m m )R+ 2 c f(m m )R− −
bvbv
In practice, the output of EA (Va ) should not be tempered, and a compensation ramp of +mc is added to m1 instead.
compensationramp
ddV
Ki 31
Synchronous Rectification
ddV
L
CLR
iPM
NM
To eliminate loss due to forward diode drop, the power diode is replaced by a power NMOS MN , and the scheme is known as synchronous rectification. To eliminate short-circuit loss of MP and MN , a break-before-make (BBM) buffer is used.
S
RQ
QBBM
Buffer
PV NV
PQ,V
NV
Q(ck) φ1
φ =2 NV
φ1
φ2
φ =1
PV
φ2Additional logic is needed for DCM operation. Non-overlapping φ1 and φ2
Ki 32
Multiple-Output Converters
L
1CL1R
o2V
1S
L
2CL2R
o1V
1i
2i 2i
1i
0S
2S
0S
ddV
Consider two boost converters that operate in deep DCM:
T 2T
T 2T
ddV
Ki 33
Single-Inductor Multiple-Output Converters
2C
o2V
L
L2R
i
0S
2S
ddV
1CL1R
1S o1V i
Time-multiplexing allows sharing one inductor and diverting the inductor current to two or more outputs [Ma 03a]:
T 2T
Ki 34
SIMO Converter in PCCM
2C
o2V
L
L2R
i
0S
2S
ddV
1CL1R
1S o1Vi
To handle large load currents, raise the inductor current floor to operate in PCCM. Add a free-wheeling switch (SFW ) to short the inductor when the inductor current reaches Ipccm [Ma 03b].
T 2T
i
T 2T
FWS
pccmI
Ki 35
SI-MIMO Converter
Energy-harvesting Boost 1 Rechargeable Boost 2 Loadsource battery
srcV
srcV
batV
batV
loadV
loadV
Energy-harvesting SI-DIDO boost Load Rechargeablesource battery
batV
Some applications need two converters in series with reduce efficiency.
Reorganize by using a SI-DIDO converter that needs only one inductor [Lam 04b], [Lam 07b], [Sze 08].
Ki 36
Development of SI-MO and SI-MIMO Converters
The recent years sees active R&D activities of SI-MO and SI-MIMO switching converters for low power applications. It is important to recognize the contribution of the first developers.
The idea of SI-MO converters was first conceived in [Goder 97], and only boost sub-converters were considered.
An SI-DO converter with buck-boost sub-converters was discussed in [Ma 97] to demonstrate the switching flow graph modeling method.
SI-DO converters became commercial products [MAX 98, UCC 99].
The concept of SI-MO was reinvented [Li 00, Ma 00, Ma 01, May 01]. [Ma 01] stressed the importance of DCM operation for reducing cross-regulation. A systematic classification is discussed in [Ki 01].
DCM operation is extended to PCCM operation in [Ma 02].
The concept of SI-MIMO was conceived [Lam 04, Lam 07].
Ki 37
References: Switching Converter Fundamentals
Books:[Brown 01] M. Brown, Power Supply Cookbook, EDN, 2001.
[Erickson 01] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd Edition, Springer Science, 2001.
[Kassakian 91] J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Principle of Power Electronics, Addison Wesley, 1991.
[Krein 98] P. E. Krein, Elements of Power Electronics, Oxford, 1998.
Papers:[Jung 99] S. H. Jung et. al., "An integrated CMOS DC-DC converter for
battery-operated systems," IEEE Power Elec. Specialists Conf., pp. 43–47, 1999.
[Ki 98] W. H. Ki, "Signal flow graph in loop gain analysis of DC-DC PWM CCM switching converters," IEEE TCAS-1, pp.644-655, June 1998.
Ki 38
[Goder 97] D. Goder and H. Santo, “Multiple output regulator with time sequencing,” US Patent 5,617,015, April 1, 1997.
[Ma 97] Y. H. Ma and K. M. Smedley, "Switching flow-graph nonlinear modeling method for multistate-switching converters," IEEE Trans. on Power Elec., pp.854–861, Sept., 1997.
[MAX 98] "MAX685: Dual-output (positive and negative) DC-DC converter for CCD and LCD", Maxim Datasheet, 1998.
[UCC 99] "UCC3941: 1V synchronous boost converter," Datasheet, Unitrode Semiconductor Products, Jan. 1999.
[Li 00] T. Li, "Single inductor multiple output boost regulator," US Patent 6,075,295, June 13, 2000.
[Ma 00] D. Ma and W. H. Ki, "Single-inductor dual-output integrated boost converter for portable applications," 4th Hong Kong IEEE Workshop on SMPS, pp. 42- 51, Nov. 2000.
References: Early Development of SI-MIMO Converters (1)
Ki 39
[Ma 01a] D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling", IEEE/ACM Asia South Pacific Design Automation Conf., LSI University Design Contest, pp.19–20, Jan. 2001.
[May 01] M. W. May, M. R. May and J. E. Willis, "A synchronous dual-output switching dc-dc converter using multibit noise-shaped switch control," IEEE Int’l Solid- State Circ. Conf., pp.358–359, Jan 2001.
[Ma 01b] D. Ma, W. H. Ki, P. Mok and C. Y. Tsui, "Single-inductor multiple-output switching converters with bipolar outputs", IEEE Int'l. Symp. on Circ. and Syst., pp. III-301 - III-304, Sydney, May 2001.
[Ma 01c] D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "A 1.8V single-inductor dual-output switching converter for power reduction techniques," IEEE Symp. on VLSI Circ., Kyoto, Japan, pp. 137-140, June 2001.
[Ki 01] W. H. Ki and D. Ma, "Single-inductor multiple-output switching converters", IEEE Power Elec. Specialists Conf., Vancouver, Canada, pp.226–231, June 2001.
[Ma 02] D. Ma, W.H. Ki, and C.Y. Tsui, "A pseudo-CCM / DCM SIMO switching converter with freewheel switching", IEEE Int'l Solid–State Circ. Conf., San Francisco, pp.390–391+476. Feb. 2002.
References: Early Development of SI-MIMO Converters (2)
Ki 40
[Ma 03a] D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode," IEEE J. of Solid-State Circ., pp. 89-100, Jan. 2003.
[Ma 03b] D. Ma, W. H. Ki and C. Y. Tsui, "A pseudo-CCM/DCM SIMO switching converter with freewheel switching," IEEE J. of Solid-State Circ., pp. 1007- 1014, June 2003.
[Lam 03] Y. H. Lam, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor dual-input dual- output switching converter for integrated battery charging and power regulation," IEEE Int'l. Symp. on Circ. and Syst., Bangkok, Thailand, pp. III.447-III.450, May 2003.
[Lam 04] H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control switching converter with self-biased current sensor," IEEE Int'l Midwest Symp. on Circ. & Sys., pp.II.305–II.308, July 2004.
[Koon 05] S. C. Koon, Y. H. Lam and W. H. Ki, "Integrated charge-control single- inductor dual-output step-up/step-down converter," IEEE Int'l. Symp. on Circ. and Syst., Kobe, Japan, pp. 3071-3074, May 2005.
[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Single-inductor multiple-input multiple- output switching converter and method of use," US Patent 7,256,568, Aug 14, 2007.
[Ma 09] D. Ma, W. H. Ki, and C. Y. Tsui, "Single-inductor multiple-output switching converters in PCCM with freewheel switching," US Patent 7,432,614, Oct. 7, 2008.
References: Early Development of SI-MIMO Converters (3)
IC Design ofPower Management Circuits (II)
Wing-Hung KiIntegrated Power Electronics Laboratory
ECE Dept., HKUSTClear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated CircuitsSingapore, Dec. 14, 2009
Ki 2
Part II
Switching Converters:IC Design
Ki 3
IC Design: Control LoopBiasingRTCT oscillatorComparators, hysteretic comparatorOperational amplifierCurrent sensorsCompensation ramp
IC Design: Power StagePower transistor and gate driveSynchronous rectificationActive diodes
IC Design: Peripheral CircuitsUnder voltage lockout (UVLO)Over current protection (OCP)Soft start circuit
Content
Ki 4
Analog IC design is ENGINEERING.Analog IC design is ART.
There is no best design but good and reasonable designs.
Design examples shown are suggestions rather than instructions, and unavoidably opinionated.
Suggestions and corrections are most welcome to make a more relevant and accurate presentation.
Foreword
Ki 5
Guidelines for Analog IC Design
(1) Length of transistors are at least 4λ
to 8λ
for better matching.
(2) Gate overdrive voltage Vov = (Vgs –Vt ) of a transistor should be at least 150mV for better current mirror matching.
(3) Use 1% rule as initial point for matching, delay and losses.
Ki 6
PWM Voltage Mode Control (1)
A regulated switching converter consists of the power stage and the feedback circuit.
For a buck converter, if an on-chip charge pump is not available, then the NMOS power switch is replaced by a PMOS power switch.
S
RQ
Q
refVA(s)
EACMP
gV
oV
ckramp
L
CLR
1R
2R
obVav
av
PM
NM
avramp
ck
Q
Q
Ki 7
Current Mode PWM with Compensation Ramp
In practice, the output of EA (Va ) should not be tempered, and a compensation ramp of +mc is added to m1 instead.
S
RQ
Q
refVA(s)
EACMP
ddV
oV
ck
L
CLR
1R
2R
obVav
i
i /N
fNR
PM
NM
V2I
ramp from OSCav
DT
1 c f(m m )R+ 2 c f(m m )R− −
bvbv
compensationramp
ddV
Ki 8
Synchronous Rectification
To eliminate loss due to forward diode drop, the power diode is replaced by a power NMOS MN , and the scheme is known as synchronous rectification. To eliminate short-circuit loss of MP and MN , a break-before-make (BBM) buffer is used.
Additional logic is needed for DCM operation. Non-overlapping φ1 and φ2
ddV
L
CLR
iPM
NM
S
RQ
QBBM
Buffer
PV NV
PQ,V
NV
Q(ck) φ1
φ =2 NV
φ1
φ2
φ =1
PV
φ2
Ki 9
Simple Current Source and Current Mirror
ddV
1M
( ) −⎛ ⎞= μ − =⎜ ⎟⎝ ⎠
2 dd 11 n ox 1 tn
1 1
V V1 WI C V V
2 L R1R
1V
2I1I
2M
n ds222 1
1 n ds1
(1 V )(W / L)I I
(W / L) (1 V )+ λ
=+ λ
21 n ds2 ds1
1
(W / L)I (1 (V V ))
(W / L)≈ + λ −
The simple current source is supply dependent. If the power supply would change considerably, for example, from 5V to 12V, then the simple current source should not be used.
Ki 10
CMOS Widlar Current Source
The self-biased CMOS Widlar current source appears very often in textbooks. The version with a startup circuit is shown below.
1R
1M2M
1I 2I
ddV
1:41V
2V
3V
6M
5M
4M3M
7M
startup
5
wideW
6
longL
( )⎛ ⎞= μ − −⎜ ⎟⎝ ⎠
2
1 n ox gs1 1 1 tn1
1 WI C V I R V
2 L
( )⎛ ⎞= μ −⎜ ⎟⎝ ⎠
2
2 n ox gs2 tn2
1 WI C V V
2 L
1iv 1ov = = ⇒ =−
1m1 m1 1
1 tn 1
2I 2g g R 2V V R
For (W/L)1 = 4(W/L)2 gives
A positive loop exists:− − −
= = =+
1o m1 m2 m4V1
1i m1 1 m3
v g / g g 2Tv 1 g R g 3
Ki 11
CMOS Peaking Current Source (1)
1R
1M 2M
1I 2I
ddV
bR
1 : 4
1V
2V
( ) −⎛ ⎞= μ − =⎜ ⎟⎝ ⎠
2 dd 11 n ox 1 tn
1 b
V V1 WI C V V2 L R
( )⎛ ⎞= μ − −⎜ ⎟⎝ ⎠
22 n ox 1 1 1 tn
2
1 WI C V I R V
2 L
−= ⇒ = 1 tn2
1 11
V VdI0 I R
dI 2
For I2 = I1 , set (W/L)2 = 4(W/L)1 .
The original peaking current source was designed in bipolar processes. [Gray 01] gives a CMOS sub-threshold version, while we suggest operating all transistors in the active region [Lo 09]. This current source does not need a start-up circuit.
3M3V
2V
Ki 12
bRm31 / g
m1 1g v
1R
ddv
1v 3v
2v
m2 2g v
−= =
+2 m1 1
dd m1 b
v 1 g R0
v 1 g R
− −= =
+dd 3 m2 m1 1
dd m3 m1 b
v v g 1 g R0
v g 1 g R
The peaking current source has very good power supply rejection.
From previous analysis,
−= = ⇒ =1 tn
1 m1 11 m1
V V 1R g R 1
2I g
Small signal analysis gives
That means the currents generated by current mirroring using V2 and (Vdd –V3 ) has a very low dependence on the supply voltage.
CMOS Peaking Current Source (2)
Ki 13
Assuming a 0.25µ CMOS process:µn Cox = 50µA/V2 Vtn = 0.8V λn Ln = 0.05µm/Vµp Cox = 25µA/V2 |Vtp | = 0.8V |λp |Lp = 0.05µm/V
Example: Vdd ranges from 4V to 6V, need I2 = 40μA.
Set ∂I2 /∂I1 = 0 at Vdd = 5V with I1 (5V) = 40μA. (W/L)2 = 40 gives Vgs2 -Vtn = 200mV, and 1mV change in Vtn causes 1% change in I2 (1% rule):
Vtn = 0.799V ⇒
I2 = 40.4μAVtn = 0.800V ⇒
I2 = 40.0μAVtn = 0.801V ⇒
I2 = 39.6μA
Vdd I1 I24V 30μA 38.7μA5V 40μA 40.0μA6V 50μA 38.9μA
μ50 A
μ40 A
μ30 A
4V
1I
ddV
1I
2I
5V 6V
CMOS Peaking Current Source (3)
Ki 14
1R
1M 2M
1I 2I
ddV
1 : 4
1V
1V
b2V
2V
Self-Biased Peaking Current Source
4M3M
b1V
6M
5M7M
startup
5
wideW
6
longL
A current mirror (M3 , M4 ) can be used to replace the large Rb to reduce silicon area. The peaking current source becomes self-biased and needs a startup circuit (may not be favorable).
Ki 15
RT CT Oscillator (1)
HV
LV
HV
=ch ref TI V /R
TCV
TCTR
refV
LVck
dchI
hystereticcomparator
ddV
QEA
CMP
CMP
The RT CT oscillator generates a ramp that synchronized with the clock, which fits the requirement of a PWM switching converter.
ramp mV
dchM = sT 1 / f
R
S
currentgenerator
Ki 16
RT CT Oscillator (2)
The charging current Ich is well-controlled by a bandgap derived voltage Vref and an accurate 1% (external) resistor RT (1% rule).
Ich charges an accurate 1% (external) capacitor CT slowly from the lower bound VL to the upper bound VH . The ramp excursion is Vm .
The hysteretic comparator trips when VCT > VH , and ck = 1.
When ck = 1, the NMOS Mdch is turned on, and discharges CT with a large current Idch that is around 10 times of Ich .
When VCT < VL , the comparator trips again, and ck = 0.
Idch is not well-controlled, but the accuracy of the oscillation (switching) frequency fs is well-controlled because it is dominated by the accurate Ich .
Ki 17
Current Regulator / Voltage Mirror
The error amplifier for generating the charging current can be realized using a differential amplifier stage.
refV
refch
T
VI
R=
TR
ddV
ref
T
VR
bI
Ki 18
Comparators
V+
bV
−V
ddV
oV −V V+ oV
ddV
bV
Two-stage comparatorOne-stage comparator
Higher gainRise time longer than fall timeA second V- input may be added to both comparators
Low gainEqual rise and fall timesAdd inverters to increase gain
−2V
V+
−1V−2V
oV
Ki 19
V+
cC zR
oV
2-Stage Simple Operational Amplifier
supplyindependent bias
1M
7M
6M
5M
4M3M
2M
2-stage op amp
LC
−V
bM
bR
ddV
b2R
bI
The op amp of the PWM compensator should be ground-sensing (common mode voltage close to ground).
Ki 20
Frequency Response of Op Amp
+=
+ +
= ×
=−
=
=
ω =
= ω φ =
dc 1op
1 2
dc m1 ds2 ds4 m6 ds6 ds7
1c z m6
1c m1 ds2 ds4 ds6 ds7
m62
L
m1t
co
2 t m
A (1 s / z )A (s)
(1 s /p )(1 s /p )
where
A g (r || r ) g (r || r )1z
C (R 1 /g )1p
C g (r || r )(r || r )g
pCgC
choose p 3 for 70
dcA 1p
1z2p
tω ω
ω
o90−
o180−
|A|
/A
mφ
The op amp gain is Aop (s) (but the EA (compensator) gain is A(s)):
Ki 21
Current Mirror Amplifier
V+
bpV
−V
ddV
oV
bR
LC
1M 2M
6M5M 4M3M
The simple 2-stage op-amp can be modified to be a 1-stage current mirror amplifier.
7M 8M=dc m1 ds6 ds8A g (r || r )
=1L ds6 ds8
1pC (r || r )
ω = m1t
L
gC
=+
dcop
1
AA (s)
(1 s / p )
self-biasedWidlar current source
0M
4 :1
Ki 22
V+
oV
Folded Cascode Op Amp (1)
supplyindependent bias
1M
7M
6M5M
4M3M
2M
folded cascodegain stage
LC
−V
b5MbR
ddV
b2R
bI
To achieve high DC gain, a folded cascode op amp could be used (assume μn =2μp ).
b2V
b1V
b3V
b4V
b1M
b4M
b3M
b2M
0M 10M9M
8M
b0M
b6M
μ10 Aμ10 Aμ20 A
μ20 Aμ20 A1 : 4 : 4 :1
8 : 8: 2
oR
Ki 23
Folded Cascode Op Amp (2)
The gain function of the folded cascode op amp is:
where
=+
dcop
1
AA (s)
(1 s / p )
=dc m1 oA g R
=1L o
1pC R
=o m6 ds6 ds4 ds2 m8 ds8 ds10R [g r (r || r )]|| [g r r ]
ω = m1t
L
gC
with
and
Ki 24
cCzRoV
2-Stage Folded Cascode Op Amp (1)
supplyindependent bias
folded cascodegain stage
LC
To achieve high DC gain, a folded cascode op amp followed by an inverting stage could be used (assume μn =2μp ).
12M
11M
invertinggain stage
μ20 A
μ20 A
o1RV+1M
7M
6M5M
4M3M
2M−V
b5MbR
ddV
b2R
bIb2V
b1V
b3V
b4V
b1M
b4M
b3M
b2M
0M10M9M
8M
b0M
b6M
μ10 Aμ10 Aμ20 A
μ20 Aμ20 A1 : 4 : 4 :1
8 : 8: 2
Ki 25
2-Stage Folded Cascode Op Amp (2)
The gain function of the folded cascode op amp is:
where
+=
+ +dc 1
op1 2
A (1 s / z )A (s)
(1 s /p )(1 s /p )
= ×dc m1 o1 m11 ds11 ds12A g R g (r || r )
=−
=
=
ω =
1c z m11
1c m1 o1 ds11 ds12
m112
L
m1t
c
1zC (R 1 / g )
1pC g R (r || r )g
pCgC
=o1 m6 ds6 ds4 ds2 m8 ds8 ds10R [g r (r || r )]|| [g r r ]
Ki 26
R
ddV
bI
V-to-I Conversion for Compensation Ramp
To add a compensation ramp to the inductor current, a V-to-I (V2I) converter could be used. Two versions are shown below.
R
inVR
inV
1V
2V
inVR
inVR
inV=gsn
gsp
(if V| V |)
ddV
Ki 27
Power Transistor Design
Switch voltage of an ideal switch is 0V when conducting⇒
MOS switch should have small Vds when conducting⇒
MOS switch in triode (linear) region when conducting⇒
For an NMOS power switch MN ,
2d n ox dd tn ds ds
N
dsN
d n ox N dd tn
W 1I C (V V )V VL 2
V 1RI C (W /L) (V V )
⎛ ⎞ ⎡ ⎤= μ − −⎜ ⎟ ⎢ ⎥⎝ ⎠ ⎣ ⎦
= =μ −
1% rule: conduction loss of RN is 1% of the load RL
If RL is 10Ω, 1% is 100mΩ. If duty ratio is 0.5, then MN conducts half of the time, and RN can be 200mΩ.
Ki 28
Buffer Design
To drive a power switch effectively starting from control logic blocks, buffers (digital inverters) have to be used.
Minimum delay gives a ratio of e (=2.718), but too many stages are then needed:- large transistors give large switching loss;- large buffers give large shoot-through (short-circuit) loss;- last stage buffer should have a ratio of 25 to 40.
1 : 4 : 40 : 600 : 30000
Ki 29
Eliminate Short-Circuit Loss (1)
nV
pV
For a large inverter, insert a starving resistor Rstarve to limit shoot- through (short-circuit) current, but the most important observation is at Vp and Vn . For input changes from ‘0’ to ‘1’, Vn drops immediately, but Vp drops with a delay due to Rstarve .
nV
pV
starveRstarveR
Ki 30
Eliminate Short-Circuit Loss (2)
Short circuit loss of the last stage (largest) buffer could be eliminated if driven by a buffer with starving resistor.
40 : 600 40 : 600
Starving resistor can be replaced by transistors operating in the linear region. A rule of the thumb design is 1/10 of the inverter transistors.
=n(W /L)
4
Ki 31
Power PMOS or Power NMOS?
The PMOS switch may be replaced by an NMOS switch driven from an on-chip step-up charge pump [Sze 08].
PSM
Example: Vdd = 1.2V, and needs a 50mΩ
switch (RPS = RNS = 50mΩ)
P-switch: (W/L)PS = 1/(μp Cox ×(Vdd -|Vtp |)×RPS )= 500,000μ/0.25μ
N-switch: (W/L)NS = 1/(μn Cox ×(3.8-Vtn )×RNS )= 33,300μ/0.25μ
Charge pump (1pF caps) + auxiliary circuits is about the size of MNS⇒
P scheme : N scheme = 7.5 : 1
NSM3.8V
5Xchargepump level
shifter
=ddV 1.2V
+−
PSVNSV
refV⇒
Ki 32
Simple P-Current Sensor
toPWMCMP
s1M s2M
s3M s4MsbM
PGnd
AGnd
iSW1M
1
PM
PsM
20000 /2
20 /2
SW2M
Q
Q
s5M
ddPV
fR
fi RN
1A
1 Aμ
1mA
0.999mA
NM
L
CLR
oV
:1000
On-chip current sensing can be achieved by a small sensing transistor Mps that is forced to have the same Vd , Vg and Vs as the power transistor MP using a matched current source [Ki 98].
Ki 33
Symmetrical Matching of CMOS Transistors
When a pair of transistors M1 and M2 of the same type are matched, their W/L ratios are the same, i.e., (W/L)1 = (W/L)2 , and in most cases, W1 =W2 and L1 =L2 . However, their drain currents may not be the same due to channel length modulation.
If in addition to having the same W/L ratio, M1 and M2 are forced (by an additional circuit) to have essentially the same drain, gate and source voltages, then they are called symmetrically matched (SM) [Lam 04b, Lam 07].
The simple current sensor uses the 4T cell to force Mps to be symmetrically matched with MP . However, the accuracy is limited by the 4T cell that itself is not symmetrically matched.
Ki 34
Symmetrically Matched N-Current Sensor
3M 4M
1M 2M
8M
7M5M
9M 6M
2V
1VxV yV
NMNsM
3V4V
ddV
senseI
Q
1000 : 1
i
M : 1 : 1 : M
Replace 4T cell by 8T cell with internal cross-biasing such that paired transistors (M1 , M2 ), (M3 , M4 ), (M5 , M6 ), (M7 , M8 ) are symmetrically matched, forcing Vy =Vx . Start-up circuit is needed [Lam04b, Lam 07].
Ki 35
Concept of Active Diode
ddV
L
CLR
PM
NM(active diode)
oVxV (A) (K)
A K
A K
The lossy passive diode may be replaced by an active diode, and eliminate the need to control two switches for synchronous rectification:
An active diode is simply a power transistor controlled by a (current) comparator:
CMP
CMP
Ki 36
Active Diode Implementation (1)
LV (A) HV (K)
HV
One implementation of the active diode is discussed in [Man 06], and is used in a DCM boost converter. The capacitor C is added to improve transient response.
C
Ki 37
Active Diode Implementation (2)
LV HVHV
HV
LV HV
bV
1V maxV2V
Active diodes can be used as maximum voltage selector for biasing substrates of PMOS power switches in a multiple-output converter.
Another active diode is used in a regulated charge pump [Lam 06].
Ki 38
Power Management Peripherals
For a low-voltage system, e.g., Vdd =5V, there is usually only one trimmed voltage reference.
For a system with Vdd = 15V, there are usually two voltage references, one trimmed for accuracy, and a second one untrimmed and could work at very low voltage for start-up, UVLO (under voltage lockout) and OVP (over voltage protection).
untrimBGR
trimmedBGR
15V
BG(untrim)V
5V
+_
functionalblocks
REFV
UVLO OVP
linear regulator
Ki 39
UVLO Comparator
ddV
LV
inVHV
bpV
oLVoHV
Ki 40
Soft Start Circuit
ddV
SSV
SSC
1R
bnV
2M1M
Consider the buck converter. When Vo =0, EA drives Va to Vdd , and D=1. SW1 is always on, causing large in-rush current. The soft start circuit uses a very tiny current to charge a large CSS , such that VSS rises very slowly, limiting the duty ratio.
ramp
aV
SSVsoftstart
CMP
S Q
Q
ck
R
M2 is in sub-threshold region, sourcing a current in the range of nA.
Ki 41
I/O Connections
I / O I / O
Schottkydiodes
largediodes
diode- connected transistors
Different types of ESD (electrostatic discharge) diodes.
ddV
GND
Ki 42
Continual Fraction Expansion
Consider the continual fraction expansion of π:
π
= 3.14159265359
≈ +
≈ ++
≈ ++ +
13
7.062513313
7 (1 /15.99659)13
7 (1 / [15 (1 /1.0034)])
Now,
+
++
++
137
137 (1 /15)
137 (1 /16)
=227
=333106
=355113
= 3.14285714286
= 3.14159292035
= 3.14150943396
Ki 43
Resistor String using Unit Resistors
In an analog circuit array (compared with a digital gate array), all components are fixed except for the metal layers for interconnection. Resistors are thus formed using unit resistors.
For example, if the unit resistor is 9.5kΩ
and R1 =10.8kΩ
is needed. Use continual fraction expansion:
= =
= +
= ++
= ++ +
1
unit
R 10.81.136842
R 9.51
17.3077
1 17 (1 /3.25)
1 1
7 (1 /[3 (1 / 4)])
Ki 44
Parallel/Series Connection of Resistors
For Runit = 9.5kΩ[1+(1/7)]×Runit = 1.14286×Runit = 10.86kΩ
8 Runit[1+(1/[7+(1/3)])]×Runit = 1.13636×Runit = 10.8kΩ
11 Runit[1+(1/[7+(1/[3+(1/4)])])]×Runit = 1.13684×Runit = 10.8kΩ
15 Runit
Use 11 Runit (instead of 15 Runit ) is accurate enough and save components. The structure is:
= + ⇒+
1
unit
R 11
1R 73
unitR
1R
Ki 45
IC References: Books/Theses
Books / Book Chapters / Thesis:[Gilbert 96] B. Gilbert, "Monolithic voltage and current references: Theme and Variations," in
[Huijsing 96], 1996.
[Gray 01] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Ed., Wiley, 2001.
[Huijsing 96] J. H. Huijsing, R. van de Plassche and W. Sansen, Analog Circuit Design, Kulwer, 1996.
[Johns 97] D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
[Lam 08] Y. H. Lam, Differential Common-Gate Techniques for High Performance Power Management Integrated Circuits, PhD Thesis, HKUST, Jan. 14, 2008.
[Meijer 96] G. Meijer, "Concepts for bandgap references and voltage measurement systems," in [Huijsing 96], 1996.
[Razavi 01] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
[R-Mora 02] G. A. Rincon-Mora, Voltage References, IEEE Press, 2002.
[Sansen 06] W. Sansen, Analog Design Essentials, Springer, 2006.
[Sze 81] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., Wiley, 1981.
Ki 46
IC References: Current Sources
Current Sources and Circuits:[Frederiksen 72] T. M. Frederiksen, "Constant current source," US Patent 3,659,121, Apr. 25,
1972.
[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and applications therefor," US Patent 7,215,187, May 8, 2007.
[Lo 09] A. Lo, W. H. Ki and W. H. Mow, “A 20MHz switched-current sample-and-hold circuit for current mode analog iterative decoders,” IEEE Int’l Symp. on IC, pp. 283-286, 2009.
[Kessel 71] T. van Kessel and R. van der Plaasche, "Integrated linear basic circuits," Philips Tech. Rev., pp.1-12, 1971.
[Smith 68] K. C. Smith and A. Sedra, "The current conveyor: a new circuit building block," Proc. of the IEEE., pp.1368-1369, 1968.
[Widlar 65] R. J. Widlar, "Some circuit design techniques for linear integrated circuits," IEEE Trans. Circ. Theory, pp.586-590, 1965.
Ki 47
On-Chip Current Sensors:[Ki 98] W. H. Ki, "Current sensing technique using MOS transistors scaling with matched
bipolar current sources," U.S. Patent 5,757,174, May 26, 1998.
[Lam 04a] H. Lam, W. H. Ki and D. Ma, "Loop gain analysis and development of high-speed high-accuracy current sensors for switching converters," IEEE Int'l. Symp. on Circ. & Sys., pp.V.828–V.831, May 2004.
[Lam 04b] H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control switching converter with self-biased current sensor," IEEE Int'l Midwest Symp. on Circ. & Sys., pp.II.305–II.308, July 2004.
[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and applications therefor," US Patent 7,215,187, May 8, 2007.
IC References: Current Sensors and Active Diodes
Active Diodes:[Lam 06] Y. H. Lam, W. H. Ki and C. Y. Tsui, "An integrated 1.8V to 3.3V regulated voltage
doubler using active diodes and dual-loop voltage follower for switch-capacitive load," VLSI Symp. on Tech. & Circ., pp.104-105, June 2006.
[Man 06] T. Y. Man, P. Mok and M. Chan, "A CMOS-control rectifier for discontinuous- conduction mode switching DC-DC converters," IEEE Int'l Solid-State Circ. Conf., pp.358-359, Jan. 2006.
Ki 48
Blank
IC Design ofPower Management Circuits (III)
Wing-Hung KiIntegrated Power Electronics Laboratory
ECE Dept., HKUSTClear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated CircuitsSingapore, Dec. 14, 2009
Ki 2
Part III
Switching Converters:Stability and Compensation
Ki 3
Stability and Compensation
Nyquist criteriaSystem loop gainPhase margin vs transient responseType I, II, III compensatorsCompensation for voltage mode controlCompensation for current mode control
Content
Ki 4
Consider the feedback system:
Feedback Systems
F(s)in
G(s)
out
Note that F(s) and G(s) are ratios of polynomials in s, that is,
= F
F
n (s)F(s)
d (s)= G
G
n (s)G(s)
d (s)
The closed loop transfer function is
= = =+ +
out F(s) F(s)H(s)
in 1 F(s)G(s) 1 T(s)
and the loop gain is
= =n(s)
T(s) F(s)G(s)d(s)
Ki 5
Stability Criteria
Local stability: all poles of T(s) (= all roots of d(s)) are in LHP
System stability:∗
all poles of H(s) are in LHP⇒
all zeros of (1+T(s)) are in LHP⇒
all roots of (n(s)+d(s)) are in LHP
If all functional blocks satisfy local stability, the Nyquist criterion for system stability is:
∗
Nyquist plot of 1+T(s) does not encircle (0,0)⇒
Nyquist plot of T(s) does not encircle (-1,0)
If all functional blocks satisfies local stability, the Bode plot criteria for system stability is:
phase margin φm >0o and gain margin GM>0dB
Ki 6
1st Order Loop Gain Function
=+
o
1
TT(s)
s1p
+ω = 0ω = +∞
1−1
oTRe
Im
unit circle
oT / 2
o-45
−∞
0
−0
ωUGF
oT
ωUGF
| T |
/ A
ω
ω
− o90
1p
− o45
1p
Nyquist Plot
Bode Plots
stable
Ki 7
2nd Order Loop Gain Function
=⎛ ⎞⎛ ⎞
+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
o
1 2
TT(s)
s s1 1p p
−1 oTRe
Im
0
ωUGF
oT
ωUGF
| T |
/ A
ω
ω
− o90
2p
− o180φm
1p
φm
Nyquist Plot
Bode Plots
stable
Ki 8
3rd Order Loop Gain Function
=⎛ ⎞⎛ ⎞ ⎛ ⎞
+ + +⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠
o
1 2 3
TT(s)
s s s1 1 1p p p
−1 oTRe
Im
0
ωUGF
oT
ωUGF
| T |
/ A
ω
ω
− o90
2p
− o180φ <m 0
1p
φm
Nyquist Plot
Bode Plots
unstable(encirclement
of -1)
3p
− o270
Ki 9
Observations on Loop Gain Function
• 1st order systems are unconditional stable.
• 2nd order systems are stable, but a high damping factor would cause large overshoot and excessive ringing before settling to the steady state.
• For 3rd order systems, if the 3rd pole p3 is less than 10X of the unity gain frequency ωUGF , the system is unstable.
Hence, for a stable system, the loop gain function could be approximated by a 2nd order loop gain function with the 2nd pole p2 usually larger than ωUGF to achieve small overshoot.
Ki 10
Loop Gain Function and Transient Response
The transient response of a feedback system is given by
where L-1(⋅) is the inverse Laplace transform of (⋅).
The exact transient response is affected by F(s), however, if only T(s) is considered, we may consider the modified feedback system:
− − ⎛ ⎞⎛ ⎞= × ×⎜ ⎟ ⎜ ⎟+⎝ ⎠ ⎝ ⎠1 1
o1 1 F(s)v (s) H(s)s s 1 T(s)
L = L
F(s)in
G(s)
out T(s)in '
1
out '
=+F(s)
H(s)1 T(s)
=+T(s)
H'(s)1 T(s)
Ki 11
For a loop gain function approximated by a 2-pole function:
= ≈⎛ ⎞⎛ ⎞ ⎛ ⎞
+ + +⎜ ⎟⎜ ⎟ ⎜ ⎟ω⎝ ⎠⎝ ⎠ ⎝ ⎠
o
1 2 UGF 2
T 1T(s)
s s s s1 1 1p p p
ωUGF
The closed loop function (with unity gain feedback) is
2p
− o90
− o180φm
= =+
+ +ω ω
2
UGF UGF 2
T(s) 1H'(s)
1 T(s) s s1p
| T |
/ T
=+ +
ω ω
2
2o o
1H'(s)
1 s s1Q
Write H'(s) in standard 2nd order form:
ω = ωo UGF 2p
ω= UGF
2
Qp
Compensator Considerations
1p
Ki 12
Relationship between p2 /ωUGF and φm
ω2
UGF
p ω=UGF
2
1p k
π−
−24Q 1e−φω
1 2m
UGF
p=tan
k Q overshoot phase margin
1
≈2.73 3
=3 1.73
1 0.163 o45
o70
o60
o30=1 / 3 0.577
≈0.605 0.6 0.01
0.76 0.064
1.316 0.275
Note that φm =60o gives an overshoot of 6.4%, and the 1% settling time (tset ) would be very long. By setting p2 =3ωUGF , then φm =70o, and the overshoot is only 1%.
Ki 13
Type I Compensator (0Z1P)
1R1C
inV
= − = −out
in 1 1
V 1A(s)
V sC R
outVrefV
ω =UGF1 1
1C R
− o180
− o90
| A |
/ A
The simplest Type I compensator is an integrator with ωUGF = 1/C1 R1.
Assume Aop (s) is first order with ωt >> 1/C1 R1 :
= ≈+ ω ω
opop
1 t
A 1A (s)1 s / s /
⇒ ≈+ ω1 1 t
1A(s)sC R (1 s / )
ωt
ω
ω
Ki 14
Type I compensator can be implemented using transconductance amplifier (OTA). OTA has a very high output resistance ro and cannot drive resistive loads.
mg
or oC
inVoutV
refV
= − = −+
out m o
in o o
V g rA(s)
V 1 sC r
Type I Compensator (0Z1P)
m og r o o1 / C r
ω = mUGF
o
gC
| A |
/ A
Using OTA may save one IC pin.
ω
ω
− o90
Ki 15
1R1C
inVoutV
refV
+= −
+ +out 2 2
in 1 2 1 1 2 2
V 1 sC RV s(C C )R [1 s(C || C )R ]
2R2C
+≈ <<
+2 2
1 22 1 1 2
(1 sC R )A(s) (C C )
sC R (1 sC R )
Type II Compensator (1Z2P)
1 2
1C R2 2
1C R
2 11 /C R
ω =UGF
1 11 / C R
| A |
/ A
o90 phaseboosting
Type II compensator consists of a pole-zero pair with ωz <ωp , and a maximum phase boosting of 90o is possible.
ω
ω
− o90
Ki 16
mg
or
2C
inVoutV
refV2R
+= − = −
+ +out m o 2 2
in 2 o 2
V g r (1 sC R )A(s)
V 1 sC (r R )
+≈
+m o 2 2
2 o
g r (1 sC R )A(s)
(1 sC r )
Type II Compensator (1Z1P)
m og r
2 2
1C R
2 o
1C r
Type II compensator can also be implemented using OTA.
ω = mUGF
2
gC
| A |
/ A
ω
ω
− o90
Ki 17
1R
1C
inVoutV
refV
+ + += −
+ + +out 2 2 3 1 3
in 1 2 1 1 2 2 3 3
V (1 sC R )[1 sC (R R )]V s(C C )R (1 sC || C R )(1 sC R )
2R2C
3R3C
Type III Compensator (2Z3P)
+ +≈
+ +2 2 3 1
2 1 1 2 3 3
1 2 1 3
(1 sC R )(1 sC R )A(s)
sC R (1 sC R )(1 sC R )
(C <<C , R >>R )
1 2
1C R
2 2
1C R
2 1
1C R
3 3
1C R
o180boosting
− o90
| A |
/ A
ω
=UGF
1 3
1C R
3 1
1C R
Type III compensator consists of two pole-zero pairs, and phase boosting of 180o is possible to compensate for complex poles.
ω
ω
+ o90
Ki 18
PWM Voltage Mode Control
S
RQ
Q
refVA(s)
EACMP
gV
oV
ckramp
L
CLR
1R
2R
obVav
av
PM
NM
A regulated switching converter consists of the power stage and the feedback circuit.
For a buck converter, if an on-chip charge pump is not available, then the NMOS power switch is replaced by a PMOS power switch.
avramp
ck
Q
Q
Ki 19
Loop Gains of Voltage Mode CCM Converters
The system loop gain is T(s) = A(s)×H(s), where A(s) is the frequency response of the EA (compensator). Loop gains of voltage mode PWM CCM converters with trailing-edge modulation are compiled. Parasitic resistances except ESR are excluded [Ki 98].
+= ×
+ +
o esr
2m
L
bV 1 sCRT(s) A(s) .
sLDV 1 s LCR
Buck:
Boost:
Buck-boost:
−= ×
+ +
2o L
2m
2 2L
bV [1 sL / (D ' R )]T(s) A(s) .
D ' V sL s LC1D' R D'
−= ×
+ +
2o L
2m
2 2L
b | V | [1 sDL / (D ' R )]T(s) A(s) .
DD' V sL s LC1D' R D '
Ki 20
Voltage Mode Compensation (1)
Example: Consider a buck converter with the following parameters:
Vdd =4.2V, Vo =1.8V (D=0.429), Vm =0.5V, b=0.667L=2μH, C=3.3μF, RL =1.8Ω
(Io =1A), Resr =100mΩ, fs =1MHz
The system loop gain is given by
× + × × += ⋅ =
+ + + +ω ω
2 2
2 2o o
5.6 [1 s /(3M)] A(s) 5.6 [1 s /(3M)]T(s) A(s)
1 s s 1 s s1 12.3 390k Q(390k)
The system loop gain consists of a pair of complex poles, and one strategy is to use dominant pole compensation.
For a buck converter, the complex pole frequency ωo /2π
is 10 to 30 times lower than the switching frequency fs .
Ki 21
Voltage Mode Compensation (2)
60
40
20
0dB
=+1330
A(s)1 s /10
⇒5.6 15dB390k
3M1M 10M100k10k1k10010
80
0.1 1
− o90
− o180
=1330 62.5dB
− o270
/H(s)/ A(s)
o0 ω
ω
× +=
+ +2
2
5.6 (1 s /3M)H(s)
1 s s12.3 390k (390k)
Dominant pole compensation
Ki 22
Voltage Mode Compensation (3)
60
40
20
0dB
× +=
⎛ ⎞+ + +⎜ ⎟
⎝ ⎠
2
2
7500 (1 s /3M)T(s)
1 s s(1 s /10) 12.3 390k 390k
390k
3M
1M 10M100k10k1k10010
80
0.1 1
− o90
− o180
=7500 77.5dB
− o270
/H(s)
/ T(s)
φ =mo90
ω=
UGF75k
o0 ω
ω
Ki 23
Stability inferred from Line and Load Transients
Measuring loop gain could be difficult, and for some circuits, and especially integrated circuits, due to loading effect and that loop- breaking points may not be accessible, stability is inferred by simulating or measuring the line transient and/or load transient.
If the circuit is stable and has adequate phase margin, line and load transients will show first order responses.
If the circuit is stable but has a phase margin less than 70o, line and load transients will show minor ringing.
If the circuit is unstable, line and load transient will show serious ringing/oscillation.
Ki 24
Current Mode PWM with Compensation Ramp
In practice, the output of EA (Va ) should not be tempered, and a compensation ramp of +mc is added to m1 instead.
S
RQ
Q
refVA(s)
EACMP
ddV
oV
ck
L
CLR
1R
2R
obVav
i
i /N
fNR
PM
NM
V2I
ramp from OSCav
DT
1 c f(m m )R+ 2 c f(m m )R− −
bvbv
compensationramp
ddV
Ki 25
Loop Gain of Current Mode Buck Converter (1)
The loop gain of a current-mode CCM buck converter with trailing- edge modulation is shown below. Others can be found in [Ki 98].
Buck:( )× +
= ×⎛ ⎞ ⎛ ⎞−
+ + + +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
esrf 1
2 1
L 1 1 L
1 1b 1 sCRCR n D' T
T(s) A(s)(n D ' D)T1 1 1 1 1s s
CR n D' T n D' T C R L
The two poles are in general real.
−= + > ⇒ >c 2
1 c 11
m m 2 Dwith n 1 , m nm 2 2D'
<L2Land R
D ' T
Ki 26
Loop Gain of Current Mode Buck Converter (2)
If the poles are real and far apart, the denominator could be simplified.
Buck: + ω= ×
⎛ ⎞⎛ ⎞+ +⎜ ⎟⎜ ⎟ω ω⎝ ⎠⎝ ⎠
L a z
f
a t1
R ||R 1 s /T(s) A(s) b. .
R s s1 1
= = +−
ca 1
1 1
mLR n 1
(n D ' D)T m
For two real poles that are farther apart, pole-zero compensation could be used to extend the bandwidth.
ω = ω = ω =z a t1c L a 1
1 1 1 CR C(R ||R ) n D ' T
Ki 27
Example: Consider a current mode buck converter with the same parameters as those of the voltage mode converter for comparison.
Vdd = 4.2V, Vo = 1.8V (D = 0.429), b = 0.667, fs = 1MHz, Rf = 1ΩL = 2μH, C = 3.3μF, RL = 1.8Ω
(Io =1A), Resr = 100mΩ, mc = m2
+= ×
⎛ ⎞⎛ ⎞+ +⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠
0.8(1 s /3M)T(s) A(s)s s1 1
290k 880k
Current Mode Compensation (1)
⇒
n1 =1.75, 1/n1 D’T ≈
1/1μ
The system loop gain is given by
Ki 28
We may assume the poles are far apart and use the simplified equation, and we have
+= ×
⎛ ⎞⎛ ⎞+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
0.8(1 s /3M)T(s) A(s)s s1 1
250k 1M
Current Mode Compensation (2)
n1 =1.75, Ra =3.5Ω, ωz =3M rad/s, ωa =250k rad/s, ωt1 =1M rad/s
The system loop gain is then given by
Instead of a pair of complex poles as in voltage mode control, two separate poles are obtained, and both dominant-pole compensation and pole-zero compensation could be employed.
Ki 29
Current Mode Compensation (3)
60
40
20
0dB
=+10000
A(s)(1 s /10)
⇒ −0.8 2dB250k
1M 10M100k
10k1k10010
H(s)
1
− o90
− o180
/H(s)
o0 ω
ω
−20
1M
3M
80Dominant pole compensation
Ki 30
Current Mode Compensation (4)
60
40
20
0dB250k
1M 10M100k10k1k100101
− o90
− o180/ T(s)
o0 ω
ω
−20
1M
80
ω=
UGF80k
⇒8000 78dB
φ=
mo70
× +=
+ + +8000 (1 s /3M)
T(s)(1 s /10)(1 s /250k)(1 s /1M)
Ki 31
Pole-zero cancellation
− o90/H(s)
o0 ω
/ A(s)
1M 10M100k10k1k100101ω
60
40
20
0dB
250k 3M
H(s)−20
+=
+(1 s /250k)
A(s)(s /375k)(1 s /3M)
375k
Current Mode Compensation (5)
− o180
Ki 32
Bandwidth increased by 4 times to 300k rad/s
1M 10M100k10k1k100101
− o90
− o180
o0 ω
ω
60
=+
1T(s)
(s / 300k)(1 s /1M)40
20
0dBω =UGF 300k
φ=
mo70
/ T(s)
Current Mode Compensation (6)
Ki 33
References: Switching Converter Compensation
[Brown 01] M. Brown, Power Supply Cookbook, EDN, 2001.
[Ki 98] W. H. Ki, "Signal flow graph in loop gain analysis of DC-DC PWM CCM switching converters," IEEE Trans. on Circ. and Syst. 1, pp.644-655, June 1998.
[Ma 03a] D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode", IEEE J. of Solid-State Circ., pp.89-100, Jan. 2003.
[Ma 03b] D. Ma, W. H. Ki and C. Y. Tsui, "A pseudo-CCM / DCM SIMO switching converter with freewheel switching," IEEE J. of Solid-State Circ., pp.1007- 1014, June 2003.
Ki 34
SUPPLEMENTS
Ki 35
Voltage Mode Converters: Loop Gain Function
In discussing fast-transient converters, one important parameter is the loop bandwidth.
The loop gain function of the buck converter with voltage mode control operating in CCM ignoring ESR is given by [Ki 98]
T(s) o
2m
L
bV 1A(s) .sLDV 1 s LCR
= ×+ +
The resonance frequency ωo and the pole-Q are
oω1LC
= Q CRL
=
The converter enters DCM at
L(BCM)R 2LD'T
= ⇒ BCMQo
2 1D ' T
=ω
Ki 36
For voltage mode buck, the ripple voltage is given by
If ΔVo /Vo =0.01 and D=0.5, then the complex pole pair is at
Δ o
o
VV 2
s
D ' 18 LCf
=
To have adequate gain margin GM, say, 6dB, the unity gain bandwidth fUGF has to be reduced by 10×2=20 times:
oω s0.4f=
Voltage Mode Converters: Bandwidth Limitation
andBCMQ
o
2 1 10D ' T
= =ω
ofo sf
2 16ω
= ≈π
⇒
If fs =1MHz, then fUGF is at around fs /320 = 3.125kHz.
UGFf s s1 f f20 16 320
= × =
Ki 37
VM Buck: Loop Gain Function with Rδ
The unity gain frequency fUGF of fs /320 is too low. Fortunately (or unfortunately), the converter inevitably has parasitic resistors such as RESR , Rℓ
(inductor series resistor), Rs (switch resistance) and Rd (diode resistance), and the loop gain function is [Ki 98]
T(s)
δ
≈ ×⎛ ⎞
+ + +⎜ ⎟⎝ ⎠
o
2m
L
bV 1A(s) .DV L1 s CR s LC
Rwhere
Rδ ESR s dR R DR D'R≈ + + +
This Rδ
is at least 200mΩ, thus reducing QBCM to around 3. With GM to be 6dB, fUGF is reduced by 3×2=6 times, and
If fs =1MHz, then fUGF is at around fs /100 = 10kHz.
UGFf s s1 f f6 16 100
= × ≈
Ki 38
ωsωUGF
ω
ω
− o90
− o270
− o180
o0
|T|
/T
0dB
20dB
40dB
60dB
ωo
φm
− o45 / dec
o-180 ×Q/dec
=GM 6dB
oT
VM Buck: Dominant Pole Compensation
-20dB/dec
-60dB/dec
100X
ωp (dominant pole)
Ki 39
Current Mode Converters: Loop Gain Function
The loop gain function of the buck converter with current mode control operating in CCM ignoring ESR is given by [Ki 98]
T(s)
In general, the two poles are real, as discussed next.
−= + > ⇒ >c 2
1 c 11
m m 2 Dn 1 , m nm 2 2D'
f 1
2 1
L 1 1 L
1 1A(s)bCR n D' T
(n D ' D)T1 1 1 1 1s sCR n D' T n D' T C R L
×=
⎛ ⎞ ⎛ ⎞−+ + + +⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠
L(BCM)R 2LD'T
=
with
and
Ki 40
To compute the upper limit of fUGF w.r.t. fs , we simplify the current mode case as follows. Let D=0.5 and choose n1 =2 such that sub-harmonic oscillation could be suppressed even for D=0.667. The loop gain function at heavy load is
Current Mode Converters: Bandwidth Limitation
T(s) ≈+ +
L
f L
R 1A(s)bR (1 sCR )(1 sT)
At RL(BCM) =2L/D’T,
BCMT (s) ≈+ +
L(BCM)
f
R 1A(s)bR (1 s8T)(1 sT)
Pole-zero cancellation at ω1 =1/CRL should be done at the highest load current Iomax (smallest load resistance). To achieve φm of 70o, fUGF should be 3 times lower than f2 , and fUGF ≈
fs /20. Hence, a current mode converter could have a unity gain frequency 5 times higher than its voltage mode counterpart.