©2013 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

©2013 Micron Technology, Inc. | !1

Hybrid Memory Cube Your New Standard for Memory Performance

November 26, 2013

©2013 Micron Technology, Inc. | !2November 26, 2013

HMC: A Memory Revolution

► Evolutionary DRAM roadmaps hit limitations of bandwidth and power efficiency ► Micron introduces a new class of memory: Hybrid Memory Cube ► Unique combination of DRAMs on Logic

► Micron-designed logic controller

► High speed link to CPU ► Massively parallel

“Through Silicon Via” connection to DRAM

!Revolutionary Approach to Break Through the “Memory Wall”

Key Features

HMCUnparalleled performance!

► Up to 15X the bandwidth of a DDR3 module

► 70% less energy usage per bit than existing technologies

► Occupying nearly 90% less space than today’s RDIMMs

| ©2013 Micron Technology, Inc. | !3

HMC Architecture

DRAM

Start with a clean slate

November 26, 2013

| ©2013 Micron Technology, Inc. | !4

HMC Architecture

DRAM

Re-partition the DRAM and strip away the

common logic

November 26, 2013

| ©2013 Micron Technology, Inc. | !5

DRAM

Stack multiple DRAMs

HMC Architecture

November 26, 2013

| ©2013 Micron Technology, Inc. | !6

DRAM

Vault

3DI & TSV Technology

DRAM0DRAM1DRAM2DRAM3DRAM4DRAM5DRAM6DRAM7

Logic Chip

Re-insert common logic on to the Logic Base die

HMC Architecture

Logic Base

November 26, 2013

| ©2013 Micron Technology, Inc. | !7

HMC Architecture

3DI & TSV Technology

DRAM0DRAM1DRAM2DRAM3DRAM4DRAM5DRAM6DRAM7

Logic Chip

Logic BaseVault Control Vault Control Vault Control Vault Control

Memory Control

Crossbar Switch

Link Interface Controller

Link Interface Controller

Processor Links

Link Interface Controller

Link Interface Controller

DRAM

Vault

Add advanced switching, optimized memory control

and simple interface to host processor(s)…

Logic Base

November 26, 2013

| ©2013 Micron Technology, Inc. | !8

(*) Aggregate DRAM peak bandwidth remains 160GB/s

Link Controller Interface

HMC (Gen2) has Four Links Each Link has 32 differential Lanes

RX

TX

Host

TX

RX

HMC

16 Lanes

16 Lanes

16 Transmit Lanes @ 10Gb/s Each

16 Receive Lanes @ 10Gb/s Each

(*) HMC-SR supports up to 15Gbps SERDES options

Link Interface Examples

4 Link Example (160GB/s) ➢10Gb/s per lane ➢ 32 lanes per link (320Gb/s = 40GB/s)

➢16 TX and 16 RX ➢ 4 Links (40GB/s x 4) = 160GB/s

November 26, 2013

Designed with Off-the-Shelf, High Speed SerDes Interface

| ©2013 Micron Technology, Inc. | !9

RAS Feature ComparisonFEATURE DRAM RDIMM HMCExtensive Test Flow ✓ ✓Data ECC ✓ ✓Address/Command Parity ✓ ✓Mirroring (back-up memory)

✓✓

Sparing (Chipkill) ✓✓Lockstep (redundancy w/better ECC)

✓✓

CRC Coding ✓Self Repair ✓BIST ✓Error Status and Debug Registers

✓DIMM Isolation (flags faulty DIMM)

✓✓

Memory Scrubbing ✓✓Supported ✓✓Redundant or not

November 26, 2013

©2013 Micron Technology, Inc. | !10

High Performance Memory Comparison

Requirements TCO Valuation

Bandwidth

Energy Efficiency

Board Footprint

Channel Complexity90% simpler than DDR3L 88% simpler than DDR4

95% smaller than DDR3L 94% smaller than DDR4

66% greener than DDR3L 55% greener than DDR4

10.2X greater than DDR3L 8.5X greater than DDR4

Single-Link HMC vs. DDR3L-1600 and DDR4-2133 What does it take to support 60 GB/s?

HMC

DDR4

DDR3L

0 250 500 750

pins

HMC

DDR4

DDR3L

0 3,000 6,000 9,000

mm2

HMC

DDR4

DDR3L

0 20 40 60

pJ/b

HMC

DDR4

DDR3L

0 300 600 900

MB/ pin

| ©2013 Micron Technology, Inc. | !11

HMC Near Memory

▶ All links between host CPU and HMC logic layer

November 26, 2013

▶ Maximum bandwidth per GB capacity ▪ HPC/Server – CPU/GPU ▪ Graphics ▪ Networking systems ▪ Test equipment

| ©2013 Micron Technology, Inc. | !12

HMC “Far” Memory

• Far memory ▶ Some HMC links connect to host,

some to other cubes ▶ Scalable to meet system

requirements ▶ Can be in module form or soldered-

down

• Future interfaces may include ▶ Higher speed electrical (SERDES) ▶ Optical ▶ Whatever the most appropriate interface for the job!

November 26, 2013

| ©2013 Micron Technology, Inc. | !13

HMC Consortium Update

▶ Developers working on next speed grade for SR and USR PHY: ▪ SR speed bump to 30Gb/s

▪ USR speed bump to 15Gb/s

November 26, 2013

HMCC Mission

Promote widespread adoption and acceptance of an industry standard serial interface and protocol for

Hybrid Memory Cube

http://www.hybridmemorycube.org/

▶ HMCC specification final and

available!

▶ Visit hybridmemorycube.org

for more information.

!

| ©2013 Micron Technology, Inc. | !14

Broad Adoption & Momentum

Accel, Ltd Fujitsu Limited Luxtera Inc. Pico ComputingADATA Technology Co., LTD Galaxy Computer System Co., Ltd. Marvell Renesas Electronics Corporation

AIRBUS GDA Technologies Mattozetta Technologies Science & Technology InnovationsAltior GLOBALFOUNDRIES Maxeler Technologies Ltd. SEAKR Engineering

APIC Corporation GraphStream Incorporated MediaTek ST MicroelectronicsArira Design HGST, a Western Digital Company Memoir Systems Inc. Suitcase TV Ltd

Arnold&Richter Cine Technik HiSilicon Technologies Co., Ltd Mentor Graphics TabulaAtria Logic, Inc. HOY Technologies Miranda Tech-Trek

BroadPak Huawei Technologies Mobiveil, Inc. Teradyne, IncCadence Design Systems, Inc. Infinera Corporation Montage Technology, Inc. The Regents of the University of CaliforniaConvey Computer Corporation Information Sciences Institute USC Napatech A/S Tilera Corporation

Cray Inc. Inphi National Instruments Tongji UniversityDAVE Srl ISI/Nallatech NEC corpration T-Platforms

Design Magnitude Inc. Israel Institute of Technology Netronome TU KaiserslauternDream Chip Technologies GmbH Juniper Networks New Global Technology UC, Irvine

Engineering Physics Center of MSU Kool Chip Northwest Logic UMCeSilicon Corporation Korea Advanced Institute of Science Obsidian Research University of Heidelberg ZITI

Exablade Corporation Lawrence Livermore National Laboratory OmniPhy University of RochesterEzchip Semiconductor LeCroy Corporation Oregon Synthesis Winbond Electronics Corporation

FormFactor Inc. LogicLink Design, Inc. Perfcraft Woodward McCoach, Inc.ZTE Corporation

Over 110 Adopters to date!

| ©2013 Micron Technology, Inc. | !15

Product Description

November 26, 2013

Micron Part Number Density Link Description Links Max Memory BW (GB/s) Package Description

MT43A4G40100NFA-S15:A 2GB 15G SR 4 160 BGA, 896-ball, 31x31

MT43A4G80100NFH-S15:A 4GB 15G SR 4 160 BGA, 896-ball, 31x31

MT43A4G40100NGF-S15:A 2GB 15G SR 2 120 FBGA, 666-ball, 16x19.5

MT43A4G80100NGK-S15:A 4GB 15G SR 2 120 FBGA, 666-ball, 16x19.5

HMC-15G-SR

▶ 2GB Sampling available now!

▶ 4GB Sampling available early 2014