ht specifications
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HT
Specifications
HTConnectors
and Cables
Design
SupportWhite Papers
Members
Material
HyperTransport OverviewHyperTransport (HT) is a state-of-art packet-based, high-bandwidth, scalable, low latency point-to-
point interconnect technology that links processors to each other, processors to coprocessors and processors to I/O and peripheral controllers.
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HyperTransport is an open standard technology managed, promoted and licensed to the industry at
large by the HyperTransport Consortium
HyperTransport’s market-proven solidity and highly efficient protocol make it the ideal choice as
chip-to-chip, board-to-board and chassis-to-chassis high-performance interconnect, successfully
deployed in the widest rage of consumer, commercial and mission-critical applications, includinggaming systems, embedded designs, networking equipment, personal computers, workstations,
servers, and supercomputers.
HyperTransport Evolution and MilestonesSince its inception in 2001, the Consortium has pushed HyperTransport technology toward greater
performance, features and architectural flexibility through new revisions of the HyperTransport
link, the High Node Count specifications and a comprehensive portfolio of HT connector and cablestandards. Below is a synthetic view of HyperTransport technology evolution.
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Want to Learn More?• HyperTransport Technology Overview
• HyperTransport Technology White Papers
• HyperTransport Specifications
• Design Support
• Become a Member
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HTSpecifications
HT
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HT High Node Count
HyperTransport Link SpecificationsSince its first HyperTransport 1.0 release in 2001, the HyperTransport standard has evolved to
support higher speeds, increased functionality and scalability, while maintaining the same state-of-the-art low latency capability. Thus, the HyperTransport standard has solidly maintained its lead as
the industry's highest performance and most efficient interconnect. All HyperTransport Link
specification releases are backwards-compatible with previous revisions to preserve the industry'slong-term investments in the technology.
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The chart below lists key features delivered by each release of the HyperTransport Link
specification.
HyperTransport Link Specifications Features Summary
Want to Learn More?•
HyperTransport 3.1• HyperTransport 3.0
• HyperTransport 2.0
• HyperTransport 1.x
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©2012 HyperTransport Consortium
HTSpecifications
HT
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DesignSupport
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HTX Product Validation
HyperTransport Design SupportThe HyperTransport Consortium offers a complete array of support tools and services intended to
simplify the design effort and minimize the time-to-market of HyperTransport products. Central tothe Consortium’s design support strategy are:
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Technical Support Database
HyperTransport product developers can access an extensive technical support documentation andsoftware tool database available to members of the HyperTransport Consortium. The online
database includes HyperTransport specifications, design and test guides, compatibility checklists,
as well as simulation and compliance tools that facilitate and expedite HyperTransport productdesign. For details on the available documentation and software platforms please click on the PDF
link below.
HTC Technical Support Database
To access, review and download the technical support material, simply click on the Members Log-
In button above, sign-in using your personal log-in information and click on Documentation. If your organization is a member of the HyperTransport Consortium and you have not yet obtained
log-in access to the HyperTransport Consortium member-only database, just click on the Members
Log-In button above and fill up the request form. Your temporary password and ID will be emailed
to you upon the Consortium’s validation of your applications. If your company is not anHyperTransport Consortium member and would like to become one, please click the yellow
Become a Member button above for details and guidelines on how to apply for membership.
HyperTransport Center of Excellence (HTCE)
HTCE is the premier source of HyperTransport testing and validation services to HyperTransport product developers. The center, sponsored by AMD and the HyperTransport Consortium, is lead by
world-renowned team of technology experts and researchers of the University of Heidelberg,
Germany and it is located on the campus of the University of Mannheim, also in Germany. For more details on HTCE and HTCE’s services, please click on the HT Center of Excellence button
above.
HTX Product ValidationThe HyperTransport Center of Excellence (see above) offers test and validation services on HTX
products and designs to the industry at large. For details please click on the HTX Product
Validation button above.
Reference Designs and Development ToolsA host of HyperTransport reference design platforms and development tools are available through
the HyperTransport Consortium and the HyperTransport Center of Excellence (see above) to
enable rapid design and prototyping of HyperTransport-based and HTX-based products. For more
details, please click on the Reference Design button above.
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HyperTransport 3.1 SpecificationThe HyperTransport 3.1 specification, has been released on August 18, 2008. It delivers 23% of
bandwidth improvement and proportionally lower latency capability compared to HyperTransport
3.0. HyperTransport 3.1 maintains the same advanced architectural, power management and
protocol features of HyperTransport 3.0.
HyperTransport 3.0 Features Plus:
• 2.8 GHz, 3.0GHz and 3.2 GHz Clock Rates
o 51.2 GB/s Max Aggregate Bandwidth (32-bit)
o 25.6 GB/s (204.8 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit)
o 6.4 GT/s (3.2 GHz x 2 DDR) per Lane
State-of-the-Art Technology - InvestmentPreservationWith the clock rate and bandwidth capabilities introduced with the HyperTransport 3.1Specification, the Consortium reinforces its mission of keeping HyperTransport specifications
comfortably ahead of industry requirements, thus safeguarding long term investments in the
technolog
yperTransport 3.0 SpecificationHyperTransport 3.0 is the latest release of the HyperTransport specification introduced in April
2006. The new HT 3.0 standard nearly doubles the clock speed and bandwidth of HT 2.0 whiledelivering a full slate of powerful scalability and power management features.
HyperTransport 2.0 Features Plus:
• 1.8 GHz, 2.0 GHz, 2.2 GHz, 2.4 GHz and 2.6 GHz Clock Rates
o 41.6 GB/s Max Aggregate Bandwidth (32-bit)
o 20.8 GB/s (166.4 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit)
o 5.2 GT/s (2.6 GHz x 2 DDR) per Bit
• Link Splitting (Un-Ganging) – Optional
o Each unidirectional HT link reconfigurable in real time and under software control
from any given bit width – i.e. 32-bit, 16-bit, 8-bit, 4-bit - to two independent
unidirectional links having half the bit width of the original link
o Auto-Configuration
o Asymmetry Support
Unidirectional HT links within each HT port can have different bit width
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o Powerful scalability feature - doubles the number of per-product HT ports
o More HT ports particularly useful in Symmetric Multi-Processing (SMP) topologies
• Enhanced Power Management
o HT link clock rate and bit width constantly and dynamically adjusted for best power
consumption and given workload. Real-time decision-making and adjustments handled by HT control logic via link traffic load monitoring transparently to operating system
and end-user applications
o Rapid Pause-Change-Start
• DC Operating Mode Enhancements
o Transmitter:
Enhanced Training Pattern Tolerates Multi-Bit Skew
Added Scrambling Enables Rx Phase Alignment
Retained DDR Clock
o Receiver:
Enabled Use of Rx Equalization
Support for Multi-Bit Skew Through Clock-Based Rx Phase Alignment
• AC Operating Mode – Optional
o Capacitive Coupling (vs. Direct Coupling of DC Mode)
o 8B/10B Clock Recovery
o Triples HT’s Max Link Length to 1m/3ft at Max Clock Rate
Cables, Backplanes, Chassis-to-Chassis Applications
o Higher Latency than DC Mode
o Enabled when Needed – Best of Both Worlds (DC and AC Mode)
• DC /AC Auto-Configuration
o Coupling Capacitors Auto-Detect sets HT Link to AC mode
o Same HT device configurable in DC Mode for short runs and AC mode for long runs
• Hot Plugging
o HT devices added or removed without disrupting product/system operation
Defined Link Termination Methods
Transaction Termination Behaviors
Sync Flood Isolation
Link Training Times
o Parameter Configuration Mechanisms
o "Always-up" capability for backplane and mission-critical applications
• 100% Backward Compatibility
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o Runs in HT 1.x and 2.0 Mode when New Features Not Enabled
Boot-Up Auto-Configuration
o HT Link Set to Highest HT Specification Revision Supported by all HT Link Devices
State-of-the-Art Technology - Investments
PreservationThese new HyperTransport 3.0 features and capabilities dramatically reinforce HyperTransport's
role as the most flexible, most scalable, highest performance and lowest latency processor-to- processor and processor-to-peripheral interconnect technology the market has to offer, vastly
extending its overall application latitude and market opportunity. In addition, by preserving full
backward compatibility with prior HyperTransport specifications, HyperTransport 2.0 continues tosafeguard and maximize the industry’s legacy investments in the technology.
HyperTransport 2.0 SpecificationThe HyperTransport 2.0 specification, released in February 2004, introduced a 75 percent clock
rate and bandwidth improvement over HyperTransport 1.x, as well as additional features and
capabilities.
HyperTransport 1.x Features Plus:
• 1.0 GHz, 1.2 GHz, 1.4 GHz, 2.4 GHz Clock Rates
o 22..4 GB/s Max Aggregate Bandwidth (32-bit)
o 11.2 GB/s (89.6 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit)
o 2.8 GT/s (1.4 GHz x 2 DDR) per Bit
• PCI Express Mapping
• De-Emphasis
o Ensures proper signal integrity despite the dramatic clock rate increase
• 100% Backward Compatibility
o Runs in HT 1.x Mode when Higher Clock Rates Not Used
o Boot-Up Auto-Configuration
HT Link Set to Highest HT Specification Revision Supported by all HT Link
Devices
In addition, by preserving full backward compatibility with prior HyperTransport specifications,
HyperTransport 3.0 continues to safeguard and maximize the industry’s legacy investments in the
technology.
HyperTransport 1.x Specifications
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HyperTransport 1.1 Specification (DirectPacket™)
HyperTransport DirectPacket™ Release 1.10 defines four major features to the HyperTransport 1.xtechnology specification:
• Native Packet Handling
o User packets move efficiently between devices without DMA loops
o Seamless mix of load-store and packet bus functionality
o Load-store operation with no added overhead
• Pier-to-Pier Routing
o Direct communication between HT devices
Example: framer to security processor
• 16 Additional Virtual Channels
o Optimized for streaming
o Posted-Write only with dedicated flow control
o End-to-End flow control for highly channelized applications
Example: channelized framer interface
• Robust Error Retry Protocol
o For high-reliability, mission-critical applications
o Future-proof - supporting faster electrical links
Such innovative DirectPacket™ capabilities make HyperTransport the most efficient means tostream packets with minimum overhead and the ideal technology for enhancing performance in
high speed streaming data with SPI-4, XAUI, and other communications technologies.HyperTransport DirectPacket™ features bring communications-oriented, packet-handling
capabilities to otherwise standard processor-centric computing systems.
HyperTransport 1.1 Specification
HyperTransport 1.05 SpecificationThe HyperTransport 1.05 Specification adds four major features to the previous HyperTransport
1.03 release:
•
HyperTransport Link Switch Functiono Enables connection of virtually unlimited numbers of HyperTransport devices
• Enhanced PCI-X 2.0 Inter-Working
o Simplifies connection to PCI-X 2.0 subsystems
o Supports error indications and device configuration messages up to 4K bytes
o Supports PCI-X 2.0 128-byte burst messaging
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• Extended Transaction Concurrency
o Allows up to 128 outstanding requests
o Eliminates potential bottlenecks in networking applications
• Extended 64-bit Addressing
o Extended from 40-bit
o Supports larger address topologies required by large server and networking applications
o Backward compatible with earlier generation addressing schemes
HyperTransport 1.05 Specification
HyperTransport 1.04 SpecificationThe HyperTransport 1.04 Specification introduces feature extensions, clarifications and errata fixes
to the original HyperTransport 1.03 Release:• Revision ID Capability
o For tagging functions as existing within an HT device
• PCI-X Ordering and Command Mapping
o Simplifies connection to PCI-X 2.0 subsystems
• Potential Deadlocks Prevention
o How to prevent – Documented in Appendix C
HyperTransport 1.04 Specification
HyperTransport 1.03 SpecificationHyperTransport 1.03 is the original HyperTransport™ I/O Link specification released by the
HyperTransport Consortium in October 2001. HT 1.03 defines and describes the input/output link
protocol and electrical interface for the HyperTransport interconnect technology. The document isdivided into two main parts: Protocol and Electrical. The Protocol part includes information on
HyperTransport technology signals, packets, commands, interrupts, configuration accesses, address
map, error handling, clocking, and initialization. The Electrical part includes information on I/O power supply, AC and DC characteristics, transfer timing, and phase recovery timing.
Comprehensive HyperTransport ProductEcosystemDuring its past seven years of performance leadership and technology solidity, HyperTrasport has
continued to accumulate widespread industry adoption. At present, HyperTransport technology
empowers an ever expanding variety of commercial platforms and products that cater to the entire
design-to-solution technology food chain, with a true full circle value delivery.
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As a processor-native interconnect, HyperTransport has been integrated in a large number of CPUs
and processor families from multiple manufacturers. HT-powered processors serve a wide varietyof performance-intensive applications, including x86 computing, graphics and 3D rendering,
security processing, real-time data/packet analysis, media processing, application-specificacceleration and co-processing.
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HyperTransport has been adopted by technology leaders for the widest range of productapplications.
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By clicking on the buttons above you can easily sort through and review the profile of
HyperTransport-enabled products commercially available. While we strive to keep this product list
updated at all time, due to fast market dynamics not all HyperTransport-based products may beincluded here. If you don’t find HyperTransport-enabled products that you believe should be
included in these product pages, please let us know by clicking on the "Contact Us" button above.
We will gladly provide you with the information you need and any appropriate manufacturer
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