how to use the 3 axi configurations
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How to Use The 3 AXI Configurations
Xilinx Training
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Objectives
After completing this moule! "ou will be able to#
$ist the three AXI s"stem architectural moels %configurations&
'ame the five AXI channels
(ummari)e the AXI vali*rea" ac+nowlegement moel
,escribe the operation of the AXI streaming protocol
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-asic AXI Transactions
.ea aress channel
.ea ata channel
/rite aress channel
/rite ata channel
/rite response channel
Non-posted write model:
there will always be a writeresponse
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AXI Interface# AXI0
Also calle 1ull AXI or AXI
2emor" 2appe
(ingle aress multiple
ata
-urst up to 45 ata beats
AXI4 Read
AXI4 Write
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AXI Interface# Hansha+ing
AXI uses a vali*rea" hansha+e
ac+nowlege
6ach channel has its own vali*rea"
Address (read/write)
ata (read/write)
Response (write only)
1lexible signaling functionalit"
Insertin! wait states
Always ready
"ame #y#le a#$nowled!e
Insertin! Wait "tates
Always Ready
"ame %y#le A#$nowled!e
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AXI Interface# .ea
AXI & 'rst Read
Two channels
Address
ata
Up to 45 transfer
ata phase(electable ata
transfer si)e
(ee notes for
signal etail of
each channel
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AXI Interface# /rite
AXI 'rst Write
Three channels
Address
ata
Response
Up to 45 transferata phase
(electable ata
transfer si)e
(ee notes for signal
etail of each
channel
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AXI Interface# $ite
'o burst
,ata with 3 or 50
onl"
Xilin I* will only
spport +, bits(imple 7logic shim8 to
connect AXI0 master
to AXI09$ite slave
Rele#t master.s
transa#tion IThis is best for simple
s"stems with minimal
peripherals
AXI4-ite Read
AXI4-ite Write
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AXI09$ite
The AXI09$ite interface is a subset of the AXI0 interface intene
for communication with control registers in components
The aim of AXI09$ite is to allow simple component interfaces to
be built that are smaller an also re:uire less esign an
valiation effortHaving a efine subset of the full AXI0 interface allows man"
ifferent components to be built using the same subset an also
allows a single common conversion component to be use to
move between AXI0 an AXI09$ite interfaces
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AXI $ite (ignal list
(ubset of AXI signal set
(imple traitional signalingTargete applications# simple! low9performance peripherals
0*I1
2art ite
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AXI Interface# (treaming
'o aress channel
'ot rea an write! alwa"s master to
slave
Unlimite burst length
AXI4-"treamin! 3ranser
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AXI Aitional 1eatures
I, fiels for each of the five channels facilitate overlappe
transactions
*roides or a transa#tion ta!
Transaction burst t"pe etermines aress bus behavior
5ied6 in#rement6 or wrapOptional aress $oc+ signals facilitates exclusive an atomic
access protection
("stem cache support
;rotection unit support
6rror support
Unaligne aress
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,ocumentation
Xilinx AXI .eference
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(ummar"
AXI has separate! inepenent rea an write interfaces
implemente with channels
6ach AXI channel supports a vali*rea" ac+nowlegement
hansha+e
AXI supports bursts an overlappe transactions
The AXI0 interface offers improvements over AXI3 an efines
5ll AXI memory mapped
AXI ite
AXI "treamin!
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/here Can I $earn 2ore?
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