how does the cpu execute programs? - radboud universiteit · 2017-12-06 · 2 overview so far…...
TRANSCRIPT
How does the CPU execute programs?Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren and Niek Janssen)
2
Overview
So far…• Circuits• Memory• ALU
Today…• How are instructions executed?
• Fetch-decode-execute cycle• Data Path
• RUN1718 CPU - your own processor in the practicum
3
Recall: A Six-level Computer
gates get signals 0 or 1, compute output functions (AND, OR),
may form memory or even computing engine
ALU (Arithmetic Logic Unit), registers
controls data path between ALU and registers
human-understandable
machine language
recall the levels and their meaning
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
4
“Von Neumann”-architecture
Screen Keyboard
Program
Memory
recall the structure
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
4
“Von Neumann”-architecture
Screen Keyboard
Program
Memory
recall the structure
How to execute programs?
5
Program Inside the Memory
• Consists of machine code
• RUN1718 CPU: Each machine code instruction consists of 32 bits
• Other processors: 8–120 bits
Details next week!
6
Microarchitecture — Program Execution Cycle
1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)
6
Microarchitecture — Program Execution Cycle
1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)
Decode, ExecuteFetch
6
Microarchitecture — Program Execution Cycle
1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)
Decode, ExecuteFetch
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Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
7
Fetch-Phase: Read Instruction
Screen Keyboard
Memory
Program
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
7
Fetch-Phase: Read Instruction
Screen Keyboard
Memory
Program
Instruction
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
8
Fetch-phase: Increase PC
Screen Keyboard
Memory
Program
Instruction
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
8
Fetch-phase: Increase PC
Screen KeyboardPC
Memory
Program
Instruction
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
9
Decode-phase
Screen Keyboard
Memory
Program
Instruction
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
9
Decode-phase
Screen Keyboard
Memory
Program
Instruction
what is done in the decode phase?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
9
Decode-phase
Screen Keyboard
Memory
Program
Instruction
Next week: • READ: 110000
• WRITE: 111000
what is done in the decode phase?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
10
Execute-phase: Computation
Screen Keyboard
Memory
Program
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
10
Execute-phase: Computation
Screen Keyboard
Memory
Program
what is done during a computation?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
10
Execute-phase: Computation
Screen Keyboard
Memory
Program
operands
what is done during a computation?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
10
Execute-phase: Computation
Screen Keyboard
Memory
Program
flags
resultoperands
what is done during a computation?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
11
Execute-phase: Write
Screen Keyboard
WRITE
Memory
Program
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
11
Execute-phase: Write
Screen Keyboard
WRITE
Memory
Program
what is done during writing?
Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0
11
Execute-phase: Write
Screen Keyboard
WRITE
Memory
Program
WRITE
what is done during writing?
12
Data Path (MIPS processor)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
12
Data Path (MIPS processor)
ADD R1, R2, R2 (R2 := R1 + R2)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
13
Data Path (MIPS processor): Fetch
ADD R1, R2, R2 (R2 := R1 + R2)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
14
Data Path (MIPS processor): Decode
ADD R1, R2, R2 (R2 := R1 + R2)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
15
Data Path (MIPS processor): Execute
ADD R1, R2, R2 (R2 := R1 + R2)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
15
Data Path (MIPS processor): Execute
ADD R1, R2, R2 (R2 := R1 + R2)
Read address Instruction
Instruction Register
Readreg. 1 Read data1
Registers
Readreg. 2
Writereg.Write data Read data2
Address Read data
Data Memory
Write data
18
How to construct the RUN1718 CPU
3 phases:1. Fetch read instructions2. Test preconditions satisfied?
18
How to construct the RUN1718 CPU
3 phases:1. Fetch read instructions2. Test preconditions satisfied?3. D(ecode) + Execute decoding only combinatorial
19
Decode+ ExecuteFetch
Test
Pause
CLK↘ [TEST_SUCCEEDS=1]CLK↗
CLK↘ CLK↗
Finite automaton for RUN1718 CPU
19
Decode+ ExecuteFetch
Test
Pause
CLK↘ [TEST_SUCCEEDS=1]CLK↗
CLK↘ CLK↗
CLK↘ [TEST_SUCCEEDS=0]
Finite automaton for RUN1718 CPU
22
Structure of the RUN1718 CPU
• ALU • registerbank • control unit ▪ flag register bank ▪ tester ▪ timer ▪ instruction decoder with instruction register
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
3. Combined data path
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
3. Combined data path▪ necessary connections (and multiplexers)
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
3. Combined data path▪ necessary connections (and multiplexers)
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
3. Combined data path▪ necessary connections (and multiplexers)
Afterwards: design your own parts.
24
How do I start?
1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?
2. Interfaces for each component▪ based on given information
3. Combined data path▪ necessary connections (and multiplexers)
Afterwards: design your own parts. (HADES is no design tool)