1.4 hardware review. cpu fetch-decode-execute cycle 1. fetch 2. bump pc 3. decode 4. determine...
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1.4 Hardware Review1.4 Hardware Review
CPUCPU Fetch-decode-execute cycleFetch-decode-execute cycle
1.1. FetchFetch2.2. Bump PCBump PC3.3. DecodeDecode4.4. Determine operand addr (if necessary)Determine operand addr (if necessary)5.5. Fetch operand from memory (if necessary)Fetch operand from memory (if necessary)6.6. ExecuteExecute7.7. Go to step 1Go to step 1
MIPS IA is different from Intel IAMIPS IA is different from Intel IA RegistersRegisters PCPC SPSP PSW (EFLAGS)PSW (EFLAGS)
What mode are we in?What mode are we in? Result of last operation (N,Z,V,C)Result of last operation (N,Z,V,C)
System call = way of obtaining services of System call = way of obtaining services of OSOS Often implemented via TRAP instructionOften implemented via TRAP instruction
memorymemory
RAMRAM ROM – nonvolatileROM – nonvolatile EEPROM or flash RAMEEPROM or flash RAM CMOS – low power, volatile RAMCMOS – low power, volatile RAM
Backed up by batteryBacked up by battery Date/time storage, boot parametersDate/time storage, boot parameters
Disk organizationDisk organization
Disks: sector, intersector gap, track, cylinderDisks: sector, intersector gap, track, cylinder
Multiple programs in RAMMultiple programs in RAM
Why? Better use of resource, multiple Why? Better use of resource, multiple programs running, etc.programs running, etc.
Needs:Needs: Protect processes (and kernel) from each Protect processes (and kernel) from each
otherother Handle relocationHandle relocation
Multiple programs in RAMMultiple programs in RAM
How?How? Assume all programs start at virtual address 0Assume all programs start at virtual address 0 Use base and limit registersUse base and limit registers Virtual-to-physical address translation via Virtual-to-physical address translation via
MMUMMU managed by OSmanaged by OS Context switch – switching from 1 program to Context switch – switching from 1 program to
anotheranother
I/O devicesI/O devices
Device driver = software that talks to a Device driver = software that talks to a controller, giving it commands and controller, giving it commands and accepting responsesaccepting responses
Must be loaded into kernel via one of the Must be loaded into kernel via one of the following:following:1.1. Relink kernel and reboot (Unix)Relink kernel and reboot (Unix)
2.2. Make an entry into system file & check & load Make an entry into system file & check & load entries at boot time (Windows)entries at boot time (Windows)
3.3. Dynamically loaded drivers (USB & IEEE 1394)Dynamically loaded drivers (USB & IEEE 1394)
Methods of communicating w/ device Methods of communicating w/ device registers:registers:
1.1. Use special IN/OUT instructionsUse special IN/OUT instructions
2.2. Map device registers into memory (RAM)Map device registers into memory (RAM)
Methods of performing I/O:Methods of performing I/O:1.1. Busy waitingBusy waiting
2.2. InterruptsInterrupts
3.3. Interrupts w/ DMAInterrupts w/ DMA
Busy waitingBusy waiting User User system call system call driver procedure call driver procedure call
wait (polling) wait (polling) return results & status return results & status
InterruptsInterrupts User User system call system call driver procedure call driver procedure call
w/ ISR specifiedw/ ISR specified User waits but CPU is free to do something User waits but CPU is free to do something
elseelse ISR is called only when work needs to be ISR is called only when work needs to be
accomplished (and performs the work)accomplished (and performs the work)
Interrupts w/ DMAInterrupts w/ DMA
Servicing interruptsServicing interrupts1.1. I/O device has completed operation; CPU is I/O device has completed operation; CPU is
signalled (electrically)signalled (electrically)2.2. CPU may or may not decide to service CPU may or may not decide to service
interrupt right nowinterrupt right now3.3. Service:Service:
1.1. Push PC & PSW on stackPush PC & PSW on stack2.2. Switch to kernel modeSwitch to kernel mode3.3. User interrupt vector (table) for service routine User interrupt vector (table) for service routine
addressaddress4.4. Restore PC & PSW and resume what was being Restore PC & PSW and resume what was being
performedperformed Remember: interrupts can occur at any (the Remember: interrupts can occur at any (the
worst) time so they can be disabled (ignored, worst) time so they can be disabled (ignored, queued, and/or prioritized)queued, and/or prioritized)
BusesBuses
Standard electrical connectivity w/ system/CPU Standard electrical connectivity w/ system/CPU ((ex. PCI, SCSI, USB, IEEE 1394, IDE, EIDE, ISA, ATA, ex. PCI, SCSI, USB, IEEE 1394, IDE, EIDE, ISA, ATA, SATA, AGP, cache, memory)SATA, AGP, cache, memory)
AGP 3.5AGP 3.5 - 2.1 GB/s- 2.1 GB/s ATAATA - 33 to 133 MB/s- 33 to 133 MB/s FireWire IEEE 1394bFireWire IEEE 1394b - 800 MB/s- 800 MB/s ISAISA - 16.7 MB/s (8.3 MHz)- 16.7 MB/s (8.3 MHz) PCIPCI - 528 MB/s (66 MHz)- 528 MB/s (66 MHz) SCSI Ultra-640SCSI Ultra-640 - 640 MB/s- 640 MB/s USB3USB3 - 4 GB/s- 4 GB/s
Boot processBoot process
1.1. Execution starts w/ code in BIOS (flash Execution starts w/ code in BIOS (flash RAM or ROM)RAM or ROM)
2.2. Determine amount of memoryDetermine amount of memory
3.3. Scans ISA & PCI for devices and checks Scans ISA & PCI for devices and checks keyboardkeyboard
4.4. Checks CMOS for boot deviceChecks CMOS for boot device First sector of boot device is read into First sector of boot device is read into
memory and executedmemory and executed