HIGHLY EFFICIENT AND DIMMABLE LED BACK LIGHT DRIVER FOR

PORTABLE DEVICES

BY

Venu Siripurapu, B.E

A thesis submitted to the Graduate School in partial

fulfillment of the requirements

for the degree

Master of Sciences, Engineering

Specialization in: Electrical Engineering

New Mexico State University

Las Cruces, New Mexico

April 2016

“HIGHLY EFFICIENT AND DIMMABLE LED BACK LIGHT DRIVER FOR

PORTABLE DEVICES,” a thesis prepared by Venu Siripurapu in partial fulfill-

ment of the requirements for the degree, Master of Sciences has been approved

and accepted by the following:

Dr. Louis ReyesDean of the Graduate School

Chair of the Examining Committee

Date

Committee in charge:

Dr. Paul M. Furth, Associate Professor, Chair.

Dr. Wei Tang, Assistant Professor.

Dr. Rolfe Sassenfeld, Assistant Professor.

ii

DEDICATION

Dedicated to my mother Venkata Laxshmi, father Nageswara Rao, brother

Manoj Kumar, my advisor Dr. Paul Furth, and all my friends and family mem-

bers.

iii

ACKNOWLEDGMENTS

I express my gratitude to all those people who supported me in the suc-

cessful accomplishment of my research work at NMSU.

My advisor Dr. Paul Furth, is a role model in the teaching industry. His

way of thinking on ”How to improve the educational standards” is what sets him

apart. He always motivates students to perceive and analyze things through. Due

to this students always reach higher levels of success. His encouragement and

continuous advising led this research work to move at a faster pace.

Dr. Wei Tang is one of the youngest professors in the Electrical Engineering

Department. I have always been inspired by his new ideas and working style. I

also had a great opportunity to work under Dr. Rolfe Sassenfeld for developing

the power laboratory in Engineering Technology Department. I am happy to be

a part of this success story that established an engineering technology power lab

within a limited budget.

Co-advisors for this research work are Ph.D. candidates Punith R Surkanti

and Sri Harsh Pakala. I could not imagine my research work with out either one

of their technical support and continuous status tracking. I am thankful for their

great support.

My parents Nageswara Rao and Venkata Lakshmi, always oversaw my in-

dividual steps to ensure my journey towards successful completion of my Master’s

iv

Degree in Electrical Engineering. All my life, my father inspired me to be a better

human being.

Co-workers Anurag Veerabathini, Mahendar Manda, Sai Kiran Ramidi,

Rohith Gaddam created a right balance between peer support and peer competi-

tion. Thank you all for your constant support in my successful journey at NMSU,

in Las Cruces, New Mexico.

v

VITA

Education

2008 - 2012 B.E. Electronics and Communication Engineering,Jawaharlal Nehru University, India

2013 - 2016 MSEE. in Electrical Engineering,New Mexico State University, USA

Presentations

Electro Static discharge (ESD), New Mexico State University, March, 2014.

Professional Experience

[1] Analog Design Engineer in RF Domain such as Oscillator, PLLs, LDOs etc.,Palma Ceia SemiDesign, Dallas, Texas, from Aug-2015 - Jan-2016

[2] Hardware Engineer in Hybrid Vehicle Power Control Unit, Robert BOSCHEngineering and Business Solutions, Bangalore, India, from July-2011 - Dec-2013

[3] Associate Engineer in Power Electronics Domain, Larsen & Toubro limited-IES, Mysore, India, from June-2010 - July-2011

[4] Associate Member Technical Staff in Embedded Domain, HCL Technologies,Bangalore, India, from July-2008 - June-2010

vi

ABSTRACT

HIGHLY EFFICIENT AND DIMMABLE LED BACK LIGHT DRIVER FOR

PORTABLE DEVICES

BY

Venu Siripurapu, B.E

Master of Sciences, Engineering

Specialization in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico, 2016

Dr. Paul M. Furth, Chair

MS Thesis defense scheduled on 04/07/2016, 9 AM

Thomas & Brown Hall, Room 207.

Effective power utilization is an important issue for portable devices as

it defines the battery life. The display module consumes the largest portion of

power and efficient power converters will reduce unwanted conversion losses and

improves the battery life. A highly efficient and dimmable boost converter, which

is suitable for LED back-light drivers in smart phones, is presented in this paper.

A hysteretic-mode synchronous boost converter is implemented as an LED driver

using the IBM 0.18 µm CMOS technology. The output of this converter is designed

vii

as a current source to drive 5 parallel LED strings (20 mA through each string)

with two series-connected color LEDs in each string. The simple and fast response

to load changes makes this system applicable for digital dimmable LED driver

applications. To reduce the power dissipation and improve the transient response,

the feedback loop is implemented using 1.8 V devices, whereas the power switches

can switch up to 5.5 V. A peak efficiency of 92% is measured in simulation.

Dimming control is implemented with 10 dimming ratios ranging from 1:1 to

512:1.

viii

TABLE OF CONTENTS

LIST OF TABLES xii

LIST OF FIGURES xiv

1 INTRODUCTION 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Project Background . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Objectives and Unique Contributions . . . . . . . . . . . . . . . . 4

1.4 Report Organization . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 LITERATURE REVIEW 6

2.1 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.1 Conventional Boost Converter . . . . . . . . . . . . . . . . 6

2.1.2 Synchronous Boost Converter . . . . . . . . . . . . . . . . 8

2.2 Boost Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 PWM Mode Control . . . . . . . . . . . . . . . . . . . . . 10

2.2.2 PFM Mode Control . . . . . . . . . . . . . . . . . . . . . . 12

2.3 LED Driver Topologies in the Literature . . . . . . . . . . . . . . 13

2.4 Hysteretic Boost Converter in the Literature . . . . . . . . . . . . 15

2.5 Current Mirrors and Current Matching . . . . . . . . . . . . . . . 16

2.6 Minimum or Lowest Voltage Selector . . . . . . . . . . . . . . . . 18

ix

2.7 Hysteretic Comparator . . . . . . . . . . . . . . . . . . . . . . . . 19

2.8 SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9 Non-Overlapping Clock Generator . . . . . . . . . . . . . . . . . . 21

2.10 MOS Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.11 Level Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.12 Inductor Current Sense Module . . . . . . . . . . . . . . . . . . . 25

2.13 Zero Cross Detector . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.14 Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 DESIGN AND BLOCK-LEVEL SIMULATIONS 30

3.1 Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Boost Converter Design . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.1 Inductor Value Calculation . . . . . . . . . . . . . . . . . . 32

3.2.2 Capacitor Value Calculation . . . . . . . . . . . . . . . . . 34

3.3 Power FETs sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.4 Power MOSFET Gate Driver Sizing . . . . . . . . . . . . . . . . . 40

3.5 Hysteretic Voltage Mode Control . . . . . . . . . . . . . . . . . . 42

3.6 Hysteretic Current Mode Control . . . . . . . . . . . . . . . . . . 44

3.7 Minimum Voltage Selector . . . . . . . . . . . . . . . . . . . . . . 44

3.8 Current Matching Circuit . . . . . . . . . . . . . . . . . . . . . . 51

3.9 LED Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.10 Inductor Full-Range Current Monitor . . . . . . . . . . . . . . . . 54

4 CHIP-LEVEL SIMULATIONS AND LTA MEASUREMENT RE-SULTS 59

4.1 Simulation Results of Closed-Loop Design . . . . . . . . . . . . . 59

4.1.1 Virtuoso Simulation Test Bench . . . . . . . . . . . . . . . 59

x

4.1.2 Virtuoso Simulation Result - Full Load . . . . . . . . . . . 60

4.1.3 Virtuoso Simulation Results - During Digital Dimming . . 63

4.2 Layout of Boost Converter, Power Switches & the control loop . . 66

4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.1 Parametric Failure Due To Inrush Current . . . . . . . . . 69

4.3.2 NC Pins In The Layout . . . . . . . . . . . . . . . . . . . 70

4.4 Measurement Results For Minimum Voltage Selector . . . . . . . 71

5 CONCLUSIONS 78

5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2 Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 Comparison with the State-of-the-Art . . . . . . . . . . . . . . . . 79

5.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

REFERENCES 81

APPENDICES 85

A. Test Document 86

A.1 Pin Diagram of the Boost Converter . . . . . . . . . . . . . . . . 87

A.2 Supply Voltages and Currents . . . . . . . . . . . . . . . . . . . . 87

A.3 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

B. External Capacitor and Inductor Selection 95

B.4 External Inductor and Capacitor Selection . . . . . . . . . . . . . 96

xi

LIST OF TABLES

2.1 Truth Table of SR Latch using NOR Gates. . . . . . . . . . . . . 21

3.1 Boost Converter Specifications. . . . . . . . . . . . . . . . . . . . 31

3.2 Inductor and Capacitor Design Values. . . . . . . . . . . . . . . . 36

3.3 Power MOSFET Sizing. . . . . . . . . . . . . . . . . . . . . . . . 41

3.4 Sizes of the MOSFETs used in Current Matching Circuit. . . . . . 42

3.5 Hysteretic Comparator MOSFET Sizes. . . . . . . . . . . . . . . . 46

3.6 LTA comparison with state-of-art. . . . . . . . . . . . . . . . . . . 51

3.7 Sizes of the MOSFETs used in Current Matching Circuit. . . . . . 52

3.8 Values of Parasitic Components in LED. . . . . . . . . . . . . . . 54

3.9 NMOS Current Sensing Module sizes. . . . . . . . . . . . . . . . . 56

3.10 PMOS Current Sensing Module sizes. . . . . . . . . . . . . . . . . 57

4.1 Test Bench Input and Component Specifications. . . . . . . . . . 61

4.2 Simulation Results Summary. . . . . . . . . . . . . . . . . . . . . 65

4.3 Load Transient Analysis. . . . . . . . . . . . . . . . . . . . . . . . 66

4.4 Module Sizing Summary. . . . . . . . . . . . . . . . . . . . . . . . 68

4.5 Input Specification for LTA. . . . . . . . . . . . . . . . . . . . . . 76

4.6 Simulation and Measured Results of LTA. . . . . . . . . . . . . . 77

5.1 Simulation Results Summary of LED Driver. . . . . . . . . . . . . 80

xii

1 Pin Description of Fabricated Chip. . . . . . . . . . . . . . . . . . 92

2 Off-Chip Inductor and Capacitor. . . . . . . . . . . . . . . . . . . 96

xiii

LIST OF FIGURES

1.1 Power Management Schemes for Smartphone Devices [1]. . . . . . 2

1.2 LED Driver Application. . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Conventional Boost Converter. . . . . . . . . . . . . . . . . . . . . 7

2.2 Synchronous Boost Converter. . . . . . . . . . . . . . . . . . . . . 9

2.3 Synchronous Boost Converter (ON State). . . . . . . . . . . . . . 9

2.4 Synchronous Boost Converter (OFF State). . . . . . . . . . . . . 10

2.5 PWM Mode Control Scheme for DC-DC Converter. . . . . . . . . 11

2.6 PFM Mode Control Scheme for DC-DC Converter. . . . . . . . . 12

2.7 Energy Recycling Technology for Back light Unit [2]. . . . . . . . 13

2.8 Double-Loop Control LED Driver [3]. . . . . . . . . . . . . . . . . 14

2.9 Current Mode Hysteretic Control [4]. . . . . . . . . . . . . . . . . 15

2.10 Double-Loop Control LED Driver [3]. . . . . . . . . . . . . . . . . 17

2.11 High Output Impedance and Low Output Voltage Current MirrorCircuit [5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.12 Loser-Take-All Circuit [6]. . . . . . . . . . . . . . . . . . . . . . . 19

2.13 Comparator with Positive Feedback Decision Circuit [7]. . . . . . 20

2.14 SR Latch using two NOR Gates. . . . . . . . . . . . . . . . . . . 21

2.15 Nonoverlapping clock generation circuit [8]. . . . . . . . . . . . . . 22

2.16 Waveforms of non-overlapping clock generator [8]. . . . . . . . . . 22

xiv

2.17 MOS Transistor Gate Driver with scale factor S. . . . . . . . . . . 24

2.18 Level Shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.19 Full Range Inductor Current Sensor [9]. . . . . . . . . . . . . . . . 26

2.20 Zero Cross Detector [9]. . . . . . . . . . . . . . . . . . . . . . . . 27

2.21 Digital Dimming [10]. . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1 LED Driver Application. . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 Inductor Voltage & Current Waveforms while Operating in BCM. 33

3.3 Inductor Current at the Boundary of CCM and DCM. . . . . . . 35

3.4 Inductor Current at the Boundary of CCM and DCM. . . . . . . 36

3.5 Synchronous Boost Converter. . . . . . . . . . . . . . . . . . . . . 37

3.6 Paracitic Components for Power Switches. . . . . . . . . . . . . . 38

3.7 MOS Transistor Gate Driver. . . . . . . . . . . . . . . . . . . . . 41

3.8 Hysteretic Voltage Mode Control Loop Implementation. . . . . . . 43

3.9 Hysteretic Current Mode Control Loop Implementation. . . . . . 45

3.10 Hysteretic Voltage and Current Mode Control Loop Implementation. 45

3.11 Schematic of High Speed Hysteretic PMOS-Input Comparator Stage. 46

3.12 Top level schematic of the proposed N-input Loser-Take-All (LTA). 47

3.13 Top level schematic of the proposed N-input Loser-Take-All (LTA). 48

3.14 Top level schematic of the proposed N-input Loser-Take-All (LTA).Weird caption - PMF . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.15 Hysteresis simulation of 2-input LTA slow ramp and 0.45 V DC. . 50

3.16 High Output Impedance and Low Output Voltage Current Match-ing Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.17 LED I-V Characteristics [11]. . . . . . . . . . . . . . . . . . . . . 53

3.18 LED Simulation Model used. . . . . . . . . . . . . . . . . . . . . . 54

3.19 NMOS current sensor with current-offset cancellation [9]. . . . . . 55

xv

3.20 PMOS current sensor with current-offset cancellation [9]. . . . . . 56

3.21 Full Range Inductor Current Sense Module [9]. . . . . . . . . . . . 58

4.1 Test Bench of Hysteretic Synchronous Boost Converter.Add textannotations to be able to follow text - PMF . . . . . . . . . . . . 60

4.2 Output Voltage and Inductor Current. . . . . . . . . . . . . . . . 62

4.3 Switching Node and Load Current. . . . . . . . . . . . . . . . . . 63

4.4 Output Voltage and Output Current (Zoom). . . . . . . . . . . . 64

4.5 Switching Node and Inductor Current (Zoom). . . . . . . . . . . . 64

4.6 Dimming at 200 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.7 Chip Level Layout for Hysteretic Synchronous Boost Converter. . 67

4.8 NMOS Power Switch. . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.9 PMOS Power Switch. . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.10 NMOS Transistor Gate Driver. . . . . . . . . . . . . . . . . . . . 70

4.11 Current Matching Circuit. . . . . . . . . . . . . . . . . . . . . . . 71

4.12 Output Voltage and Inductor Current. . . . . . . . . . . . . . . . 72

4.13 No Connect on Multiplexer Layout. . . . . . . . . . . . . . . . . . 73

4.14 Test Chip Layout for Looser-Take-All. . . . . . . . . . . . . . . . 74

4.15 4-Input LTA simulation resultas with 24 pF load capacitance andreduced input frequency. . . . . . . . . . . . . . . . . . . . . . . . 75

4.16 LTA Testbench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.17 LTA Measurement Results. . . . . . . . . . . . . . . . . . . . . . . 76

A.1 QFP Pin Diagram of Hysteretic Boost Converter. . . . . . . . . . 87

A.2 QFP Pin Diagram of Hysteretic Boost Converter. . . . . . . . . . 88

xvi

Chapter 1

INTRODUCTION

1.1 Motivation

It is always interesting and challenging to develop a circuit block that can

bring a significant performance change to the products that are used in day-to-

day life. Rapid technology changes in the electronic industry has made mobile

devices ubiquitous. These mobile devices are designed as multi-purpose systems

known as smart phones, which are integrated with many features such as MP3

players, wireless communication, cameras, memory, sensors etc. The International

Telecommunication Union (ITU) announces 5.3 billion cellphone subscriptions

have been replaced by smart phones in 2010 worldwide [1].

A single Li-ion battery source is used in most of the mobile device ap-

plications and its output voltage varies from 2.8 V to 4.2 V . The user demand

on high performance application processor and increased data traffic in wireless

communication results in higher power dissipation [1] and leads to short lifespan

of the battery. Additionally, the amount of space available for the energy source

is also reducing due to decreasing portable device size. Furthermore, the rate of

improvement in energy density has been very slow for Li-ion batteries [12].

There are several battery technologies that are gaining significance for in-

creasing energy density. Amongst them, fuel cells are preferred due to significant

improvement over traditional batteries. Fuel cells such as the methanol fuel cell,

proton exchange membrane fuel cell, and aluminium-air fuel cell suffer from chem-

1

Figure 1.1: Power Management Schemes for Smartphone Devices [1].

ical refilling of methanol, hydrogen, and aluminium cartridges, respectively, over

time. Additionally, hydrogen fuel cells have the potential of explosion [12]. Even

though fuel cells offer higher energy density, due to the above mentioned draw-

backs, they are not preferred as complete replacements for Li-ion batteries in

portable device applications.

The feature rich applications on smart phones devices forces one to effi-

ciently use the battery life i.e., to utilize the full range of battery voltage and

improve module efficiency. So it is extremely challenging to improve the battery

utilization time in portable devices. Moreover, devices that operate with continu-

ous display are power hungry as the back-light display is one of the modules that

2

consumes the most power. As such, I am motivated to research and improve the

efficiency and performance of an LED display driver.

1.2 Project Background

There are a wide variety of Power Management Circuits with different

topologies available. The selection of an efficient topology depends on the ap-

plication and load requirements. An LED backlight display is the load in this

application. Choosing an LED configuration or the total number of LEDs used

for a backlight display depends on the display size and application. Usually the

display module suppliers would provide the recommended LED configuration. The

bigger the display size, the larger the number of LEDs used. Generally, LEDs un-

der the same display are driven with the same current so that the same luminous

intensity is observed from all LEDs.

In an application like smartphones it is very important to utilize the full

extent of battery life for long duration. Effective utilization of display backlight

can bring significant improvement in the battery life. The display luminous in-

tensity will be automatically adjusted depending on the external ambient light.

In that way, the load will be varied and not always used at full power. So the

selected Power Management Integrated Circuit (PMIC) topology should provide

good efficiency for wide range of load conditions.

Luminous intensity can be automatically adjusted through dimming. Dig-

ital dimming is implemented in this thesis work as digital dimming is preferred to

analog dimming while operating at low load currents [10]. The continuous current

through LEDs is controlled to adjust the brightness.

Presently, driving a mobile backlight display is a challenging domain to

work in due to its demand for high efficiency and accuracy. To achieve high

3

efficiency across a wide range of load, inductor-based synchronous converters are

highly recommended in backlight LED driver applications. Current matching

modules are needed to achieve accurate matching between strings of LEDs.

Vi1

Vi2

Current Matching Circuit

L Synchronous Boost Converter

ViN

Minimum

Voltage

Selector

(LTA)

PWM

Controller

VFB

VOUT

COUTVBATT

Figure 1.2: LED Driver Application.

1.3 Objectives and Unique Contributions

This thesis report is a DC-DC Synchronous Boost Converter implemented

as an LED driver in smartphone applications. A lithium ion battery is selected

as the input source. Its output voltage varies between 2.8 V and 4.2 V . The key

design criteria for this research work is to design a highly efficient boost converter

with the best possible current matching between LED strings. Additionally, a

third goal is to reduce the manufacturing cost by minimizing bill of material

(BOM) cost and chip area.

The unique contributions of this project are :

4

1. We published a sub-circuit of this design, a circuit known as a loser-take-

all in the paper ”A High Precision and High Speed Voltage-Mode Loser/Winner-

Take-All Circuit” at the IEEE Midwest Symposium on Circuits and Systems [13].

2. Several features of this design are firsts of the NMSU VLSI Laboratory:

(i) the first hysteretic-mode boost converter, (ii) the first continuous inductor

current sensing technique, and (iii) the first to use boundary-conduction mode

(BCM) control.

1.4 Report Organization

This thesis report is organized into four chapters, where:

Chapter 2 provides a literature review of the boost converter, emphasizing

those implemented in LED driver applications. Moreover, detailed control loop

and sub-circuit blocks for the hysteretic Boost converter are also discussed.

Chapter 3 presents the methodology used to design a Boost Converter

which operates over an input range of 2.8 V to 4.2 V . The proposed hysteretic

voltage-mode control loop with integrated current-mode feedback is discussed in

this chapter. All the sub-circuits that are modified from conventional circuit are

discussed here.

Chapter 4 contains simulation results and summarizes key results in sim-

ulation. Chip-level test procedures and measurement results are also given. The

details of layout size of sub-modules are also discussed in this chapter.

Chapter 5 summarises the fulfillment of thesis objective and compares this

work with other state-of-the-art works. After analysing the results, the areas for

improvement are identified and specified in future work.

5

Chapter 2

LITERATURE REVIEW

The increase in the usability of portable devices has brought significant changes

in the efficient design of power management circuits. The display block consumes

most of the power in these devices. This thesis work is focused on the design of a

highly efficient boost converter that drives and controls the LED display [3].

Portable devices are typically powered using Li-Ion batteries, which have

an operational range from 4.2 V down to 2.8 V. Blue and white LEDs have forward

voltage drops close to 3.3 V. Thus, any LED application with at least 2 blue or 2

white LEDs in series requires a boost converter to drive it.

2.1 Boost Converter

This section discusses voltage boost and energy storage mechanisms with

different modes of operation in a non-isolated boost converter [3]. Also, to improve

the converter performance in terms of efficiency, a synchronous boost converter is

used and its different phases of operation are discussed below.

2.1.1 Conventional Boost Converter

A boost converter is well known as a DC-to-DC step-up power converter

i.e. the input voltage is stepped-up to a higher level, as required by the load. As

shown below in Fig. 2.1, the power switch is controlled using Vc(t). When the

switch is ON, energy is stored in the inductor in the form of magnetic energy, as

the inductor current, iL increases. This energy along with input source is delivered

6

to the load with higher voltage during the OFF state. During this mode, the iL

decreases. So the input current is continuous, meaning it never goes to zero.

LOADC

VIN

Vout

SW

+

iin ioutiC

LiL(t)

VD

iD

+ -

-

+ -

Vc(t)

VL VSW

Figure 2.1: Conventional Boost Converter.

The duty cycle of the control signal Vc(t) determines the input current

through the switch. Duty cycle is defined as:

D =TON

TSW

(2.1)

where TON is the ON time of control signal Vc(t) and TSW is the period.

Equation for Vout in terms of Vin and D.

Vout =VIN

1 −D(2.2)

Variations in the input voltage VIN are compensated by varying the duty

cycle in order to maintain a constant output voltage. Alternately, you can solve

that equation for D.

D =Vout − VIN

Vout

(2.3)

7

Modes of operation in Boost converter:

A) Continuous conduction mode: The current through the inductor never goes to

zero between switching cycles, i.e., the inductor is only partially discharged for

each cycle.

B) Discontinuous conduction mode: The current through the inductor goes to

zero and stays zero for some portion of the switching cycle, i.e., the inductor is

completely discharged in each cycle. If the design enforces the inductor into charge

phase when the current reaches zero, it is known as Boundary Conduction Mode

(BCM).

The discharge current though the inductor depends on the load current,

switching frequency and pulse width of the power switch. To reduce the switch-

ing losses of the converter the uncontrolled diode switch can be replaced with a

controlled PMOS switch and is known as a synchronous boost converter.

2.1.2 Synchronous Boost Converter

The synchronous boost converter topology consists of two integrated switches

with an off-chip capacitor and inductor.

As shown in Fig. 2.2, the control signal used to drive the PMOS device is

an inverted signal generated from the gate signal of the NMOS transistor. RDCR

is the series dc resistance of the inductor (L) and RESR is the equivalent series

resistance of the output capacitor (COUT ) are included in the schematic.

The intersection node between inductor and the NMOS and PMOS tran-

sistors is labeled VSW . The power switches are controlled in two phases. As shown

in Fig. 2.3, during phase 1, the NMOS transistor (M1) is turned ON i.e. the node

VSW will be pulled close to ground voltage and the input energy is stored in the

inductor in the form of magnetic field. PMOS transistor (M2) is open during

8

VIN

Vout

+

M1

-

M2L

Vc(t)

Vc(t)

iout

ROUT

RESR

COUT

RDCR VSW

Figure 2.2: Synchronous Boost Converter.

phase 1. The ratio of the ON time, that is, the time of being in phase 1, to one

complete switching cycle is defined as the duty cycle (D).

VIN

Vout

+

-

L

iout

ROUT

RESR

COUT

RDCR

M1

M2

iLiin

iL

iout

VSW

Figure 2.3: Synchronous Boost Converter (ON State).

As shown in Fig. 2.4, during phase 2, the NMOS transistor (M1) is turned

OFF and then PMOS transistor (M2) is turned ON. The tiny interval between ON

and OFF times is known as dead time. Now the stored energy from the inductor is

9

delivered to the load through the PMOS device. Assuming boundary-conduction

mode (BCM), once the inductor is completely discharged to zero, the phase 1 is

activated and re-charges the inductor. The switching action between both the

phases is continuous in order to form a train of cycles and produces a desired DC

output voltage (VOUT ).

VIN

Vout

+

-

L

iout

ROUT

RESR

COUT

RDCR

M1

M2

iL

iin

iL

ic

VSW

Figure 2.4: Synchronous Boost Converter (OFF State).

2.2 Boost Control Loop

Every switching converter should be able to maintain constant output volt-

age regardless of changes in the input voltage, output current, temperature or

process. So a feedback control loop is implemented to track these changes in the

converter and control, or regulate, the output voltage precisely.

2.2.1 PWM Mode Control

Pulse width modulation (PWM) is the technique most widely used by

power converters. The switching frequency is held constant and the pulse width

is varied in this technique to control the output voltage. The average output

10

voltage delivered is proportional to the pulse width. (Only true of buck converter

- PMF)

Switching Converter

Compensator

Gate

Driver

-

+

-

+

R1

R2Comparator

Error

Amplifier

Vref

D

VFB

VE

Vout

Sensed

CurrentSlope Comp

Ramp

Figure 2.5: PWM Mode Control Scheme for DC-DC Converter.

As shown in Fig. 2.5, the Conventional PWM control system contains a

sensor gain block, an error amplifier, compensator, PWM comparator, and gate

driver. The output voltage (VOUT ) is sampled down using a resistor divider in the

sensor gain block. The sampled output signal VFB is compared with a reference

voltage Vref and the difference between them is amplified to create the error signal

(VE). This error signal is compared with an oscillator ramp signal to generate a

PWM signal that controls the state of the power switches. A change in duty cycle

changes the output voltage in such a way as to drive the feedback signal, VFB,

equal to the reference voltage, Vref .

11

The PWM technique achieves high efficiency during full load but the con-

verter suffers from low efficiency during light load conditions due to dominating

switching losses.

2.2.2 PFM Mode Control

Varying the ON time of a fixed frequency wave is not the only technique

to control the output voltage of the converter. It is also possible to vary the

frequency of the square wave and known as Pulse Frequency Modulation (PFM).

Switching Converter

Gate

Driver

-

+

R1

R2

Comparator

Vref

D

VFB

VE

Vout

Sensed

Current

Vbat

Q

QSET

CLR

S

R

Off-Time

Controller

Figure 2.6: PFM Mode Control Scheme for DC-DC Converter.

PFM mode operation has high efficiency as the regulator skips few cycles

during light load condition and reduces the switching losses. As shown in Fig. 2.6,

the ”off time controller” monitors the zero inductor current to define the rising

edge of the control signal and the voltage feedback monitors lower limit of output

ripple to define the falling edge of the control signal. Higher the load current,

increases the discharge rate of output capacitor and inductor and hence, faster

the PFM pulse happen. So the switching frequency of the converter is proportional

12

to the load current. PFM offers some advantages over PWM such as high power

efficiency during medium - light loads, low cost, low complexity due to no loop

compensation etc. But it is always challenging to design a PFM due to noise

frequencies generated across wide range of frequencies.

2.3 LED Driver Topologies in the Literature

The architecture shown in Fig. 2.7 is a synchronous boost converter for

LCD back-light application proposed in [2].

Figure 2.7: Energy Recycling Technology for Back light Unit [2].

To maintain a regulated output voltage, the power switches are controlled

through voltage and current mode feedback loops. Voltage loops consist of a

current balance circuit to achieve the highest current matching between strings,

an RVT (Reference Voltage Tracking) circuit that processes voltage drops across

the current balance circuit and an ON-time controller module. The voltage loops

generate control signals so that sufficient output voltage is achieved to maintain

the required voltage drop across the current balance circuit. The drop across RSEN

13

is used to monitor the current through the inductor for current-mode feedback and

to detect zero current for the Zero Cross Detector (ZCD). The ON-time controller

and ZCD allow operation of this converter in Boundary Conduction Mode (BCM).

This topology suffers from low efficiency due to continuous I2R loss across RSEN .

The higher the input current, the lower the efficiency.

The double-loop control LED driver of Fig. 2.10 uses voltage and current

mode feedback loops to maintain a regulated output boost voltage, as proposed

in [3].

Figure 2.8: Double-Loop Control LED Driver [3].

The voltage loop includes a reference voltage known as an adaptable ref-

erence voltage (VAREF ). This loop processes the lowest voltage across the current

matching circuit and the output voltage is maintained to achieve sufficient head-

room across the current matching module. The 2nd voltage loop samples the

14

output voltage to closely monitor and control the ripple across VOUT . This feed-

back scheme doesnt monitor inductor or input current. So any sudden change

in input current is not tracked. Implementation of the frequency compensator

consumes high layout area.

2.4 Hysteretic Boost Converter in the Literature

As shown in Fig. 2.9, the hysteretic voltage-mode and current-mode feed-

back technique can be implemented to overcome the technical drawbacks from the

above two LED driver topologies. In particular, lossless inductor current monitor-

ing is achieved and reduced layout area due to the lack of frequency compensation

circuit [4]. The inductor charging current is sampled across the NMOS transistor

and the discharge current across the PMOS transistor. So there is no series RSEN

integrated in this implementation. Implementation of comparators in the voltage

loop eliminates amplifiers and frequency compensation networks.

Figure 2.9: Current Mode Hysteretic Control [4].

15

Due to comparative advantages, this feedback topology is selected as a

suitable implementation for LED driver application. The detailed description of

sub-modules in the feedback loop are discussed in the following sections.

2.5 Current Mirrors and Current Matching

Multi-string LED driver architectures need a current matching circuit to

maintain the same current in all of the LED strings. Most topologies from the

literature uses cascode current mirror techniques to precisely match the currents

in all strings [3]. The higher the voltage headroom of the current matching cir-

cuit, the better the performance of the current matching function; however, the

efficiency of the power converter degrades, since VOUT is higher than necessary.

If VOUT is too low, one or more of the LED strings would have reduced current

compared to the others. So it is challenging for every architecture to ensure that

the VOUT is minimally sufficient so as to achieve high current matching.

The double-loop control LED driver of Fig. 2.10 uses regulated cascode cur-

rent mirrors to maintain constant current through individual channels. If same

resistance is used from RS1 to RSn then regulated cascode forces individual chan-

nels to operate at same channel currents from ICH1 to ICHn. The digital dimming

is implemented by controlling input signal of regulated cascode with a square

wave.

To achieve better current matching with higher output impedance, a cas-

code current mirror is highly recommended. But in an applications like driving

multi-string LEDs it is very important to maintain very low output voltage com-

pliance to achieve better efficiency. The schematic in Fig. 2.11 from [5] is selected

as suitable implementation of a current mirror due to its high output impedance

and low headroom voltage requirement.

16

Figure 2.10: Double-Loop Control LED Driver [3].

VDD

VSSM4

M5

IBIOUT

M2

IB

IIN =

10*IB

M1 M3

Figure 2.11: High Output Impedance and Low Output Voltage Current Mirror

Circuit [5].

17

The operation of the current mirror circuit in Fig. 2.11 is as follows. The

circuit maintains M2 and M4 at same VDS so that identical drain to source currents

are achieved. The output transistor M7 is added to compensate for the influence

of the input current source IIN . Even if the output transistor M7 enters the

triode region, high loop gain is maintained from the drain of M4 to the gate of

M7, maintaining high output resistance. Designing IB ten times smaller than IIN

insures M2 and M4 are always on the edge of saturation.

2.6 Minimum or Lowest Voltage Selector

Minimum voltage selector circuits are well known as LTA (Loser-Take-All)

circuits. LTA’s are gaining importance in multi-string light emitting diode (LED)

driver applications in order to achieve maximum efficiency with precise current

matching [6]. LTA circuits find the lowest node voltage from given inputs. It

compares all the input voltages and the lowest of them will be selected as the

output. LTAs can be implemented using different topologies such as common

drain amplifiers, comparators, flipped voltage followers, or multiplexers. The

performance analysis between these topologies is compared in [6]. Circuits that

function opposite to LTAs are know as WTAs (Winner-Take-All).

Minimum Voltage Selectors in the Literature:

The LTA circuit shown in Fig. 2.12 is based on a voltage follower config-

uration. A multiple-input differential pair is implemented by placing n NMOS

transistors in parallel on one side of the differential pair and their inputs are V1

to Vn. The other side of the differential amplifier is connected to output Vo,

which provides unity-gain feedback to the amplifier. This design has good perfor-

18

Figure 2.12: Loser-Take-All Circuit [6].

mance, high speed and load driving capability, but suffers from stability issues.

Compensation for each cell is required, which increases the die size.

To eliminate the module die size requirement this thesis work also focused

to redesign minimum voltage selector module to achieve high precision and high

speed LTA with less die size.

2.7 Hysteretic Comparator

Hysteresis in a comparator is the difference between two inputs at which

the output state transition happens. This is a three-stage comparator implemen-

tation i.e. preamplifier, decision circuit, post amplifier. Preamplifier increases the

sensitivity of the comparator by amplifying input signal and also helps to isolate

noise between input and decision stage. Decision stage uses positive feedback to

compare input signals. This type of feedback improves the processing time. The

decision information is amplified by the post amplifier and converted into digital

signal. Various design parameters that are considered during comparator design

are input common mode range, propagation delay, comparator gain and power

dissipation.

19

VDD

VIN-VIN+

M10

VSS

VOUT

M9

M13

M7

M1

M11

M2

M5 M6

M3 M4 M8

M12VBIAS

Figure 2.13: Comparator with Positive Feedback Decision Circuit [7].

The circuit shown in Fig. 2.13, contains a differential pair M1 - M2 with

diode-connected loads M3 - M4. Transistors M5 - M6 creates the positive feedback.

The hysteresis band can be varied by changing the relative dimensions between

M5 - M6 to M1 - M2. In particular, reducing M5 - M6 reduces the amount of

positive feedback and hence, the amount of hysteresis [7] [13].

2.8 SR Latch

Latches are frequently used as data storage elements. A latch can store one

bit of digital data. The SR (set-reset) latch implemented in Fig. 2.14 is a sequential

logic circuit using two NOR gates. The two inputs S and R are designed for set

and reset function. The output of one NOR gate is fed back as the 2nd input to

opposite NOR gate and vice versa.

Outputs Q and Qbar are supposed to be in opposite states because comple-

mentary signals should never be at same state. This invalid condition can occur

when both inputs are high, so S=1, R=1 is categorized as an invalid state. When

S is high, it is referred as the set state and Q goes high. The function of a latch

20

VDD

VSS

M2

M1

M3

S

M4

M6

M5

M7

R

M8

QQbar

Figure 2.14: SR Latch using two NOR Gates.

occurs when both inputs are low i.e. it holds the previous state of Q and Qbar.

These different states of outputs Q and Qbar due to input changes S and R are

tabulated as a truth table below.

Table 2.1: Truth Table of SR Latch using NOR Gates.

S R Q Qbar

0 0 latch latch

0 1 0 1

1 0 1 0

1 1 0 0

2.9 Non-Overlapping Clock Generator

Generation of synchronized signals that drive the power switches in a con-

verter is critical. Switching losses in the power converter will increase due to

21

improper selection of dead time and/or rise and fall time of the synchronized

signals to drive the gates of the power MOSFETs.

CLKINPh1

Ph2

Ph1_bar

Ph2_bar

Figure 2.15: Nonoverlapping clock generation circuit [8].

DTs

Ts0

VDD

V

t

(1-D)Ts

Ts0

VDD

t

Ph1

Ph2

Dead t ime

tdf tdr

Figure 2.16: Waveforms of non-overlapping clock generator [8].

The circuit in Fig. 2.15 shows the NAND-gate implementation of an SR-

latch structure. The series of inverter stages helps to creates dead time between the

output signals [8]. During dead time the circuit generates output signals such that

both the NMOS and PMOS power switches are OFF and shoot-through current

22

is eliminated. As the dead time is a delay, higher dead time will eventually slow

down the control loop. So it is recommended to use dead time as approximately

1% of the signal period. Output signals Phi1 and Phi2 are the two phase clock

signals that are non-overlapped. Their complements are also generated.

As shown in Fig. 2.16, the dead time before the rising edge of Ph2 is known

as tdr and after the falling edge of Ph2 tdf . The signals Phi1 and Phi2 bar are used

to drive the NMOS and PMOS power transistors respectively. The complementary

signals Phi1 bar and Phi2 are used in the level shifter module.

2.10 MOS Gate Drivers

The output pulse signal from a non-overlapping clock generator will not

have sufficient drive strength to drive the gate capacitance of the power switch.

So a gate driver that can drive a higher load capacitance is designed to achieve

better performance.

As shown in Fig. 3.7, series-connected inverter stages are used to increase

the drive strength. An even number of stages is implemented to maintain input

and output signals at the same phase. The individual stage is designed to maintain

a scale factor ratio S of eight to ten times between input and output capacitance.

2.11 Level Shifters

To achieve a faster feedback loop, the feedback control system is designed

using 1.8 V devices. So the output signals from the feedback system are not

compatible to drive 5 V domain power switches. Therefore level shifters are used

to solve the incompatibility between different power domains.

As shown in Fig. 2.18, gate cross-coupled level shifter is used. The input

signal VIN swings between 1.8 V and 0 V and this signal experiences two inversions

23

VDD

VSS

VOUTVIN

M1

M2

M3

M4

M5

M6

M6

M7

1 S S3

S2

Figure 2.17: MOS Transistor Gate Driver with scale factor S.

VSS

VOUT

VIN

M4

M6

VDDH

M5

M3

VOUTB

VINB

VOUT

Figure 2.18: Level Shifter.

from gate of M3 to drain of M6 makes VOUT to follow VIN with same phase. So

the output signal swings between VDDH and VSS

24

2.12 Inductor Current Sense Module

The inductor current sense module is implemented to continuously track

the current through the inductor and protect from over-current. A conventional

implementation integrates a series resistor with the inductor and monitors the

voltage across the resistor to track the inductor current, but this implementa-

tion leads to a lower efficiency of the converter [9]. An efficient way to monitor

continuous inductor current in a boost converter can be implemented by monitor-

ing the charging current through the NMOS transistor and the discharge current

through PMOS transistor. A ratio-sensing transistor can be placed across the

power switches with the same channel length and width ratio of N:1, where N is

typically 1000. In that way, the sensed current is a tiny fraction of the inductor

current.

As shown in Fig. 2.19, the gate and source terminals of the sensing tran-

sistor M1 and M7 are shorted with the gate and source of power switches M9

and M3, respectively. Differential source-input high-gain amplifier are used to

maintain drain terminals at the same potential. The sensed current is copied into

a resistor Rs. The voltage drop across Rs is proportional to the sensed current.

This architecture is presented in the work of [9].

2.13 Zero Cross Detector

Protection of a converter from entering into DCM is done by detecting

zero current in the inductor. After detecting zero current through the inductor,

the PMOS transistor is turned OFF and the NMOS transistor is turned ON to

recharge the inductor. Through this implementation the reverse current that can

flow back to the input power supply can be eliminated. Boundary Conduction

Mode (BCM) is maintained since the NMOS transistor is turned ON immediately

after the PMOS transistor is turned OFF.

25

VD

D

M4

VS

S

VO

UT

M3

M1

M5

M10

VS

W

CLK

NM

OS

VX

I BIA

S

M9

M1

M1

CLK

NM

OS

N :

1

M4

M4

RS

i com

p

RD

um

my

i O

VO

UT

M4

VS

S

M3

M1

M5

CLK

PM

OS

I BIA

S

M7

M6

M3

CLK

PM

OS

1 :

N

M6

M1

i com

p i Oi N

MO

S

i PM

OS

+

VS

W

Figure 2.19: Full Range Inductor Current Sensor [9]..

26

VOUT

M3

VSS

C

M2

M4 M5

IBIAS

M1

M6

M7

M8

M9

M10 M11

M12 M13

A

B

S

SVSW

S

S

Figure 2.20: Zero Cross Detector [9]..

As shown in Fig. 2.20, the input voltages VSW and VOUT are compared

to detect zero current through the inductor and series PMOS switch. After zero

inductor current is reached, the load capacitor tries to discharge through the

PMOS transistor. Therefore the potential at VSW becomes slightly higher than

VOUT . This difference is detected and processed as a select line for transmission

gates. The default state for S is low and output C equals input B. During zero

inductor current, S goes high and input A is selected as output C.

2.14 Dimming

The luminous intensity from the LEDs is proportional to the conduction

current flowing through it. The two methods used to control this current are

analog and digital dimming. The LED driver is a current regulator and output

current is regulated to different values during analog dimming. The efficiency of

the converter degrades during low load currents using analog dimming. Addition-

ally, analog dimming is prone to color shifting [10]. Hence, digital dimming is

more preferred in most of the LED driver applications. During digital dimming

27

the LED driver is periodically switched to turn ON and OFF the load at a high

frequency.

Rst

C0

C1

C9

Dim_sel<3:0>

Clk

C0

C1

C2

C3

C4

10 bit

Counter

Clk 10x1

MUX

(a)

(b)

Dim_ctrl

Dim_ctrl

Figure 2.21: Digital Dimming [10]..

The top level architecture of digital dimming is shown in Fig. 2.21. This

dimming architecture is implemented from the work presented in [10] and consists

of a 9-bit counter, a 10-to-1 multiplexer and an output buffer. The 9-bit counter

generates different dimming signals and a 10-bit multiplexer (MUX) is used to

select the appropriate dimming signal, depending on the user input. The 4-bit

binary select lines are used to select any one of 10-input lines as output.

Ten dimming ratios are generated ranging from 1:1 to 512:1. The 9-bit

counter is implemented using 9 half-adders and 9 D-flipflops. The carry outputs

C1 −C9 from each half-adder create fixed ON times with different OFF times, as

shown in Fig. 2.21. The signal C0 is a logic high DC signal selected during the no

dimming condition and signal C9 is selected during maximum dimming condition

i.e. the dimming ratio is 512:1, which means the signal is ON for 1-cycle and OFF

for the other 511 cycles. The dimming signal Dimctrl turns ON and OFF the

LED load and it is also used to switch OFF the control loop during dimming to

28

reduce the power losses. As the Dimctrl is an input to many modules, a buffer is

used at the output to increase the drive strength of the dimming signal.

It is relatively easy to implement digital dimming technique but the driver

performance during load transient should be acceptable to the application.

29

Chapter 3

DESIGN AND BLOCK-LEVEL SIMULATIONS

The objective of this thesis work is to design an effective driver topology that can

be implemented in multi-string LED applications. The key requirement in any

LED driver domain is to achieve a highly efficient boost converter with the best

possible current matching.

Maintaining constant current between strings helps to achieve constant

luminous intensity between LEDs in the different strings. So the designed driver

should be a constant current source, whereas the output voltage is allowed to vary

depending on the LED forward voltage drop.

3.1 Design Specifications

This LED driver is designed using IBM 0.18 µm technology. The maximum

voltage of devices in this technology limits the number of series-connected LEDs

to two; as such, we propose to drive a five parallel strings of two LEDs each.

Due to five parallel strings, with each string requiring 20 mA of constant

current, 100 mA is the output current specification. The input Lithium-Ion bat-

tery voltage varies from 2.8 V - 4.2 V. The target efficiency is > 90% at a 5 MHz

operating frequency. The maximum required dimming ratio is 1:512. All the input

specifications for this design are summarized in table 3.1.

3.2 Boost Converter Design

The input specifications for the boost converter design are derived from the

above design specifications. This is a synchronous design that uses only switches.

30

Vi1

Vi2

Current Matching Circuit

L Synchronous Boost Converter

Vi5

Minimum

Voltage

Selector

(LTA)

PFM

Controller

VFB

VOUT

COUTVBATT

Figure 3.1: LED Driver Application.

Table 3.1: Boost Converter Specifications.

Technology IBM 180 nm CMOS process

Input Voltage 2.8 V - 4.2 V

Output Voltage 5.4 V

Output Current 100 mA

Switching Frequency 5 MHz

Efficiency > 90%

Dimming Ratio 512 : 1

The detailed switching operation of the synchronous boost is discussed in sec-

tion 2.1.2.

Applying KVL during ON and OFF states, the voltage drop across inductor

results in below equations:

vL,ON = VIN − VSW

31

vL,OFF = VIN − VOUT − VSW (3.1)

where vL,ON is the voltage drop across inductor during ON-state and vL,OFF is

during OFF-state. VIN ; VOUT ; VSW are the input voltage, output voltage and the

Vds drop across MOS transistor respectively. Since the average voltage across the

inductor for one period is zero, therefore,

< vL > =vL,ONDTs + vL,OFF (1 −D)Ts

Ts

= 0 (3.2)

Solving for VOUT in (3.2), we obtain

< VOUT > =VIN

(1 −D)(3.3)

Additionally, we can solve for duty cycle (D) in (3.2), to get

D =VOUT − VIN

VOUT

(3.4)

Since the duty cycle is 0 < D < 1 the output voltage VOUT is always higher than

VIN .

3.2.1 Inductor Value Calculation

The inductor values should be selected so that converter operates in bound-

ary conduction mode (BCM) for the given operating frequency. The term <

iL >crit is the critical average inductor current. Critical implies that the inductor

is at the boundary between continuous conduction mode (CCM) and discontinu-

ous conduction mode (DCM), which is exactly where we are choosing to operate.

During the ON time DTs the inductor is in charging mode and input voltage

VIN − V SW is across the inductor. During OFF time (1 − D)Ts the inductor

discharges and the voltage across the inductor is VIN − V OUT − V SW .

The following parameters should be defined before calculating inductor

value. i) Ripple current ∆iL, ii) Input voltage VIN , iii) Duty cycle, and iv)

32

0Ts

ΔiL<iL>crit

t

iL

imax

0Ts t

VL

DTs

VIN-VSW

(1-D)Ts

VIN-VOUT-VSW

Figure 3.2: Inductor Voltage & Current Waveforms while Operating in BCM.

Switching frequency. According to Faraday’s Law the voltage across inductor

can be calculated from

vL = L× diL(t)

dt≈ L× ∆iL

∆t(3.5)

where vL is the voltage drop across inductor and equal to VIN during ON-state

and diL(t) is the ripple current. Here dt is the ON-time and it is defined as ratio

between the duty cycle D and switching frequency Fsw.

To calculate the value of the inductor from (3.5), the ripple current is still

unknown, whereas VIN and Fsw are taken from design specifications and duty

cycle (D) can be calculated using (3.4).

The amount the inductor current changes during a given switching cycle

is known as the ripple current. The ripple current in BCM is defined as:

∆iL = 2 × < iL > (3.6)

33

where the average iL (< iL >) is derived from (3.7).

< iL >=iOUT

1 −D(3.7)

In a boost converter, as the inductor is connected in series with the input

voltage source, the input current is equal to inductor current. The duty cycle

varies with variations in the input voltage and affects the amount of energy stored

in the inductor. So the inductor should be selected to deliver sufficient load current

at the minimum input voltage. Solving for inductance (L) in (3.5), we obtain

L =VIN D Ts

2 < iL >(3.8)

For the highest efficiency it is recommended to use an inductor with low

DC resistance. The inductor saturation current should be always greater than

the peak switching current. Exceeding the rated peak current will result in core

saturation, heating of the inductor and power losses.

3.2.2 Capacitor Value Calculation

The output voltage VOUT is equal to the voltage across the output capaci-

tor. The average DC current through the capacitor is zero but the AC current will

flow through the capacitor as it exhibits low impedance to high frequency com-

ponents. Hence the output ripple voltage across the output capacitor depends on

the capacitance value (C) and the ripple current through it.

∆VOUT =1

C

∫ DTs

0

ic(t) dt (3.9)

Higher capacitance lowers the output ripple but the system loop response will be

slowed and vice-versa.

In a boost converter, the output capacitor sources the required load current

iOUT during the ON state DTs. After integrating the amount of current discharged

34

from capacitor during the period from 0 to DTs, we obtain

∆VOUT =1

CDTs < iOUT > (3.10)

0

Ts

ΔiL

t

iC

imax

-iOUT

0

Ts

ΔVC

t

VC

<VC>

VC = VOUT

Capacitor

Voltage

Capacitor

Current

Figure 3.3: Inductor Current at the Boundary of CCM and DCM.

The voltage and current waveforms of the output capacitor are shown in

Fig 3.3. The ∆VC is the ripple voltage across the output capacitor, equal to the

output voltage ripple.

There is a parasitic DC resistance associated with all the capacitors known

as Equivalent-Series-Resistance (RESR). As RESR is connected in series with the

inductor, the voltage drop across RESR is RESR times the current flowing into the

capacitor. Therefore the effective voltage ripple is approximately given as

∆VOUT =1

CDTs < iOUT > + < iL > RESR (3.11)

After accounting the effect of RESR, the resultant voltage and current

waveforms across the output capacitor are shown in Fig 3.4. During the ON state

35

0

Ts

ΔiL

t

iC

imax

-iOUT

0

Ts

ΔVC

t

VC

<VC>

VC = VOUT

Capacitor

Voltage

Capacitor

Current

RES R drop

Figure 3.4: Inductor Current at the Boundary of CCM and DCM.

to OFF state transition in the converter, the sudden change in capacitor current

occurs. This change in current times the RESR results as the DC shift on the

capacitor voltage.

The capacitor and inductor values used in this thesis work are 1 µH and

220 nF, respectively. Even though off-chip components are preferred due to re-

duced component value tolerance and the ability to achieve high component val-

ues.

Table 3.2: Inductor and Capacitor Design Values.

Component Value

Inductor 1 µH

Capacitor 220 nF

36

3.3 Power FETs sizing

Optimum power device sizing is influenced by the device losses. The de-

vices that significantly contribute to power losses in a DC-DC converter are the

power switches (PFET and NFET). The losses in any FET can be divided into i)

Conduction Loss and ii) Switching Loss. Conduction loss is due to the finite on-

resistance (Rds (ON)), whereas switching loss is due to the parasitic capacitances

of a MOSFET.

VIN

Vout

+

M1

-

M2L

Vc(t)

Vc(t)

iout

ROUT

RESR

COUT

RDCR

iM1

iM2VSW

iL

ic

Figure 3.5: Synchronous Boost Converter.

As shown in Fig. 3.5, during the ON time, the NMOS transistor is switched

ON. The inductor charging current flows through the on-resistance of the NFET,

causing power dissipation in that resistor which accounts for conduction loss.

When the PMOS transistor is turned ON during the converter OFF time, the

inductor discharge current flows through the PFET, causing PFET conduction

loss. These losses can be calculated from the equations below. RMS values of a

ramp waveform are derived at [14].

Pcond(NMOS) = i2M1,rmsRds(ON)NMOS =i2PRds(ON)NMOS D

3

37

Pcond(PMOS) = i2M2,rmsRds(ON)PMOS =i2LRds(ON)PMOS (1 −D)

3(3.12)

where Pcond(NMOS) and Pcond(PMOS) are the losses of NFET and PFET devices,

respectively and iP is the peak inductor current.

Conduction losses are dissipated as heat energy into the environment. Ad-

ditionally, it also increases the junction temperature of the device. So the higher

the conduction losses the greater need for external thermal management tech-

niques to operate the devices at a safe temperature.

While implementing the switching function using power devices it takes

finite time to turn the MOSFETs ON or OFF. This finite time is due to the time

needed for charging and discharging of gate-drain (Cgd) and gate-source (Cgs)

capacitances of the MOSFETs. See Fig. 3.6.

Vout

M1

M2

Vc(t) Vc(t)

VSW

Cdb

_N

MO

S

Cdb_PMOS

Dbody

L

Figure 3.6: Paracitic Components for Power Switches.

38

The total effective gate capacitance Cg is the sum of gate-source (Cgs) and

two-times the gate-drain (Cgd) capacitance. The factor of two is due to the Miller

Effect [8] on capacitance Cgd, which sees a voltage change of 2 VIN across its

terminals. Therefore the switching loss at the gate can be approximated as

Psw,g = Cg V 2IN fsw (3.13)

where Psw,g is the switching loss at the gate, Cg is the effective gate capacitance,

VIN is the input voltage and fsw is the switching frequency.

As shown in Fig 3.6, the intersection node of NMOS and PMOS switches,

VSW will experience the high parasitic capacitance. The gate-drain (Cgd) and

drain-to-body (Cdb) parasitic capacitance of both the power switches are added

to create the total capacitance at switching node VSW . The switching losses at

node VSW , connected to the drains of the two MOSFETs, are given by

Psw,d = 0.5Cd V 2OUT fsw (3.14)

where Cd = Cdb,NMOS + Cdb,PMOS + Cgd,NMOS + Cgd,PMOS, and the factor 0.5

occurs because charging capacitance Cd is done by the inductor, not a switch.

Switching losses due to the power FETs can be summarized as:

Psw = Psw,g + Psw,d (3.15)

Decreasing the device size will reduce the parasitic capacitance but increase

the on-resistance of the FET as Rds(ON) is inversely proportional to width of

the FET. Therefore, the larger the device size will reduce the on resistance of the

device but increase the parasitic capacitance. In such cases it will slow down the

signal transitions and result in reduced dead-time.

Along with the above losses there are body diode losses during dead time.

These are also known as dead time losses. As both the power switches are OFF

39

during dead time, the inductor creates a discharge path though the body diode of

the PMOS transistor, shown as Dbody, in Fig. 3.6. These losses can be calculated

as

Pdiode = VBDIOUT

(1 −D)2 (tDEAD) (fsw) (3.16)

where VBD is the body diode voltage of the PFET, approximately 0.7 V, fsw is

the switching frequency, tDEAD is the dead time between MOSFET transitions,

assumed to the be same, and IOUT is the output load current.

Conduction losses can be summarized as:

Pcond = Pcond(NMOS) + Pcond(PMOS) + Pdiode (3.17)

In order to achieve high efficiency both the losses should be balanced.

So the best optimized point to operate is when conduction losses are equal to

switching losses. The size (width) of the FET which satisfies the above equal loss

condition is considered the optimum size.

Here, as the output and input voltages are greater than the regular supply

voltage of 1.8 V in the IBM 180 nm process, 5 V devices from the same technology

are used to withstand the higher output voltage. Such devices have higher gate-

oxide thickness. As such, the minimum gate length of the NMOS transistor is

0.7 µm and for the PMOS transistor it is is 0.6 µm.

Power switch device sizes for this thesis work are shown in Table 3.3. Be-

cause the mobility of holes is approximately one-half that of electrons deep in

triode, the PFET is sized approximately twice that of the NFET.

3.4 Power MOSFET Gate Driver Sizing

Series connected inverter stages are used to increase the drive strength and

an even number of stages are implemented to maintain input and output signals

40

Table 3.3: Power MOSFET Sizing.

MOSFET Sizes (W/L) m

NFET 15m/0.7µ

PFET 30m/0.6µ

at the same phase. As shown in Fig. 3.7, four series inverter stages are used. A

scale factor of S is maintained between each stage.

VDD

VSS

VOUTVIN

M1

M2

M3

M4

M5

M6

M6

M7

1 S S3

S2

Figure 3.7: MOS Transistor Gate Driver.

The detailed MOSFET sizing of individual inverter stages is captured in

table 3.4. Here, a device ratio of four times is maintained between NMOS tran-

sistor to PMOS transistor. Individual stages are designed to maintain a scale

factor ratio S of eight to ten times between input and output capacitance i.e., the

inverter drive strength is increased by eight to ten times from stage to stage.

41

Table 3.4: Sizes of the MOSFETs used in Current Matching Circuit.

MOSFET Sizes (W/L) m

M8 1.2m/0.7µ

M7 300µ/0.7µ

M6 96µ/0.7µ

M5 24µ/0.7µ

M4 8µ/0.7µ

M3 2µ/0.7µ

M2 4µ/0.7µ

M1 1µ/0.7µ

3.5 Hysteretic Voltage Mode Control

Voltage mode control helps to directly track and control the output volt-

age of the converter. As shown in Fig. 3.8, the voltage drop across the current

matching circuit is sampled and processed as a feedback voltage. In an application

like multi-string LEDs it is more critical to maintain the highest current match-

ing between all the strings. This can be achieved when every individual string

is biased with sufficient headroom voltage across the current matching circuit.

So the minimum headroom voltage among voltages Vi1–ViN is detected using the

minimum voltage selector block and used as a feedback voltage VFB. The voltage

comparator generates an output signal by comparing the feedback voltage with a

predefined reference voltage V REF . A low-to-high transition in the voltage com-

parator output initiates the turning OFF of the PFET power switch and turning

ON of the NFET power switch. The other transition, that is the turning OFF

42

of the NFET power switch and the turning ON of the PFET power switch is

controlled by the current limiting comparator.

Current Limiting Comparator

Drive

rRDCR L

RESR

COUT

VBATT

ViFB

OFF-Chip

OFF-Chip

VSWVOUT

Q

QSET

CLR

S

R

Inductor Current Sense

Voltage Comparator

Drive

r

VLIM

VREF

VFB

ViFB

CLK

CLK

0 1 Zero Current

VZERO Vi1

Vi2

Current Matching

Circuit

ViN

Minimum

Voltage

Selector

(LTA)

VOUT

VSW

VOUT

dim

_ctrl

Non-OverlapClk Gen d

im_

ctrl

dim

_ctrl

Level Shifter

Level Shifter

Figure 3.8: Hysteretic Voltage Mode Control Loop Implementation.

This feedback topology can be described as a clockless voltage and current

mode negative feedback control loop. The frequency of switching at node CLK

varies with the load current and input voltage. The nominal switching frequency

is 3.5 MHz. In order to avoid unwanted shoot-through current through power

switches and to decrease switching losses of the parasitic diode at node VSW , a

non-overlapping clock generator is used.

As shown in Fig. 3.8, level shifters are used to interface 1.8 V feedback

domain and 5 V power switches. To achieve a faster feedback loop, the feedback

control system is designed using 1.8 V devices. Gate driver modules are used

to drive the huge gate capacitance of NMOS and PMOS power switches. As

discussed in section 3.4 series-connected inverter stages are used to increase the

drive strength.

43

3.6 Hysteretic Current Mode Control

To limit the input current, the inductor current is continuously tracked

using the inductor current sense module. As the inductor L is connected in se-

ries with the input source VIN , the inductor current is continuously monitored

and maintained below the maximum peak current and above zero current. The

maximum current is predefined by the value of VLIM and the current limiting

comparator continuously compares the sensed inductor current ViFB and VLIM . A

low-to-high transition in the current limiting comparator will reset the SR latch

and results in the turning OFF of the NFET power switch and turning ON the

PFET power switch.

Detecting zero current protects the inductor current from becoming neg-

ative. After detecting zero current through the inductor, the PMOS transistor

is turned OFF and the NMOS transistor is turned ON to recharge the induc-

tor. Through this implementation the reverse current that could flow back to the

power supply can be eliminated. As shown in Fig. 3.9, to sense the peak inductor

current and zero current, a continuous full range inductor current sense monitor is

implemented. Integrating the current mode control inside the control loop helps

to improve the loop stability and loop response.

The integrated voltage and current mode control loop for the synchronous

hysteretic converter is shown in Fig. 3.10. Signal dim ctrl is implemented as an

enable signal for various modules to disable these modules during dimming and

reduce static power losses to zero in the feedback loop.

3.7 Minimum Voltage Selector

To overcome the compensation issues discussed in section 2.6, the below

novel mixed-signal LTA circuit is proposed that has high accuracy and high speed

with low power consumption. It is suitable for LED driver applications. LTAs are

44

Current Limiting Comparator

Drive

r

RDCR L

RESR

COUT

VBATT

ViFB

OFF-Chip

OFF-Chip

VSWVOUT

Inductor Current Sense

Voltage Comparator

Drive

r

VLIM

VREF

VFB

ViFB

CLK

CLK

0 1 Zero Current

VZERO Vi1

Vi2

Current Matching

Circuit

ViN

Minimum

Voltage

Selector

(LTA)

VOUT

VSW

VOUT

dim

_ctrl

Non-OverlapClk Gen d

im_

ctrl

dim

_ctrl

Level Shifter

Level Shifter

Q

QSET

CLR

S

R

Figure 3.9: Hysteretic Current Mode Control Loop Implementation.

Current Limiting Comparator

Drive

r

RDCR L

RESR

COUT

VBATT

ViFB

OFF-Chip

OFF-Chip

VSWVOUT

Q

QSET

CLR

S

R

Inductor Current Sense

Voltage Comparator

Drive

r

VLIM

VREF

VFB

ViFB

CLK

CLK

0 1 Zero Current

VZERO Vi1

Vi2

Current Matching

Circuit

ViN

Minimum

Voltage

Selector

(LTA)

VOUT

VSW

VOUT

dim

_ctrl

Non-OverlapClk Gen d

im_

ctrl

dim

_ctrl

Level Shifter

Level Shifter

Figure 3.10: Hysteretic Voltage and Current Mode Control Loop Implementation.

gaining importance in multi-string light emitting diode (LED) driver applications

in order to achieve maximum efficiency with precise current matching. As shown

in Fig. 3.11, a hysteretic comparator is used as the basic block in the design of

the proposed LTA. Hysteresis is created in comparators via positive feedback.

45

M1

VDD

IBIAS

Vi2

V2

Vi1

V1

M2

M3 M4M6M5

VSS

V1V2

Figure 3.11: Schematic of High Speed Hysteretic PMOS-Input Comparator Stage.

The bias current IBIAS used in this design is 20 µA and the detailed MOS-

FET sizing is captured in Table 3.5. The length is selected as 2 times the minimum

length in the process.

Table 3.5: Hysteretic Comparator MOSFET Sizes.

MOSFET Sizes (W/L) m

M1 & M2 20µ/0.36µ

M3 & M4 2µ/0.36µ

M5 & M6 2µ/0.36µ

Without loss of generality, assume input voltage Vi1 is lower than Vi2. Then

the current in M1 is greater than M2. Diode-connected transistor M3 mirrors the

higher current to node V2 through positive feedback transistor M6. Since the

sinking current from V2 is higher than the sourcing current, the voltage at node

V2 pulls down close to VSS. This turns OFF transistor M5 and maintains node V1

at one VGS above VSS. Now, when Vi1 goes higher than Vi2 then the current in

46

M1 becomes lower than M2. But the nodes V1 - V2 will not change immediately

because of the extra current in positive feedback transistor M6. Until the current

in M2 exceeds that in M1 by the extra current through M6, voltages V1 - V2

will not shift. This behavior provides hysteresis in the comparator. The relative

dimensions of M5 - M6 to M3 - M4 sets the hysteresis band of the comparator. In

particular, reducing M5 - M6 reduces the amount of positive feedback, hence, the

amount of hysteresis. Since this comparator uses a PMOS input transistors, the

winner in current will be the loser in input voltage.

IBIAS

V1 V2 VN

ViN

Cell-N

V1 V2 VN

Vi2

Cell-2

V1 V2 VN

Vi1

Cell-1

Vi1

Vi2

ViN

VOUTN x 1 MUX

S1 S2 SN

S1

V1 V2 VN

S2 SN

IBIAS

N

IBIAS

N

IBIAS

N

NMOS Common-Source Amplifiers

(a)

LTA

Figure 3.12: Top level schematic of the proposed N-input Loser-Take-All (LTA).

A top-level schematic of the proposed N -input LTA is shown in Fig. 3.12.

It consists of an N -cell core LTA circuit, N common-source amplifiers with in-

47

verters and an N x 1 multiplexer. Each cell is a half-sided circuit of the PMOS

comparator. It has one diode-connected transistor and (N − 1) positive feedback

transistors from the other (N − 1) cells. All cells have a common bias current.

The operation is similar to that of the comparator. The cell with the lowest input

voltage among Vi1 to ViN will have a detection voltage V1 to VN that is one VGS

above VSS. The other (N − 1) cells detection voltages will be pulled down to

VSS. The common-source amplifiers with bias currents equal to IBIAS/N generate

select lines S1 to SN based on the values of V1 to VN from the core block. The

lowest input among Vi1 to ViN is passed to the output using an N ×1 multiplexer.

The multiplexer is designed using N NMOS pass transistors.

Figure 3.13: Top level schematic of the proposed N-input Loser-Take-All (LTA).

Replacing the comparator cells with NMOS input transistors and PMOS

transistor loads, the common-source amplifier with PMOS input transistors, and

the MUX with PMOS pass gates modifies the proposed LTA into a voltage-mode

winner-take-all (WTA).

48

The DC characteristic of a 2-input LTA are evaluated by sweeping one of

the inputs (Vi1) and changing the second input voltage (Vi2) in steps. Performing

these DC sweeps determines the input voltage range of the circuit. The Fig 3.13(a)

and 3.13(b) shows the simulated results sweeping the LTA and WTA, respectively.

In the LTA simulation, input Vi1 is swept from 0 to 1.0 V at different Vi2 voltages

from 0.1 to 0.9 V with a fixed step size of 0.2 V. Similarly for the WTA, input Vi1

is swept from 0.8 to 1.8 V at different Vi2 voltages from 0.9 to 1.7 V with a fixed

step size of 0.2 V. The output transition looks smooth. The LTA operates from

VSS up to 0.9 V and the WTA from VDD down to 0.9 V.

Figure 3.14: Top level schematic of the proposed N-input Loser-Take-All (LTA).Weird caption - PMF

To evaluate the speed of a 4-input LTA, transient analysis with 4 inputs

is performed using 1, 2.5 and 5 MHz signals which are triangular, sinusoidal and

49

triangular, respectively. The 4th input is a DC voltage in the middle of the input-

voltage range. Simulated result of the LTA and WTA are shown in Figs 3.13(a)

and 3.13(b), respectively. Recovery time during output transitions is very fast,

within 10 ns. The RMS error in tracking the lowest of the 4 input voltages is

9 mV for the LTA and 11 mV for the WTA. Part of this RMS error is attributed

to delay, and not an error in tracking the minimum input voltage.

Figure 3.15: Hysteresis simulation of 2-input LTA slow ramp and 0.45 V DC.

Positive feedback in the proposed circuits creates hysteresis, which resists

change in the state of the output signal. To quantify the hysteresis band, the LTA

is simulated with a slow moving ramp and a 0.45 V DC input. The hysteresis

voltage is measured as 2.6 mV and -3 mV, as shown in Fig. 3.15. When two

inputs are close to each other, that is, within the hysteresis band, then two select

signals will be high. In this case, the output voltage becomes the average of the

2 lowest inputs. The overlapped select signals and averaged output voltage can

be observed in Fig. 3.15. To achieve non-overlapping signals, bias currents in the

common-source amplifier should be set to IBIAS/N2 rather than IBIAS/N , at the

cost of reduced switching speed and higher RMS error.

50

The detailed performance comparison with LTA state-of-art are captured

in Table 3.6.

Table 3.6: LTA comparison with state-of-art.

This Work

2011 [15] 2011 [16] 2011 [6] Simulation

Technology 350nm 350nm 250nm 180nm

Accuracy +/-3.5mV +/-4mV +/-4mV +/-3mV

Max. Frequency 10MHz 500kHz 5MHz 5MHz

Supply Rail 3.3V 3.3V 2.5V 1.8V

Power Dissipation - 110 µW 620 µW 72 µW

External Comp. Yes Yes Yes No

Year 2011 2011 2010 2015

3.8 Current Matching Circuit

The current matching circuit show in Fig. 2.11 is based on the current

mirror found in [5], described in section 2.5. High output impedance and low

output voltage make the proposed current matching circuit most suitable for LED

driver applications. In a multi-string implementation all the strings must maintain

the same current, so a current branch is used for every individual string.

As shown in Fig. 3.16, ILED1 to ILED5 are the output currents from the

LED strings. To insure M2 and M4 always operate on the edge of saturation, the

bias current IBIAS is selected to be ten times smaller than IIN . So IBIAS is 100 uA

and IIN is 1 mA. MOSFET sizing used for the input current and ILED1 string is

defined in Table 3.7. The same sizing is used for all other strings.

51

VDD

VSSM4

M7

IBIAS

ILED1

M2

IBIAS

IIN =

10*IBIAS

M6

M8

IBIAS

M1 M3 M5

ILED5

Figure 3.16: High Output Impedance and Low Output Voltage Current MatchingCircuit.

Table 3.7: Sizes of the MOSFETs used in Current Matching Circuit.

MOSFET Sizes (W/L) m

M1 30µ/2µ

M2 260µ/0.7µ

M3 30µ/2µ

M4 4.8m/0.7µ

M7 3.6m/1µ

3.9 LED Model

LED I-V characteristic curves are shown in Fig. 3.18 [11]. The forward

current is exponential with respect to the forward voltage. As discussed in sec-

tion 2.5, a constant current should be maintained through all the strings so that

same luminous intensity is observed from all the LEDs. Maintaining the current

constant results in different forward voltage drops across individual LEDs due

52

to normal process variations. For example, consider random LEDs selected from

Brand A in Fig. 3.17. At a fixed forward current of 20 mA, the voltage drop across

the LED can vary from 3.3-3.5 V.

Figure 3.17: LED I-V Characteristics [11].

The model from Fig. 3.18 is used as the LED load for simulations. The

model consists of a DC forward voltage drop, a series resistance RLED and parallel

junction capacitance CLED. It is a linearized model of an exponential diode char-

acteristic. The voltage drop across resistor RLED is proportional to the current

through the LED.

The target forward voltage assumed for the red color LED is 2.5 V so the

series combination of 2.25 V DC supply and 12.5 Ω resistance at 20 mA produces

2.5 V. The value of junction capacitance is taken from LED datasheet. The

parasitic components in the selected LED are given in Table 3.8.

53

CLED

DC

RLED

CLED

DC

RLED

Figure 3.18: LED Simulation Model used.

Table 3.8: Values of Parasitic Components in LED.

Component Value

CLED 50 pF

RLED 12.5 Ω

DC 2.25 V

3.10 Inductor Full-Range Current Monitor

As discussed in section 2.12, the full-range of inductor current is sensed in

this boost converter by sensing the charging current through the NMOS transistor

and discharge current through the PMOS transistor. Two different circuits are

used to sense individual currents through NMOS and PMOS power transistors.

54

After sensing, this current is summed together by pumping together into a sense

resistor RS.

As shown in Fig. 3.19 [9], the current through NMOS switch is sensed by

placing a ratio-sensing transistor across the power switches with the same channel

length and width ratio of 1000:1.

VDD

M4

VSS

VOUT

M3

M1 M5

M10

VSW

CLKNMOS

VX

IBIAS

M9

M1

M1

CLKNMOSN : 1

M4 M4

RS

icomp

RDummy

iO

iNMOS

Figure 3.19: NMOS current sensor with current-offset cancellation [9].

The MOSFET sizes and component values for the NMOS current sensing

circuit are given in the Table 3.9. A design value of of 50 uA was selected for the

bias current IBIAS. IBIAS can be increased to speedup the circuit.

In the similar way as shown in Fig. 3.20 [9], the current through PMOS

switch is sensed by placing a ratio-sensing transistor across the power switches

with the same channel length and width ratio of 1000:1.

The MOSFET sizes and component values for the PMOS current sensing

circuit are given in the Table 3.9. A design value of of 50 uA was selected for the

bias current IBIAS. IBIAS can be increased to speedup the circuit.

55

Table 3.9: NMOS Current Sensing Module sizes.

Component Value

M1 15µm/0.7µm

M3 15µm/0.7µm

M4 − M6 2µm/1µm

M7 − M10 4µm/1µm

M11 5µm/1µm

RS & Rdummy 1.2979 K

CX 200 fF

RS

VOUT

M4

VSS

M3

M1M5

CLKPMOS

IBIAS

M7

M6

M3 CLKPMOS

1 : N

M6

M1

icomp

iOiPMOS

VSW

Figure 3.20: PMOS current sensor with current-offset cancellation [9].

The individually sensed NMOS and PMOS switch currents are pumped

to flow through a single sense resistor RS. So the above circuits from Fig. 3.19

and Fig. 3.20 should be integrated together to implement the function of full-

range inductor current sensor module as shown in Fig. 3.21. During a single time

56

Table 3.10: PMOS Current Sensing Module sizes.

Component Value

M2 30µm/0.6µm

M12 20µm/0.6µm

M13 − M14 4µm/1µm

M15 − M17 2µm/1µm

M18 2µm/4µm

RS 1.2979 K

period, the inductor charging current is sensed during ON state and discharge

during OFF state. So this design is challenging to maintain smooth transition

between charging and discharge currents.

57

VD

D

M4

VS

S

VO

UT

M3

M1

M5

M10

VS

W

CLK

NM

OS

VX

I BIA

S

M9

M1

M1

CLK

NM

OS

N :

1

M4

M4

RS

i com

p

RD

um

my

i O

VO

UT

M4

VS

S

M3

M1

M5

CLK

PM

OS

I BIA

S

M7

M6

M3

CLK

PM

OS

1 :

N

M6

M1

i com

p i Oi N

MO

S

i PM

OS

+

VS

W

Figure 3.21: Full Range Inductor Current Sense Module [9].

58

Chapter 4

CHIP-LEVEL SIMULATIONS AND LTA MEASUREMENTRESULTS

4.1 Simulation Results of Closed-Loop Design

In the previous chapters the design of the synchronous boost DC-DC

switching converter and modules implemented as a hysteretic control loop are

discussed. The performance of this topology is evaluated through Cadence Vir-

tuoso™simulations. This chapter discusses the input/output waveforms and com-

pares performance with other state-of-the-art designs.

4.1.1 Virtuoso Simulation Test Bench

Virtuoso Analog Design Environment L (ADE-L) uses hierarchical schematic

design. The high-level test bench is shown in Fig. 4.1.

An off-chip discrete inductor and capacitor helps to achieve highly accurate

component values. But there exist some parasitic series resistances due to the

bonding wire, pin resistance and component lead resistance. To account for these

parasitic elements an inductor DC Resistance (DCR) of 400 mΩ and capacitor

Equivalent Series Resistance (ESR) of 100 mΩ is added to these components.

The feedback reference voltage for the voltage loop (VREF ) and current loop

(ViREF ) are set to 400 mV and 220 mV, respectively. A nominal input voltage

(VBATT ) of 3.6 V is used with a start-up rise time of 1 µsec in simulation. A

separate 1.8 V supply voltage (VDD18) is used to supply power to the feedback

modules. Input reference currents of 20 µA (Ibias20uin) and 1 mA (Iin) are used.

The detailed LED model is described in section 3.9. A forward voltage mismatch of

59

Figure 4.1: Test Bench of Hysteretic Synchronous Boost Converter.Add text an-notations to be able to follow text - PMF

0 to 100 mV is assumed between individual LEDs. All these input and component

specifications are captured in Table 4.1.

4.1.2 Virtuoso Simulation Result - Full Load

Transient analysis is performed to understand the steady-state and start-

up behavior of the circuit. This simulation has a run time of 30 µsec. The

waveforms captured in Fig. 4.2 are the output voltage (VOUT ), NMOS gate signal

(CLK NMOS), PMOS gate signal (CLK PMOS), and inductor current (L0 I).

The in-rush current observed though the inductor during start-up is 1.2 A. This

amount of in-rush current is likely too much for the real hardware system, so a

60

Table 4.1: Test Bench Input and Component Specifications.

Component Value

DCR 400 mΩ

ESR 100 mΩ

VREF 400 mV

ViREF 220 mV

Ibias20uin 20 µA

Iin 1 mA

VBATT 3.6 V

VDD18 1.8 V

longer start-up period will be needed in hardware testing. There is no ringing

observed in the output voltage VOUT .

The waveforms captured in Fig. 4.3 are the switching node (VSW ), set (S),

reset (R), and the load current through a single LED string (R33 I).

As shown in Fig. 4.3, by observing the reset (R) signal we can understand

that it takes about 1.5 µsec for the current loop to reach the desired value, since

that is when R begins toggling. However, it takes 9 µsec for the voltage loop to

settle. As soon as VOUT reaches a sufficient output voltage, the voltage loop is

activated and the set (S) signal starts toggling.

To understand the steady-state performance, the stabilized waveform at

the end of the simulation is in Figs. 4.4 and 4.5. The waveforms captured in

Fig. 4.4 are the output voltage (VOUT ), NMOS and PMOS gate signals on the same

61

Figure 4.2: Output Voltage and Inductor Current.

axis (CLK NMOS, CLK PMOS), inductor current (L0 I) and load current

through a single LED string (R33 I).

The waveforms captured in Fig. 4.5 are the output voltage (VOUT ), switch-

ing node (VSW ), set (S), reset (R) and inductor current (L0 I).

From the simulated waveforms, we see that the average output voltage

VOUT settles at 5.496 V with a ripple voltage of 74.8 mV. The average load current

that flows through five strings is 102.1 mA. The observed input power (Pin) of

606.6 mW and the output power (Pout) of 561 mW yields an efficiency of 92.49 %.

The deadtime during rising and falling edges are captured as TDeadtime−Rise of

2.06 nsec and TDeadtime−Fall of 2.64 nsec with an operating frequency of 3.5 MHz.

62

Figure 4.3: Switching Node and Load Current.

As we used separate supply source (VDD18) for the feedback loop, we

need to count this power loss while calculating the overall power efficiency of the

converter.

Efficiency =(Pout + V DD18 Pout)

Pin

(4.1)

Considering the power consumed from 1.8 V voltage source, the resultant

efficiency of the converter is reduced to 92.4 %.

Simulations results are summarized in Table 4.2.

4.1.3 Virtuoso Simulation Results - During Digital Dimming

To reduce the luminous intensity the current flowing through the LED load

is controlled through digital dimming. The load is turned OFF and ON in burst

63

Figure 4.4: Output Voltage and Output Current (Zoom).

Figure 4.5: Switching Node and Inductor Current (Zoom).

64

Table 4.2: Simulation Results Summary.

Component Value

< VOUT > 5.496 V

VOUT Ripple 74.8 mV

< IOUT > 102.1 mA

PIN 606.6 mW

POUT 561 mW

TDeadtime−Rise 2.06 nsec

TDeadtime−Fall 2.64 nsec

Frequency 3.5 MHz

Efficiency 92.4 %

mode at high frequencies to control the average current. The flicker frequency

should be greater than 60 Hz as any frequency beyond 60 Hz cannot be detected

by the human eye.

The waveforms captured in Fig. 4.6 are output voltage (VOUT ), NMOS and

PMOS control signals on the same y-axis (CLK NMOS, CLK PMOS), inductor

current (L0 I) and the load current through a single LED string (R33 I).

A shown in Fig. 4.6, the dimming functionality is evaluated at 200 kHz.

During the OFF state the load current is set to zero and every module in the

feedback loop is also disabled. The power switches are also pulled to safe turn

OFF states. After 2.5 µsec of OFF state, the load is turned ON and only 0.4 µsec

of recovery time is observed. The recovery time observed from simulations is

captured in Table 4.3.

65

Figure 4.6: Dimming at 200 kHz.

Table 4.3: Load Transient Analysis.

Component Value

Dimming Frequency 200 kHz

TRecovery 400 nsec

4.2 Layout of Boost Converter, Power Switches & the control loop

The synchronous boost converter is fabricated in the IBM 7RF 0.18 µm

process and packaged in QFP-44 packages through MOSIS. The major area of a

chip in the boost converter is consumed by the PMOS and NMOS power switches

and current matching circuit as shown in Fig. 4.7.

In this boost converter chip design, the PMOS and NMOS power switches

are laid out using a gate strapping technique. This technique is adopted to reduce

the gate resistance by using a metal layer for connecting the gates of the MOS-

66

FETs. Initially, we laid out each P-type and N-type power FET of size 800 µm

and 600 µm respectively. For the P-type power FET, we joined 25 of 800 µm to

get the desired size of 20 mm and for N-type power FET, we joined 23 of 600 µm

to get the desired size of 13.8 mm. In a similar way we joined 6 of 600 µm to get

the desired size of 3.6 mm and 8 of 600 µm to get the desired size of 4.8 mm in

the current-matching circuit.

Figure 4.7: Chip Level Layout for Hysteretic Synchronous Boost Converter.

The layout areas consumed by the individual modules in this converter are

captured in Table 4.4. Some of the major module-level layouts are shown in this

section, including the NMOS power switch in Fig. 4.8, PMOS power switch in

Fig. 4.9, NMOS gate driver in Fig. 4.10, and current matching circuit in Fig. 4.11.

The layout of the current matching circuit is shown in Fig. 4.11 with a total area

of 578.2 µm × 569.8 µm.

67

Table 4.4: Module Sizing Summary.

Module Size (W/L) m

Chip 1500µ/1500µ

Current Matching 578.2µ/569.8µ

NMOS Power Switch 420µ/137.6µ

PMOS Power Switch 431µ/173.2µ

Inductor Current Sense 211.1µ/52µ

Gate Driver 119.3µ/42.9µ

Inductor Zero Current Detector 97.1µ/38µ

LTA 69.4µ/52.4µ

Bias Current Generator 78.7µ/21.6µ

10-bit Counter 90.9µ/34.6µ

Hysteretic Comparator 25.4µ/16.5µ

Non Overlapping Clock Generator 25.1µ/16µ

Level Shifter 17.3µ/15.6µ

SR Latch 8.8µ/5.3µ

4.3 Measurement Results

During the verification phase of the fabricated chip in IBM 0.18 µm CMOS

technology, we observed a series of IC failures during start-up. We performed sev-

eral tests with high precautions and the issue we encountered was parametric

failure due to inrush current. In addition, one pin was not connected (NC) inter-

nally , rendering the dimming block non-functional.

68

Figure 4.8: NMOS Power Switch.

Figure 4.9: PMOS Power Switch.

4.3.1 Parametric Failure Due To Inrush Current

From the module simulation shown in Fig. 4.12, we observed the input

inrush current through the inductor is 1.2 A, which is too high to withstand for

this process.

After the start-up time we observed a change in resistance value at the

input pin with respect to ground. It changed from hundreds of mega Ω to 26 Ω.

69

Figure 4.10: NMOS Transistor Gate Driver.

This variation in the resistance value indicates that there is a failure on the input

pin and we predict that high inrush current could damage the series connected

NMOS power switch.

First, we limited the output current on the power supply to 400 mA. Sec-

ond, we applied a slow linear rise on the power supply input voltage. As a result,

the inrush current is limited to a value significantly less than 1.2 A.

4.3.2 NC Pins In The Layout

The designed Boost Converter did not work due to no load current. As the

load current is controlled by the current matching circuit, we started analysing the

bias current and enable signals. We did post layout simulations to find out why

the chip is not working and figured out the error as two select lines of a multiplexer

are not grounded. This error affected the state of dim ctrl signal which is used

as the enable for the current-matching module. The no connect is captured in

Fig. 4.13.

70

Figure 4.11: Current Matching Circuit.

4.4 Measurement Results For Minimum Voltage Selector

The minimum voltage selector is fabricated in the IBM 7RF 0.18 µm pro-

cess and packaged in a QFP-44 package through MOSIS. The layout is as shown

in Fig. 4.14. This is a test chip that contained 4 independent projects.

It is extremely difficult to evaluate the performance of this minimum volt-

age selector (LTA) circuit from lab measurements due to low capacitive load driv-

ing capability. In this work, a high precision and high speed voltage-mode loser-

take-all circuit is designed to drive the gate capacitance of a comparator input

stage, which is on the order of fempto-farad(fF). As discussed in the published

paper [13], capacitive and resistive loading adversely affects the accuracy of the

output voltage.

71

Figure 4.12: Output Voltage and Inductor Current.

The regular passive 10x voltage probe used for measurement has a capac-

itive load of approximately 12 pF. The test setup including the breadboard used

during measurements will also add some parasitic capacitance, which can range

between 5 pF to 15 pF. So the best-case minimum load capacitance that will get

added will be 17-27 pF, as much as 1000x that of the circuit driving capability.

Using active voltage probes and a customized PCB would reduce this loading

effect, but not into the fF range.

To understand the amount of capacitive loading, we applied a square wave

at a no connect (NC) pin. Analysing the slew rate of the square wave we cal-

culated the capacitance at that node as approximately 24 pF. Considering this

load capacitance we have re-simulated in Virtuoso with a new test setup and an

increased load capacitance and reduced input frequency. The load capacitance is

set to 24 pF and the input frequency is reduced by a factor of 30 to compensate

72

Figure 4.13: No Connect on Multiplexer Layout.

for the text measurement setup and evaluate the circuit performance. Simulation

waveforms are shown in Fig. 4.15. The blue signal is the output signal that always

tracks the lowest of the given inputs.

The testbench for the minimum voltage selector is shown in Fig. 4.16 and

the input specifications of the voltage sources are captured in Table 4.5. The

supply voltage VDD is 1.8 V and bias current Ibias is 20 µA. The input voltages

Vi1, Vi2, Vi3 and Vi4 are set to 150 kHz triangular, 100 kHz sinusoidal, 50 kHz

triangular and 500 mV DC respectively.

The performance of the LTA module is evaluated and hardware results

are shown in Fig. 4.17. The RMS voltage error and the delay during tracking

are considered as key functional parameter to compare between simulation and

73

Figure 4.14: Test Chip Layout for Looser-Take-All.

measurement results. The measured results are very close to the simulations

results, as captured in Table 4.6.

74

Figure 4.15: 4-Input LTA simulation resultas with 24 pF load capacitance andreduced input frequency.

RIN

Minimum Voltage

Selector

(LTA)

CLOAD

VOUT

DC

Vi2

Vi3

Vi4

Vi5

Vi1

AC

AC

AC

ibiasVDD18

VDD=1.8V

VSS

VOUT

20 µA

ENDC

VDD

Figure 4.16: LTA Testbench.

75

Table 4.5: Input Specification for LTA.

Parameter Values

VDD 1.8 V

Ibias 20 µA

Vi1 150 kHz Triangular

Vi2 100 kHz Sinusoidal

Vi3 50 kHz Triangular

Vi4 450 mV

Vi5 900 mV (disabled)

Figure 4.17: LTA Measurement Results.

76

Table 4.6: Simulation and Measured Results of LTA.

Parameter Simulated Measured

RMS Error 6 mV 12.4 mV

Delay 146.3 nsec 120 nsec

77

Chapter 5

CONCLUSIONS

5.1 Summary

Effective power utilization is a very important issue for portable devices as

it defines the battery life. The display module consumes most of the power. So

a hysteretic synchronous boost converter has been proposed to provide a power-

efficient LED driver with low fabrication cost. The comparator-based feedback

technique helps reduce the number of devices. It consumes low quiescent current

and low area due to absence of compensation components. This driver is suitable

for multi-string LED back-light modules of portable devices.

The driver is fabricated in IBM 180 nm CMOS technology with a die size

of 1.5 mm2. The output of this converter is designed as a constant current source

to produce constant illumination. It is capable of driving 5 parallel LED strings

(20 mA through each string) with two series-connected color LEDs in each string.

The maximum efficiency achieved is 92.3 % with 3.6 V input voltage. The detailed

simulation results are captured in Section 4.1.

5.2 Issues

Some limitations exist in the proposed circuit due to inaccurate full range

inductor current sense and inductor zero current detection.

A more accurate inductor current sensing technique is needed in the current

loop. Improving the zero current module can decrease the losses and increase the

efficiency due to faster detection that eliminates negative current through the

PMOS switch.

78

5.3 Comparison with the State-of-the-Art

In Table 5.1, we present a summary of results comparing the implemented

LED driver with other state-of-the-art LED drivers reported in the literature.

In [17], a boost converter is implemented in a 40 nm standard CMOS

process. The single lithium-ion rechargeable battery of 2.5 V to 4.3 V is boosted

up to 21 V for lighting white LEDs. The output current is programmed between

0.5 mA and 21 mA at a switching frequency 250 kHz to 2 MHz, respectively. The

maximum efficiency of 84% is achieved at about 3.5 V battery voltage.

In [18], a high efficient boost white LED driver is implemented in TSMC

250 nm. The input voltage of 3.7 V to 4.2 V is boosted up to 43 V to connect

12 series WLEDs at 60 mA. The maximum efficiency of 89.6% is achieved at a

switching frequency 1.1 MHz.

The proposed design has achieved a higher efficiency at a higher switching

frequency.

5.4 Future Work

Working with power management integrated circuits always forces design

engineers to find a way to increase the efficiency and performance of the power

converter. Furthermore, digital dimming demands relatively fast load regulation

and recovery. Suggested future work items are identified as follows:

1. Using more accurate and fast response zero cross detector module can

decrease the losses due to negative current through the PMOS power switch and

increase the efficiency.

2. Implementing a higher switching-speed power converter helps to de-

crease inductor size and increase the range of dimming ratio.

3. Implementing a switched-capacitor converter using external capacitors

in an LED driver application.

79

Table 5.1: Simulation Results Summary of LED Driver.

This Work

2010 [18] 2012 [17] Simulation

Technology 250nm 40nm 180nm

Supply Voltage 3.7V - 4.2V 2.5V - 4.3V 3.6V

Output Voltage 43V 21V 5.4V

Load Current 60mA 0.5-21mA 100mA

Output Ripple Voltage - - 72mV

Inductor 22 µH 10 µH 1 µH

Capacitor 2.2 µF 0.1 µF 0.22 µF

Switching Frequency 1.1MHz 250kHz - 2MHz 3.5MHz

Efficiency 89.6% 84% 92.4%

80

REFERENCES

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84

APPENDICES

APPENDIX A

Test Document

’

A.1 Pin Diagram of the Boost Converter

Using IBM 0.18 µm CMOS process this work is fabricated on Quad Flat

Package (QFP). In this 44-pin QFP surface mount package, every 11th pin is not

used as the pad frame consists of only 40 pins. The pin diagram of the hysteretic

boost converter is shown in Fig. A.1. The detailed description of individual pin is

captured in Table 1.

1

2

3

4

5

6

7

8

9

10

32

31

30

29

28

27

26

25

24

23

44

43

42

41

40

39

38

37

36

35

12

13

14

15

16

17

18

19

20

21

VOUT

VOUT

VOUT

VOUT

VOUT

Ibias20uin

Vref

Viref

CLK_NMOS

CLK_PMOS

PVSS

PVSS

PVSS

PADVDD5

DVSS

VOUT1

VOUT2

VOUT3

VOUT5

VOUT4

NC

PA

DV

SS

VS

W

VS

W

VS

W

VS

W

VS

W

VS

W

PV

SS

PV

SS

AV

SS

S R

CL

Kin

S1

Iin -

PA

DV

DD

18

-

S0

SYNCHRONOUS

HYSTERETIC

BOOST CONVERTER

11NC

22

NC

33NC

34

PV

SS

Figure A.1: QFP Pin Diagram of Hysteretic Boost Converter.

A.2 Supply Voltages and Currents

VBATT = 3.6 V typical

87

PVSS = DVSS = AVSS = 0 V

PADVDD5 = 5 V

PADVDD18 = 1.8 V

Vref = 400 mV

Viref = 220 mV

Iref = 20 µA

Iin = 1 mA

Clock = 0 to VDD18 peak-to-peak with 50 % duty cycle

A.3 Test Procedure

The implemented test bench with external input sources and components

is shown in Fig. A.2.

6

18

7

8

15

16

17

27

26

25

24

23

12

28

43

VSW

Iin(1mA)

Vref(400mV)

Viref(220mV)

CLK

S0

S1

VOUT1

VOUT2

VOUT3

VOUT5

VOUT4

AV

SS

DV

SS

PA

DV

SS

SYNCHRONOUS

HYSTERETIC

BOOST CONVERTER

VBATT

P30

,31

,32

,34

,35

,36

P37,38,39,40,41,42

Ibias(20µA)

PV

SS

VOUTP1,2,3,4,5

0.22µF

100m

1µH400m

10µF

+VCLK

21

29

PADVDD18

PADVDD5

5V10µF

1.8V10µF

I L1(2

0m

A)

I L2(2

0m

A)

I L3(2

0m

A)

I L4(2

0m

A)

I L5(2

0m

A)

Figure A.2: QFP Pin Diagram of Hysteretic Boost Converter.

1. Set the digital input signals at a fixed state i.e. to disable the dimming, set

the dimming control signals CLKin (pin 14) to 1.8 V and S0 (pin 15), S1

(pin 16) to 0 V.

88

2. Connect PADVDD18 (pin 29) to 1.8 V, PADVSS (pin 43) to 0 V and check

whether the chip is good or not fired up.

3. Connect global ground as star connected with DVSS (pin 26), AVSS (pin 11),

and PVSS (pin 28, 29, 30, 31, 32, 33). DVSS goes to digital circuit and AVSS

goes to analog circuits in control-loop and PVSS goes to power return path

i.e. source of NMOS switch and current mirror at load.

4. Attach bias resistor to generate bias currents

• Ibias20u: The bias current is 20 µA and the supply voltage is 1.8 V.

Therefore the bias resistor is given by

Vbias = 1 V

R =Vdd−(Vbias)

Iref(1)

On substituting the above values, we get

R = 40kΩ

Connect Ibias20u (pin 6) to one end of the bias resistor and other end

of resistor is connected to VDD18 (pin 27).

• Iin: The bias current is 1 mA and the VDD18 supply voltage is 1.8 V.

Therefore the bias resistor is given by

Vbias = 1 V

R =Vdd−(Vbias)

Iin(2)

On substituting the above values, we get

RComp = 800Ω Connect Iin (pin 6) to one end of the bias resistor and

other end of resistor is connected to VDD18 (pin 27).

89

5. Supply reference voltages, 400 mV of Vref (pin 7) and 220 mV of Viref (pin

8) using external voltage source. Vref for voltage feedback loop and Viref for

current feedback loop.

6. Connect boost energy storage components:

• Inductor: Inductance of 1 µH is connected to VSW (pin 34, 35, 36, 37,

38, 39) and other end of the Inductor is connected to VBATT 3.6 V

• Capacitor: Capacitance of 220 nF is connected to VOUT (pin 1, 2, 3, 4,

5) and other end of the Capacitor is connected to PVSS

7. Connect five parallel strings of LEDs with 2LEDs on each string. One

end of all the strings are connected to VOUT and other ends are individually

connected to VOUT1 (Pin25), VOUT2 (Pin24), VOUT3 (Pin23), VOUT4 (Pin22),

VOUT5 (Pin21).

8. Using oscilloscope capture the signals VOUT, CLK NMOS, CLK PMOS, S,

R.

Load Regulation:

Procedure:

1. Clock input of 1 MHz with 1.8 Vpp is supplied to CLKin (pin 14).

2. Vary inputs signals S0 (pin 15), S1 (pin 16) in binary form to achieve low

dimming ratio.

3. Now observe the given input signal on the oscilloscope.

4. Provide the clock signal to the converter.

5. Now observe the output voltage waveform on the oscilloscope with the step

change in the supply voltage

90

6. Calculate the load regulation of the converter.

7. Load regulation is the ratio of steady–state change in output to the steady–state

change in load current. The load regulation is given by,

Load regulation =∆Vout,steady−state

∆IL,steady−state

(3)

91

Table 1: Pin Description of Fabricated Chip.

Pin # Name Pad type Description

1 - 5 VOUT High Current BareFinal output of the LED

Driver where anode of LEDsare connected

6 Ibias20uin Protected Reference bias current of 20A

7 Vref ProtectedReference voltage of 400mA

used in feedback voltage loopto compare with LTA output

8 Viref Protected

Reference voltage of 220mAused in feedback current loopto compare tracked inductor

current

9 CLK PMOS Digital BufferMonitoring signal at the gate

of PMOS

10 CLK NMOS Digital BufferNMOS (M2) Monitoring signal

at the gate of NMOS

11 NC - No Connect pin

12 AVSS High Current Bare

Analog ground pin connectedto analog modules like LTA,

Comparators, SR Latch,Non-overlapping clock

generator

13 S Digital BufferMonitoring signal SET at the

input of the SR latch

14 R Digital BufferMonitoring signal RESET at

the input of the SR latch

92

Pin # Name Pad type Description

15 CLKin Protected200 KHz input clock signal for

frequency divider10bitcounter.

16 S0 ProtectedLSB select line to select

Dim18 signal from 10bitMUX

17 S1 ProtectedMSB select line to select

Dim18 signal from 10bitMUX

18 Iin ProtectedReference current of 1 mAthat goes to the modified

current mirror circuit

19 - - -

20 - - -

21 PADVDD18 Protected1.8 V supply voltage for theprotection circuits connected

to pad

22 NC - No Connect pin

23 - 27 VOUT5 - VOUT1 High Current BareLED string return current isconnected back to modified

Wilson current mirror circuit

28 DVSS Protected

Digital ground pin connectedto digital modules like level

shifters, ZCD, buffers,counters, MUX

93

Pin # Name Pad type Description

29 PADVDD5 Protected5 V supply voltage for the

protection circuits connectedto pad

30 - 32 VSS High Current Protected

Ground for the input NMOSswitch and load current from

modified Wilson currentmirror

33 NC - No Connect pin

34 - 36 VSS Protected

Ground for the input NMOSswitch and load current from

modified Wilson currentmirror

37 - 42 VSW High Current Bare

Connected to NMOS Switchand PMOS Sync Switch. Oneend of inductor is connected to

this pin

43 PADVSS High Current BareGround for the protectioncircuits connected to pad

44 NC - No Connect pin

94

APPENDIX B

External Capacitor and Inductor Selection

B.4 External Inductor and Capacitor Selection

The off chip components, inductor and capacitor for the boost converter

are selected for the switching frequency of 3.5 MHz from the website: DigiKey

Electronics. The detailed specification of these are captured in Table 2.

Table 2: Off-Chip Inductor and Capacitor.

Specifications Inductor Capacitor

Part # 445-15739-1-ND PCF-1128CT-ND

Manufacture Part # MLP2520K1R0ST0S1 ECP-U1C224MA5

Type MULTILAYER

Material Core Ferrite Film

Component Value 1 µH 0.22µF

Tolerance ±20% ±20%

Voltage Rating 16V

Current Rating 2.3A

ESR

DCR 62.4 mΩ

Mounting Type Surface Mounting

Frequency Test 2MHz

Dimensions 2.50mm×2.00mm 3.20mm×1.60mm

96