high speed lateral power devices -...
TRANSCRIPT
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Analog Tech. Development
High Speed Lateral Power Devices
Sameer Pendharkar
Analog Technology Development
Texas Instruments Inc.
Dallas, TX, USA
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Analog Tech. Development
Outline
• Integrated LDMOS
• Isolation Requirements
• Interconnect & Packaging
• Discrete lateral DMOS & Packaging
• Summary
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Analog Tech. Development
High Frequency Switching
• End solution size is the primary driver
POWER CONVERSION SOLUTION SIZE
(10:1 STEP DOWN)
1MHzInductor
3MHz
>2X Less Volume
>10x Less Volume
10MHz
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Analog Tech. Development
Key Power Device Drivers
• Rsp important Key Si cost driver
BUT
• R x Qtot(Qgd) & Qrr Key performance
drivers and system cost drivers
ALSO NEED
• Reduced parasitics (gate loop and power loop L, CSI)
Integration and Integrated LDMOS
![Page 5: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/5.jpg)
Analog Tech. Development
LDMOS
GATE
n+
p or n-region
D
n+n- (low doped)
applied highvoltage (Vds)
low voltage
drain extension
p-body
S
GATE
n+ n+
p-region
S D
NMOS RESURF
![Page 6: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/6.jpg)
Analog Tech. Development
LDMOS Benefit
• Multi-voltage, Easy to Integrate
• Lowest Qg/Qtot for given Rdson – monolithically integrated – Low voltage integrated VDMOS not efficient due to significantly high Rsp
60
65
70
75
80
85
90
0 1 2 3 4 5
Effi
cie
ncy
(%
)
Switching Frequency (MHz)
Int. LDMOS (msrd)
Pseudo VDMOS (model)
Synchronous Buck Converter – Monolithically Integrated
Vin=12V, Vout=1.5V, I=10A
GATES D
P-well
p n nn-drift
GATES D
P-well
p n nn-driftFlip chip packaging
(step gate)
![Page 7: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/7.jpg)
Analog Tech. Development
Integrated Power Conversion
• Monolithic integration helps reduce both gate
loop and power loop inductance
High speed Synchronous Buck Converter
![Page 8: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/8.jpg)
Analog Tech. Development
Integrated FET Scaling – Drives Technology
• Integrated FET improvement at TI
– about 25-30% node-on-node improvement
Rsp
(m
oh
m-c
m2)
Timeline
~50V ldmos
~20V ldmos
~14%/year
~20%/year
LBCn
LBC(n+4)
Architectural
Change
![Page 9: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/9.jpg)
Analog Tech. Development
Outline
• Integrated LDMOS
• Isolation Requirements
– Functionality
– Efficiency
• Interconnect & Packaging
• Discrete lateral DMOS & Packaging
• Summary
![Page 10: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/10.jpg)
Analog Tech. Development
Isolation - Functionality
• Protect circuitry from carrier injection
– Diode recovery, Substrate bounce/noise
Nwell
N+
Nwell
P+ N+ P+ N+ N+ P+
P-EPI
P+ P+ N+
Nwell
Rn
Rp
Vcc GND
GND GND
Injecting
Nwell
Guardring
Bias
Substrate
Injection
Guardring CMOS Inverter
DE
EP
TR
EN
CH
(flo
ati
ng o
r gro
un
ded
)
P-sub P+ sub P-sub
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Analog Tech. Development
Isolation – Efficiency Improvement
• Integrated guard ring significantly reduces diode recovery loss enables faster switching
S D
p-substrate
p-body
n-drain n+n+p+
P-base
+ve / ground
n-tank withn+ at surface
N-buried layer
Isolated ldmos
S
connected to source
D
n-buried layer (for isolation)
p-body
n-drain n+n+p+
P-base
Isolation tied
to drain
Isolation tied
to source
20V, 10A switcher
![Page 12: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/12.jpg)
Analog Tech. Development
Outline
• Integrated LDMOS
• Isolation Requirements
• Interconnect & Packaging
– Electro migration
– Parasitic inductance
– Size and footprint
• Discrete lateral DMOS & Packaging
• Summary
![Page 13: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/13.jpg)
Analog Tech. Development
Interconnect Optimization
• Thick Copper allows direct bonding on top of active device – delivers distributed current
• Enables flip chip package eliminating bondwires
Au Ball
Bond
Plated
Ni/Pd
Plated
CopperLDMOS
Transistor
AlCu
Thick copper and
bonding technology
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Analog Tech. Development
Package Bottom
Leadframe Cu bumps on die
Die
COA
Bump
Leadframe
Solder
Thick Cu
For Power Pins
For Signal Pins
Flip-Chip Eliminates Wire Resistance &
Wire Inductance
HOTRODTM – Flip chip Package for Power
![Page 15: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/15.jpg)
Analog Tech. Development
Outline
• Integrated LDMOS
• Isolation Requirements
• Interconnect & Packaging
• Discrete lateral DMOS & Packaging
– Path towards higher current
– Reduced design cycle time
– Product flexibility
• Summary
![Page 16: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/16.jpg)
Analog Tech. Development
Discrete FET Technology
Planar
• Commercialized in 1980’s
• Lower density structure
• Relative large gate area
• Mid resistance and charge
N+
N+ substrate
P+
N+
P
Trench
• Commercialized in the
1990’s
• Very High Density structure
• Large gate area
• Low resistance, high charge
N+-substrate
PN+
P+
+
LDD-N
Gate
NexFETTM LV Technology
• LDMOS with Vertical Current Flow
• High density and low Rdson
• Low gate charge
NexFETTM MV Technology
• Planar gate for low gate charge
• SJ Trench for lower Rdson
• Low gate charge & fast switching
![Page 17: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/17.jpg)
Analog Tech. Development
Power Loss vs. Frequency for
Trench DMOS and NexFET
For same output inductor losses (I2R): Inductor Volume (1/Fsw)
40% System size reduction by using Lateral channel NeXFET
![Page 18: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/18.jpg)
Analog Tech. Development
“Lateral” Discrete FET Flexibility
• Same architecture allows both “drain down” & “source down” structures
• Accomodates functional integration
– Gate clamp, Gate segmentation, slew control
DRAIN DOWN SOURCE DOWN
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Analog Tech. Development
Stacked Die Packaging – Power Block VIN / Cu Clip
High Side Die
Low Side Die GND / Cu Lead frame VSW / Cu Clip
Stacked die reduces board space by more
than 50%
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Analog Tech. Development
Power Block – Efficiency Improvement
• About 20% reduction in losses with stacked die
• Similar die temperature/thermal performance
![Page 21: High Speed Lateral Power Devices - pwrsocevents.compwrsocevents.com/wp-content/uploads/2014-presentations/ts/S3_3... · High Speed Lateral Power Devices Sameer Pendharkar Analog Technology](https://reader031.vdocuments.us/reader031/viewer/2022011802/5b4f96257f8b9a166e8cb858/html5/thumbnails/21.jpg)
Analog Tech. Development
Summary
• Power conversion switching frequency
increasing to enable footprint reduction
– Switching losses and diode losses more critical
• Lateral power DMOS structure ideally suited
– Can be implemented as integrated or discrete
• Lower gate and power loop as well as package
inductances while maintaining high current
interconnect
– Monolithic for low/mid current – flip chip
– Stacked die for high current – Cu clip
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Analog Tech. Development
THANK YOU