High Efficiency Integrated DC-DC Converter

Luís Eduardo Gomes Sobral Gonçalves

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Supervisor: Professor Marcelino Bicho dos Santos

Examination Committee

Chairperson: Professor Gonçalo Nuno Gomes TavaresSupervisor: Professor Marcelino Bicho dos Santos

Member of the Committee: Professor Maria Beatriz Mendes Batalha Vieira VieiraBorges

November 2018

Declaration

I declare that this document is an original work of my own authorship and that it fulfills all the

requirements of the Code of Conduct and Good Practices of the Universidade de Lisboa.

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Acknowledgments

I would like to thank my supervisor Marcelino Bicho dos Santos for the encouragement and guid-

ance during this project.

Secondly, I would like to thank to my colleagues with whom I have worked in Técnico for their

friendship and support through all this years.

I want also to thank my parents for being at my side even when they were in my home town, and

to my sister, brother in-law and uncles for having given me my home far from home.

Finally, I also want to thank to my girlfriend, for helping me to finish this degree, for supporting me

when everything went wrong, and for being at my side ad helping me to do the right thing.

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Abstract

In the last years, with the reduction in the size of electronic devices and the need to make them

more efficient and with a better performance, created the need to find efficient substitutes for linear

regulators. From that point, came the main purpose of this thesis, which is developing a method

that allow, to build direct current to direct current converter capable of being placed inside a chip. To

achieve these goals, it is required to raise the switching frequency allowing a reduction in size in the

inductance and capacitance.

In this report, it will be presented the main characteristics of the converters, and its main causes

for power losses. It will also to develop this kind of converters, for a specific set of current and voltage

targets.

In the end of this report, the results obtained using the method explored before will be presented

and analyzed. It will also figure all the conclusions taken from these experiments as well as some

possible changes to the method that could increase the converters efficiency and allowing them to be

used for a bigger range of output currents.

Keywords

High-frequency, low losses, dead time, direct current to direct current converter, low dropout reg-

ulator.

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Resumo

Nos últimos anos a redução do tamanho dos dispositivos eletrónicos, bem como a necessidade

de os tornar mais eficientes e de aumentar a sua autonomia, criou a necessidade de encontrar

substitutos para os reguladores lineares. Assim sendo, o propósito desta dissertação de mestrado

é desenvolver um método que permita o desenvolvimento de conversores de corrente continua em

corrente continua, capazes de serem colocados no interior de um chip. Para atingir os objetivos pro-

postos foi necessário aumentar a frequência de comutação de modo a permitir reduzir o tamanho da

bobina e do condensador.

Este relatório apresenta as principais características dos conversores de corrente continua em

corrente continua, bem como as principais causas de perda de potência. Neste relatório consta tam-

bém a demonstração do método desenvolvido para projetar este tipo de conversores, partindo de um

conjunto específico de correntes e tensões.

No final do relatório serão apresentados os resultados obtidos dos testes feitos ao conversor de-

senhado para servir de prova do método desenvolvido, bem como todas as conclusões que possam

ser obtidas, e que venham a ser uteis quer para aumentar a eficiência energética do conversor, quer

para tornar a mesma estável para uma maior gama de valores de corrente de saída.

Palavras Chave

Alta frequência, conversores de corrente continua em corrente continua, reguladores low dropout.

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Contents

1 Motivation and Introduction 2

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.1 Low Dropout Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.2 DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.3 DC-DC converters using MOSFET’s Power loses . . . . . . . . . . . . . . . . . . 7

1.2.4 Simultaneous Conduction Losses and Solutions . . . . . . . . . . . . . . . . . . 9

1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4 Structure of the Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 State of the Art 13

2.1 Digital Modular Control of High Frequency DC-DC Converters . . . . . . . . . . . . . . . 14

2.2 A 65MHz Switching Rate, Two-Stage Interleaved Synchronous Buck Converter with

Fully Integrated Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Integrated DC-DC Converter Design for Improved Wide-Band Code Division Multiple

Access (WCDMA) Power Amplifier Efficiency in SiGe BiCMOS Technology . . . . . . . 16

2.4 Intel’s Fully Integrated Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 PowerSwipe Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.5.1 Design of a highly integrated, high frequency, low power DC-DC converter with

cascode power stage with a 2.5D approach . . . . . . . . . . . . . . . . . . . . . 24

2.6 Dead-Time Control System for a Synchronous Buck DC-DC Converter . . . . . . . . . . 24

2.7 Projects Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Power Converter Design and Simulation 29

3.1 Method Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Converter’s Characteristics and Passive Devices . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Power MOSFET’s design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3.1 PMOS design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3.2 NMOS design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.4 Non-overlap control system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 MOSFET gate drivers design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.5.1 Regular Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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3.5.2 Non-overlap gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.5.3 Gate Driver’s comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6 Output stage design and parasitic quantification . . . . . . . . . . . . . . . . . . . . . . . 47

3.7 Simulation and results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4 Conclusion 53

5 Future Work 55

Bibliography 57

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List of Figures

1.1 LDO’s basic circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Basic DC-DC buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Inductor’s current and voltage for Continuous Conduction Mode (CCM). . . . . . . . . . 6

1.4 Inductor’s current and voltage for Discontinuous Conduction Mode (DCM). . . . . . . . . 6

1.5 Charging and Discharging in MOSFET’s Gate parasitic capacitor. . . . . . . . . . . . . . 8

1.6 Fix dead time control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.7 Adaptive dead time schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.8 Predicted dead time control signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Delay line and inverter’s current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Usual power efficiency for power amplifiers and the probability distribution of the power

efficiencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 Single unity and complete architecture for the converter. . . . . . . . . . . . . . . . . . . 17

2.4 Architecture of Intel’s Power Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5 Circuit of a two-phase FIVR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6 Inductores from Intel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7 PowerSwipe integrated power management architecture to supply a µcontroller. . . . . 21

2.8 Relation between the converter’s efficiency and the switching frequency. . . . . . . . . . 22

2.9 Type Racetrack micro-inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.10 Circuit with cascode MOSFET’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.11 Undershoot detector schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.12 Efficiency increase with the use of the control dead-time system. . . . . . . . . . . . . . 26

2.13 Total losses decrease (in %). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 Flowchart for the design method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 Schematic to obtain the value of µ times Cox to the PMOS transistors. . . . . . . . . . . 35

3.3 Schematic to obtain PMOS Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4 Schematic for transient simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 Relation between the transistor’s width and the Joule power losses. . . . . . . . . . . . 37

3.6 Schematic to obtain the value of µ times Cox to the NMOS transistors. . . . . . . . . . . 38

3.7 Schematic to obtain NMOS Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.8 Relation between the transistor’s width and the Joule power losses. . . . . . . . . . . . 39

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3.9 Joule loss relation between the transistor’s width and the Joule power loss. . . . . . . . 40

3.10 Schematic for the non-overlap circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.11 Signals changes when the control signal change from low to high. . . . . . . . . . . . . 42

3.12 Signals changes when the control signal change from high to low. . . . . . . . . . . . . 42

3.13 Simple Gate Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.14 Relation between transistor’s width and the power losses both inside the gate driver

and by the Joule effect for the PMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.15 Relation between transistor’s width and the power losses both inside the gate driver

and by Joule effect for the NMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.16 Non-overlap Gate Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.17 Power consumption in regular gate driver (in blue) and in non-overlap gate driver (in

orange) and the difference between them (in grey). . . . . . . . . . . . . . . . . . . . . . 46

3.18 Power stage complete schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.19 Schematic used to do the converter’s complete simulation. . . . . . . . . . . . . . . . . 48

3.20 Variation in the output voltage with time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.21 Variation in the inductor’s current and output voltage ripple for steady state. . . . . . . . 49

3.22 Power consumption split between all components. . . . . . . . . . . . . . . . . . . . . . 50

3.23 Schematic used to perform the converter’s complete simulation. . . . . . . . . . . . . . 51

3.24 Relation between the power efficiency and the output current. . . . . . . . . . . . . . . . 52

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List of Tables

2.1 Converters Required Characteristics [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Comparison of calculated and simulated results for multiple 100nH micro inductors. . . 23

2.3 Fluctuation in dead-time and generated delay. . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 Relation between the inductance, capacitance and the output current with the con-

verter’s efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1 Input and Output parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2 Width and length values for both power transistors. . . . . . . . . . . . . . . . . . . . . . 45

3.3 List of converter’s parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.4 Relation between the power efficiency and the output current. . . . . . . . . . . . . . . . 50

3.5 Relation between the power efficiency and the output current. . . . . . . . . . . . . . . . 51

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Abbreviations

AC Alternated current

CMOS Complementary Metal Oxide Semiconductor

CCM Continuous Conduction Mode

DC Direct Current

DC-DC Direct Current to Direct Current

DCM Discontinuous Conduction Mode

ESR Equivalent Series Resistance

ESL Equivalent Series Inductance

FIVR Fully Integrated Voltage Regulators

HF High Frequency

HV High Voltage

LDO Low-dropout

LV Low Voltage

MOSFET Metal Oxide Semiconductor Field Effect Transistor

MIM Metal Isolater Metal

NMOS Negative Metal Oxide Semiconductor

nanoCMOS Nanometer Complementary Metal Oxide Semiconductor

PCU Power Control Unity

PICS Passive Integration Connective Substrate

PMOS Positive Metal Oxide Semiconductor

PVT Process, Voltage and Temperature

PSU Power Supply Unit

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PWM Pulse Width Modulation

SoC System on a Chip

WCDMA Wide-Band Code Division Multiple Access

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1Motivation and Introduction

2

1.1 Motivation

Over the last years, the reduction in consumer electronic’s products dimensions boosted the de-

mand for small and high-efficiency power converters, with the purpose of increasing peak available

power and extending battery lifetime for portable devices. Considering this, the research on these

devices (that have the ability to transform the battery stored energy into the voltage levels required by

the following circuits as well as being small and efficient enough for consumer applications) started

to focus on high-efficiency integrated buck DC-DC converters, more specifically on the in-package

power devices.

The design of in-package buck DC-DC converters demands the existence of capacitors and induc-

tors with dimensions small enough to fit on a chip. The reduction in the size of this two devices gener-

ates a decrease in both capacitance and inductance, which consequentially increases the switching

frequency used to operate the converter. This increase in frequency also increases the power dissipa-

tion related to the charge and discharge of the MOSFET’s parasitic capacity both from the converter

itself as well as from the driver’s circuit. This phenomenon is the main cause of the decreasing effi-

ciency in DC-DC converters when the size is reduced.

This work will focus on achieving a method that can be used in the design of output stages for

high-frequency in-package DC-DC converters suitable to replace the Linear Regulators, starting from

a set of specifications and achieving the optimum efficiency.

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1.2 Introduction

1.2.1 Low Dropout Linear Regulators

To understand this project’s goals, it is required to know how the technology that this project in-

tends to replace works and be aware of its efficiency limitations.

The most common power converter is the linear regulator converter because it is a low-cost de-

vice, easy to use and to manufacture, which enables a precise output voltage. As shown in [2], the

basic design for this type of devices does not require inductors and may be built using only one tran-

sistor, two resistors, and one operational amplifier placed in the die. Outside the die, there are two

capacitors with a capacity of a few dozens micro Farads connected to the input and output.

Figure 1.1: LDO’s basic circuit.

Figure 1.1 shows a simplified model of a Low-dropout (LDO) schematic and reveals that the con-

nection between the supply and the output is made only by the power transistor, which works at linear

mode. The control of the transistor’s conduction characteristics is assured by the error amplifier,

which compares the voltage from the resistance divider placed in parallel with the device’s output,

with a reference voltage, thus increasing or decreasing the transistor’s current to obtain the correct

output voltage value.

To obtain the relation between the power supplied to the regulator and the block output power, it

is required to take into account that the input current is equal to the output current. Therefore the

efficiency is equal to:

η =VOutIOut

VInIOut=VOut

VIn(1.1)

4

Understanding the device’s operation and knowing the correlation between the input voltage, the

output voltage and the regulator’s efficiency, it is easy to assume that power losses will increase with

the difference between the input and output voltages. These losses occur due to the dissipation of

power in the transistor, which has to limit the current delivered to the load. The use of LDOs will

create an unnecessarily high power dissipation that reduces the effective use of the power stored in

batteries and will increase the amount of heat that has to be extracted from the integrated electronic

device’s die, in order to avoid circuit damage.

1.2.2 DC-DC Converters

A DC-DC buck converter is a power block which provides a specific output voltage from a higher

input voltage supply. The voltage levels conversion must be performed with maximum efficiency. The

power stage of the buck DC-DC uses two MOSFETs (M1 and M2 from figure 1.2), an inductor and a

capacitor, which works as an output low pass filter, to convert the supply voltage to the required level.

Contrary to an LDO, the two transistors used in DC-DC converters will work in cutoff or triode region,

leading to the increase of efficiency.

Figure 1.2: Basic DC-DC buck converter.

Each of the MOSFETs acts like a switch, connecting the inductor to the device’s power source in

the case of M1 being turned on, or to the ground, when M2 is on.

The duty cycle(D) is defined as the ratio between the time M1 is on (and M2 is off), ton and the

period of operation, Ts [3].

Vo =1

Ts

∫ Ts

0

v0(t)dt =1

Ts(

∫ ton

0

Vddt+

∫ Ts

ton

0dt) =tonTs

× Vd = DVd (1.2)

While M1 is on the inductor current rises with the slope (Vi −Vo)/L and when M2 is on, the induc-

tor current falls with the slope −Vo/L.

From the charge and discharge of the inductor used to build the low-pass filter, two different oper-

ating modes can be obtained: the Continuous Conduction Mode and the Discontinuous Conduction

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Mode.

Continuous Conduction Mode (CCM) is present when the time gap between the MOSFET M1

cutoff and the next turn on (toff ) is not enough to fully discharge the energy stored in the inductor,

leaving the coil permanently charged. The start of a new cycle, without the total discharge of the

energy stored in the inductor, will produce a current that is always higher than zero, as shown in figure

1.3 from [4].

Figure 1.3: Inductor’s current and voltage for CCM.

The second mode, the Discontinuous Conduction Mode (DCM), is present when all the energy

stored in the inductor is fully discharged to the capacitor and load, thus creating a period where the

inductor current is zero, as shown in Figure 1.4 from [4].

Figure 1.4: Inductor’s current and voltage for DCM.

The separation between this two work modes takes place when the inductor’s current achieves the

value of zero in the precise point where the next cycle will start, corresponding to the minimal value

for the inductor that allows the converter to operate in CCM [3].

6

Lb =(1 −D)Vout

2fIout(1.3)

The purpose of the capacitor is to smooth the voltage variation created by the MOSFETs switch-

ing, to achieve a nearly constant voltage source. The value of the voltage ripple at the output voltage

(δVout) is a function of the charge fluctuation (δQ) and the capacitance.

∆Vout =∆Q

C=

∆I

8fC(1.4)

1.2.3 DC-DC converters using MOSFET’s Power loses

To achieve the best efficiency possible in a DC-DC converter, it is required to understand each of

the losses causes. These power losses can be split into conduction losses and switching losses.

The conduction losses, are caused by the Joule effect (PJ ) due to the current that flows into their

parasitic resistance (RP ).

PJ = RP × I2 (1.5)

For the MOSFETs, the value of RP will be the value of the resistance between the transistor’s

drain and source (RDS). This parameter will decrease with the increase in the ratio between the width

and the length (W/L), as shown in the following equation for a MOSFET in triode [5]:

RDS =VDS

ID=

VDS

12µCox

WL (2(VGS − Vt)vDS − V 2

DS)(1.6)

As shown by the Joule effect equation (1.5), conduction losses are independent of the converter’s

switching frequency. Therefore, to reduce Joule losses, the solution is to use devices with the minimal

parasitic resistance possible.

One the other way, the second type of power losses is caused by the switching between on and

off, in the power transistors and their gate drivers. These losses are caused by the charge and dis-

7

charge of the transistor gate’s parasitic capacitance, which has to be charged every time the transistor

changes from cutoff to conduction and consequentially discharged when it changes from conduction

to cutoff [6].

Figure 1.5: Charging and Discharging in Gate parasitic capacitor.

These parasitic capacitances will be dependent on the channel area and on the capacitance den-

sity of the oxide below the gate Cox [5].

CG = Cox ×W × L (1.7)

The amount of power that is lost in the switching process of a MOSFET switching depends on the

gate capacitance value, the square of the voltage at the gate (VG) and the switching frequency (f ).

PG = CG × V 2G × f (1.8)

These kind of power losses occur in all the switching components, increasing with the increase in

the transistor’s size or in the switching frequency.

Lastly, an additional source of power losses results from the simultaneous conduction of both

PMOS and NMOS transistors (shoot-through). This results in direct conduction between the power

supply and ground through the two MOSFETs, and will increase with the increase of the MOSFETs

size. The MOSFETs where shoot-through causes more losses are the ones placed in the power

stage, and the ones present in the gate driver’s last stage. The shoot-through will occur every time

the transistors change from conduction to cutoff or reverse, so the increase of the switching frequency

will magnify the impact of this kind of power losses.

In conclusion, since the gate capacitance increases with the MOSFET width, a trade-off exists

between Joule losses that are minimized increasing the width, and switching losses, that are mini-

8

mized reducing the width. To reduce the common conduction, must be used a system that ensures

the non-overlap of the power transistors conduction, limiting the losses, using well-known solutions,

as discussed next.

1.2.4 Simultaneous Conduction Losses and Solutions

To limit the impact of shoot-through the switching of both transistors must be separated to ensure

that both transistors are not in conduction simultaneously [7].

The use of a gap between the MOSFET’s on time (dead time) will reduce the power losses created

by the short-circuit, but will bring a new source of power losses.

To achieve the best possible efficiency, Texas Instruments developed several architectures to build

the circuits that control the dead time between the MOSFETs conduction (in the future called non-

overlap circuits) [8].

The first architecture uses a fixed delay, which means that in every cycle, regardless of all possi-

ble changes occurred in the converter’s supply or load, the dead time between the cut down of one

transistor and the conduction of the next will be the same(Figure 1.6).

Figure 1.6: Fix dead time control signals.

The use of a fix dead time requires the time gap to be long enough to ensure that cross-conduction

does not happen in any work condition. The fixed delay method provides a solution, at the cost of a

delay that will be longer than the required for the majority of the cases. This extra time will lead to

power losses related to the conduction of the NMOS body-diode.

To solve the problems related to the fix dead time architecture, the architecture depicted in figure

1.7 was developed. This architecture makes the delay time dependent on the voltage level of the

node that connects the inductor to both the power MOSFETs. This method redefines the dead time

9

between the transistor’s turn off, and on every time it is required. This method will require a gap time

more extensive than the minimal, so will create a power loss.

Figure 1.7: Adaptive dead time schematic.

For low-voltage high-efficiency power converter’s it was required to develop a new method that

could use the information from the present cycle to predict what would happen in the next cycle. The

method mentioned above is named Predictive Delay [8]. This method uses a delay line that allows

to increase or decrease the number of delay segments (and consequentially change the dead time).

To control the delay line, a NOR gate that uses as input the drain-to-source and the gate-to-source

of the NMOS is used. This connection allows for a high output when the gap between VGS is more

significant than Vth and VDS are lower than Vth, and low output in all other cases, as shown in figure

1.8.

Figure 1.8: Predicted dead time control signal.

Every time the NOR gate’s output is high, one floor less is used in the next cycle’s delay line. This

reduces the gap between the drop in VDS and the rise of VGS , but the opposite will happen when the

gate’s output is low, the next cycle will use one extra floor in the delay line, and consequently, increase

the dead time.

The use of this last technique allows the total converter’s efficiency to increase between 1% and

2%, depending on the output voltage level.

10

1.3 Objectives

The primary purpose of this project is to develop a method that allows to built high-frequency,

DC-DC converters capable of achieving the highest efficiency possible to replace the linear voltage

regulators.

To achieve high-efficiency, the power converter’s passives have to be chosen to place the minimal

power consumption, the power transistors and them gate drivers architecture have to be chosen, and

consequentially designed to generate the best relation between switching and conduction loses.

The design of an high-efficiency DC-DC converter also require the development of a solution to

reduce the shoot-trough that will happen every time the power MOSFETs switch.

1.4 Structure of the Report

This thesis report is organized in five chapters, each one of them focused on an independent part

of the project.

This first chapter, named "Motivation and Introduction", addresses the motivation behind this work

as well as the theoretical background required to understand it. In this section, the major causes for

power losses inside DC-DC converters are presented. The first chapter also defines the project goals.

In the second chapter, named "State of the Art", projects related to high-frequency DC-DC con-

verters design are discussed. This project presents an extensive range of solutions to the same

problem, allowing the reader to grasp the advantages and disadvantages of each one. At the end

of this chapter, a subsection presents a comparison between all projects, thus laying out the most

effective characteristics of each project.

The third chapter encompasses the work done to develop the method used to design the high-

efficiency and high-frequency DC-DC converter. This method is divided into six subsections: i) the

method used to choose the right inductor; ii) the obtaining of the relation between the transistors

width and its Joule power losses; iii) the design of the non-overlap circuit; iv) the design of two differ-

ent architectures for the gate drivers; v) the analysis of the width’s value to achieve the best case for

minimal power losses; vi) the design of a converter, that works as proof of concept for this method.

The subsection that follows describes the entire device and the internal losses for the fully developed

converter. The last subsection presents the whole set of simulations done for this device as well as

the results obtained, in output current, efficiency and power losses in every component that forms the

converter.

11

The fourth chapter addresses the changes required that may be done to this kind of devices to

increase its power efficiency, output current range, or to reduce the output voltage ripple.

Finally, the fifth and last chapter presents this work’s conclusion and the base for this design

method’s application.

12

2State of the Art

13

This chapter introduces the most relevant projects used to study the topic of high frequency, inte-

grated DC-DC converter and to develop this thesis work. At the end of this chapter, a summary will

be presented of the projects refereed.

2.1 Digital Modular Control of High Frequency DC-DC Convert-ers

The authors of [9] propose a digital solution used in the control of a high-frequency DC-DC con-

verter. This solution implements a nonlinear sliding mode control using only tree comparators, with

an hysteresis window with 10 mV amplitude around the reference voltage level (vref ). The use of a

non-analog solution solves the problem created by the slow response of regular comparators, that

would be longer than the switching period of high-frequency DC-DC converters, and the issue with

the high current requirements of fast comparators, which would substantially cut down the converter’s

power efficiency.

The converter designed in [9] uses an inductance of 80nH and an output capacitance of 10µF .

The paper’s author did not specify the exact type of inductor and capacitor used.

To establish the duty-cycle required to operate the converter, an ideal duty-cycle was defined

(Dideal). Dideal is added to the duty-cycle needed to balance out the converters losses (DIRloss) and

to a temporary duty-cycle that enables the control of small variations created in the transients of both

converter and load (d). The first one is obtained dividing the reference voltage (vref ) and the supply

voltage (vBat). The DIRloss value will be achieved using a delay line, that allows to enable or disable

consecutive elements to increase or decrease the delay. The delay line has the first inverter’s tran-

sistor’s gates controlled by a clock signal with a fixed frequency. This way it is possible to make small

and continuous changes to the effective duty-cycle, without having to change the clock frequency.

Finally, a temporary duty-cycle was defined, which can control the quick adjustments required

every time a change in the load or the supply. This fluctuation is controlled by the regulation of the

current that flows to the inverters which form the delay line. The change enables an increase or de-

crease of the time required to change the logic value from 1 to 0 or 0 to 1, because this change will

so much fast, as higher the current that flow can flow through the inverter, to the next inverter’s gate,

as shown by 2.1 from [10].

dV

dt=

i

CGate(2.1)

14

By understanding the three types of contributions to the duty-cycle, it was possible for the authors

to design a control system that could control them and be functional for Process, Voltage and Tem-

perature (PVT) when working at high frequency, achieving a control architecture that is represented

in the schematic below.

Figure 2.1: Delay line and inverter’s current control.

From the schematic, it is possible to observe that when the value of the duty-cycle’s component

that controls fast transients (d) resets, the number of inverters at work will change, thus maintaining

the value of DIRloss.

After all the implementation the output voltage level at a stable output voltage ripple lower than

20mV , even when the supply voltage changes from 3V to 4.2V or when the current required by the

load goes from 100mA to 1.1A.

This work helps to understand the losses inside the converter that, in this case, will be compen-

sated by the offset DIRloss, and the need to fast change the duty-cycle to make a DC-DC converter

able to be used.

2.2 A 65MHz Switching Rate, Two-Stage Interleaved SynchronousBuck Converter with Fully Integrated Output Filter

The work [11] describes the, fully integrated, two-stage, interleaved, synchronous, buck DC-DC

converter with an on-chip filter, which works at a maximum frequency of 45MHz with an output current

15

of 200mA. This converter can achieve an efficiency of 64%. These results were obtained by the use

of a dead-time between the power transistor’s conduction. This time gap allows the MOSFETs body

diode to conduct instead of the transistor’s channel connection, which discharges the output parasitic

capacitance. This condition enables both MOSFETs to switch under zero voltage switching [12], de-

creasing that way switching losses generated by the Miller effect in both transistors.

Another feature included in this project is the use of multiple stages operating in parallel, con-

nected to the same output capacitor. This design choice allows the converter to work using a low size

capacitor do to the 180o phase gap between stages. By applying this gap between stages, the output

current ripple can be reduced while holding the fast transient response, typical from a single stage

converter.

To build this converter, a 0.18µm SiGeRFBiCMOS technology was used, which allows for an N-

buried layer. This layer, together with the N-Well ring, isolates the NMOS from the substrate injection.

Another important design choice was the creation of the filter capacitor using the parallelisation of

small components. In this case, capacitors with a value of 1pF are required to achieve them 6nF

capacitance value.

For the inductor, a high-performance inductor was chosen, capable of creating an inductance of

11nH, with a quality factor (Q)1 higher than 20. This inductor was built using a 10µm copper layer.

The paper concluded that the inductor is the main cause for power losses in this converter due to its

conduction losses. However, the losses may decrease by the use of micro-magnetic materials, that

will increase the inductance per area, and consequentially reduce the size of the inductor, which will

lead to an increase o the Q factor.

2.3 Integrated DC-DC Converter Design for Improved Wide-BandCode Division Multiple Access (WCDMA) Power Amplifier Ef-ficiency in SiGe BiCMOS Technology

In [1], a DC-DC converter was designed to be integrated into a WCDMA power amplifier, and

increase the system’s efficiency from the usual 30 to 40% at maximum output levels. Unfortunately,

due to the variation in the operation point, the power efficiency changes, as shown in Figure 2.2.

1Q = $×LR

16

Figure 2.2: Usual power efficiency for power amplifiers and the probability distribution of the power efficiencies.

The solution for this power efficiency range was to build a synchronous rectifier based buck con-

verter because it achieves higher efficiency and provides a wither output voltage range. As shown in

Figure (2.3), this was created based on 4 modules and was designed to have switching losses equal

to the conduction loses, which ensures minimal overall losses for the converter.

Each module is formed by two power MOSFETs (PMOS and NMOS), their gate driver’s circuit and

the enable circuit, which connects to an inductor common to all modules.

The ability to increase or decrease MOSFET’s power by enabling or disabling units, to reach the

output voltage level/power with minimal efficiency changes, is called "W-Switching" as defined in [13].

This method results in reduced switching losses, created by the charge and discharge of parasitic

capacities placed in the MOSFET’s gate. It has the disadvantage of increasing conduction losses but

ultimately leads to better power efficiency.

Figure 2.3: On the left, the circuit used on converter’s single unit. On the right, the complete architecture for theDC-DC converter.

To use the W-switching, the output voltage was divided into 5 steps, where the first one has all

four units enabled but at conduction without switching, supplying the output with the supply voltage.

The remaining four steps with up to four stages enabled and at switching allow the converter to supply

the output voltage in the 1.3V to the 3.3V range, according to the power amplifier’s requirements, as

17

shown in Table 2.1.

Table 2.1: Converters Required Characteristics [1]

To obtain the Vout and Iout values, it was also required to get the switching frequency used to

control the power converter. The converter’s switching frequency was a critical issue because the de-

vice has to work within a frequency range, which creates harmonic distortion outside the 1920MHz-

1980MHz transient band, for WCDMA applications. Considering this, the frequency was established

at the 88.7MHz frequency which in its turn set the value of the inductance to 9.1nH. This value is

small enough to allow the device to be placed inside the chip, however, due to a high series resistance

(between 1Ω and 2Ω), this project opted for an off-chip inductor and a capacitor.

The power transistor’s architecture used in this project boosts the power amplifier’s efficiency

from the 30% to 40% range to output levels, whit an average efficiency of 78.8%, achieving a peak

efficiency of 86%.

2.4 Intel’s Fully Integrated Voltage Regulators

Project [14] describes the Fully Integrated Voltage Regulators (FIVR) used in Intel’s R© 4th gen-

eration CoreTM microprocessors. This device is the first high-frequency converter able to produce a

large output current, and capable of being built in-package. These converters are designed using a

two-stage voltage regulator, as shown in the schematic of Figure 2.4. The first stage of the voltage

converter changes the voltage from the battery or PSU. The device can range from 12V to 20V, down

to approximately 1.8V, which will then supply the device’s second stage. That stage is formed by an ar-

ray of between eight, and up to 31 FIVRs, each one providing a different microprocessor’s component.

18

Figure 2.4: Power converter architecture.

Each of the FIVRs forming the converter’s second stage works with a switching frequency of ap-

proximately 140MHz (critical to allow the use of in-package inductors) and up to 16 phases. The

multiphase converters were tested in [15] and proved able to achieve an output current of 12A and an

efficiency between 79.3% and 84.0% for a voltage of 1.2V and up to 1.5V. The number of phases is

controlled by a PCU, which used since the 2008 Intel microprocessors, which individually manages

in real time the power losses from each FIVR, and generates the PWM used to control both HS and

LS. The circuit of a two-phase FIVR is shown by Figure 2.5.

19

Figure 2.5: Two-phase FIVR.

The Switch’s components (HS and LS) were built by a cascade of regular 22nm technology tran-

sistors, this way the power device can sustain voltage levels higher than 1.8V , which allows avoiding

the use of other processes to build high voltage devices, and keep a good switching characteristic.

In Figure 2.5, it is possible to see that this kind of converter, while being fully integrated, is divides

in divided into two different parts, the die and the package. The die contains the power devices (HS

Switches and LS Switches) and the MIM capacitors, which ensure a high-frequency decoupling. In

the package were placed the ceramic capacitors, that complete the decoupling made by the on-die

capacitors, and the Air Core Inductors, represented in Figure 2.6, placed over the die.

Figure 2.6: Air Core Inductor.

The multiphase architecture, together with the ability to use a large number of FIVR’s and in pack-

age passives, allows building converters that achieve 90% of power efficiency for output currents

between 1 and 15A and easily scalable for higher output currents. These current values were ob-

tained connecting multiple phases, allowing a maximum current of 750mA. The changes generate a

50% increase in battery lifetime for mobile products, and 2 to 3 times the rise of the converted avail-

able power. Ultimately, this leads to an increase in the burst performance.

20

2.5 PowerSwipe Project

Seven European institutions developed the PowerSwipe Project [16] with the purpose of building

a power supply in nanoCMOS technology to be used in future automotive electronics. It created in

Europe the ability to fully produce System on a Chip (SoC) power supplies required for the industry.

In the automotive industry, the use of batteries with voltage levels between 6V and 40V demands

the use of power converters capable of supplying the CMOS low voltage technology, as these require

a voltage source of approximately 1.2V. To change the supply voltage level to the defined value, Pow-

erSwipe’s solution uses a two-stage (HV DC-DC and LV DC-DC or HF DC-DC) power device.

The first one, the HV DC-DC, converts the power supplied from the battery to values between 3.3V

and 5V, achieving a maximum output current of near 500mA. This device was developed in 130nm

BCD-CMOS technology, to operate at 10MHz using for that an output low-pass filter built with a 10µH

inductor and a 1µF capacitor.

The converter’s second stage, named LV DC-DC, was designed to be placed next to the first

stage, supplied by the first stage output voltage and achieving a targeted peak efficiency of 90%. It

transforms the range of 3.3V and 5V to the voltage used by the CMOS technology used to build the

micro-controllers, as shown in Fgure 2.7.

Figure 2.7: PowerSwipe integrated power management architecture for µ controller.

As depicted in Figure 2.7, the LV DC-DC converter used in the second stage can be replaced by

a High Frequency (HF) DC-DC converter designed by Ampère Lyon [17]. This company has built a

21

200 MHz DC-DC converter with an off-chip inductance and capacitance of 51nH and 4.7nF . This

project uses a CMOS 0.25µm technology, which creates a sizable parasitic gate and drains capaci-

tances. Therefore, to boost power efficiency, it is required to use resonant gate drivers to control the

power devices. This type of gate drivers makes it possible to achieve a delivered power of 2W and an

efficiency of 77%.

Figure 2.8 shows the efficiency achieved by the step-down converters and relates it to the working

frequency. The correlation expressed in this graph allows understanding that the switching frequency

was a significant constraint to reach the Power Swipe’s target (peak efficiency higher than 90%).

Figure 2.8: Relation between the converter’s efficiency and the switching frequency.

To develop power converters capable of hitting the target peak efficiency, it is needed to boost

the performance of the two components that more decrease the power efficiency the inductor and

the output capacitor. To study and improve these components, the Power Swipe Group has Tyndall

Magnetics Research Group and IPDIA.

Tyndall’s core work was to develop and test the techniques required to build industrial inductors

used as part of SoC power devices [18]. Those inductors can be split into three types [19]: i) Spiral,

where the spiral conductor is placed between two magnetic thin-film layers; ii) the Racetrack, which

is similar to the previous one, but has a racetrack shaped conductor between the magnetic deposits;

iii) the Solenoidal type, where the conductor is coiled around the magnetic core, using several metal

layers. This last one is the less attractive alternative, due to the amount and difficulty of work required

to build it.

22

Figure 2.9: Type Racetrack micro-inductor.

The tests performed by Tyndall’s micro-inductors concluded that a silicon-based inductor could

achieve an efficiency of 93%. The significant disadvantages of a micro-inductor compared to discrete

components are higher DC winding losses and the losses by core Eddy current. As per the information

from [20] in Table 2.2, racetrack inductors, like the one in figure 2.9 are the easiest and cheaper to

build and can be designed to support an extensive range in the inductor current.

Table 2.2: Comparison of calculated and simulated results for multiple 100nH micro inductors.

As Table 2.2 shows, the same value of inductance can be achieved from a range of inductors,

thus obtaining the required output current with the minimal inductor area and resulting in the minimal

inductor power losses.

The design of high-efficiency DC-DC converters also requires the use of output capacitors with

minimal power losses and with the area and current limitation characteristics of the in-package power

systems. Targeting the development of this technology, the French company IPDIA was recently

bought by Murata. For this project, IPDIA’s capacitors provide the required ESR, ESL and capaci-

tance while the maximum area was not overtaken. The technology used to build those capacitors is

a Passive Integration Connective Substrate (PICS) technology that can achieve 500nF/mm2 in the

production version of the PICS3. Together with the "quasi-fractal2" design allows the parallelism of2quasi-fractal = form created for a repetition of the same base process.

23

multiple small capacitors to achieve a correct capacitance value, without increasing ESR and ESL

values, which leads to higher efficiency.

2.5.1 Design of a highly integrated, high frequency, low power DC-DC con-verter with cascode power stage with a 2.5D approach

To achieve greater efficiency, the PowerSwipe group has built the converter referred in [21] and

shown in Figure 2.10. This project uses integrated PICS3 deep trench capacitors, like the ones

created by IPDIA (which allow building a 16nF capacitor for the output filter), and cascode 1.2V

MOSFETs with, an in-package commercial 60nH inductor. The use of cascode transistors to work

as a macro-transistor should create lower gate capacity and lower on-state resistance. That kind of

assembly requires the use of auxiliary transistors to shortcut gate and source of the first ones and

ensure the balance between the voltage in all the devices.

Figure 2.10: Circuit with cascode MOSFET’s.

The project concludes that the use of cascode 1.2V transistors as an alternative to the conven-

tional 3.3V transistors can increase the converter’s efficiency between 10 and 91% efficiency for a

frequency of 100MHz.

2.6 Dead-Time Control System for a Synchronous Buck DC-DCConverter

As explained in section 1.2.4, all the DC-DC converters require a circuit, which places a gap be-

tween the converter’s on period (dead-time). The non-overlap circuit ensures that both MOSFETs will

not be turned on simultaneously. The project in [22] describes a methodology to change the dead-

time, using as a parameter the difference between the voltage in the Lx node and a reference voltage.

24

The solution proposed is divided into three components, the on-off block, the undershoot detector

and a delay generator as shown in figure 2.11.

Figure 2.11: Undershoot detector schematic.

The first device is the on-off block, built to enable the Lx voltage level only for the high to low

transitions. This corresponds to the PMOS change from on to off and NMOS change from off to on.

The output of the on-off block connects to the input of the undershoot detector. The purpose of

these devices is to continuously calculate the difference between the reference voltage and the volt-

age at the Lx node during the non-overlap. The undershoot detector’s output has a DC component of

V dd/2V to ensure positive voltages and a maximum dynamic range.

The last device developed in this project was the Delay Generator, that generates V sw’s delays

in the transition from high to low, being the size of the delay controlled by the average value of VDetec.

When the circuit is operating, the transistors are controlled by the high to low transition of VLx

(VBat to 0 V). The PMOS transistor is turned off by the change from high to low of the control signal,

and the NMOS transistor is turned on by the low to high transition of the dead-time controller.

Every time the voltage in the VLx node rises from 0V to VBat, the NMOS is placed at cutoff by the

control signal’s transition from low to high. The PMOS is placed at on by the low to high transition of

an output signal, which sets a fix dead-time. This fix dead-time is implemented using a simple RC

circuit.

After designing the circuit in CMOS 0.13µm technology, the power block was simulated to obtain

the dead time dependence on the load current. The results are presented in Table 2.3. This table

contains the values for the generated delay and the dead-time for a set of detection voltages pairs

(VDetec) and load currents.

The values placed in the previous table demonstrate that the system can counteract the fluctua-

25

Table 2.3: Fluctuation in dead-time and generated delay.

tion in the load current since the required dead-time are in the 8 ns to 15 ns range. This allows us

to conclude that the non-overlap interval will decrease with the rise in of the load current due to the

increase of the power supplies fluctuation created by the bonding-wires effects.

The use of a delay generator control system decreases the power losses as shown in figures 2.12

and 2.13.

Figure 2.12: Efficiency increase with the use of the control dead-time system.

Figure 2.13: Total losses decrease (in %)

As depicted in the last two figures, the losses are significantly reduced. However, with the current

increase, the reduction in power losses decreases due to the dominating effect of the converter’s

Joule losses.

26

In conclusion, the system controls the dead-time duration between 8 ns and 15 ns, for current

values between 600 mA and 100 mA. This swap results in an efficiency increase of nearly 3.5 % for

the load current’s complete range, in comparison with the fixed dead time technique.

The increase in efficiency is generated by the decrease in power losses from 19 to 32%, only

requiring an extra 4% of the die area.

2.7 Projects Comparison

Table 2.4 presents a comparison between the papers described in the previous sub-sections. This

table contains the values of the inductance, capacitance and switching frequency used in the project,

as well as the output current and efficiency. Some of the projects do not present some of the required

information.

Table 2.4: Relation between the inductance, capacitance and the output current with the converter’s efficiency.

Reference frequency (MHz) inductance (L) Capacitance (C) IOut(A) Efficiency2.1 20 MHz 80nH A 10µF A 0.15 *2.2 45 MHz 11nH C 6nF B 0.2 64%2.3 88.7MHz 9.1nH D 100nF D 0.25 78.8%2.4 140MHz * C * B and C 0.75 90%2.5 200 MHz 51nH D 4.7nF D 0.329 77 %

2.5.1 100 MHz 60µH C 16nF C 0.2 91%

* = Value not available in the paper;A = Type of devices not specified by the project authors;B = Device placed in the chip;C = Device placed in-package;D = External device.

The paper described in sub-section 2.6 was not placed in the previous table because of the infor-

mation such as the inductance value, the capacitance or the switching frequency is not available.

The information placed in Table 2.4, allows us to conclude that it is possible to design a DC-DC

converter using the inductance and capacitance previously defined, which achieve power efficiency

values large enough to be a substitute to the LDOs. It is also possible to conclude that the use of a

cascode MOSFET or a "modular" set of transistors boosts the converter’s performance.

27

28

3Power Converter Design and

Simulation

29

3.1 Method Definition

The proposed method starts with the definition of the converter’s general parameters. These val-

ues are the input and the output voltages and currents.

From the converter’s general parameters, it is possible to define the value of duty-cycle (D) that

converts the supplied voltage to the required output level, and the chose the passives (inductor and

capacitor) which support the current defined and that have the best relation between the used area

and the power dissipation and fell the requirement of specifications of distortion in current and voltage.

After been chosen the passives, the design of the MOSFETs must be done. Both the PMOS and

the NMOS transistors must be designed starting from a theoretical approach, where it will be obtained

a value for the relation between width and length near to the required to allow the maximum current

to flow through this device. The theoretical value obtained previously will be used as a starting point

to a first simulation, which will be used to get the value for the width over length ratio that supports

the required current.

The width over length relations obtained from the first simulations will be used for both the PMOS

and NMOS, as the initial value to a DC simulation, where it will be obtain the relation between the

width over length and its respective power consumption inside each of the transistor. At the same time

as the power transistors are designed, the non-overlap system is designed. This system will be used

to reduce the simultaneous conduction in the power transistor and inside the last stage of both gate

driver’s for the non-overlap architecture. The non-overlap system design will be almost independent

of the converter’s input and output voltage, depending only from the converters switching frequency.

After the design of the non-overlap system, the power transistor’s gate drivers must be designed.

For the gate driver’s design, two architectures, the regular and the non-overlap, must be tested to find

what will be the one with the best relation between power consumption, required area and complexity

for the converter’s chosen parameters.

To conclude the converter’s design, all the chosen devices must be assembled and simulated to

get the converter’s efficiency, and demonstrate its correct work.

The complete design flow for the proposed method can be seen in the flowchart in Figure 3.1.

30

Figure 3.1: Flowchart for the design method.

31

3.2 Converter’s Characteristics and Passive Devices

To design a DC-DC converter, it is required to understand what are the general specifications the

converter must be able to support to ensure that each component be correctly projected in order to

achieve the targets of this DC-DC converter.

Since this thesis goal is to develop a way to build high efficiency, in-package buck DC-DC convert-

ers, the input and output voltage and current must have the specific values. The values considered

are then placed in Table 3.1.

Table 3.1: Input and Output parameters.

Input Voltage (V) vin 3Output Voltage (V) vout 1

Output Current (mA) iout 100

The converter’s design starts with the definition of the passive components (capacitor and induc-

tor), which are used to ensure that the parameters from Table 3.1.

Taking into account the specifications and that the designed converter will be used as a replace-

ment for the low-efficiency Low-dropout (LDO) converters, this architecture will be developed to take

advantage of the external output ceramic capacitor, used to build the LDOs. This device’s ceramic

multi-layer capacitors have a capacitance of around 10µF , placed outside the converter’s die.

The relation between the inductor’s value and the minimum switching frequency required to place

the converter working at Continuous Conduction Mode (CCM) is significant for the inductor’s choice.

Therefore, it is required to know the relation between the inductor voltage level, and its charge and

discharge time.

The values of ton and toff are obtained from the boundary between the CCM and the Discontinuous

Conduction Mode (DCM), shown in 1.2.2, using for that the equations 3.1 [10]:

v = Ldi

dt(3.1)

This equation may also be written as shown in equation 3.2 and 3.3, describing the converter’s

charge (ton) and discharge (toff ).

di

dt=vin − vout

L<=> ton =

∆IL × L

vin − vout(3.2)

32

di

dt=voutL

<=> toff =∆IL × L

vout(3.3)

From this two time gaps, it is possible to obtain the switching period for the boundary between the

converter’s work modes. The ton and toff values also allow to obtaining the frequency of operation

and the duty-cycle using, respectively, equation 3.4 and equation 3.5.

fs =1

ton + toff(3.4)

D =voutvin

= 0.3333 (3.5)

From this set of equations and taking into account the output average current 100mA (which trans-

lates into a ∆iL of 200mA), it is possible to understand that the in-package inductor’s, like the ones

created by Tyndall and referenced in sub-section 2.5, can support the required inductor current (IL).

These inductors achieve an inductance of 100nH, with a minimal ton of near 10ns and a toff of near

20ns, which match with a switching frequency(fs) of 33.3MHz.From these values, it can be concluded

that the L3 from sub-section 2.5, that uses an area of 3.92mm2 and has a series resistance of 68mΩ,

would be a recommemded choice for this project.

By establishing the switching frequency at 33.3MHz the output capacitor ESR can be placed at

near 2mΩ, as per [23].

The switching frequency is also an important factor to be taken into account regarding the output

voltage ripple(∆v), created by the MOSFET’s switching and that is related with the inductor, capacitor,

duty-cycle, and switching frequency, as presented in equation 3.6 [24].

∆v =(1 −D) × vout

8CLf2s= 0.068mV (3.6)

33

3.3 Power MOSFET’s design

As explained in subsection 1.2.2, a DC-DC converter design requires great effort in developing

power MOSFETs that can hit the current values required by the inductor. For converters which use

in-package passive devices, like this one, the design of the power transistors has a large influence,

on the converter’s total efficiency, because the in-die architecture represents the majority of the power

losses. Therefore, even a small decrease in the power transistor’s losses is going to be noticeable. In

order to obtain the maximum efficiency possible for both the PMOS and NMOS power transistors it is

required to set the specific transistor’s design.

The development of both, the power transistors and their respective gate drivers was done with

the Virtuoso toolkit, developed by Cadence and using the UMC 130nm technology [25].

3.3.1 PMOS design

To prove the designed method, it was established a PMOS power transistor using the p_12hsl130e

transistor from Virtuoso’s library umc13mmrf.

To start the development, it is required to set the peak current of the inductor as the maximum

current the transistors have to support. The maximum inductor’s current was calculated, assuming

the converters working in the border between the DCM and CCM, using the equation 3.7 from [4].

IMax =Vin − Vo

LDTs = 199.8mA ≈ 200mA (3.7)

From this value, and considering the minimal supply voltage and the maximum VDS allowed, the

minimum width over length (W/L) -which allows for the maximum inductor’s current to flow - can now

be calculated from the value obtained in equation 3.10 from [24], when using the following known

equations.

ID = K × (2(VGS − Vt)VDS − V 2DS) (3.8)

K =µp × COX

2(W

L) (3.9)

ID =1

2µCox

W

L(2(VGS − Vt)VDS − V 2

DS) (3.10)

34

Equation 3.10 describes the linear relation between the transistor’s triode drain current and the

ratio of width over length. This relation allows simulating the required width and length to obtain a

specific drain current. To use the equation 3.10, it is required to know the value of µ times Cox. To get

the µ times Cox value, a small PMOS transistor have to be tested to a known pair of values for VDS

and VGS . To make the calculation easier, the simulation was done with the transistor at saturation,

setting for that VDS equal to VGS , as can be seen in the schematic of Figure 3.2, getting the value of

µ times Cox from equation 3.11 [5].

Figure 3.2: Schematic to obtain the value of µ times Cox to the PMOS transistors.

ID =1

2µCox

W

L(VGS − Vt)

2 (3.11)

The use of a VDS and VGS of three volts, with a width of 400nm and a length of 120nm, generate

a drain current of 560µA. This set of values, together with the equation 3.11 allow to obtain a µCox of

3.78 × 10−5A/V 2 to a PMOS transistor.

From the PMOS’s µCox, and from the equation3.10 it is possible to obtain a near value to the re-

quired ratio of width over length, using for VGS three volts, and for VDS two volts, getting a theoretical

width of 175µm for a length of 120nm. The chosen values were defined to be closer to the ones used

in the converter.

After been defined the theoretical width value, it was done a simulation to prof the transistor’s

35

ability to conduct the required current, using the schematic present in Figure 3.3.

Figure 3.3: Schematic to obtain PMOS Drain Current.

The schematic was used to do a transient simulation for 1ms, thus allowing to observe current that

flows through the PMOS, using for that a current prob. From the simulation, a 201mA current was

seen, proving the ability to support IMax .

Concluded the obtaining of the minimal pair of width and length that allows the maximum current to

flow, a second simulation was performed, to get the relation between the PMOS parasitic resistance

(RDS) and the width value. The schematic presented in Figure 3.4 was simulated with the purpose of

putting the transistor’s at conduction, while a current equal to the average current flows from the tran-

sistor(the average current will be half of the 200mA). As the size of the transistors could be too large,

the schematic was designed using ten PMOS connected in parallel, thus reducing the maximum size

of each one.

36

Figure 3.4: Schematic for transient simulation.

Schematic 3.4 was used to perform a DC simulation, where the width of each one of the ten tran-

sistors placed in parallel was changed from 1.1µm to 20mm in 100nm steps. Simulation 3.4 derives

the Joule losses used to develop the power transistor’s gate drivers, which will be explained in sub-

section 3.5.3.

Figure 3.5: Relation between the transistor’s width and the Joule power losses.

From these two simulations, it is possible to obtain the width values that allow the transistor to have

a power consumption small enough to be used in the converter, without decrease the power efficiency.

37

3.3.2 NMOS design

To design this power transistor, a reference inductor’s maximum current (IMax) 3.7, of approxi-

mately 200mA was used. As shown in subsection 3.3.1, this will be the maximum current that the

power MOSFET has to support.

As in the PMOS power transistor design, the first step was to obtain the value of Cox times µ for

this type of MOSFETs. So a simulation similar to the one done to develop the PMOS, was done to

get the value of Cox times µ for this type of transistors.

Figure 3.6: Schematic to obtain the value of µ times Cox to the NMOS transistors.

The schematic in Figure 3.6, consists in a transistor with a length of 120nm, a width of 400nm and

support a drain current of 1.06mA, when VGS and VDS are three volts, what means a Cox times µ

of 7, 16 × 10−5. After being obtained the Cox times µ value, it was used to get the theoretical width

to ensure the transistor’s ability to support the maximum current, using for that equation 3.10. To

ensure that the transistor is at triode zone, VGS and VDS have been forced to three volts and one volt,

respectively to replicate the converter’s voltage levels.

Using the values previously presented, it was possible to set a width of 140µm with a length of

120nm to ensure the maximum current required. This value was tested, using the schematic placed

in Figure 3.3, to ensure that the drain current is higher enough.

38

Figure 3.7: Schematic to obtain NMOS Drain Current.

The result of the previous simulation will be the starting point for the second simulation, depicted

by the schematic in Figure 3.8. The schematic will be used to obtain the power losses range and its

relation to the transistor’s width. Therefore, to ensure that the transistor’s drain current can be higher

than the maximum inductor’s current, the transistor’s width has to be larger than 140µm for a length

of 120nm.

Figure 3.8: Relation between the transistor’s width and the Joule power losses.

Schematic 3.8 was used to perform a DC simulation, where the width of each one of the ten tran-

39

sistors placed in parallel was changed from 1.1µm to 20mm in 100nm steps. The schematic was used

to obtain the Joule power losses in figure 3.9 and to optimize the power NMOS gate drivers. These

will have maximum efficiency point when the Joule power losses are equal to the power required to

charge and discharge the gate driver’s in each work cycle.

Figure 3.9: Joule loss relation between the transistor’s width and the Joule power loss.

From these two simulations, it is possible to obtain the width values that allow the transistor to have

a power consumption small enough to be used in the converter, without decrease the power efficiency.

40

3.4 Non-overlap control system

As explained in subsection 1.2.4, the largest source of power simultaneous is the common con-

duction between the power MOSFETs. To solve this problem, it was developed a system that allows

establishing a fix dead-time between the change from conduction to the cutoff state of one transistor.

Hereafter, it is designated as the non-overlap system.

The use of a fix dead-time to solve the overlap will reduce the shoot-through. However for the

majority of the switches, the dead-time will not be the exact time required to completely erase the

shoot-through.

The non-overlap system was developed using just logical devices from the CommonLib, and it is

divided into two separated segments, as seen in figure 3.10.

Figure 3.10: Schematic for the non-overlap circuit.

The schematic’s upper segment is used to generate the signal controlling the PMOS gate driver

(using the Ppulse signal). The PWM signal that will actuate this gate driver will have a low value (rep-

resenting the conduction to this transistor) when the control system’s signal is high, and the signal

that controlling the NMOS power transistor is already low. This ensures that when the PMOS power

transistor starts to conduct, the NMOS is already cut. On the other hand, the lower segment is used

to produce the PWM signal controlling the NMOS (the Npulse signal). This signal will be high when

the control signal is low, and the signal coming from the PMOS gate driver (the Pdriver) is high.

As per Figure 3.11, when the control signal (represented in pink in the upper graphic) changes

from low to high, it the NMOS gate driver control signal changes from high to low. Consequentially, it

makes the signal that actuates the NMOS gate to change, which will allow the signal that controls the

PMOS gate driver to change to the low value.

41

Figure 3.11: Signals changes when the control signal(up signal) changes from low to high.

On the other hand, when the control signal changes from high to low both segments are ready to

change its state. This, way four sequential changes from low to high appear: i) change in the Ppluse

signal (in dark blue); ii) followed by the signal Pdriver actuating the PMOS power transistor (in red);

iii) Npulse signal supplying the NMOS gate drivers (in light blue); iv) and finally the signal change in

the NMOS power transistor gate (in green).

Figure 3.12: Signals changes when the control signal changes(up signal) from high to low.

42

3.5 MOSFET gate drivers design

The switching of large size transistors, like the power transistors used in buck DC-DC converters,

require a large current to charge the parasitic gate capacitance fast enough, as in equation 2.1. This

device allows for the use of digital logic to control the power transistors, thus ensuring the minimum

possible between the control signal’s generation and the effective switching of the power transistors.

To reduce power consumption, two different architecture types (presented in sub-sections 3.5.1

and 3.5.2) can be used. To choose the best option, both will be tested, and the decision will take in

account if they can perform the required task, as well as factors such as power dissipation, required

area and complexity.

3.5.1 Regular Gate Drivers

The first gate driver architecture to be tested and developed will be the simplest one. These drivers

were built with an array of inverters, with the output connected to the next inverter input to form a delay

line, as shown in figure 3.13.

Figure 3.13: Simple Gate Driver Schematic.

To ensure the ability of the gate driver to supply the power transistors, the first stage counting from

the power transistor has to be 20 times smaller than the power transistor. The remaining have to be

10 times smaller than its predecessor until the minimal transistor’s size is achieved. This reduction in

the transistor’s width allows for the logical circuit to be used to control the switching, and for all stages

to be able to force the switch in the transistors, which have to be controlled with the minimal delay

possible.

Once the gate driver’s basic architecture was defined, a set of transient simulations were carried

out. These were designed to obtain the relation between the power dissipated inside the gate drivers,

and the power transistor’s size (which is going to be proportional to every gate driver stage).

43

From the previous simulation, and from the relation between the power transistor’s size and its

internal Joule, it is possible to obtain the width value for both MOSFETs, which will produce the

lowest power consumption by the power converter. To achieve this, a set of points have to be chosen

to obtain the initial values for both gate driver’s power consumption. These values vary approximately

linearly with the power consumption and together with the minimizing of the Joule losses, will let

us obtain the width value leading to Joule power losses similar to the power consumption in the gate

driver. For the tested converter the relation between the width and gate driver and between width, and

Joule power losses for both the PMOS and NMOS power transistors and the gate driver is depicted

in figures 3.14 and figure 3.15 respectively.

Figure 3.14: Relation between transistor’s width and the power losses both inside the gate driver and by theJoule effect for the PMOS.

Figure 3.15: Relation between transistor’s width and the power losses both inside the gate driver and by Jouleeffect for the NMOS.

Now that the values of the two widths are known, it is possible to find them in Table 3.2.

44

Table 3.2: Width and length values for both power transistors.

Width (mm) Length (nm)PMOS 6.65 120NMOS 1.55 120

3.5.2 Non-overlap gate drivers

After defining the power transistor’s width as well as the size for all the gate driver’s stages, the

use of a non-overlap circuit may be required. This circuit may be similar to the one designed to place

a dead time between the power transistors switching and referenced in 3.4, inside both power transis-

tor’s gate drivers, to remove the shoot-through which may occur in this device’s last stage. This gate

driver’s architecture allows for the reduction of the shoot-through power losses, in the gate driver’s

last stage, but requires the use of almost twice the number of inverters, as can be seen in figure 3.16.

Figure 3.16: Non-overlap Gate Driver Schematic.

The non-overlap gate drivers will be advantageous when the shoot-through power consumption is

higher than the one required by the extra inverters used in this type of gate drivers. So, to develop

high-efficiency power converters, it is needed to test the architecture that allows the best relation be-

tween efficiency increase, required area and complexity, as described in section 3.5.3.

3.5.3 Gate Driver’s comparison

To choose between the regular and the non-overlap gate driver architecture, it is required to un-

derstand the relation between the power losses in both the devices. To do so, both architectures

45

have to be simulated with the purpose of defining the width value, which sets the same amount of

shoot-through power losses like the one required for the extra inverters. For the tested converter, both

architectures have been tested for width values of 100µm, 1mm, 5mm and 10mm.

Figure 3.17: Power consumption in regular gate driver (in blue) and in non-overlap gate driver (in orange) andthe difference between them (in grey).

As in Figure 3.17, for small width values, both the architectures achieve similar deficiencies.The

gate driver architecture without non-overlap system will start to be less efficient than the non-overlap

gate driver for width values greater than 1mm. For width values higher than 1mm, the choice between

the two architectures has to be done taking into account the relation between power saved in the gate

driver, its implication in the converter power efficiency, the required area and complexity.

For the tested converter, a decrease in power consumption of a few micro Watt will not result in

a significant increase in the power efficiency. Therefore the choice was the gate driver architecture

without the non-overlap system due to the reduced required area.

46

3.6 Output stage design and parasitic quantification

After developing all devices comprising the power converter, it was possible to obtain the maximum

theoretical efficiency. This value may be derived through the theoretical value of output current, the

inductor’s parasitic resistance, and the values obtained by simulating the power consumption inside

both the gate driver and the power transistor’s parasitic resistance. For the designed converter, the

values obtained can be found in Table 3.6, with their relation shown by equation 3.12.

Table 3.3: List of converter’s parameters.

Iout 100 (mA)Inductor’s Parasitic Resistor (RL) 0.068 (Ω)Capacitors ESR (CESR) 0.02 (Ω)PMOS Gate Drivers 1.61 (mW)NMOS Gate Drivers 2.11 (mW)

ηTheoretical =IoutVout

IoutVout + I2out(RL + CESR) + 2 × PPMOS + 2 × PNMOS= 92.32% (3.12)

From equation 3.12, the maximum power efficiency for the designed converter will be near 92%.

The difference between the converter’s power efficiency and the effective converter’s efficiency will be

closer to the power spend by common conduction.

Figure 3.18: Power stage schematic with the parasitic resistances of both inductor and capacitor.

The figure 3.18 have the converter’s schematic with all the sources of power dissipation placed in

the right place.

47

3.7 Simulation and results

After concluding the power converter’s design, it has to be tested to prove its correct work. For

that, a transient simulation allows us to see all signal changes until the converter achieves its steady

state. This simulation will present all internal waveforms, from which all the sources of power con-

sumption are observed and quantified.

To test the developed converter, the schematic present in Figure 3.19 was built. This schematic

places together the designed blocks (both power transistors and their gate drivers), the inductor used

to simulate the one developed by Tyndall, a pulse voltage source to replace the block responsible for

controlling the MOSFET’s switching and the supply voltage (ground and load).

In addition to all components previously referred, a set of voltage sources were also added to

the schematic. These will not supply the converter but instead will going to work as current probes,

allowing us to observe the current flowing from critical parts.

Figure 3.19: Schematic used to do the converter’s complete simulation.

The vpulse voltage source, used as a control for the converter, has been configured to work at a

frequency of nearly 33MHz, that match with a period of 30ns and with a ton value of 10.2ns and a rise

and fall time of 100ps.

From the simulation’s execution, for a period of 60µs and with a step1 of 100ps, it is possible to ob-

tain the variation of the output voltage, which will be equal to the current change due to the resistance

1step is the difference between the time of two consecutive iterations in the simulation

48

(10Ω) used as a load. The output voltage waveform can be observed in figure 3.20.

Figure 3.20: Variation in the output voltage with time.

By observing the output voltage waveform, it is possible to conclude that the power converter

achieves the steady state after 20µs when working at a frequency of 33MHz and with a duty-cycle of

nearly 33%. After 20µs, the converter’s signals start to be periodic, as per figure 3.21.

Figure 3.21: Variation in the inductor’s current( in blue), the output voltage ripple( in pink), and the control signal(at red) for steady state.

The figure 3.21 shows the relation between the fluctuations in the inductor’s current with the con-

trol signal. The inductor’s current has a range of 200mA with a mean value equal the output current

value, charging when the control signal is set to high and discharging when that signal is set to low.

The rise time is half the time required to return the inductor current value to zero, due to the difference

between the voltage levels in the converter’s input and output.

The fluctuation in the inductor’s current will be passed to the output voltage, being the AC compo-

nent of the current will be absorbed by the capacitor.

49

After observing the inductor’s current variation for a converter at a steady state, it was necessary

to get the values for the power supplied to the converter and its distribution by the different compo-

nents, as a way to obtain the value for the converter’s power efficiency. For the defined output current

of 100mA, the voltage sources placed in the schematic in figure 3.19 were used to divide the current

flowing from the power source between the components. From this, the causes of power consumption

in this converter were observed. The results for the power supplied by the power source, the power

consumed in the internal components and the power efficiency can be found in Table 3.4.

Table 3.4: Relation between the power efficiency and the output current.

Power Supplied (mW) 116.57Power Stage Loses (mW) 12.67PMOS Driver Switching Loses (mW) 4.49NMOS Driver Switching Loses (mW) 2.17Non-overlap Circuit Loses (mW) 0.01935Total Loses (mW) 19.35Power Efficiency (%) 83.4

From the values in Table 3.4, the graphics in Figure 3.22 are obtained. These show the relation

between the different sources of power losses.

Figure 3.22: Power consumption split between all components.

To conclude the simulations performed to a DC-DC converter, a set of transient simulations have

to be done to test the relation between the converter’s power efficiency with the output current. To

obtain this relation, the test schematic has to be changed, by replacing the resistance working has

a load for a current source, as represented in figure 3.23. The use of a current source as the load

will allow us to fix a current value, and from that obtain the power required by the converter from the

source to generate it.

50

Figure 3.23: Schematic used to perform the converter’s complete simulation.

The developed converter has an output current of 100mA. The current values used in these tests

were 10mA, 20mA, 40mA, 60mA, 80mA, 100mA, 120mA and 140mA. The converter’s efficiency to

the corresponding output current is shown in Table 3.5 and used to generate the efficiency fluctuation

graph.

Table 3.5: Relation between the power efficiency and the output current.

Output Current (mA) Efficiency (%)10 36,320 55,940 71,160 77,480 81,3

100 83,3120 84,5140 84,3

51

Figure 3.24: Relation between the power efficiency and the output current.

From figure 3.24, we may observe the influence of all power dissipation sources in the fluctuation

of the converter’s power efficiency. When the output current is low, the efficiency will also be lower

because the power required to switch the converter is going to be much higher than the output power

supplied. With the increase of the output current, and consequently of the power delivered to the load,

the impact of the switching losses starts to decrease, but at the same time, the Joule power losses

begin to increase. When the efficiency value achieves its peak, both power dissipation sources are

equal, and this happens for current values between 100mA and 120mA. For currents higher than this

range, the dissipation created by the Joule power losses will start to increase, at a higher rate than

the increase in the output power, thus decreasing the converter’s power efficiency.

52

4Conclusion

53

The research for this report was focused on the existent techniques and designs used to build

high-frequency in package DC-DC converters efficient enough to be an alternative to the linear volt-

age regulators. With this work, it was demonstrated that the use of in-package passives, like the

inductors created by Tyndall or the capacitors developed by IPDIA [16], improve the converter’s effi-

ciency. On the other hand, the project [21] also confirms that the use of cascode MOSFET’s allows

increasing the power efficiency.

Also, this report also describes a method that can be used to develop high-efficiency power stages

for buck DC-DC converters, capable of supplying a high range of output currents. To achieve this goal,

this method uses passives placed in-package to reduce their internal resistance and consequentially

decrease the converter’s total power losses. This method also focuses on achieving the point where

the losses created by the transistor’s parasitic resistance, the power required to make it, and its gate

driver switch are the same because that is the lowest power loss for the sum of both the components.

The use of the method proposed by this project allows designing power converters with the higher

power efficiency possible for an extensive range of output currents, according to the limitation made

for the inductance and capacitance.

With this project, it is possible to prove that the main advantage of use Buck DC-DC converters,

when compared with the linear regulators, is the higher power efficiency. When compared with the

linear regulator’s, the Buck converter will achieve a higher efficiency gain, as higher is the difference

between the supply and the output voltage. On the other way, the DC-DC converter requires a much

complex control system, a much larger area (that can not be tested for the developed converter, be-

cause this value is obtained from the converter’s layout) and generates an output voltage and current

with higher ripple, due to the continuous switching, that is not present in the linear regulators.

54

5Future Work

55

Having concluded the method’s description to design high-efficiency DC-DC converters, the next

steps will be divided into two separated categories, the structural changes and the architectonic

changes.

The first type of changes encompasses adjustments inside the power converter itself and the im-

plementation of new modules. These will enable this type of converters to work independently of

external devices or to decrease the power consumption.

The structural changes may include placing the capacitor inside the package, as it was done in this

project for the inductor, and by developing a method to build high-efficiency control systems capable

of controlling the power converters. This allows for the converter to have all components required to

work inside the power converter package.

In the architectural changes, the evolution of this kind of devices may comprise the development

of an high-efficiency, high-frequency modular DC-DC converter, as the one described in section 2.3.

This kind of converter allows designing devices with a high range of output current, without suffering

from efficiency decrease. This is because every block is designed for a specific output current, and

the increase or decrease of the total block output current will be controlled by the enabling, or disable

of the modules, thus ensuring that every block is as close as possible to the maximum efficiency.

As addiction to a modular architecture to the power MOSFETs implementation 2.3 the use of

multiple inductors connected to the power MOSFETs block, as it is done by Microsoft 2.4, can be a

way to achieve better efficiency and to reduce the output voltage ripple, due to the module’s out of

phase switching that made the first filtration before the one formed by the capacitor.

All these advances together will be useful to design a DC-DC converter capable of being used in

a large range of devices, increasing their power efficiency and their output current range.

56

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