HardWireTM FpgASIC

The Superior ASIC Solution

FPGA FpgASIC

CORES

Mission

Help our customers with faster time to market andflexible product life cycle management through programmable logic solutions

of software, application engineering and siliconSili

con

Software

Application Engineering

ASIC Alternatives

FPGAFPGA

CustomHighest DensityASIC Tools

CPLD

ProgrammableGA ArchitectureHigh DensityASIC Tools

ProgrammablePAL ArchitectureMedium DensityPAL-like ToolsProgrammable

AND/ORArchitectureLow DensitySimple Tools

XilinxProduct

LineFpgASIC

CustomTransparentConversion100% Tested

PAL™

ASICASIC

FPGA Technology Roadmap

1995 1997 1998 1999

Year

XC4000ELargest DeviceXC4025E0.5m5 Volt Power Supply

XC4000EXLargest DeviceXC4036EX0.5m5 Volt Power Supply30% faster than E

XC4000XLLargest DeviceXC4085XL0.35m3.3 Volt Power Supply30% faster than EX

XC4000XVLargest DeviceXC40250XV0.25m2.5 Volt Power Supply30% Faster than XL

1996

Next GenerationUp to 400klogic gates0.25/0.18

Den

sity

/Per

form

ance

2.0M gates(175K logic cells)

in the year2001

2.0M gates(175K logic cells)

in the year2001

Reduced Simulation Requirements— Hardware Verification

Concurrent Development of System Hardware and Software

Highly Flexible No Test Vector Generation No Prototype or Re-spin Leadtime

FPGA Design Advantages

* Source: Integrated Circuit Engineering Corporation, 1996

ASIC Design Time by Task

Test VectorGeneration

40%

ASIC Test Vector

ASIC Test VectorGeneration

Generation40%40%

Prototype TestPrototype Test10%10%

Vendor InterfaceVendor Interface10%10%

Schematic CaptureSchematic Capture10%10%

Specifications - 5%Specifications - 5%

25%25%

Simulation

Simulation

The Xilinx Advantage “Design-Once”

Fast Development Time-to-Market Concurrent Engineering Flexibility

No Customer Re-design No Customer Vectors All FPGA Features Mask Programmed Pricing

FpgASIC

ConversionFPGADesign

HardWireASICFpgASIC

Fastest Time from Design Concept to Low-cost Silicon

Typical Product Life Cycle ModelVO

LUM

E

PRODUCTIONRAMP-UP

UNPLANNED UPSIDE

END-OF-LIFE

PROGRAMMABLE VOLUME

HardWiire FpgASIC

Design and prototype with FPGAProduction ramp in FPGA during FpgASIC conversionFPGA for production upsides and system E-O-L

Xilinx FPGA + FpgASIC Advantage“Design Once”

Logic Design

FPGA

FpgASIC

ASIC

“Make”Non-Turn-key

“Buy” Turn-Key

FPGA Implementation

FpgaASIC Implementation

Option

ASIC Implementation

Powerful Unique Xilinx Logic Methodology

Xilinx Holds the Patenton “FPGA Conversion Without Re-Design”

HardWire FpgASIC Technology Roadmap

1992 1994 1997 1998

HW1• 0.8 Technology• FPGA Replica• Single Mask Personalization• “Direct-Map” Conversion

HW2• 0.6Technology • Sea of Gates Architecture (S.O.G.)• Die Size Optimized• “DesignLockTM” Conversion Methodology

XH3• 0.5/ 0.35 Technology• First FpgASIC • High performance/Size-optimized ASIC Core• “DesignLock 3”

XH4• 0.25/ 0.18Technology• FPGA-specific Architecture• High Performance/Embedded

Cores• Advanced Mapping

1999

Xilinx Introduces the FpgASICXH3 HardWire ASIC Family

Built in Xilinx Features

Package Optimized Die Sizes

Same Proven DESIGNLOCK Flow

Performance Optimized for Xilinx FPGA’s

Competitive With Commercial ASIC’s

XH3 Family Product Support

DEVICE XH302 XH304 XH306 XH308 XH310 XH312

DLM USABLE 14,000 25,000 45,000 70,000 90,000 140,000GATES

MAX PADS 136 172 204 240 292 352

PACKAGES PC84 TQ144 PQ160 PQ240 PQ240 SUPPORTED PC84 PQ100 PQ208 BG225 BG225 PQ304

PQ100 TQ100 BG256 BG256 BG352 TQ100 VQ100 HQ304 BG432 VQ100 TQ144 BG352 PQ160

E/EX XC4005 XC4010 XC4013 XC4020 XC4025 XC4028FPGAs XC4008 XC4013 XC4020 XC4025 XC4028 XC4036SUPPORTED XC4010 XC4025 XC4028 XC4036 XC4013

FPGA + HardWire FpgASIC The Superior ASIC Solution

FPGA +FpgASIC

Benefit ASICAlternative

Flexible Developmentwith FPGA

Quickly respond tomarket requirements

Delays for redesign

Working silicon atdesign start with FPGA

Early systemverification and rapid

prototype

Can use onlysimulation to verify

design

Cost-effective earlyproduction device

Off-the-shelfavailability with noNRE commitment

Inventory risk,minimum order qty

Turn-key conversion toHardWire FpgASIC

Little engineeringrequirement for cost-

reduction

Need test vectordevelopment by

design engineering

FPGANOWHW2

NOWXH3

4Q98 *XH3L

TBDXH4

E/ EX(5V) X

XL(3.3V) X X

XV(3.3V) X X

Virtex (3.3V) X

Spartan NotNeeded

* 1st Production submittals

HardWire FpgASIC Roadmap

FpgASIC Differentiation vs. ASIC

Key Differentiator Customer Benefit

DesignLock™ No verification/simulation Same I/O as FPGA Same start-up timing Same RAM as FPGA No test vectors to write

FpgASIC Architecture FPGA Compatibility

Turn-key Conversion No customer resources

FPGA FpgASIC

CORES

Summary

Result: Superior Time-To-Volume

• Increased demand for ASIC• HardWire ASIC best solution• Essential for selling hi-density FPGAs

Faster, Denser

Design Trend