hard disk controller technical manual jan84

8/2/2019 Hard Disk Controller Technical Manual Jan84

1/31

Technical Manual Hard Disk Controller

Preliminary documentation on hard disk controllerand multi hard disks. November 23, 19820Updated, 6/23/83 Finmware 2.7 ORBUpdated, 1/06/84 Firmware 3.0 ORB1 .0 HARD DISK CONTROLLER

1.1 OVERVEIWThe CPU-floppy disk drive sub-system of a OSC-3/4hard disk unit may be operated under CP/M in thenormal way. However, a second board is necessaryfor the harddisk. This board is called the HardDisk Controller (HOC).The HOC! has i ts own Z80 CPU with 32K of RAM buffer.I t also has a 1K prom. The flow of data for a diskwrite is as follows:A. Data exits the host CPU board through J3 (parallel port).B. Data enters the HOC board through P1h (parallelport) .C. Data is converted to serial data by the HOC


2/31


A. Power up or hard reset ini t ial ization.B. Host command and data communication.C. Disk read am wr i te operations.D. Error detection.NOTE--Error correction is handled by fi rmware in

RAM.

1.2.1 Power Up or Hard Reset In i t i a l i za t ionThe HOC begins execution upon power up a t OOOOh. I fyou executed a system reset, the HOC jumps to thislocation. The ini t ial izat ion procedure begins bysetting the stack pointer, clearing the host inter-face status f l ip-flop. .Next, 1K of the software for operation with yourCP1M or Oasis operating systan is read into memoryfrom track 0, head 0, sector 1 and stored in memorystar t ing a t 4100h. The HOC now waits in a loop for acommand from the host computer.When the f i r s t commarrl for operating system firmwarei s received, the firmware does i ts ini t i l izat ion.This includes finding which volumes are present for


3/31


memory star t ing at 4080h. The host can sen::l com-mands to the HOC. '!he commands have been discussedpreviously.

1.2 .3 Disk Read and Write Opera t ionsA read commaoo causes a disk read. I f an erroroccurs, the location on the harddisk wil l be rereadthe number of times specified by byte 6 of thecommand block.The BST is consulted to determine i f the disklocation is written on a replacement sector on thelast two valid tracks. When the correct location isdeterminoo, the head is selected arrl the differencebetween the old track and the new track computed.

1.2 .4 Error Detect ionAn error message is genera oo and the read operationstops i f the track number generate3 is greater thanthe maximum number of tracks on the harddisk. I fa l l is correct, step pulses are generated aoo thehead is move3 to the new position on the harddisk.The HrC program wai ts for the SEEK COMPLETE signal


4/31


The correct sector is foum usirg a read am abort.The f i rs t 32 bytes of each sector are read. If thesector read is not the sector previous to the sectorwanted, the read is repeated on the next sector.When the sector previous to th e desirErl sector isfound the HOC reads the entire next sector.The hardware sequence for a read am abort or a fullsector read is identical. The only difference isthe HOC software aborts the read after 32 bytes.1.3 .5 HARD. DISK READThe hardware read sequence is started with an outputcommand from the HOC CPU. This resets the bytecounter and turns over memory buffer control to theHOC control logic. Data is read off the disk at thebeginning of the next sector pulse. The controllogic searches fo r th e sync byte. When the syncbyte is read, a bit counter starts and data isshiftErl into a shif t register. After 8 bits havebeen shifted, the data is loaded into the memorybuffer. The memory location of the buffer is incre-mented and more data is stored as each byte is


5/31


ERRORthe disk read is finished.Error "on", indicates that data read offthe disk failErl the Ex::x: check.

BYTE2048 This signal is used to time the hardwareportion of the error correction.When BYTE32 returns to "0", control is returned tothe HOC CPU. If the CPU is doi03 a complete sectorread, i t moniters the BUSY line. When the disk hascompletErl the read, BUSY returns to "0" am the HOCCPU checks the ERROR line. If ERROR is "0", thereis no error in the read am control returns to theHOC CPU. Data is movErl from the HOC data buffer tothe host computer RAM am the harddisk read iscomplete.

1 .2 .6 Read Error Correct ionI f ERROR i s" ' ' ' , the HDC CPU does not take overmemory control from the HOC control logic. Instead,the CPU monitors BYTE2048 am takes control when i tbecomes active.


6/31


length 11 or less or two errors of length 2 or less.When the data is corrected, i t is transmitted to thehost computer am the HOC waits in a loop foranother command.

1.2 .7 Hard Disk wri tesA "write command" writes a1K byte block of data tothe harddisk. The HOC wil l retry a write error thenumber of times specified by bits 0 through 6 ofbyte 6 of the commam block. The HOC wil l alsoperform a read after write to verify data written tothe harddisk i f b i t 7 of byte 6 of the command blockis se t to "1".A write sequence begins with a transfer of data fromthe host CPU to the HOC. This data is stored in theHOC I/O buffer beginning a t E017h. Next, the speci-fied disk location is compare1 to entr ies in theBST. I f a match occurs, a specific sector from thespare tracks is used for the write. The correcthead is now moved to the track for the wri tee '!hisis done in the same manner as a read from the harddisk.


7/31

Technical Manual

the following format:14 l!ttes 8 l!ttes

O's l(;bllmk IHard Disk Controller

1024 l!ttes 4 l!ttes 8 + l!ttesD:lta I 0'5

The correct S e c t o ~ to be written to on the harddiskis fourrl in the same manner as for a read from theharddisk.The hardware write sequence begins with an outputcommaoo from the CPU. For the Format write Commaoo(command 4), sector 1 is written using INDEX as thereference point. This is necessary for an unfor-matted harddisk because the previous sector may nothave been created- yet. If this was the case, thenormal reference for reading and writing a sectorwill not exist. All other sectors are written inthe normal manner.


8/31


The sector pulse follow ing the CPU output commandclocks WRTGATE to "1" and resets the EIX: shiftregisters (to zero). WR'roATE write enables theharddisk. Control of the data buffer memory isgiven to the controller logic. The bit counter isalready counting in sync with the disk generatedclock. All disk write functions are synchronouswith this clock. With the bit counter counting,data is read from memory startirg at EOOOh. I t isshifted out of the shift register at 7.1 mbits persecom. The En: hardware is generating an ax codewhile data is being written. After the data preambleam data have been written to the disk, a four byteEIX: code is written. The rest of the sector isfilled with O's from the buffer until the nextsector pulse. The sector pulse clocks WRTGATE to"0" which disables wr i tes to the harddisk. Thiscompletes the hardware write sequence.1 .2 .8 Write Error Correct ionDuring the t ime the HOC log ic i s sh i f t ing data tothe disk , the HOC CPU i s monitoring BUSY and WRTFLT.I f a faul t condi t ion develops during a disk wri te , aWRTFLT signal i s generated. This resul ts in the HOC


9/31


1.3 BOARD DESCRIPTIONThe HOC has the following subsections:1. A Z80 CPU operatiOJ a t 4Mhz under ROM or RAMcontrol.2. 16K of CPU executable memory, 16K of I/O buffermemory, am a 1K prom.3. Parallel port interface to DOC-3 or DOC-4.4. HOC board to harddisk drive interface port.5. HOC control program. 'Ibis program is run by the

Z80 CPU on the HOC board. The program performs3 major functions:A. Operate the 16K buffer area.B. Control head select and seek.Moniter the drive status signals.C. Generate check bits on write and verifiyon read. Perform error correction i fnecessaryD. Communicate with the host CP/M

Host CPU to HDC In t e r faceThe parallel port interface is the means of commun-ication between the host CPU am the HOC CPU. The


10/31


OUTDATA/ When OtrrDATA is active low, data is gatedfrom the host's data bus to the interfacechip on the HOC board.RESET/ When RESET is active low, rom is reset andrestarts from location o.NMI/ When NMI is active low, a non maskableinterupt occurs and the i n t ~ u p t proces-sing restarts the rom at location o.

These signals have the following port numbers on a DSC 3/4:I NSTATUS/ 8HINDATA/ 1HOtJrDATA/ 1HRESET/NMI/ OH


11/31


1 .4 SOFTWARE FOR HANDSHAKINGThe CPU and fIDe boards work asynchronously and handshaking is necessary to communicate. This programsample is the handshake code which is executedbefore a transfer of data. Both subroutines must beinitialized for the same sized block of data. '!hey.also must use the same buffer address in memory.

1.4 .1 Host CPU Write Block Subrout inei This subroutine writes a block of data to the PP interface; Enter the subroutine with registers set as follows:i DE = Block size or byte count; HI. = Address of data buffer;writPP:mvi C,outdatamov B,Emov A,D

ora Brzwrtloop:ini i f byte count = 0, finishediwrite data to parallel portinstatusrrcj rc wrtloop ; loop i f IIDC has not r e c ~ i vErl data


12/31


; HL =Address of data buffer;readPP:mvi C,fbmov B, Emov A,Dora Arzrdloop:in fc

rrcrrc

; i f byte cOunt = 0, finished;read data fran the parallel portjrnc rdloop ; loop i f host CPU hasn' t sent datain i ;rec data fran port, HL=HL+1, B=B-1jrnz rdloop ; i f B=O, fal l throughdcr Dj rnz rdloop ; loop i f D has morere t ;finished reading from parallel port


13/31


1 .5 HDC TO HARDDISK INTERFACE BOARDThe HOC to harddisk interface provides all of thenecessary signals for the operation of the harddisk.The interface connects these signals to the HOClogic.The following interface signals are necessary:A. WRTGATE/ active low enables harddisk for writingdataB. WRTDATA write serial data to the harddiskC. ROCLK clock signal to recrl to aoo write fromharddiskD. RDGATE/ active low enables harddisk fo r readingdataE. RDDATA serial data input line from the harddiskF. SEX:TOR/ active low pulse marks beginning ofeach sectorAll other signals are connected via input and outputports. These ports are FE am FF.The signals fo r each port are as follows:


14/31


Bit Description

DO A logical one irrlicates that the drive is readyfor operation.01 A logical one indicates seek complete. ( S ~ M P ) 02 A logical one irrlicates the R/W arm is on track

O.03 A logical one indicates a WRTFLT. 'Ibis meansthat a fault corrlition exists on the harddisk.'Ibis condition is reset by an. active FAULT

CLFAR. Read am write operations to theharddisk are inhibited unt i l FAULT CLEAR goesactive then inactive.04 A logical one indicates that INDEX status f l ip-

flop has been set by an index pulse.C.OUT FF Outputs harddisk command data to thedrive


15/31


The correct head is selecte1 usiOJ the binary number .given by the above bits. DO is the low order bitand 03 i s the high order bit .04 This bit indicates the direction of the headmovement when step pulses are appl ied. Alogical zero defines the direction as towardsthe edge of the disk. A logical one defines thedirection as towards the center of the disk.05 This is the step pulse line which causes headmovement. The harddisk control program providesthe tep pulses to the harddisk read/write heads.A step pulse is a low level outpudt followe1 bya high level followed by a low level output.06 This is the FAULT CLEAR bi t . 'Ibis is an activehigh signal. When this bit is toggle1 high then

low bits 0 and 1 are interpreted as thecomplement of the volume to select by the diskmultiplexor.07 Not used.


16/31


F. OUT R: Comnaoo to hard disk, bits as follows:DO One for read request.01 One for write request.02 One to give ram to disk interface.04 One for write enable06 Sets bit 14 in ram address when disk has ram.07 Sets bit 15 in ram address when disk has ram.G. IN FD Samples status of controller hardware,bits as follows:Bit Description

04 Set i f byte 32 has been read.05 Set if busy with write.


17/31


1 .6 DESCRIPTION OF FIRMWAREThere are two levels of HOC firmware. Level oneresides in ROM. I t is 1K bytes from 0000 to 03FFh.I t controls all of the basic disk operations andcommunication with the host CPU. Level 2 resides inRAM from 4000h to 7FFFh max and is loaded from theharddisk. A cold boot or hard reset loads 1k oflevel 2 firmwarefrom the harddisk, track 0, head 0, sector 1.Level one FirmwareThe ROM program contains the routi"nes for:

A.B. System in i t i a l i za t ionDisk seekC. Disk read. A physical sector = 1024 bytesD.E.Host to

A.B.

Disk wri te . A physical sector = 1024 bytesHost system communicationHOC communication always s ta r t s with:

Attent ion and syncronizat ion handshake8 byte command block sen t from the hos t to


18/31


no r e t r i e s ( ie . t h i s byte spec i f i e s t o t a l number ofr e t r i e s ) .The fo l lowing t ab le summarizes the 7 commandsava i lab le in l eve l one f i rmware .-1 . Boot Volume

Byte 0 = Offh command typeByte 1 = volume to boot (0-3)Byte 2-7 unused

Firmware i s loaded from the se lec ted volume and a l lreads and wri tes wi l l be di rec t ed to the se lec tedvolume un t i l a new volume is se l ec t ed .-0 . Load l eve l 2 f irmware

Byte 0 = 0 command typeByte 1 = t rackByte 2 = headByte 3 = sec to rByte 4 thru 7 - not used


19/31


Byte 6 = number of r e t r ie s + 1the value of the high order b i t ' of ther e t r y by te n eed s to be a "1" if youwant er ro r co r rec t ion . This shoulda lmost always be the case .Byte 7 = 02. Absolute sec to r wri t e

Byte 0Byte 1Byte 2Byte 3Byte 4Byte 5Byte 6

=======

2 Command typet rackheadsec to rTAGOTAGlnumber of r e t r i e s + 1the value of the high order b i t of there t ry byte needs to be "1" to reques t a"read a f t e r w r i t e check". Ther ema i n i n g 7 b i t s o f th e r e t r y b y tedetermine the number of r e t r i e s .Byte 7 = 0

* Command 2 must be fo l lowed by a lK block o f b y t e s .


20/31


4. Format write (write sec tor 1 from INDEX)Byte 0 = 4 Command typeByte 1 = t rackByte 2 = headByte 3 = sec torByte 4 = TAGOByte 5 = TAG1Byte 6 = number of r e t r i e s + 1

If high order b i t = 1, read a f t e r write check Byte7 = 05. Get contents of HOC memory

Byte 0 = 5 Command typeByte 1 = 0 (not used)Byte 2 = low 8 bi t s from HOCByte 3 = high 8 bi t s from HOCByte 4 = low S bi t s of byte countByte 5 = high 8 bi t s of byte countByte 6 = not usedByte 7 = not used


21/31


Level two f i ~ a r e Digital Microsystems, Inc. currently supports fouro p e r a t i ~ systems, CP/M 1.4, CP/M 2.2, HiNet, arrlHIOOS.The following table summarizes the 9 commands forCP/M 1.4 or 2.2 1Oh. Warm star t (No longer supported or used)Byte 0 = 10h Comnarrl typeByte 1 = 0 for track 0Byte 2 = 1 fo r head 1Byte 3 = 1 fo r sector 1Byte 4 = number of logical sectors requiredByte 5 thru 7 not used11h. CP/M read (128 byte)Byte 0 = 11h Comnand typeByte 1 = sector (1 to 128)Byte 2 = track (low order byte)Byte 3 = track (high order byte) .Byte 4 thru 5 not used


22/31


Command 12h must be followErl by a 128 byte block ofbytes.13h. CP1M drive selectByte 0 =-13h Command typeByte 1 = parti t ion numberByte 2 = volume number (new to multi disks)Byte 3 thru 5 not usedByte 6 = ascii 'M' (indicates host knows ofmulti disk drives) (byte 2 will beignored i f anything but "M")Byte 7 not used14h. Buffer FlushByte 0 = 14h Command typeByte 1 thru 7 not used

&1 {Ae


23/31


24/31

Technical Manual Hard Disk Control ler

l8h. Get Volune InformationByte 0 = 18h Comnand typeByte 1 = ROM versionByte 2 = ROM reversionByte 3 = finmware versionByte 4 = firmware reversionByte 5 thru 7 unusedOn return:Byte 0 = l8h Coomand echoByte 1 = ran version number (all versions binary)Byte 2 = ram revision numberByte 3 = finmware version numberByte 4 = firmware revision numberByte 5 thru 6 unusedstatusIf status = 0 there follows 128 bytes, 32 bytes foreach volume. Each volume's info is as follows:Byte 0 = volume present (true or false)Byte 1 = current track for volumeByte 2 = tracks on volume


25/31


19h. write cae error to last sector on diskByte 0 = 19hBytes 1 thru 7 unused


26/31


1 . 6 . x Completion o f a commandCommands 1,2,11h,12h,13h,14h,15h, an d 16h, r e su l t inthe HOC re turn ing a s t a t u s block upon comple t ion ofth e command or an in te r rup t ion of the command due toan e r ro r . The s t a t u s block w i l l be a copy of thecommand block, wi th the fo l lowing changes:For commands 1 and 2, if b y t e s 1 , 2, o r 3 have beenchanged, the HOC has subs t i tu ted a spare sec tor fo ra defec t ive sec to r . The t rack byte w i l l be 200 or201 fo r a Shugart dr ive and 241 or 242 fo r a Fuj i t sudr ive .I f the re t ry byte has been decremented, e r r o r s wereencountered. I f the byte i s decremented to 0, theer ro r is permanent . (see s t a t u s byte) .Commands 11 and 15, (reads) w i l l have a data blockfo l lowing the re tu rn s t a tus only i f ' no e r r o roccured. For command 15h, a 1K read , byt e 5 wi l l bet rue {FFh) i f the sec to r came from the buf fe r andf a l s e (Oh) i f the sec to r was read d i r e c t ly from thehard d i sk .


27/31


Byte 7 wi l l be "0" for a non-error re turn . Anonzero in byte 7 (the l a s t byte) indica tes ' one ofthe fol lowing e r ro r s :Hex Valueof byte Problem11 Write fau l t : Poss ib le dr ive problem12 Drive not ready13 In te rna l t imeout HOC problem14 Read a f t e r wri te compare er ro r15 Unprocessed CRC e r ror . ROM detected erro 'r butf i rmware e r ro r cor rec t ing code was not present .16 Volume se lected (command 13h) not presen t .17 No index mark on disk . Indica tes no power todisk or disk not present .18 Timeout while seeking a t r ack .19 Timeout while seeking t rack O.20 Error in firmware i n i t process21 HOC cannot f ind sec to r header22 Bad t r ack , sec to r , or head assignment in header23 Header checksum e r ro r24 Track inval id ( too big)-25 Head- inval id fo r dr ive26 Sector inval id fo r dr ive


28/31


NOTE: A 41 h in by te 6 and a OOh in byte 7 of thes ta tus block indica tes a CRC e r ror occurred and wascorrec ted .NOTE 2: Error 31 wi l l occur in response to acommand 13 (CP/M dr ive se lec t ) . The s ta tus of theproblem is as fol lows:Byte 0 = Command generat ing e r rorByte 1 = t rackByte 2 = headByte 3 = sectorByte 4 = block number (low order byte)Byte 5 = block number (high order byte)Byte 7 = ACTUAL ERRORByte 8 = 31h


29/31

A. B C1A7 (,.h-')..... P5h-8 .&, MAO -7." -0."01 .....,., -30I ~ H ~ ...., -,J.'Jt.'iJ HAo -20 Ii l l ' >J "to'W P3\,-3\)

tt l G'lrr:61

CO HDt (n":G)5 ID7 ; , -n; : ~ l eD7 tiD (Plh : t ~

ntr tNF8! " "4 "e

ttl lNFe!

31117 pOt!

bsc.-2. INrEIU=Ac..6

Z

D E

INTERFACE. l'C.l 0lJrFA/roD7: i A,h

e o ~ ' 1 ' I L . S ~ 7 !

1C.' ~ F A I

1Cl INFc./

1A' Z ~ S ~ T I 107 OllTF2./

INTERFACE 110, oUl'"FBI1\ro DAShq!JD7 7'115313 5

ttT !NFS/

ICT INFC!

,AO ~ A E . S E T I ,A7 OUTF2./

F

1FIWCI (,tool.)' -,:l. -,, -tUlliI7 (n":,n:1NAI (Plio-II)lFlnlll ( p l f ~ - n )

I


30/31

A B c D,

,. , DD. - - - - - - ' -F, : - :O} ' - - - - - - f l J> . - - - - - meuv Cpu- 2S)p.:.---- H ~ S E L I I -2

tt l O!lrFF/--- ......-,;:--___ HDSELU

5 "'" -----"---' - " - - - - - - HtlSELBI -8p=----- DIRt -zq

-'------ STEP / -2.t.:E)----------_ ~ , j ' " ! I - - - - - V 1 R T & ~ l E I -,."r ~ A I T In

. RT'PI\TJ.________ ~ ~ ~ ' ~ " ' ~ ' - - - - - - W t l .

-lA(",,",,"-,_ _ _ _ _ WD- -4-0+ 10+ lIItn\TE ,,-----RD4.\"TE/ -3", - b ' - - - - - - - "c - ~ 1 .

IE3 RDCL.KI+5,

l C . S J " ~ 5ECmR -------------,;

D ~ 3 - - + ! .Q : f"--------' '4' p " - + ~ - _ + ' - - - w R T F L T t - 3 ~ 3DDZ __ ---1.-bATA/--------.!. 1 ~ / f S - '3 6,7 '- _ ....__- _ (Pld - 4q)115 BuSY

E F

A B c D E F c. H I J


31/31

a

7

~ . '

2

..- '''-'1.,-_._-,", our 11

'-""',","I'"1"==r-__ __ ~ ~ T ' " " . . . ; ; A o ; ; . - . . ; A . ; ; . _______ Dl>R ~ " 5 " l .u'"

El CLC."1'/+--_----t ---,

., O\TrPCI ++---:---" - t 1 H - i + ' Y N ' o / ' - ~ - 'SAt Do1 " " - ~ I + I - t ' ' ' l v ' W V ' - - f . L - < .. O'p----'4-l-t 'yN'O/,-L-SA. 0+

f-L----'-i...p"v'M"y':':"'-

hard disk controller technical manual jan84

Documents