h. huang transparency no.6-1 the 68hc11 microcontroller chapter 6: interrupts and resets the 68hc11...
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H. Huang Transparency No.6-1
The 68HC11 Microcontroller
Chapter 6: Interrupts and Resets
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
H. Huang Transparency No.6-2
The 68HC11 Microcontroller
Basics of Interrupts
What is an interrupt?
A special event that requires the CPU to stop normal program execution andperform some service related to the event. Examples of interrupts includeI/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0, etc.
Functions of Interrupts
- Coordinating I/O activities and preventing CPU from being tied up- Providing a graceful way to exit from errors- Reminding the CPU to perform routine tasks
Interrupt Maskability
- Interrupts that can be ignored by the CPU are called maskable interrupts. Amaskable interrupt must be enabled before it can interrupt the CPU. An interrupt isenabled by setting an enable flag.
- Interrupts that can’t be ignored by the CPU are called nonmaskable interrupts.
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The 68HC11 Microcontroller
Interrupt priority
The order in which the CPU will service interrupts when all of them occur at the same time.
Interrupt Service
The CPU provides service to an interrupt by executing a program called the interrupt service routine.
A complete interrupt service cycle includes
1. Saving the program counter value in the stack2. Saving the CPU status (including the CPU status register and some other registers) in the stack3. Identifying the cause of interrupt4. Resolving the starting address of the corresponding interrupt service routine5. Executing the interrupt service routine6. Restoring the CPU status and the program counter from the stack7. Restarting the interrupted program
H. Huang Transparency No.6-4
The 68HC11 Microcontroller
Interrupt Vector
Starting address of the interrupt service routine
Interrupt Vector Table
A table where all interrupt vectors are stored.
Methods of Determining Interrupt Vectors
1. Predefined locations (8051 approach)2. Fetching the vector from a predefined memory location (68HC11)3. Executing an interrupt acknowledge cycle to fetch a vector number in order to
locate the interrupt vector (68000 and x86 families)
Steps of Interrupt Programming
Step 1. Initializing the interrupt vector tableStep 2. Writing the interrupt service routineStep 3. Enabling the interrupt
H. Huang Transparency No.6-5
The 68HC11 Microcontroller
The Overhead of Interrupts
Saving and restoring of CPU status and other registers.(68HC11 needs to save all CPU registers)
tPCSU
PWIRQ
E
1 2 3 4 5 6 7 8 9 10 11 12 13
nextopcode
nextop + 1 SP SP - 1 SP - 2 SP - 3 SP - 4 SP - 5 SP - 6 SP - 7 SP - 8 SP - 8
vectoraddr
vectoraddr + 1
newPC
opcode PCL PCH IYL IYH IXL IXH B A CCR
vectMSB
vectLSB
opcode
IRQ1
IRQ2
addr
data
R/W
1. Edge sensitive IRQ pin
2. Level sensitive IRQ pinFigure 6.1 68HC11 Interrupt timing diagram
H. Huang Transparency No.6-6
The 68HC11 Microcontroller
Resets
- The initial values of some CPU registers, flip-flops, and the control registers in I/O
interface chips must be established in order for the computer to function properly.
- The reset mechanism establishes these initial conditions for the computer system.
- There are at least two types of resets: power-on reset and manual reset.
- The power-on reset establishes the initial values of registers and I/O control registers.
- The manual reset without power-down allows the computer to get out of most error
conditions if hardware doesn’t fail.
- A reset is nonmaskable.
H. Huang Transparency No.6-7
The 68HC11 Microcontroller
68HC11 Interrupts
The 68HC11 supports 16 hardware interrupts and two software interrupts. Hardwareinterrupts include:
SCI serial systemSPI serial transferPulse accumulator input edgePulse accumulator overflowTimer overflowTimer output compare 5Timer output compare 4Timer output compare 3Timer output compare 2Timer output compare 1Timer input capture 3Timer input capture 2Timer input capture 1Real time interruptIRQ pinXIRQ pin
Software interrupts: SWI instruction and illegal opcode. Both are nonmaskable.
H. Huang Transparency No.6-8
The 68HC11 Microcontroller
The 68HC11 Interrupt-Handling Procedure
- Saving the CPU registers in the stack- Fetching the interrupt vector from a predefined memory location for
the pending interrupt.- Resuming program execution from the fetched interrupt vector.
The 68HC11 Interrupt Stacking Order
CCRBA
XHXLYHYL
PCHPCL
SP after interrupt
SP before interrupt
Low address
High address
Figure 6.2 68HC11 interrupt stacking order
H. Huang Transparency No.6-9
The 68HC11 Microcontroller
Vector address Interrupt source Priority
FFC0, C1...FFD4, D5FFD6, D7FFD8, D9FFDA, DBFFDC, DDFFDE, DFFFE0, E1FFE2, E3FFE4, E5FFE6, E7FFE8, E9FFEA, EBFFEC, EDFFEE, EFFFF0, F1FFF2, F3FFF4, F5FFF6, F7FFF8, F9FFFA, FBFFFC, FDFFFE, FF
reserved...reservedSCI serial systemSPI serial transfer completepulse accumulator input edgepulse accumulator overflowtimer overflowtimer output compare 5timer output compare 4timer output compare 3timer output compare 2timer output compare 1timer input capture 3timer input capture 2timer input capture 1real timer interruptIRQ pin interruptXIRQ pin interruptSWIillegal opcode trapCOP failureCOP clock monitor failRESET
lowest
highest
Table 6.1 68HC11 interrupt vector address and priority
68HC11 Interrupt Vector Address and Priority
H. Huang Transparency No.6-10
The 68HC11 Microcontroller
Example 6.1 The 68HC11 is executing the TAP instruction of the following program when the IRQ interrupt occurs. List the stack contents immediately before the interrupt service routine is entered.
Line Location OpcodeInstructionmnemonics
1234567
E000E002E005E008E009E00BE00C
C6208E00FFCE10004F183006AB00
ORG $E000LDAB #$20LDS #$00FFLDX #$1000CLRATSYTAPADDA 0,X
Solution:
1. After line 1: [B] = $202. After line 2: [SP] = $FF3. After line 3: [X] = $10004. After line 4: [A] = 05. After line 5: [Y] = $1006. After line 6: [CCR] = $00
The Stack contents are shown in Figure 6.4 in next page.
H. Huang Transparency No.6-11
The 68HC11 Microcontroller
0 0
2 0
0 0
CCR
B
A
X
Y
PC
SP
1 0 0 0
0 1 0 0
E 0 0 C
0 0 F F
Figure 6.3 Register contents after theTAP instruction
0 02 00 01 00 00 10 0E 00 C
Figure 6.4 Stack contentswhen TAP is completed
SP (= $00F6)
$00FF
H. Huang Transparency No.6-12
The 68HC11 Microcontroller
Priority Structure of the 68HC11 Maskable Interrupts
- The priority of each 68HC11 interrupt source is fixed.- The user can promote one of the maskable interrupts to the highest priority among those
maskable interrupts by programming the HPRIO register.- The selection of highest priority interrupt is shown in Table 6.2.
RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 at $103Cvalue after
reset(refer to Table 6.4) 0 1 0 1
Figure 6.5 Contents of the HPRIO register
H. Huang Transparency No.6-13
The 68HC11 Microcontroller
PSEL3 PSEL2 PSEL1 PSEL0 Interrupt source promoted
0000000011111111
0000111100001111
0011001100110011
0101010101010101
timer overflowpulse accumulator overflowpulse accumulator input edgeSPI serial transfer completeSCI serial systemreserved (defaults to IRQ)IRQ pin (external pin)real time interrupttimer input capture 1timer input capture 2timer input capture 3timer output compare 1timer output compare 2timer output compare 3timer output compare 4timer output compare 5
Table 6.2 PSEL3-PSEL0 bits for selecting highest priority interrupts
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The 68HC11 Microcontroller
IRQ interrupt
- can be masked by the I bit of the CCR register- is level-sensitive by default (asserted low)- IRQ interrupt can be configured to be falling edge-sensitive by setting the IRQE bit
(bit 5) of the OPTION register to 1 within the first 64 E clock cycles after reset.- IRQ interrupt vector is shared by the IRQ pin interrupt and the I/O handshake subsystem
XIRQ interrupt
- can be masked by the X bit of the CCR register- the X bit can only be cleared during the first 64 E clock cycles after reset and cannot be
cleared and reset after that- when an XIRQ interrupt occurs, all registers are saved in the stack and the X bit in the CCR
register is set to 1 (not by the user program) to prevent further XIRQ interrupts.- XIRQ interrupt is often used to detect emergent situation because of its high priority.
Illegal Opcode Trap
- some of the opcode byte (s) combinations are not defined and hence are illegal instructions- can’t be masked
H. Huang Transparency No.6-15
The 68HC11 Microcontroller
The Software Interrupt Instruction (SWI)
- CPU registers are saved in the stack like any other maskable instruction- cannot be masked by the I and X bits in the CCR register- often used to implement the breakpoint
Low-Power Modes
- A microcontroller is mainly used as the controller of an embedded product.- An embedded product is often powered by batteries.- A good microcontroller should consume as little power as possible.- The power consumption can’t be avoided during normal operation.- The power consumption of a microcontroller-based product should be reduced to minimal
when the CPU is not performing useful works. - The 68HC11 provides two low-power modes: WAIT and STOP modes.
The WAIT instruction
- The 68HC11 is placed in a low power mode while keeping the oscillator running.- Upon the execution of this instruction, all CPU registers are saved in the stack.- The wait state can be exited only through an unmasked interrupt or reset.- This instruction can be used when the CPU has nothing to do but wait for the arrival
of an interrupt.
H. Huang Transparency No.6-16
The 68HC11 Microcontroller
The STOP instruction
- When the S bit in the CCR register is 0, the STOP instruction places the CPU in the lowest power mode.
- All clocks including the internal oscillator are stopped, causing all internalprocessing to be stopped.
- Exit from the STOP mode can be accomplished by RESET, an XIRQ interrupt, or an unmasked IRQ interrupt.
- When the XIRQ interrupt is used and the X bit in the CCR register is 1, then noXIRQ service routine is executed. The CPU continue to execute the instructionfollowing the STOP instruction. Otherwise, the XIRQ service routine will be executed.
H. Huang Transparency No.6-17
The 68HC11 Microcontroller
The 68HC11 Resets
Four possible sources of resets: RESET pin, power-on reset, computer operating properly,and clock monitor failure.
RESET pin Reset
- This pin must be driven low for 8 E clock cycles in order to be detected.- This pin should be kept low when VDD is below its minimum operating level so that the
contents of the EEPROM won’t be corrupted.- A low-voltage inhibit circuit that holds reset pin low whenever VDD is below its minimum
operating level is required to protect against EEPROM corruption.
IN
GND
RESET
To RESETof 68HC11
V DD
MC34064
V DD
4.7
1
3
Figure 6.6 A typical external reset circuit
manual reset
4.7
4.7
2F
H. Huang Transparency No.6-18
The 68HC11 Microcontroller
The Power-On Reset
- The power-on reset occurs when a positive transition is detected on VDD.- The power-on circuitry provides a 4064-cycle time delay from the time of the first
oscillator operation.- This reset should not be used to detect drops in power supply.
The CPU after reset
- After reset, the CPU fetches the reset vector from locations $FFFE and $FFFF ($BFFE and $BFFF in the special test or bootstrap mode) during the first three cyclesand begins instruction execution.
- The stack pointer and other CPU registers are indeterminate after reset.- The X and I bits of the CCR register are set to mask any interrupt requests.- The S bit of the CCR register is set to 1 to disable the STOP mode.- All I/O control registers are initialized by reset.
H. Huang Transparency No.6-19
The 68HC11 Microcontroller
Establishing the Mode of Operation
- The voltage levels on MODA and MODB pins are latched on the rising edge of the RESET signal to determine the mode of operation.
- The upper four bits of the HPRIO register are also set by these mode select signals.
InputsMODB MODA Mode description
Control bits in HPRIO (latched at reset)
RBOOT SMOD MDA IRV
1100
0101
normal single-chipnormal expandedspecial bootstrapspecial test
0010
0011
0101
0011
Table 6.4 Hardware mode selection summary
H. Huang Transparency No.6-20
The 68HC11 Microcontroller
The Computer Operating Properly (COP) Watchdog Timer Reset
- The COP watchdog timer system is intended to detect software processing errors.- The COP circuit will not reset the CPU as long as the application software reset the
COP timer before it times out.- If the COP timer times out, it is an indication that the application software is no longer
being executed in the intended sequence and thus a system reset is initiated.- The COP system is enabled by clearing the NOCOP bit in the CONFIG register and is
disabled by setting the same bit. After the change of the NOCOP bit, the CPU must be reset before the new status becomes effective.- The software COP reset is a two-step sequence. The first step is to write a $55 to the
COPRST register and then write a $AA into the same register.
H. Huang Transparency No.6-21
The 68HC11 Microcontroller
- The default COP time-out interval is 215 E cycles.- The COP time out interval is programmable by setting the CR1 and CR0 bits of the OPTION
register. - CR1 and CR0 together select a divide factor for E/215.
Crystal frequency8 MHz 4 MHz
Nominal time-out
16.384 ms65.536 ms262.14 ms
1.049 s
32.768 ms131.07 ms524.29 ms
2.1 s
CR1 CR0E / 2 15
divided by
0011
0101
14
1664
E clock = 2 MHz 1 MHz
Table 6.5 Watchdog rates vs. crystal frequency
H. Huang Transparency No.6-22
The 68HC11 Microcontroller
Clock Monitor Reset
- The clock monitor circuit is based on an internal RC time delay.- If no clock (E clock) edges are detected within this RC time delay, the clock monitor
can optionally generate a system reset (by asserting the RESET pin).- The clock monitor function is enabled/disabled by the CME bit (bit 3) of the OPTION
register.- The RC time-out may vary from lot to lot and from part to part due to the IC fabrication
process variation.- An E clock frequency lower than 10 KHz will be definitely detected as a clock monitor
error and an E clock frequency higher than 200 KHz will not be detected as a clock monitor error.
- The clock monitor is often used as a backup for the COP watchdog system because theCOP system requires a clock signal to operate.
- The second application of the clock monitor is to protect against unintentional executionof the STOP instruction.
H. Huang Transparency No.6-23
The 68HC11 Microcontroller
Writing the Interrupt Service Routine
- In assembly language
xxx_ISR ……RTI
- In C language
#pragma interrupt_handler xxx_ISRvoid xxx_ISR ( ){
…}
The statement “#pragma …” tells the C compiler to generate RTI instead of RTS as the lastinstruction of the function.
H. Huang Transparency No.6-24
The 68HC11 Microcontroller
Set Up Interrupt Vector Table
- Use assembler directives to set up interrupt vector table- For example, the vector entry for IRQ interrupt can be set up as follows (in assembly
language):
ORG $FFF2FDB IRQ_ISR
where IRQ_ISR is the label of the first instruction in the service routine.
In C language,
#pragma abs_address:0xfff2void (*interrupt_vectors [ ]) (void) ={
IRQ_ISR}#pragma end_abs_address
H. Huang Transparency No.6-25
The 68HC11 Microcontroller
- The complete interrupt vector table in C language is as follows :
#pragma abs_address:0xffd6void (*interrupt_vectors [ ] (void) ={
SCI_ISR, /* SCI interrupt service routine */SPI_ISR, /* SPI */PAI_ISR, /* PAI */PAOV_ISR, /* PAOV */TOF_ISR, /* TOF */TOC5_ISR, /* TOC5 */TOC4_ISR, /* TOC4 */TOC3_ISR, /* TOC3 */TOC2_ISR, /* TOC2 */TOC1_ISR, /* TOC1 */TIC3_ISR, /* TIC3 */TIC2_ISR, /* TIC2 */TIC1_ISR, /* TIC1 */RTI_ISR, /* RTI */IRQ_ISR, /* IRQ */XIRQ_ISR, /* XIRQ */SWI_ISR, /* SWI */ILLOP_ISR, /* ILLOP */
COP_ISR, /* COP */CLM_ISR, /* clock monitor */_start /* reset */
}
H. Huang Transparency No.6-26
The 68HC11 Microcontroller
The EVB & EVBU Interrupt Vector Jump Table
- The design of EVB and EVBU precludes the user program to write into interrupt vector table because the memory space for the interrupt table is in ROM.
- The EVB and EVBU reserve 60 bytes ($00C4-$00FF) of the on-chip SRAM as an interruptvector jump table.
- Each entry of the vector jump table consists of three bytes. The first byte should be set tothe opcode ($7E) of the JMP instruction, and the second and third bytes should be set tothe starting address of the corresponding service routine.
- Each entry (two bytes) of the default vector table of the 68HC11 should contain the addressof the first byte of the corresponding entry in the interrupt vector jump table.
- To set up interrupt vector jump table (use IRQ as an example)
In assembly language, In C language,
ORG $00EE void IRQ_ISR ( );JMP IRQ_HND main ( )
{…*(unsigned char *)0xee = 0x7E;*(void (**)())0xef = IRQ_ISR;…
}
H. Huang Transparency No.6-27
The 68HC11 Microcontroller
Interrupt vector
serial communication interface (SCI)serial peripheral interface (SPI)pulse accumulator input edgepulse accumulator overflowtimer overflowtimer output compare 5timer output compare 4timer output compare 3timer output compare 2timer output compare 1timer input capture 3timer input capture 2timer input capture 1real time interruptIRQXIRQsoftware interrupt (SWI)illegal opcodecomputer operate properlyclock monitor
Field
$00C4-$00C6$00C7-$00C9$00CA-$00CC$00CD-$00CF$00D0-$00D2$00D3-$00D5$00D6-$00D8$00D9-$00DB$00DC-$00DE$00DF-$00E1$00E2-$00E4$00E5-$00E7$00E8-$00EA$00EB-$00ED$00EE-$00F0$00F1-$00F3$00F4-$00F6$00F7-$00F9$00FA-$00FC$00FD-$00FF
Table 6.6 68HC11 EVB, EVBU, and CMD-11A8 interrupt vector jump table
Interrupt Vector Jump Table for Demo Boards that Use Buffalo Monitor
H. Huang Transparency No.6-28
The 68HC11 Microcontroller
Enable Interrupts
- Clear the I bit of the CCR register will enable interrupt globally.- Most maskable interrupts have an enable bit that must be set to enable the individual
interrupt in addition to setting the I bit.- For example, to enable the OC1 interrupt, we need to use the following statements:
In assembly, In C language
TMSK1 EQU $22 Use in-line assembly code asm (“cli”); orLDX #$1000 macro INTR_ON ( ); to enable interruptBSET TMSK1,X $80 globally.CLI Use the statement TMSK1 |= 0x80 to enable
OC1 interrupt locally.
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The 68HC11 Microcontroller
Example 6.2 Write a main program and an interrupt service routine. The main program will initialize a variable count to 5, enable the IRQ interrupt, and stay in a loop to checkthe value of count. When the value of count is 0, the program jump to the BUFFALO monitor. The IRQ pin is connected to some circuit that will generate an interrupt from timeto time. Solution:* set up the interrupt vector jump table entry
ORG $00EEJMP IRQ_ISR
* the main program is in the followingORG $00
count rmb 1ORG $C000SEI ; disable all maskable interruptsLDS #$DFFF ; set up stack pointer for EVBLDAA #5 ; initialize the variable count to 100STAA count ; “CLI ; enable interrupt to the 68HC11
loop LDAA countBNE loopSWI ; jump to BUFFALO monitor
IRQ_ISR DEC countRTIEND
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The 68HC11 Microcontroller
Example 6.3 Write a C program for the problem in Example 6.2.Solution:
#include <hc11.h>int count;main ( ){
count = 5;*(unsigned char *)0xee = 0x7E; *(void (**)())oxef = IRQ_ISR;INTR_ON ( ):while (count);INTR_OFF ( );asm (“swi”);
}#pragma interrupt_handler IRQ_ISR ( )void IRQ_ISR ( ){
count -= 1;}