h. huang transparency no.11-1 the 68hc11 microcontroller chapter 11: 68hc11 analog to digital...

H. Huang Transparency No.11-1

The 68HC11 Microcontroller

Chapter 11: 68HC11 Analog to Digital Converter


Han-Way Huang

Minnesota State University, Mankato



Basics on A/D Conversion

- Almost any measurable quantity, for example, current, voltage, temperature, speed, and time, is analog in nature.

- Analog signals must be represented in digital format in order to be processed by the digitalcomputer.

- An analog to digital (A/D) converter can convert a electrical voltage to a digital value.- A non-electrical quantity must be converted into electrical voltage before it can be

converted into digital value.- A transducer is normally used to convert a non-electrical quantity into a electrical voltage

so that it can be further processed by a computer.- The accuracy of an A/D converter is dictated by the number of bits it used to represent the

digital value.- An A/D conversion system is illustrated in Figure 10.1



Transducer

temperature

pressure

lightweight

airflow

humidity...

Nonelectric quantitysuch as

Such as asensor,load cell,photocall, orthermocouple...

signalconditioning

circuit

(optional)

voltage voltage A/Dconverter

Computer

Digitalvalue

Figure 11.1 The A/D conversion process



Successive Approximation Method

V in (analog input)

Digital-to-analog converter

Output Latch

Digital code

Successiveapproximationregister (SAR)

Control LogicClock

Figure 11.2 Block diagram of a successive approximation A/D converter

+

-

analogcomparator



Start

SAR[n-1, ..., 0] 0i n - 1

SAR[i] 1

Convert the value in SAR to a voltage

Is theConverted voltage

greater thanthe input?

SAR[i] 0yes

no

i = 0?

i i - 1

Sop

yes

no

Figure 11.3 Successive approximation A/D conversion method

Algorithm of Successive Approximation Method

Starting the most significant bitof SAR, for each bit

1. Guess the bit to be a 1.2. Converts the value of the SAR to an analog voltage3. Compares the D/A output with

the analog input.4. Clears the bit to 0 if the D/A

output is larger.



Optimal Voltage Range for the A/D Converter

- A/D converter needs a low reference voltage and a high reference voltage to operate.- The low reference voltage (VLREF) is often set to 0 and the

high reference voltage (VHREF) is often set to VCC.- Most A/D converters are ratiometric.- To take advantage the whole dynamic range of the A/D converter, we should set scale and

shift the sensor output to VLREF ~ VHREF.- The A/D conversion result x corresponds to an analog voltage given by

Vx = VLREF + (range x) (2n – 1)

where, range = VHREF – VHREF



Example 11.1 Assume there is a 12-bit A/D converter with VLREF = 0V and VHREF = 5V.Find out the corresponding voltage values for A/D conversion results of 100, 400, 800, 1200, and 2400.Solution:

range = VHREF – VLREF = 5 V.

V(100) = 0V + (100 5) (212 – 1) = 0.12 VV(400) = 0V + (400 5) (212 – 1) = 0.49 VV(800) = 0V + (800 5) (212 – 1) = 0.98 VV(1200) = 0V + (1200 5) (212 – 1) = 1.46 VV(2400) = 0V + (2400 5) (212 – 1) = 2.93 V



Voltage Scaling Circuit

V OUT

+V IN

R1 R2

OP AMP

Figure 11.4 A voltage scaler

A V =R1 + R2

R1= 1 +

R1R2 11.2

Example 11.2 Convert the output voltage of an A/D converter from 0-200mV to the range of 0-5V.Solution:

AV = 1 + (R2/R1) = (5V/0.2V) = 25

R2/R1 = 24

Choose 10K for R1, then R2 = 240K.



Voltage Scaling and Shifting Circuit

Can translate a voltage from V1 - V2 to the range of 0V – 5V.

V IN

V OUTV 1

R 1

R 2

R f

- 11-3R f

R 1R 2

R f-

+

+12 V

- 12 V

741

-

+

+12 V

- 12 V

741

R 0

R 0

V IN

= -

(a) Summing circuit

V OUT

V 1V I

N

= V IN 11-4

(b) Inverting voltage follower

V IN

V 1

R 1

R 2

R f

-

+

+12 V

- 12 V

741

-

+

+12 V

- 12 V

741

R 0

R 0

V OUT

V OUT- 11-5

R f

R 1R 2

R f= V 1V I

N

(c) Level shifter and scaler

Figure 11.5 Level shifting and scaling circuit

voltage follower

V M

V M = - V IN



Example 11.3 Use the circuit in Figure 11.5 to scale and shift the transducer output from-2.5 ~ 2.5 V to 0 ~ 5V.Solution:

0 = Rf R1 × (- 2.5) – Rf R2 × V1 ---- (1)5 = Rf R1 × (2.5) – Rf R2 × V1 ---- (2)

By choosing V1 = - 12V and Rf = 5K, R1 and R2 are solved to be 5K and 24K. R0 is independent of other parameters, we arbitrarily set it to 5 K.



An Overview of the 68HC11 A/D Converter

- Eight-channel, 8-bit, multiplexed input, successive-approximation conversion method.- A weighted array of capacitors are used to implement the successive-approximation

method.- A clock signal is required to control the A/D conversion that must have a frequency

no lower than 750 KHz.- Reference voltages are required for the conversion: one is high reference (VRH) voltage,

the other is low reference (VRL) voltage. The difference between VRH and VRL cannot belower than 2.5 V.

- Accuracy is only guaranteed for VRL = 0 V and VRH = 5 V.- The conversion is ratiometric. The input voltage VRL converts to $00 and the input voltage

VRH converts to $FF.



The Clock Frequency Issue

- The A/D converter requires a clock to operate.- Either the E clock or the on-chip RC clock signal can be used.- The RC clock runs at 1.5 MHz.- To choose the E clock signal, clear the bit 6 of the OPTION register to 0. - To select RC clock signal, set the bit 6 of the OPTION register to 1. This circuit requires

10 ms to start and settle.- The 68HC11 completes the conversion of one sample in 32 clock cycles.

Registers Related to the A/D Operation

- ADCTL: A/D control/status register- OPTION: bits 7 and 6- ADR1-4: A/D result registers 1 to 4



CCF : Conversion complete flag . This read-only flag is set when all fourA/D result registers contain valid conversion results. Each time theADCTL register is written, this bit is automatically cleared to 0 and aconversion sequence is started.SCAN : Continuous scan control . When this bit is 0, the four requestedconversions are performed once to fill the four result registers. When thisbit is 1, conversions continue in a round-robin fashion with the resultregisters being updated as data becomes available.MULT : Multiple-channel/single-channel control . When this bit is 0, theA/D system performs four consecutive conversions on the single channelspecified by the four channel select bits (CD through CA, bits 3-0 of theADCTL register). When this bit is 1, the A/D system is configured toperform a conversion on each of four channels, with each result registercorresponding to one channel.CD : Channel select D .CC : Channel select C.CB : Channel select B .CA : Channel select A.These four bits are used to select one of the sixteen A/D channels. Whena multiple-channel mode is selected, the two least significant bits (CB andCA) have no meaning, and the CD and CC bits specify which group offour channels is to be converted. The channels selected by the fourchannel select bits are shown in Table 11.1.

CCF 0 SCAN MULT CD CC CB CA

0 0 u u u u u u

7 6 5 4 3 2 1 0

Value afterreset

ADCTLat $1030

A/D Control Register (ADCTL)



CD CC CB CAChannel

signalResult in ADRx

if MULT = 1

0000000011111111

0000111100001111

0011001100110011

0101010101010101

AN0AN1AN2AN3

AN4*AN5*AN6*AN7*

reservedreservedreservedreserved

V RH pin**V RL pin**(V RH )/2**reserved**

ADR1ADR2ADR3ADR4ADR1ADR2ADR3ADR4ADR1ADR2ADR3ADR4ADR1ADR2ADR3ADR4

* Not avaliable in 48-pin package.** These channels are intended for factory testinig.

Table 11.1 Analog-to-digital channel assignments



The OPTION Register

ADPU: A/D power up. When set to 1, it enables the A/D converter. After setting this bit,the user must wait at least 100 s before using the A/D converter.

CSEL: clock select. When set to 1, the RC clock signal is selected. Otherwise, the E clock is selected. It takes 10 ms for RC clock to stabilize.

ADPU CSEL IREQ DLY CME 0 CR1 CR2

0 0 0 1 0 0 0 0Value after

reset

OPTIONat $1039



The Procedure for Using the A/D Converter

Step 1. Connect the hardware properly. Scale and shift the analog inputs, when necessary, so that they fall between VRH and VRL.

Step 2. Set the ADPU bit of OPTION register to enable the A/D converter.

Step 3. Select the appropriate clock signal by setting or clearing the CSEL bit of theOPTION register.

Step 4. Wait for the A/D converter to stabilize.

Step 5. Select the appropriate channel(s) and operation modes by programming the ADCTLregister.

Step 6. Wait until the CCF flag of the ADCTL register becomes 1 and collect the conversion results.



Example 11.5 Write an instruction sequence to set up the following A/D conversion parameters:

Nonscan modeSingle-channel modeSelect channel AN0Choose the E clock as the clock source for the A/D converterEnable A/D converter

Solution:

Set bit 5 of ADCTL to 0 to select nonscan mode.Set bit 4 of ADCTL to 0 to select single-channel mode.Set bits 3-0 of ADCTL to 0000 to select channel AN0.

Write the value $00 into the ADCTL register.

Set the bit 7 of the OPTION register to enable A/D charge pump.

Clear the bit 6 of the OPTION register to select E clock as the A/D control clock signal.

Wait for 100 s for the converter to stabilize.



regbas EQU $1000ADCTL EQU $30OPTION EQU $39

LDX #regbasBCLR OPTION,X $40 ; select E clock for the A/D clock signalBSET OPTION,X $80 ; enable the A/D charge pump

LDY #30 ; delay for 105 s fordelay DEY ; the charge pump to

BNE delay ; stabilizeLDAB #$00STAA ADCTL,X ; start the conversionEND



Example 11.6 Write an instruction sequence to set up the following A/D conversionparameters:

Non-scan modeMultiple-channel modeSelect channels AN4-AN7Choose E clock as the clock source for the A/D converterEnable the A/D converter

Solution:

Set bit 5 of ADCTL to 0 to select non-scan modeSet bit 4 of ADCTL to 1 to select multi-channel modeSet bits 3-0 of ADCTL to 0100 to select channels AN4-AN7

Write the value $14 into the ADCTL register.

Set the bit 7 of the OPTION register to enable A/D charge pump.

Clear the bit 6 of the OPTION register to select E clock as the A/D control clock signal.

Wait for 100 s for the converter to stabilize.



regbas EQU $1000ADCTL EQU $30OPTION EQU $39

LDX #regbasBCLR OPTION,X $40 ; select the E clock as the A/D control clockBSET OPTION,X $80 ; enable the A/D converterLDY #30 ; wait for 105 s

delay DEY ; “BNE delay ; ”

LDAB #$14 ; start the A/D conversionSTAA ADCTL,X ; “END



Example 11.7 Write an instruction sequence to convert the analog signal connected to channel AN0 into digital form. Perform four conversions and stop. Assume the frequency of the E clock is 2 MHz.Solution:1. Circuit connection is shown in Figure 11.6.

2. Write one byte into the ADCTL register and four conversions will be performed.3. Perform A/D conversion on the AN0 input in single-channel and nonscan mode.

Write $00 into ADCTL.

5 V

0 V

Analog signal

V RH

V RL

AN0

68HC11

Figure 11.6 Circuit connections for Example 11.7



regbas equ $1000OPTION equ $39ADCTL equ $30ADR1 equ $31ADR2 equ $32ADR3 equ $33ADR4 equ $34

org $00result rmb 4 ; result four bytes to hold A/D results

org $C000ldx #regbasbset OPTION,X $80 ; enable the charge pump to start A/D conversionbclr OPTION,X $40 ; select E clock as the clock source to A/D converterldy #30 ; delay for 105 s to wait for the charge pump

delay dey ; to stabilizebne delay ; “ldaa #$00staa ADCTL,X ; initialize ADCTL and start the A/D conversion

again ldaa ADCTL,X ; check CCF bitbpl again ; wait until CCF flag is 1ldaa ADR1,X ; get the first result



staa result ; save itldaa ADR2,X ; get the second resultstaa result+1 ; save itldaa ADR3,X ; get the third resultstaa result+2 ; save itldaa ADR4,X ; get the fourth resultstaa result+3 ; save itend



In C Language,#include <hc11.h>unsigned char result [4];main ( ){

OPTION &= 0xBF; /* select E clock as the A/D clock source */OPTION |= 0x80; /* enable A/D converter */TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 200; /* start an OC2 operation with 100 s delay */while (!(TFLG1 & 0x40)); /* wait for 100 s */ADCTL = 0x00; /* start an A/D conversion */while (!(ADCTL & 0x80)); /* wait until A/D conversion is complete */result [0] = ADR1; /* save A/D conversion results */result [1] = ADR2;result [2] = ADR3;result [3] = ADR4;return 0;

}



Example 11.8 Take 20 samples from each of the A/D channels AN0 to AN3, convert themto digital values, and store them in memory locations from $D000 to $D04F.Solution:1. Circuit connection is shown in Figure 11.7.

2. Perform A/D conversion on channels AN0 to AN3 in multi-channel, non-scan mode.Write the value $10 into ADCTL.

3. Take samples at as regular intervals as possible. This can be achieved by starting thenext conversion immediately after the previous conversion has been completed but beforecollecting the result.

Ana

log

inpu

ts

5 V

0 V

V RH

V RL

AN3

AN2

AN1

AN0

68HC11

Figure 11.7 Circuit connections for Example 11.8



N EQU 20 ; number of samples to be taken per channelORG $D000

result RMB 80 ; reserve 80 bytes to store A/D conversion resultsORG $C000LDX #regbasBSET OPTION,X $80 ; enable A/D charge pumpBCLR OPTION,X $40 ; select E clock to control A/D conversionLDY #30 ; wait for 105 s for charge pump to stabilize

delay DEY ; “BNE delay ; “LDAA #$10 ; initialize ADCTLSTAA ADCTL,X ; “LDAB #N ; number of samples remained to be taken on each channelLDY #result ; Y points to the buffer that holds the result

wait LDAA ADCTL,X ; wait until the current A/D conversion is completedBPL wait ; “

* Start the next conversion immediately so that samples can be taken more uniformly in timeLDAA #$10 ; start the next A/D conversionSTAA ADCTL,X ; “



* The following eight instructions collect the previous results

LDAA ADR1,X ; fetch the result from channel 1STAA 0,Y ; save the resultLDAA ADR2,X ; fetch the result from channel 2

STAA 1,Y ; save the resultLDAA ADR3,X ; fetch the result from channel 3STAA 2,Y ; save the resultLDAA ADR4,X ; fetch the result from channel 4STAA 3,Y ; save the resultINY ; move the result pointer INY ; “INY ; “INY ; “DECB ; decrement the loop countBNE waitEND



In C Language,

#include <hc11.h>unsigned char result[80];main ( ){

int i;OPTION &= 0xBF; /* select E clock as the A/D conversion clock source */OPTION |= 0x80; /* enable A/D converter */TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 200; /* create 100 s delay */while (!(TFLG1 & 0x40)); /* “ */ADCTL = 0x10; /* start an A/D conversion */for (i = 0; i < 20; i++) {

while (!(ADCTL & 80));ADCTL = 0x10;result [4*i] = ADR1;result [4*i + 1] = ADR2;result [4*i + 2] = ADR3;result [4*i + 3] = ADR4;

}return 0;

}



The LM35 Precision Centigrade Temperature Sensors

Pins and circuit connections

Features

- No external calibration required.- Very linear over the temperature range- Draws only 60 A from power supply and has very low self-heating. - Converts the ambient temperature into voltage

Output

+10.0 mV/ o C

+V S(4 V to 20 V)

LM35

+V S(4 V to 20 V)

(a) (b) -V S

R 1

V XChoose R 1 = V S /50 V*V X = +1500 mV at +150 o C = +250 mV at +25 oC = - 550 mV at -55 o C

LM35

(a) Basic centigrade temperature sensor (12 oC to 150 oC)(b) Full-range centigrade temperature sensor

Figure 11. 8 Circuit connections for the LM35 temperature sensor



Example 11.9 Use the circuit shown in Figure 11.8b as a building block in a system to measure room temperature. Display the result in two integer digits and one fractional digitusing the seven-segment displays. Assume the room temperature never goes below 0 oC andnever goes above 42.5 oC so that the A/D converter of the 68HC11 can be used to performthe conversion and drive the seven-segment displays.Solution:1. The voltage output from the circuit shown in Figure 10.6b will be between 0V and 425 mV.2. Better precision can be obtained by scaling the voltage corresponding to 42.5 oC to 5 V.3. Voltage scaling circuit is shown is Figure 11.9.

LM35

V S = 12 V

AN0

V RH

V RL

5 V

0 V+ 12 V

- 12 V

51 K 4.7 K

-12 V

+

-CA3140

V X

240 K

Figure 11.9 Circuit connections between the LM35 and the 68HC11

68HC11



Display Circuit

MOSI

SCK

SS

Data In

Clock

Enable

68HC11

+5 V

R X

V SS

V DDa

bcdefgh

bank5

bank4

bank3

MC14489

Figure 11.10 Digital thermometer display circuit

3.6 K

bank2

bank1



Setting of Configuration Data for MC14489

bit 7: no decode, set to 0.bit 6: special decode, set to 1.bit 5 to 3: bank 5 to 3 hex decode, set to 0.bit 2: bank 2 special decode, set to 1.bit 1: bank 1 hex decode, set to 0.bit 0: normal mode, set to 1.

Format of Display Data

C

degree

fractional digit -- bank 3

one's digit -- bank 4

ten's digit -- bank 5

set the h segment of bank 4

brighten LEDs

Figure 11.11 Temperature data format

x x x x y y y y z z z z 1 1 1 1 1 1 0 01 1 0 0



REGBAS EQU $1000SPCR EQU $28SPDR EQU $2ASPSR EQU $29DDRD EQU $09ADR1 EQU $09OPTION EQU $39ADCTL EQU $30PORTB EQU $04PORTD EQU $08TCNT EQU $0ETOC2 EQU $18TFLG1 EQU $23OC2 EQU $40 ; mask to check the OC2F flag of TFLG1OC2M EQU $BF ; mask to clear OC2F flag for the BCLR instructionSP_DIR EQU $3A ; value to configure SPI pins directionsSPCR_IN EQU $54 ; value to initialize SPCR registerADPU EQU $80 ; mask to select ADPU bit of the OPTION registerADCLK EQU $40 ; mask to select CSEL bit of the OPTION registerA2D_INI EQU $00 ; value to configure A/D control registerTCNT EQU $0ETOC2 EQU $18TFLG1 EQU $23



ORG $00byte1 RMB 1 ; storage for temperature databyte2 RMB 1 ; “byte3 RMB 1 ; “remain RMB 2 ; to hold the remainder of divisionoc2cnt RMB 1 ; output comparison count of OC2

ORG $C000LDX #regbasLDAA #$C0STAA byte1 ; store the fixed value of display dataLDAA #$FC ; “STAA byte3 ; “

* The following 4 instructions initialize the SPI systemLDAA #SPDIR ; set up SPI pin directionsSTAA DDRD,X ; “LDAA #SPCR_INI ; initialize SPI parametersSTAA SPCR,X ; “BCLR PORTD,X $20 ; enable SPI transfer to MC14489LDAA #$45 ; send configuration data to MC14489STAA SPDR,X ; “BRCLR SPSR,X $80 *BSET PORTD,X $20 ; load data into configuration register



* The following 5 instructions enable the A/D converter and select E clock to control A/D* conversion process and wait for the charge pump to stabilize

BCLR OPTION,X ADCLK ; select E clock for A/D conversionBSET OPTION,X ADPU ; enable A/D converterLDY #30 ; delay 105 ms so charge pump can stabilize

delay DEY ; “BNE delay ; “

forever LDAA #A2D_INI ; start an A/D conversionSTAA ADCTL,X ; “

here LDAA ADCTL,XBPL hereLDAB ADR1,X ; read the A/D conversion resultCLRA ; convert to temperatureLDX #6 ; readingIDIV ; “STD remain ; save the remainderXGDX ; swap integer part to DLDX #10 ; separate tens and ones digitsIDIVLSLB ; shift ones digits to upper half of BLSLB ; “LSLB ; “LSLB ; “



STAB byte2XGDX ; swap the tens temperature digit in BADDB byte1 ; combine the decimal pointer specifier with tens digitSTAB byte1 ; “LDD remain ; get back the remainder (in B)LDAA #10MULLDX #6IDIV ; compute remainder × 10 6 XGDXADDB byte2 ; combine the ones digit and the fractional digitSTAB byte2 ; “BCLR PORTD,X $20 ; enable SPI transfer to MC14489LDAA byte1 ; get byte1 and send it outSTAA SPDR,XBRCLR SPSR,X $80 * ; wait until 8 bits have been shifted outLDAA byte2 ; send out byte2STAA SPDR,X ; “BRCLR SPSR,X $80 * ; “LDAA byte3 ; send out byte3STAA SPDR,X ; “BRCLR SPSR,X $80 * ; “BSET PORTD,X $20 ; load data into the display register of the MC14489



* Use OC2 to create 1 second delayLDAB #100STAB oc2cnt ; initialize OC2 count to create 1 s delayLDX #REGBASBCLR TFLG1,X $BF ; clear OC2F flagLDD TCNT,X

repeat ADDD #20000STD TOC2,X

wait BRCLR TFLG1,X $40 * ; wait for 10 msBCLR TFLG1,X $BF ; clear the OC2F flagLDD TOC2,XDEC oc2cntBNE repeatJMP foreverEND



C Program for Temperature Measurement

#include <hc11.h>main ( ){

unsigned char byte1, byte2, byte3, temp;byte1 = 0xC0;byte3 = 0xFC; /* store characters “degree” and “C” in byte3 */DDRD = 0x3A; /* configure SPI pin directions */SPCR = 0x56; /* initialize SPI function */OPTION |= 0x80; /* start the A/D charge pump */OPTION &= 0xBF; /* select E clock as the clock source for A/D conversion */TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 200 /* wait for 100 s */while (!(TFLG1 & 0x40));PORTD &= 0xDF; /* enable SPI transfer */SPDR = 0x45; /* send configuration data to MC14489 */while (!(SPSR & 0x80));PORTD |= 0x20; /* disable SPI transfer to MC14489 */while (1) {

ADCTL = 0x00 /* start and A/D conversion */while (!(ADTCL & 0x80));



temp = ADR1/6;byte1 += temp / 10; /* place the ten’s digit in the lower half of byte1 */byte2 = 4 << (temp % 10); /* place the one’s digit in the upper half of byte2 */temp = (ADR1 % 6) * 10 /6; /* compute the first fractional digit */byte2 += temp; /* combine the one’s and fractional digits */PORTD &= 0xDF; /* enable SPI transfer to MC14489 */SPDR = byte1; /* send out byte1 */while (!(SPSR & 0x80));SPDR = byte2; /* send out byte2 */while (!(SPSR & 0x80)); /* “ */SPDR = byte3; /* send out byte3 */while (!(SPSR & 0x80)): /* “ */PORTD |= 0x20; /* transfer data to the display register */TOC2 = TCNT + 20000; /* start OC2 operation with 10 ms delay */TFLG1 = 0x40; /* clear OC2 flag */for (temp = 0; temp < 100; temp -- ) {

while (!(SPSR & 0x80));TOC2 += 20000; /* start the next OC2 operation */TFLG1 = 0x40; /* clear the OC2 flag */

}}return 0;

}



Measuring the Humidity

- The IH-3605 is a humidity sensor made by HyCal Engineering, a division of Honeywell.- The voltage output for relative humidity 0 to 100% is 0.8V to 3.9V.- Pin assignment is shown in Figure 11.12.- Specifications are shown in Table 11.2.

V OUT V SGND

IH-3605

Figure 11.12 HyCal IH-3605 humidity sensor

Specification Description

total accuracyInterchangeabilityOperating temperatureStorage temperatureLinearityRepeatabilityHumidity StabilityTemp. effect on 0% RH voltageTemp. effect on 100% RH voltageOutput voltage

VS Supply requirement

Current requirement

± 2% RH, 0-100% TH @25 oC± 5% RH up to 60% RH, ±8% RH at 90% RH-40 to 85 oC (-40 to 185 oF)-51 to 110 oC (-60 to 223 oF)±0.5% RH typical±0.5% RH±1% RH typical at 50% RH in 5 years±0.007% RH/ oC (negligible)-0.22% RH/ oCV OUT = (V S )(0.16 to 0.78) nominal relative tosupply voltage for 0-100% RH; i.e., 1-4.9V for6.3V supply; 0.8 - 3.9V for 5V supply;Sink capability 50 microamp; drive capability5 microamps typical; low pass 1KHz filterrequired. Turn on time < 0.1 sec to full output.4 to 9V, regulated or use output/supply ratio;calibrated at 5V200 microamps typical @5V, increased to2mA at 9V

Table 11.2 Specifications of IH-3605



Example 11.10 Construct a humidity measurement system that consists of the 68HC11, anIH-3605 humidity sensor, and four 7-segment displays.Solution:1. Use a signal conditioning circuit to scale and shift the voltage to 0-5V.2. Use a 1K resistor and a 0.16F capacitor to construct a 1KHz low pass filter.3. Use a MC14489 to drive four seven-segment displays.4. Blank the most significant digit when the humidity is not 100%.

- Send $91 as the configuration data to blank the most significant digit. - Send $01 as the configuration data when the most significant digit is a 1.

5. Use table lookup method to translate from A/D result to the relative humidity.



V S (= 5V)

V OUT

IH-3605

1K

0.16 FGND

V 1

R 1

R 2

R f

-

+

+12 V

- 12 V

741

-

+

+12 V

- 12 V

741

R 0

R 0

V OUT

MOSI

SCK

SS

Data In

Clock

Enable

68HC11

+5 V

R X

V SS

V DDa

bcdefgh

bank3

bank2

bank1

MC14489

Figure 11.13 Relative humidity display circuit

AN0 bank4

3.6K



Relative Humidity Data Format

fractional digit -- bank 1

one's digit -- bank 2

ten's digit -- bank 3

hundred's digit -- bank 4

not used -- bank 5 (set to all 0s)

set the h segment of bank 2

brighten LEDs

Figure 11.14 Relative humidity data format

1 0 1 0 - - - - w w w w x x x x y y y y z z z z



REGBAS EQU $1000SPCR EQU $28SPSR EQU $29SPDR EQU $2ADDRD EQU $09ADR1 EQU $31OPTION EQU $39ADCTL EQU $30PORTB EQU $04PORTD EQU $08TCNT EQU $0ETOC2 EQU $18TFLG1 EQU $23SP_DIR EQU $3ASPCR_INI EQU $54APDU EQU $80 ; mask to select ADPU bit of the OPTION registerADCLK EQU $40 ; mask to select CSEL bit of the OPTION registerA2D_INI EQU $00 ; value to initialize the ADCTL registerCONF1 EQU $91 ; configuration data that need to blank msdCONF2 EQU $01 ; configuration data that display the msd



ORG $00byte1 RMB 1 ; storage for display databyte2 RMB 1 ; “byte3 RMB 1 ; “oc2cnt RMB 1

ORG $C000LDX #REGBASLDAA #$A0STAA byte1 ; first byte of the display data is a constantLDAA #SPDIRSTAA DDRD,XLDAA #SPCR_INI ; initialize the SPI systemSTAA SPCR,X ; “BSET OPTION,X ADPU ; start A/D charge pumpBCLR OPTION,X ADCLK ; select E clock as the clock source of the A/DLDY #30

delay DEYBNE delay

forever LDAA #A2D_INISTAA ADCTL,X

here LDAA ADCTL,X ; wait until A/D conversion is completeBPL here



LDAB ADR1,XLDY #humid_upABYLDAA 0,Y ; lookup the upper byte of the humiditySTAA byte2LDY #humid_loABYLDAA 0,Y ; lookup the lower byte of the humiditySTAA byte3JSR disp_humidJSR wait_1sJMP forever

disp_humid PSHAPSHBPSHYPSHXLDX #REGBASBCLR PORTD,X $20 ; enable SPI transfer to MC14489LDAA byte2ANDA #$F0 ; check the upper four bitsBEQ blankLDAA $01 ; choose normal hex decodeBRA send



blank LDAA #$91 ; choose special decode to blank displaysend STAA SPDR,X

BRCLR SPSR,X $80 * ; wait until the SPI transfer is completeBSET PORTD,X $20 ; load data into configuration registerBCLR PORTD,X $20 ; enable SPI transfer to MC14489LDY #byte1LDAB #3

loop_disp LDAA 0,YSTAA SPDR,XBRCLR SPSR,X $80 * ; wait until SPI transfer is completeINYDECBBNE loop_dispBSET PORTD,X $20 ; load data into display registerPULXPULYPULBPULARTS

wait_1s PSHAPSHBPSHYPSHX



LDX #REGBASDESTSYLDAA #50STAA 0,Y ; initialize OC2 count to 50LDD TCNT,X

loop_50 ADDD #40000 ; start an OC2 operation with 20 ms delaySTD TOC2,XBCLR TFLG1,X $BF ; clear OC2FBRCLR TFLG1,X $40 * ; wait until OC2F is setLDD TOC2,XDEC 0,Y ; decrement OC2 countBNE loop_50INSPULXPULYPULBPULARTS

humid_up FCB $00,$00,…,$09,$10humid_lo FCB $00,$04,…,$96,$00



C Program for Humidity Measurement

#include <hc11.h>unsigned char humid_up [ ] = {…};unsigned char humid_lo [ ] = {…};main ( ){

unsigned bytes[3]; /* display data */unsigned char i, conf_dat; /* loop index and configuration data */DDRD = 0x3A;SPCR = 0x54;OPTION &= 0xBF; /* select E clock to control A/D converter */OPTION |= 0x80; /* start the A/D charge pump */bytes[0] = 0xA0;TOC2 = TCNT + 200; /* create a delay of 100 ms */TFLG1 = 0x40; /* “ */while (!(TFLG1 & 0x80)): /* “ */while (1) {

ADCTL = 0x00; /* start an A/D conversion */while (!(ADCTL & 0x80)); /* wait until A/D conversion is complete */if (!(humid_up [ADR1] & 0xF0))

conf_dat = 0x91; /* choose special decode mode */else conf_dat = 0x01; /* choose normal decode mode */



PORTD &= 0xDF; /* enable SPI transfer to MC14489SPDR = conf_dat; /* send out configuration data */while (!(SPSR & 0x80)); /* wait until SPI transfer is complete */PORTD |= 0x20; /* load data into configuration register */bytes[1] = humid_up[ADR1];bytes[2] = humid_lo[ADR1];PORTD &= 0xDF;for (i = 0; i < 3; i++) { /* send out humidity data for display */

SPDR = bytes[i];while (!(SPSR & 0x80));

}PORTD |= 0x20; /* load data into display register */TFLG1 = 0x40; /* clear OC2F flag */TOC2 = TCNT + 20000; /* start an OC2 operation */for (i = 0; i < 100; i++) {

while (!(TFLG1 & 0x40));TFLG1 = 0x40; /* clear OC2F flag */TOC2 += 20000;

}}return 0;

}



Processing the Results of A/D Conversions

- The results of A/D conversion often need to be processed.- One of the most useful measurements of an AC signal is its root-mean-square (RMS) value.- The RMS value of an AC signal is defined as:

VRMS = T1

0

TV2(t)dt 11.7

- The following equation is used to approximate the RMS value:

VRMS

N1

N-1

i = 0Vi

2 11.8

- To make equation 10.4 a good approximation of the real RMS value, samples must beas equally spaced in time as possible. The more samples collected, the better the result.



Example 11.11 Write a program to compute the average of the squared values of 64samples stored at memory locations starting with the label sample and save the result at thememory locations starting with the label sq_ave.Solution:

- Two bytes are needed to hold the square of an 8-bit value.- Three bytes are needed to hold the sum of 64 16-bit values. x- Divide-by-64 can be performed by shifting the dividend to the right by 6 positions.



ORG $D000samples FCB …sq_sum RMB 3sq_ave RMB 2

org $C000LDX #samplesCLR sq_sum ; initialize the sum to 0CLR sq_sum+1 ; “CLR sq_sum+2 ; “LDY #64 ; initialize the loop count

loop LDAA 0,X ; get a sampleTAB ; duplicate the sample in BMUL ; compute the square of the sampleADDD sq_sum+1 ; add to the running sumSTD sq_sum+1 ; “LDAB sq_sum ; add the carry to the upper byteADCB #0 ; “STAB sq_sumINX ; move to the next sampleDEY ; decrement the loop countBNE loopLDAB #6 ; prepare to shift right 6 places



* the next five instructions divide the sum by 64

loop1 LSR sq_sumROR sq_sum+1ROR sq_sum+2DECBBNE loop1

* transfer the result to sq_sum and sq_sum+1LDAA sq_sum+1STAA sq_aveLDAA sq_sum+2STAA sq_ave+1END



Computing the Square Root

- A technique for approximating the square root is based on the following equation:

i =n-1

i=0 2n(n-1)

11.9

- Equation 10.5 can be transformed into

n2 = n-1

i=0(2i + 1) 11.10

- The value n is the square root to be found. Suppose we want to find the square root of p,and n is the integer closest to the square root of p, then one of the following relationshipsis satisfied:

n2 < pn2 = pn2 > p

- By incrementing i from 0 to n-1, the square root can be found. For the first approximation,we will stop when the running sum is larger than p. The flowchart of the program is shownin Figure 11.15.



Start

sum 0i 0

sum sum + 2 × i + 1

sum >= p?

n i + 1

Stop

i i + 1

yes

no

Figure 11.15 The logic flow for finding the square root



Example 11.12 Write a program to compute the square root of the average value computedin Example 11.11 (stored at sq_ave) and save the square root at sq_root.Solution:sq_root rmb 2 ; to hold the value of (2i + 1)i rmb 1 ;

…CLR sq_root ; initialize (2i + 1) to 0CLR sq_root+1 ; “LDAB #-1STAB i ; initialize i to 0

repeat INC iLDAB iCLRALSLD ; compute 2i + 1ADDD #1 ; “ADDD sq_root ; add 2i + 1 to accumulating STD sq_root ; sum CPD sq_ave ; compare to n2

BLO repeat ; repeat when (2i + 1) < n2

INC i ; add 1 to i to obtain the square rootLDAA i ; place the square root in sq_rootSTAA sq_root ; “END



Example 11.13 Add a sequence of instructions to the previous program to find the closestsquare root of the square sum.Solution:- If n is not the true square root, then either n or n - 1 is the closest square root.- The choice can be made by comparing the following two expressions:

n2 - p (1)p - (n - 1)2 (2)

- The value n is selected if the expression (1) is smaller. Otherwise, n - 1 is selected- The program on the right-hand side should be appended to the program of the previous

example.



sq_diff1 RMB 2temp RMB 2

LDAA i ; place n in ATAB ; also place n in BMUL ; compute n2

CPD sq_ave ; compare to pBEQ exit

* We need to compare expression (1) and (2) in the followingSUBD sq_ave ; compute n2 - qSTD sq_diff1LDAA iDECA ; compute n - 1TABMUL ; compute (n - 1)2

STD tempLDD sq_aveSUBD temp ; compute p - (n - 1)2

CPD sq_diff1 ; compare p - (n - 1)2 with n2 - pBHI exit ; n is closer to the true square rootDEC i ; n - 1 is closer to the true square root

exit …



Example 11.14 Write a C routine to compute the root-mean-square value of an arrayof 8-bit unsigned integers.Solution:unsigned char root_mean_sq (unsigned char *samples, unsigned int n){

int i;unsigned int sq_ave;unsigned long int sq_sum;unsigned int temp;sq_sum = 0;for (i = 0; i < n; i++)

sq_sum += samples[i] * samples [i];sq_ave = sq_sum / n;temp = 0;i = 0;while (temp < sq_ave) {

temp += 2 * i + 1;i ++;

}if (temp == sq_ave) return i;if ((i * i - sq_ave) < (sq_ave - (i - 1) * (i - 1)) return i;else return (i - 1);

}



Using External A/D Converter MAX1241

- 12-bit resolution- Use successive-approximation method to perform conversion and completes one conversion

in 7.5 s.- Direct interface to SPI interface.- Analog input ranges from 0 to 5V with 5V power supply

1

2

3

4

8

7

6

5

V DD

AIN

SHDN

REF

SCLK

CS

DOUT

GND

MAX1241

Controllogic

T/H 12-bitSAR

INTClock Output

shiftregister

CS

SCLK

SHDN

AIN

REF

DOUT

Figure 11.16 MAX1241 12-bit A/D converter block diagram



MAX1241 Signal Pins

CS: chip select. The falling edge of this signal initiates the conversion.DOUT: serial data output. Data changes state at SCLK’s falling edge.AIN: analog input. SCLK: serial clock input. SCLK clocks data out at rates up to 2.1 MHz.GND and VDD: device supply pins.REF: analog reference voltage. Reference voltage for A/D conversion.SHDN: Shut-down input. Pulling SHDN to low shuts the MAX1241 down to 15A supply current.

Chip Functioning

- Pulling CS to low initiates the conversion.- The serial data stream consists of a high bit, signaling the end of conversion (EOC),

followed by the data bits (MSB first).- End of conversion is signaled by DOUT going high.



Timing and Control

- The CS and SCLK signals control conversion-start and data-read operations. - After DOUT goes high, it transitions on the first falling edge of the SCLK signal. The next

falling clock edge shifts out the most significant bit of the conversion result at DOUT, followed by the remaining bits.

- Since there are 12 data bits and one leading high bit, at least 13 clock periods are needed to shift out a conversion result.

- Extra clock signals only shift out trailing zeros at DOUT.

1 4 8 12 16

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CS

SCLK

DOUT

conversion

in progressEOC Clock out serial data

trailingzeros Idle

Track/holdstate hold Track hold

7.5 s

tCON 0 s 12.5 × 0.476 s = 5.65 s0.24 s

tCS

Total = 13.7 s

Cycle Time

Figure 11.17 Interface timing sequence



...

...

...

...tCH

tCL

CS

SCLK

DOUT

T/H

tCS0

tCONV

Figure 11.18 Detailed serial-interface timing

B2 B1 B0

tCS

tTR

tD0

tSTR

Hold (Track/Acquire)tAPR

tDV

Parameters Symbol Min (ns) Max (ns)

Acquisition timeConversion timeAperture delaySCLK fall to output data validCS fall to output enableCS rise to output disableSCLK pulse width highSCLK pulse width lowSCLK low to CS fall setup timeDOUT rise to SCLK riseCS pulse widthSCLK clock frequency (MHz)

tACQtCONVtAPRtDOtDVtTRtCHtCLtCS0tSTRtCS

fSCLK

1.55.5

20

200200500

2400

Typ (ns)

30 7.5

200240240

2.1

Table 11.4 MAX1241 timing parameters



Interfacing the MAX1241 with the 68HC11

SS

SCK

MISO

CS

SCLK

DOUT

68HC11

MAX1241

Figure 11.19 SPI connection to the MAX1241

AIN

5V

GND

5 V0.1 F

V DD REF

SHDN

analog input

Procedure for A/D conversion

Step 1. Use a general-purpose I/O line (SS) to pull CS low. Keep SCLK low.Step 2. Wait for maximum conversion time. Alternately, look for DOUT rising edge to determine the end of conversion.Step 3. Activate SCLK for a minimum 13 clock cycles. When interfacing with SPI, two bytes are transferred. The first bit is a 1 followed by 12 data bits and three zeros.Step 4. Pull CS high at or after 13th falling clock edge (actually 16th clock edge)Step 5. With CS = high, wait for the minimum specified time, tCS, before initiating a new conversion by pulling CS low.



first byte read second byte read

SCLK

CS

DOUT* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LSB

High-Z

EOC

* When CS is high, DOUT = high-Z

Figure 11.20 SPI serial interface timing (CPOL = CPHA = 0)

tCON

MSB

Reading A/D Result with two SPI Transfers



Example 11.15 Write a subroutine to perform an A/D conversion operation for the circuitshown in Figure 11.19 and return the result in double accumulator D.Solution: REGBAS EQU $100DDRD EQU $09SPCR EQU $28SPSR EQU $29SPDR EQU $2ACS EQU $20 ; value to select the CS pinDOUT EQU $04 ; value to select the DOUT pinget_sample PSHX

PSHYLDX #REGBASLDAA #$3ASTAA DDRD,XLDAA #$50STAA SPCR,X ; set transfer rate to 1 Mbits/s, set master modeBCLR PORTD,X CS ; start an A/D conversionBRCLRPORTD,X DOUT * ;wait until DOUT goes highSTAA SPDR,XBRCLRSPSR,X $80 * ; wait until the SPI transfer is completeLDAA SPDR,X ; place the upper byte of the A/D result in A



STAB SPDR,X ; shift in the lower byte of the conversion resultBRCLRSPSR,X $80 * ; wait until SPI transfer is completeLDAB SPDR,X ; place the lower byte in BBSET PORTD, X CS ; prepare for the next A/D conversionLSLA ; clear the bit 7 of accumulator ALSRA ; “LSRD ; place the 12-bit A/D result in the lower 12 bits of DLSRD ; “LSRD ; “PULYPULXRTS



In C language,

unsigned int get_sample ( ){

unsigned char x1;unsigned int a2d_result;DDRD = 0x3A;SPCR = 0x50;PORTD &= 0xDF; /* start an A/D conversion */while (!(PORTD & 0x04)); /* wait until conversion is complete */SPDR = 0x00; /* shift in the upper byte of the A/D result */while (!(SPSR & 0x80)); /* “ */x1 = SPDR;SPDR = 0x00; /* shift in the lower byte */while(!(SPSR & 0x80)); /* “ */PORTD |= 0x20; /* disable A/D converter */a2d_result = x1 * 256 + SPDR; /* combine upper and lower bytes */a2d_result = a2d_result << 1; /* place the A/D result in the lower 12 bits */a2d_result = a2d_result >> 4; /* “ */return a2d_result;

}

h. huang transparency no.11-1 the 68hc11 microcontroller chapter 11: 68hc11 analog to digital...

Documents