green transistor for 10x lower ic power ?
DESCRIPTION
Green Transistor for 10X Lower IC Power ?. Chenming Hu University of California, Berkeley Supported by: DARPA STEEP, FCRP-MSD. the world enabled. electronic systems. IC chips. fabs. transistors. Electronics Infrastructure. $. 6/2009 Chenming Hu. Expectation: ICs will be even more. - PowerPoint PPT PresentationTRANSCRIPT
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Green Transistor for 10X Lower IC Power ?
Chenming Hu
University of California, Berkeley
Supported by: DARPA STEEP, FCRP-MSD
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Electronics Infrastructure
6/2009 Chenming Hu
the world enabled
IC chips
fabs
transistors
30nm
Buried Oxide
27nm
30nm
Buried Oxide
27nm
electronic systems
$
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Expectation: ICs will be even more..
• Affordable (size reduction..): manufacturing, device physics limit,…
• Useful (speed, density..): natural human interface, bio-medical sensing…
• Usable (low power): heat management, portability, global energy conservation…
6/2009 Chenming Hu
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Power Consumption Problems
1.Thermal management/package issues may limit integration density.
2. IC usage of electricity at an inflection point.
• ICs use a few % of world’s electricity today and growing exponentially.
• Power per chip is growing.
• IC units in use also growing.
3.Need to reduce IC power consumption with architecture and circuit innovations, and a low voltage transistor.
6/2009 Chenming Hu
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• Because power consumption Vdd2
• and Vdd (operation voltage) scaling has slowed.
High Performance ITRS Roadmap
Technology Node
0.25 μm
0.18 μm
0.13 μm
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm
Vdd 2.5 V 1.8 V 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V 0.8 V 0.7 V
IC Power Consumption Rising Much Faster Than Past Trend
6/2009 Chenming Hu
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Why Vdd scaling slowed
•We used to control power by scaling Vdd and maintain good speed by reducing Tox.
•But, Tox can not be reduced much more, not even with high-k dielectrics.
•But new materials will raise the mobility, μ
1.2 nm SiO2
Speed transistor current μ ( Vdd – Vt ) / Tox
6/2009 Chenming Hu
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New material, e.g. Ge film on Si substrate
Industry is also funding InGaAs, InAs, and graphene MOSFET research.
Oxide
Silicon
DrainSource
Gate
3nm Ge film
6/2009 Chenming Hu
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How to Reduce Power by 20X
Two steps to reduce Vdd to 0.2V for 20x power
reduction?
1. Reduce Vdd – Vt to < 0.15V with high-mobility-
channel material (Ge, III-V, graphene...), etc.
2. Reduce Vt to 50mV. But, there is the fundamental 60mV/decade turn-off limit …..
6/2009 Chenming Hu
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9
Lowering Vt by 60mV increases the leakage current (power) by 10 times.
Vs
Vt
dd eVtVgIVgI
)()0(
Source: Intel Corporation
6/2009 Chenming Hu
Vt
Dra
in C
urr
ent,
ID
S (A
/ m
)
Gate Voltage, VGS (V)
0.0 0.3 0.6 0.910
-11
10-9
10-7
10-5
10-3
Lower
Vt
Ioff Limit - 60mV/decade Swing
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The “fundamental” 60mV/decade Limit
Electrons go over a potential barrier. Leakage current is determined by the Boltzmann distribution or 60 mV/decade, limiting MOSFET, bipolar, graphene MOSFET…How to overcome the limit:Let electrons go through the energy barrier, not over it tunneling
106/2009 Chenming Hu
Ec
Ev
COX
VG
Source Channel Drain
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Semiconductor Band-to-Band TunnelingEC
EV
6/2009 Chenming Hu
A known mechanism of leakage current since 1985.
J. Chen, P. Ko, C. Hu, IEDM 1985
Called Gate Induce Drain Leakage (GIDL) because the current depends on the gate voltage.
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Basic Tunnel Transistor Structure
Some references
~100X less current than MOSFET
Need a more optimal tunneling transistor structure.
P+ DrainN+ Source P-
12
W. Reddick, G. Amaratunga, Appl. Phys. Letters, vol. 67, 1994.W. M. Reddick, et al., Appl. Phys. Lett., vol. 67(4), pp. 494-497, 1995.C. Aydin, A. Zaslavsky, et al., Appl. Phys. Lett., vol. 84(10), pp. 1780-82, 2004.WY. Choi et al., Tech. Dig. Int. Electron Device Meet, pp. 955-958, 2005.K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006.Th. Nirschl, et al., Electron Device Letters, vol. 28(4), p. 315, 2007.
6/2009 Chenming Hu
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Large field, good capacitive coupling between gate and pocket, abrupt turn-on due to over-lap of valence/conduction bands, adjustable tun-on voltage.
Green Transistor (gFET)--Simulation
13
Energy band diagram
Simulated carrier generation rates
Hole flow
Electron flow
N+ Source
P+ Pocket Gate
P+ Drain
N+ P+
Buried Oxide
P+ Pocket
P-
6/2009 Chenming Hu
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
G
DS
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gFET vs Basic Tunnel FET-simulation
* K. K Bhuwalka, et al., Jpn. J. of Appl. Phys., vol. 45(4B), pp. 3106-3109, 2006
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
I DS
(A/u
m)
VGS (V)
EOT= 1 nm VDD=1V Lg=40nm
Gate Voltage, VGS (V)
gFETEOT= 4.5 nm VDD=4V
Dra
in C
urre
nt, I
DS (
A/µm
)
Basic Tunnel FET *
6/2009 Chenming Hu
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
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Simulated Id-Vd of 0.5V Ge gFET
• Good output resistance and DIBL. Lg = 40nm
0
100
200
300
400
500
600
700
800
0.0 0.1 0.2 0.3 0.4 0.5
Ids (u
A/um
)
Vgs (V)
Vgs: 0.5 V
Vgs: 0.4 V
Vgs: 0.3 V
Drain-Source Voltage, VDS (V)
Dra
in C
urre
nt, I
DS (
µA/µ
m)
EOT=0.5nm
6/2009 Chenming Hu
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
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Vdd (Power) Scaling Path: Reduce Band Gap
C. Hu et al, 2008 VLSI-TSA, p.14, April, 2008
6/2009 Chenming Hu
1E-11
1E-10
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
0.0 0.2 0.4 0.6 0.8 1.0
Ids (A/um)Eg=0.36eV (InAs)Eg=0.69eV (Ge)Silicon
Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS
Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS
Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS
Gate Voltage, VGS (V)
Dra
in C
urre
nt, I
DS (
µ/µm
)
Lg=40nm
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P+ Source N+ Drain
B Substrate
Gate
AEC
EV
Gat
e O
xid
e
~~~~~~~~
~~~~~~~~
Gate
A B
Egeff
Hetero-tunneling gFET• In lieu of low Eg semiconductor, a heterojunction can provide a very small effective tunneling band gap, Egeff.
Egeff is 0.3eV for Si/Ge hetero-tunneling gFET.
6/2009 Chenming Hu
A. Bownder et al., 8th International workshop Junction Technology, Extended Abstracts , p.93, 2008. AlsoIEEE Silicon Nanoelectronics Workshop, 2008.
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Compound Semiconductors
18
Egeff
•Example: InAs-AlGaSb provides tunable Egeff from positive to negative values.
• Very low voltage gFET may be possible.
• Wide choices of heterojunction materials, band engineering and strain engineering.
6/2009 Chenming Hu
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Source
SiO2
Si N+ Si
Drain
P+ Ge
Gate
I D [A
/m
]
Experiment
Model
VGS [V]
Ge-Source Tunnel Transistor
S. Kim et al., VLSI Tech Symp., 2009
)/exp( ssD EBAEI
Es = |VGS+Vtunnel|/(Toxge/ox)
Vtunnel ~ 0.6VS [m
V/d
ec]
ID [A/m]
VD=0.5V
LG=5m
W=0.33m
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Green’s Function Based SimulationSayeef Salahudin
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• ICs use of world’s electricity is several % and growing fast.
• A low voltage transistor can slow the growth.
• Green Transistor may potentially provide orders-of-magnitude IC power reduction.
Summary
6/2009 Chenming Hu