giuseppe de robertis - infn sez. di bari 1 seu – set test structures

Giuseppe De Robertis - INFN Sez. di Bari 1

SEU – SET test structures


The SEU/SET problem

Red flash symbols are for SEUBlue flash symbols are for SET

Not only SEU



Generic combinatorial logic

x

y

z

x

F(x,y,z)F f

clk

clk

y

clk

z

clk

A generic synchronus logic to make function F(x,y,z)

Input registers Combinatory logic Output register


SEU protection – Hamming code

x

y

z

F(x,y,z)F f

clk

Input registerHamming coded

Combinatorial logicOutput register

Hamming codedE

rror

cor

rect

ion

clk

Enc

odin

g

Err

or c

orre

ctio

n

clk

Enc

odin

g

• Full protection on Single bit error in each register• No SET protection


SEU+SET protection – TMR(1)> x

y

z

xA

xB

xC

xAxBxC

yAyByC

zAzBzC

F(x,y,z)F fA>

>

clk

clk

> x

y

z

xAxBxC

yAyByC

zAzBzC

F(x,y,z)F fB>

>clk

> x

y

z

xAxBxCyAyByC

zAzBzC

F(x,y,z)F fC>

>clk

clk

clk

yA

yB

yC

clk

clk

clk

zA

zB

zC

clk

clk

clk


SEU+SET protection – TMR(2)

• Full protection from SEU and SET

but

• Need to replicate ALL register and combinatorial logic three times

• Need to triplicate all signals

• No SET protection for primary inputs


x

y

z

FclkA

clkB

clkC

> f

clkA

clkB

clkC

>

clkA

clkB

clkC

>

clkA

clkB

clkC

>

x

y

z

clkA

clkB

clkC

F(x,y,z)

SEU+SET protection – TTR(1)

Clock delay > FF setup+hold + Transient_max_time


SEU+SET protection – TTR(2)

• Full protection from SEU and SET• Full SET protection for primary inputs• Insertion can be automatized!

but• Need to know Transient_max_time• Need to triplicate ALL register• Additional delay block are needed to meet the

hold time


Sensitive nets - CLOCK• A single clock signal driving all Flip-Flops is a

critical net. A transient on this net can corrupt more than one bit of a register

• We can use large clock drivers to minimize transient… but is not 100% safe

• In TTR we need in any case three indipendent clock trees

• In TMR we can triplicate the clock tree: a transient on one clock net will corrupt only one of the three register Flip-Flops


Sensitive nets - RESET• A transient on global reset can corrupt

more than one bit of a register

• We can use large buffers to minimize tansient… but is not 100% safe

• In TMR and TTR we can triplicate the reset signal: a transient on one reset net will corrupt only one of the three register Flip-Flops


Scan path• In redundant circuits a single permanent fault is

not detectable because it is masked from redundance. It is mandatory to use scan path to make the device factory testable

• Scan Enable is a critical net for SET: a transient can corrupt a lot of Flip-Flops

• In TMR and TTR we can use three indipendent scan chain with three Scan-Enable signals


TMR implementation/* Standard version*/module counter8(en, clk, resetnn);input en;input clk;input resetnn;reg [7:0] Counter;

always @(negedge resetnn or posedge clk) if (!resetnn) Counter <= 0; else if (en) Counter <= Counter+1;

endmodule // counter8

/* TMR version*/`include "tmr.v" // majority function definition

// single modulemodule counter_X(out, CounterA, CounterB, CounterC, enA, enB, enC, clk, resetnn);output [7:0] out;input [7:0] CounterA, CounterB, CounterC;input enA, enB, enC;input clk, resetnn;reg [7:0] out;

// generate corrected inputswire en; assign en = `MAJ(enA, enB, enC);wire [7:0] Counter; assign Counter = `MAJ(CounterA, CounterB, CounterC);

always @(negedge resetnn or posedge clk) if (!resetnn) out <= 0; else if (en) out <= Counter+1; else out <= Counter;endmodule

// TMR module module TMR_counter8(outA, outB, outC, enA, enB, enC, clkA, clkB, clkC, resetnnA, resetnnB, resetnnC);output [7:0] outA, outB, outC;input enA, enB, enC;input clkA, clkB, clkC;input resetnnA, resetnnB, resetnnC;

// three instancescounter_X CounterA(outA, outA, outB, outC, enA, enB, enC, clkA, resetnnA);counter_X CounterB(outB, outA, outB, outC, enA, enB, enC, clkB, resetnnB);counter_X CounterC(outC, outA, outB, outC, enA, enB, enC, clkC, resetnnC);endmodule // counter

Source code needs a complete rewrite!This is ERROR-PRONE


Hamming implementation

• Verilog description

• Clock tree synthesis using only maximum size buffers


TTR implementationA TCL script has been used to implement TTR protection during synthesis. It performs the following tasks:

1. Replace each register with three registers using three different clocks and Resets;

2. Add the majority logic at registers outputs;3. Modify hierarchical structure to triplicate clock and reset4. Add at top level a clock generator and a reset generator5. Add three scan chains with three scan-enable signals

clk

clkA

clkB

clkC

reset

resetA

resetB

resetC

X

X

> X’X’


STRURED Blocks

TTR Test

HAMMING Test

TMR Test

In[7:0]

CLK

Out_TTR[7:0]

Out_TMR[7:0]

Out_HAM[7:0]

SHIFT REGISTER [256 bits]In[0] Out_SR


XOR Matrix

Test Block diagram

Out[7:0]

Control FSM

In[7:0] 7:015:823:16

63:56

7:0

15:8

23:16

63:56

KEY64

Matrix element

Matrix have 26 rowsof 64 bits

Matrix row


XOR Matrix element

{Key[62:0],Key[63]}

Clk

In[63:0]

Clk

KeyOut[63:0]

8 XOR cells

Out[63:0]


Implementation comparison

Protection Active area

[um2]Gates Cells

Hamming 603402 139676 45329

TTR 792783 183514 45656

TMR 1045804 242084 69309


Implementation comparison (2)

0,00E+00

2,00E+05

4,00E+05

6,00E+05

8,00E+05

1,00E+06

1,20E+06

Active Area (um2)

Hamming

TTR

TMR

0,00E+00

5,00E+04

1,00E+05

1,50E+05

2,00E+05

2,50E+05

Gates

Hamming

TTR

TMR

0,00E+00

1,00E+04

2,00E+04

3,00E+04

4,00E+04

5,00E+04

6,00E+04

7,00E+04

Celles

Hamming

TTR

TMR


STRUctures for REDuntance chip

> x

y

z

xA

xB

xC

xAxBxC

yAyByC

zAzBzC

F(x,y,z)F fA>

>

clk

clk

> x

y

z

xAxBxC

yAyByC

zAzBzC

F(x,y,z)F fB>

>clk

> x

y

z

xAxBxC

yAyByC

zAzBzC

F(x,y,z)F fC>

>clk

clk

clk

yA

yB

yC

clk

clk

clk

zA

zB

zC

clk

clk

clk

x

y

z

FclkA

clkB

clkC

> f

clkA

clkB

clkC

>

clkA

clkB

clkC

>

clkA

clkB

clkC

>

x

y

z

clkA

clkB

clkC

F(x,y,z)

x

y

z

F(x,y,z)F f

clk

Err

or c

orre

ctio

n

clk

Enc

odin

g

Err

or c

orre

ctio

n

clk

Enc

odin

g

TTR

TMR

Hamming

Test beam setup


High energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova, Italy)

Measure results


Internal stagesInput registers

Sat

LET0

Result summary


UNPROTECTED SHIFT

REGISTER

HAMMING TMR TTR

Sat (cm2/bit) 65.5·10-9 1.85·10-10 1.75·10-12 9.18·10-12

LET0 (MeV·cm2/mg)

1.82 0.93 18.5 18.5

Internal stages

giuseppe de robertis - infn sez. di bari 1 seu – set test structures

Documents

set slide

robertis infn sez

seu giuseppe

set protection tmr1

set protection tmr2

set protection ttr2

signals slide

register flipflops