Georgia Institute of TechnologySchool of Electrical and Computer Engineering

Gigabit Optical EthernetECE 4006c Design Spring 2002 Group G1

ProfessorsNan Jokerst

Martin Brooke

Group MembersRyan BaldwinDavid Gewertz

Geoffrey Sizemore

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Table of Contents

Abstract ........................................................................................................................................ 2Gigabit Ethernet History.............................................................................................................. 3IEEE 802.3z ................................................................................................................................. 3Gigabit Ethernet Software Overview ........................................................................................... 4Gigabit Ethernet Hardware Overview......................................................................................... 6Cabling Concerns ........................................................................................................................ 7Making A Fiberoptic Link............................................................................................................ 8Previous Research ....................................................................................................................... 8Test Specifications ..................................................................................................................... 14Design Proposal......................................................................................................................... 16Test-Bed Setup ........................................................................................................................... 16Maxim Evaluation Kit Test Results............................................................................................ 18Logistics and Board Design....................................................................................................... 22Eliminating Portions of the Evaluation Boards......................................................................... 22Board Layout ............................................................................................................................. 23Board Assembly ......................................................................................................................... 25Board Testing............................................................................................................................. 27Conclusions................................................................................................................................ 29Bibliography .............................................................................................................................. 31Appendix A ................................................................................................................................. 32

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Abstract

The design of cheaper and more efficient Gigabit Ethernet devices was the main objective

of this project. The larger design picture revolved around the specific portion of the transceiver

we were assigned to, the receiver. By examining the wealth of information gathered from

previous semesters as well as that provided with the Maxim Kits, we were able to design a cost-

effective receiver board for use in a Gigabit transceiver module. Legacy testing verified the

functionality of the previous test-bed, which mainly served as a resource for knowledge. Maxim

Evaluation Kits for a transimpedance amplifier and post amplifier were studied and tested in lab

using the newly acquired Gigabit Test Equipment. Finally, a board was laid out in the

E.A.G.L.E. design environment and manufactured on campus. This board was put to the same

rigorous bit pattern tests as the evaluation boards, and overall, the results were successful. More

testing is required to determine the full functionality of this board with the other opto-electronic

devices of the transceiver.

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Gigabit Ethernet History

Dr. Robert Metcalf invented the basis for Ethernet in the mid-1970’s at the Xerox Palo

Alto Research Center. The idea was that the office of the future would have a personal computer

and would then need a means of communication with a mainframe and other computers in the

office. The Xerox Alto was to be the first desktop computer in the “office of the future.” The

initial design ran at 3Mbps and was known as “Experimental Ethernet.” The formal

specifications were agreed upon by the three main players in the industry: Xerox, Intel, and DEC.

The original, “Experimental Ethernet”, was expanded to 10-Mbps and standardized by IEEE in a

production quality form.

IEEE 802.3z

Recent technologies, such as ATM and FDDI, have commanded a large market share;

pushing Ethernet out of the backbone of the network and confining it to the end user. ATM and

FDDI technologies delivered higher speeds to keep up with the demands for greater throughput

and higher bandwidth applications. The introduction of Gigabit Ethernet has quickly changed

this trend. The simplicity and reliability of Ethernet is ideal, as long as it can support the

bandwidth required. IEEE 803.2z was introduced as the new Gigabit Ethernet standard. This

single standard allowed for interoperability between any type of Gb Ethernet equipment. The

standardization effort began in mid-1995, with a push to have things done as soon as possible. A

rough draft was completed in 1997 and then in June of 1998 the technology was standardized by

IEEE. The real value to the end user was that Gigabit Ethernet was built off the Ethernet

platform, and it works seamlessly with Ethernet and FastEthernet.

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Gigabit Ethernet Software Overview

Gigabit Ethernet is designed on standard Ethernet frame format so that its integration

would be as seamless as possible. Ethernet and Fast Ethernet therefore do not require frame

translation in order to interface with Gigabit Ethernet. When Xerox first designed the Ethernet

Figure 1. Ethernet Address Fields

protocol, a type field was required (see Figure 1). In the IEEE 802.3 specifications, the type field

has been changed to a length field, telling the receiver how many bytes are in the packet. This

leaves the protocol distinction in the data portion of the packet.

In order to better comprehend the hardware technology behind Gigabit Ethernet, the

physical layer must be understood. Gigabit Ethernet technology was created in 1998 with the

convergence of the IEEE 802.3 Ethernet and ANSI X3T11 FiberChannel standards. Figure 2

shows the features from both standards that were combined in the IEEE 802.3z standard.

Figure 2. Merging of IEEE 802.3 and ANSI X3T11 Standards

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There are four mediums for Gigabit Ethernet communication; two purely fiber optic, and

two integrated with copper. The 1000BaseSX standard works with multimode fiber (using short-

or long-wave lasers), and the 1000BaseLX works with single mode fiber (using long-wave

lasers). The copper based standards are 1000BaseT (using CAT5 twisted pair copper) and

1000BaseCX (using shielded 150 ohm copper cable). Our research will focus on the fiber-based

standards, since they provide high bandwidth over a much longer distance than copper based

Gigabit Ethernet (see figure 3).

Figure 3. The four Gigabit Ethernet Standards

The quickest and easiest way to integrate Gigabit Ethernet in a fast Ethernet

environment is to replace Fast Ethernet switches with Gigabit Ethernet switches, and install

Gigabit Ethernet NIC’s (network interface cards) in the servers. Since Gigabit Ethernet is

backwards compatible with Fast Ethernet, these are the only changes in the network necessary

that will result in greater bandwidth availability. Our research will focus on designing a NIC for

Gigabit Ethernet that is both cost effective and robust.

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Gigabit Ethernet Hardware Overview

We will be using the Intel Pro/1000 XF Server adapter in our test bed. This fits into the

PCI slot of the server’s motherboard, which is important because the server bus must be able to

handle 1 Gb/second data rates. Table 1 shows throughput of several computer bus types, and

demonstrates why Gigabit Ethernet NIC’s must use a PCI bus.

Table 1. Data Throughput for different server bus types

Bus Type Throughput

ISA 64 Mb/s

EISA 264 Mb/s

MCA 320 Mb/s

PCI (32 Bit, 33 MHz) 1056 Mb/s

PCI (32 Bit, 66 MHz) 4224 Mb/s

The most expensive component of the NIC is the transceiver. The transceiver contains the

transmitting laser, photodetector, optical subassemblies, electrical subassemblies, and the

packaging housing. The 1000BaseSX standard uses shorter wavelength transmitters (770-860nm)

than 1000BaseLX (1270-1355nm). Shorter wavelength transmitters are less expensive than

higher wavelength transmitters, but the signals can’t travel as far (500m vs. 3km). Last

semester’s groups utilized the Agilent HFBR-53D5 family of 850nm VCSEL (vertical cavity

surface emitting lasers).

To improve on error rates, we will continue the work of past groups in converting the

transceiver’s single ended input into a differential input. The single ended input has a high error

rate because it uses a fixed reference to the input signal. Differential inputs reduce noise by

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comparing an actual signal with its inversion. We will use Maxim evaluation boards to test

Maxim amplifiers and optoelectronic components in designing a new and improved NIC that

takes advantage of differential signaling.

Cabling Concerns

Most LAN systems currently rely on unshielded twisted-pair (UTP) technology.

Engineers are more familiar with the phrase Category 5, the most widely used standard of UTP

cable. The distance restrictions of UTP cables are the driving force behind the use of fiber optic

cables in the LAN. Table 2 shows a comparison between the current Ethernet technologies and

Table 2. Fiber Vs. Copper (UTP)

their relative distance restrictions. As one can see, the current limit on copper is 25 meters for

Gigabit Ethernet. Unfortunately distance restrictions are not the only thing hampering copper

cabling. Fiber is much thinner and lighter than copper cable, and fiber cable is immune to the

electromagnetic noise that is created by most pieces of electronic equipment; copper is not. Fiber

does have its drawbacks. It is expensive to manufacture and difficult to maintain because of the

fragile nature of the cable.

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Making A Fiberoptic Link

Making a fiberoptic link involves three main components: input, output, and

optoelectronics. A photodetector detects light waves of a certain frequency and then passes the

digital electrical information to the receiver of the circuit. The input, or the receiver, is

implemented with two amplifiers, a transimpedance amp and a post amp. The output, or the

transmitter, of any fiberoptic link is made up of a laser driver that powers a laser diode.

Much like information over a copper cable, data over fiber consists of digital bits of

information; each bit being a ‘1’ or ‘0’. These bits are put together into packages called packets.

Packets make up the majority of network traffic. In order to transmit packets over fiber, the DC

signals of 5 volts and 0 volts must first be converted into light waves. These operations are handled

by the laser diode. Once an electrical current hits the driver, it is passed to the diode. Depending

on the state of the bit, either a pulse is emitted or no pulse is emitted. These pulses are detected at

the other end by the photodetector and the bits are passed into the remaining portion of the circuit

to be analyzed. This portion of the circuit, the receiver, is the part of the transceiver that our group

will be concentrating our design efforts on.

Previous Research

A strong understanding of the research that was done, and the modifications that were

made last semester is the basis for future improvement. The task of our predecessors was to

understand the Intel Gigabit Ethernet card to the point that they were able to remove the optical

sensors from the board and build their own board (see Figure 4 on next page). Once their board

design was completed, the next task was to interface the new components to the remaining

portion of the Intel Gigabit card. Our design goals are to further break down the components of

the Intel card by replacing last semester’s opto-module board. Instead of using the original

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Figure 4. Previous Semester’s Board Design

Agilent optomodule on the Intel board, we will design a receiver board using Maxim chips that

will interface with separate transmitter and optoelectronic boards. We will study some of the

major problems that the previous groups encountered so as not to repeat the same mistakes in our

implementation.

The previous group that worked on this project found that there was a great deal of

circuitry that was dedicated to power manipulation. One power supply powered the entire card,

and there were at least 3 different components that required different currents. Both the receiver

and the transmitter required a +5 volt power supply, but they were connected in parallel. As a

result, they isolated the two power supply lines to prevent interference. Another reason why Intel

designed the card with the extra circuitry was due to the limitation of only having one power

supply to work with. Last semesters group and our group will have the luxury of using multiple

power supplies if so desired, thus eliminating the need for the complex circuitry.

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Noise is a very important concern when we are trying to achieve high data rates. The

more noise that is introduced into the circuit, the lower the chance of producing a reliable and

accurate output. Using different power supplies was the first step that was taken to ensure

electrical isolation. Another important factor that must be taken into account is decoupling

capacitors. Separate power supplies isolate one component from another, and decoupling

capacitors protect these components from the irregularities of the power supply that is driving

that component. This not only protects the circuitry, but also keeps the electrical noise that is

introduced to a minimum.

Transmission lines have the potential to introduce so much noise that the data would be

corrupted to a point where it was rendered useless. This was of great interest to the previous

designers, and proved to cause more problems than anticipated for them. Since we will be

working with frequencies above 1 GHz, we cannot use through-hole components since they may

act like transmission lines. The smaller the components used (SMT), the less chance they will

act like transmission lines. When selecting components, we must take the critical frequency into

consideration. The impedance changes as a frequency rises above the component’s critical

frequency, which alters the properties of the component and may act like a transmission line.

Generally the critical frequency depends inversely on the value and size of the capacitor or

inductor. Regulating the length of the connections on the board eliminates another element of

transmission line interference. In order to have a 10% signal error, the optimal length should be

λ/10; a 1% error would be λ/100, etc. In order to calculate λ, we will use the formula given in

Equation 1. In this equation, c is the speed of light (3x108 m/s), n is the index of refraction

(based on the material properties of the board material), and f is the desired frequency.

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nfc=λ Equation 1

Using an epoxy PCB (n=3), and a safe frequency of 2.5 GHz, the resulting length is 4mm.

Lengths ranging from 10 to 15 millimeters were reported by previous teams as being optimal.

Impedance matching was another concern that was addressed. A 50-ohm termination was

required on either side of a transmission line to avoid signal reflection. Tapered trace lines will

also lower RF impedance, compared to a trace that has a hard 90-degree angle.

This understanding was applied to future work with the Maxim board and in our personal

design. Our next step was to investigate the circuitry of the Maxim evaluation boards, and figure

out how to interface that hardware with the opto-electronics that is provided by the groups that

are researching that hardware.

Maxim Evaluation Kit

The Maxim 3266 Evaluation Kit, shown in Figure 5, is a board that is designed to

showcase the functionality of the MAX3266 chip. The basic circuit functionality of the chip is

signal cleanup. It also converts the single-ended input into differential output. When a signal is

taken in from a photodiode at very low signal levels, it is also slightly amplified to a level that

can be processed by the circuitry of the Intel card. The 3266 Evaluation Kit has circuitry that

emulates the output of a photodiode (1). Since we will be taking output from a real photodiode,

that is yet to be determined by the OE team, the photodiode emulation portion will be discarded

(1).

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Figure 5. MAX3266 Evaluation Kit

The Maxim 3266 chip (see Figure 6) requires a 10 μA – 1mA zero-to-peak signal from

the photodiode. Because a 50-ohm termination is required at each end of the signal, the signal

coming from the output of the photodiode is reduced by close to 50 percent. The existing 1k and

0.5k ohm input resistors (2) will be shorted and replaced with a ~66 ohm resistor placed in

parallel to deliver a 10 μA current. This circuit can be seen in Figure 5 (The photodiode

Figure 6. MAX3266 Operating Circuit

emulation portion and series resistors removed).

Photodiode Emulation Circuit (1)

Replace R1&R2 (2)

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The second board that we will be looking at is the Maxim 3264 Evaluation Kit

(see Figure 7). This board showcases the features of the MAX3264 chip. The chip

Figure 7. MAX3264 Evaluation Kit

has basically three set functions: buffering, limiting amplifier, and RMS power detection. The

buffer provides a 100-ohm input impedance between the two differential inputs. This

accentuates sharper edge transitions and maintains clean signal levels. The limiting amplifier

provides a 55 dB gain to the differential input signals. The output buffer provides high tolerance

to impedance mismatches and inductive connectors. Basically this means that it anticipates

problems further down the circuit. The output level of this circuit can be set to either 16 mA or

to 20 mA depending on the requirements.

Two chips are essential to this design because one complements the other. The

operational amplifiers and filters of the first chip in the series, the MAX3266, maintain the

linearity and integrity of the photodiodes output while at the same time converting it to a

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differential signal. The second chip, the MAX3264 shown in Figure 8, provides the necessary

gain that meets the needs of the TTL circuitry that resides on the Intel card.

Figure 8. MAX3264 Operating Circuit

Test Specifications

Our testing was similar to the testing performed by last semester’s design groups. We

used Agilent’s recommended Gigabit Ethernet test setup. For this setup, we planned on using

newly acquired BERTS, pattern generators, and oscilloscopes. This involved the Tektronix

GTS1250, which provides both the transmit signals, as well as the Tektronix TDS7154 series

oscilloscope, which comes with CSA software. We used the same 5-volt power supplies as last

semester’s groups. The pattern generator created random data signals and the oscilloscope’s CSA

package helped generate eye diagrams.

The eye diagram is used to test the distortion and possible collision of output signals. The

diagram, which derives its name from its appearance that is similar to the human eye, is

essentially a snapshot of the overlaying of all the different possible output signals. By measuring

the width of the “eye” at several locations, information on the signal’s integrity can be gathered.

The width of the “eye” can be used to determine the maximum time interval where the received

signal can be measured without interference from other signals. The angles of the edges of the

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eye are used to determine the sensitivity of the system to timing errors. The vertical height of the

eye is used to find the signal-to-noise ratio of the signal. Figure 9 shows the various

specifications for an eye diagram, and Figure 10 shows the expected eye diagram out of the

MAX3264 chip.

Figure 9. Specifications of Eye Diagram

Figure 10. Expected Eye DiagramsFinally, we used the Gigabit Ethernet test software provided with the Intel Pro/1000 card.

This was the final test in demonstrating that our highly modified card operates within all the

specifications of the original card.

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Design Proposal

Learning from the MAX3266 and MAX3264 chip diagrams, we intended to design a

receiver that was cheap and robust. Given the minute nature of the signal and the analog

conversion that is involved, we proposed a high-speed single-board design. This would prevent

line interference and would simplify the circuitry. We utilized the two amplifier circuits and the

chosen photodetector. Our board addressed the issues necessary to meet the high-frequency

demands of the application. One of these factors was transmission lines, which was discussed

earlier in the paper. Another major factor that must be addressed was conductor length. In Gb

Ethernet applications the traces must not be longer than approximately .7 inches. Finally,

impedance matching becomes especially significant at high frequencies because of the potential

for signal reflection and we intended to maintain proper functionality with 50-ohm terminations.

The implementation of our design was carried out using the smallest surface mount

components available. To increase the critical frequency we used 0204 components. We

implemented our design on a FR-4 PCB that is 0.062 inches thick. In order to lay out the board,

our group used a freeware version of E.A.G.L.E. software which can be downloaded from their

web page.[1] The specific parts and their values can be found in Appendix A.

Test-Bed Setup

Our first step in testing our design was to get the test-bed up and running. The previous

test-bed consisted of two PC’s, one with an unmodified Intel Pro/1000 Gigabit Ethernet Card,

and the other with the modified Gigabit Ethernet Card. This test-bed essentially tests whether the

cards work in the “real world”, i.e. establishing a medium where information can be exchanged

over a fiber optic network. After some basic lab supplies were located and purchased, the cards

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were installed in the machines and ready to be tested. A loop-back test was done between both

cards, connecting one card’s RX signal to the other card’s TX signal, and vice versa. The Intel

card’s diagnostic software, which is installed on both PC’s, sends data packets between both

cards and records any errors. Luckily, last semester’s modified card continued to work flawlessly,

as demonstrated by the successful test results shown in Figure 11. Two other simple tests were

executed to determine functionality of the setup. These tests transferred files from one PC to the

Figure 11. Successful Loop-back Test of Test-bed and Network Neighborhood Capture.

other, and checked if both PC’s could see each other on the Windows Network Neighborhood (see

Figure 11). Once again, the cards passed these tests and verified that the test-bed was robust enough

to be used for testing purposes.

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Maxim Evaluation Kit Test Results

In order to aid in our board design, testing was needed to see how well the Maxim chips

performed when configured according to Maxim’s recommendations. Performance was

determined by comparing the eye diagrams of the output of the evaluation kits to the specified

Maxim eye diagrams. Additionally, we connected the output of the MAX3266 Transimpedance

Amplifier to the differential inputs of the MAX3264 Limiting Amplifier to simulate the circuitry

of our receiver board. In order to perform these tests, the Tektronix GTS1250 Bit Pattern

Generator was used to generate pseudo-random bit streams (PRBS) at Gigabit speeds.

The first test was performed on the MAX3266 Evaluation kit. A variable output dual

power supply provided the necessary +3.3 VDC for the VCC of the chip, as well as the +15 VDC

for the photodiode emulation circuit. The GTS1250 was connected to the input of the MAX3266,

and the outputs were then connected to the Tektronix TDS7154 series oscilloscope. This

oscilloscope is equipped with the CSA software package, which has the IEEE 802.3z eye

diagram already loaded. The eye diagram was displayed on the oscilloscope by selecting the

Gigabit Ethernet option from the masks menu. Once the MAX3266 was connected to both the

GTS1250 and TDS7154, the signals neatly encapsulated the “eye” horizontally, but not

vertically. The reason for this is that the input signal (which would be from the photodiode) is

still not high enough in amplitude, and that is why the MAX3264 is used to further amplify the

signal. As shown in Figure 12, our results closely match the Maxim specifications, and nearly

pass the IEEE 802.3z specifications. Since the “eye” is open, the transmitted signal demonstrates

the low jitter characteristics of the chip.

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IEEE 802.3z Eye Diagram Spec Maxim Eye Diagram Spec

Measured Eye Diagram for MAX3266 Experimental Test Equipment

Figure 12. MAX3266 Eye Diagrams and IEEE 802.3z Mask with Test Equipment

The MAX3266 chip was also tested without the jumpers attached on the evaluation

board. This effectively eliminated the DC cancellation amplifier circuit on the chip, and resulted

in an unacceptable eye diagram, shown in Figure 13. This test made it obvious that there was a

need in the final design to incorporate this DC cancellation circuitry.

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Figure 13. Eye Diagram of MAX3266 without DC cancellation amplifier

The next step involved connecting the output of the MAX3266 to the inputs of the

MAX3264 chip, emulating a complete receiver circuit. The test was performed with the

GTS1250 connected to the input on the MAX3266 board, first with one of the outputs of the

MAX3266, and secondly with both differential inputs of the MAX3264 connected. The results

are shown in Figure 14 on the next page. The differential outputs seen in channel 1 and 2 are

slightly offset due to the fact that the lengths of the SMA cables are mismatched. Since this chip

provides tremendous amplification, the “eye” now easily fits over the IEEE mask, both

horizontally and vertically. The Post-Amp must be handled with caution due to the amount of

amplification it achieves. If a noisy signal in introduced prior to the Post-Amp, the data could be

corrupted to a point where it would be unusable. Appropriately placed decoupling capacitors

help to reduce the introduction of noise to these high-frequency signals. Also, there are power

supply filter networks present on the Maxim boards that inhibit any noise that may exist on these

lines. Our design will not incorporate the filter networks because of space and cost issues.

Instead two power supplies will be utilized.

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Maxim Eye Diagram Spec

Output with both inputs connected Output with one input connected

Figure 14. MAX3264 Eye Diagrams

Once the boards are fabricated and populated with components, these tests should be

successfully repeated with our design. An additional piece of testing will be performed once the

Bit Error Rate Test Set (BERTS) arrives. This device will be connected to the random bit

generator (GTS1250), and analyze the error rate of the output of the board. The full functionality

of our board will be investigated by testing for eye diagrams and PC-to-PC communication.

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Logistics and Board Design

One of the first issues discovered when testing our Maxim evaluation kits was the lack of

power supplies, power strips, and SMA cables in the lab. Six power strips (~$20) were ordered

from OfficeMax, as well as eight 12” long SMA cables ($36.30 each) and ten 48” long SMA

cables ($43.56 each) from Pasternak Enterprises. The shorter cables are for making connections

between boards for all groups, and the longer cables will be for connecting boards to test

equipment. Other groups have ordered power supplies, power connectors, and SMA connectors.

Our board design took into consideration Bob House’s board layout requirements, as he will be

building our board. The small trace size due to the small chip packaging required us to use very

small 0204 SMT resistors and capacitors.

Eliminating Portions of the Evaluation Boards

The circuitry on the evaluation boards was studied for better understanding of chip and

board functionality. The photodiode emulation could be eliminated because our board would be

receiving the signal from the board of the opto-electronics group. The Maxim boards

incorporated ferrite beads at the voltage supply inputs. Ferrite beads act as high-frequency

resistors, exhibiting very little inductance at high frequencies, and absorbing most of the high-

frequency noise from the supply lines. Ferrite beads, although useful, are not required, and will

not be utilized in order to limit the component count. Most of the other components on the board

were terminating resistors, coupling capacitors, or decoupling capacitors. They were required for

proper functionality of the receiver and were included in our design. The function of the

decoupling capacitors is to eliminate voltage spikes in the power supply lines. By putting

capacitors as close to IC power leads as possible, the transient current that is needed is supplied

by the capacitor thus removing the transients from supply lines. This serves to curb the

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propagation of transients to other parts on the board, while the close placement of the capacitor to

the IC will avoid creating lead inductance and therefore will not introduce ringing to the circuit.

Coupling capacitors ensure a steady AC current over signal traces. Terminating resistors prohibit

signal reflection, and all of the transmission lines in our board use 50-Ohm terminations.

Board Layout

The process of laying out the PCB began with a hand-drawn schematic of the circuit.

Using the MAXIM data sheets, each integrated circuit chip was studied to determine which pins

were necessary for correct functionality. The first chip, the TIA, was relatively easy to put down

on paper. There are only eight pins on this device. From the initial design stages of the project

we were certain that a resistor with a value of 66.7 Ω was needed in parallel with the input to

match the termination impedance from the photodetector. This simple result was achieved by

taking the parallel combination of the input impedance (200 Ω) with this resistor value to achieve

the necessary 50-Ω termination. The connections to the limiting amplifier chip were a little more

complex. This chip amplifies the signal level for use in current-mode logic (CML) circuitry. As

a result, the designer is given more freedom as to the operation of the chip. Features such as

“Squelch” and “Loss of Signal” are not vital to the initial operation of the chip so they will not be

utilized. The rest of the circuit’s design came from the typical operating circuit diagram on the

MAX3264 chip data sheet, seen in Figure 15.

Figure 15. Typical operating circuit of MAX3264 and MAX3266 chips.

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One of the most important features of any high-frequency PCB layout is the addition of

decoupling capacitors. Coupling is defined as the linkage of two traces by magnetic induction.

In order to reduce coupling, capacitors of the same value are placed between each supply pin and

ground. This reduces the presence of induction between the traces, which is especially important

at high frequencies where induction plays a larger role in impedance problems. Our initial hand-

drawn design (Figure 16) used 1 µF capacitors, but we intend to use 0.1 µF on the board.

Coupling capacitors allow AC current to pass through while preventing the transfer of DC

current. Since the correct operation of the Maxim chip is dependent on seeing only the produced

AC current of the photodetector, coupling capacitors provide the necessary roadblock for

Figure 16. Initial hand-drawn layout

unwanted DC current. Gigabit Ethernet applications require these capacitors to be greater than

.01 µF in order to minimize the deterministic jitter. In our design the resistors Rterm have a value

of 100 Ω.

The formal layout of the board was done in Eagle, a graphical layout editor. The freeware

version of Eagle allows for a board with dimensions large enough to meet the needs of our

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application (4” by 3.2”), and traces can be placed on either the top or bottom of the board. Figure

17 shows the initial layout of our PCB in Eagle.

Figure 17. Initial Eagle PCB Layout for Receiver Board

As suggested by our research efforts, we attempted to avoid right angle traces and we have made

the power and ground traces significantly larger than the other signals. Two power supplies have

been utilized to maintain isolation between the two chips. Another possible implementation of

this would be to have a long wire between the voltage traces for each separate chip. Decoupling

capacitors were oriented as close as possible to their supply lines so as to keep the inductance as

low as possible due to the fact that a high inductance will generate ringing (resonance) with the

IC.

Board Assembly

The PCB board files were delivered to Bob House and the board arrived back with no

issues. The parts for the board were all ordered from Digi-Key (see App. A). The components

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were extremely minute in nature and required very delicate handling when soldering. It was also

necessary to use thin silver solder and a temperature of only 575 degrees on the iron.

We immediately encountered some problems with the board layout though. The

diagrams for the surface mount power connectors were very confusing to follow. As a result, the

pads were placed on the boards backwards. To alleviate the issue initially, we soldered the

power connectors to thick wires (see Figure 18).

Figure 18. Front Side of PCB, with Power Connectors attached by wire

We weren’t positive whether this introduced noise or not, so the connectors were soldered

directly to the board later on in testing. We also had to place the SMA connectors on the bottom

side of the board since they were through-hole, and this may have created some electromagnetic

interference feedback issues. The material of the board and SMA connectors was not conducive

to our soldering techniques, and may have resulted in unpredictable or cold soldering joints.

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Board Testing

The procedure for testing the prototype board was exactly that of the Maxim Evaluation

boards. The GTS1250 was connected to the input of the MAX3266 and the differential output

was connected to the TDS7154 scope. We used the Iomega regulated 5V power supplies, as other

groups had problems with the cheaper unregulated supplies. A picture of our setup is shown in

Figure 19. We used the K28.5 signaling for testing, and this produced fairly good results. The

Figure 19. Test Setup

K28.5 coding is a standard form of encoding used in Gb Ethernet communication. However, our

receiver circuit did not seem to respond well to the PRBS7 coding. This may be due to the fact

that this is a more complex form of coding that required a more robust, noise free circuit. Our

results are shown in Figure 20. The eye was clearly visible with the K28.5 coding, and the bit

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K28.5 Eye Diagram PRBS7 Eye Diagram

K28.5 Bit Stream Output

Figure 20. Prototype Receiver Card Test Results for K28.5 and PRBS7 coding

pattern also looked fairly clean. Using the PRBS7 coding, the eye was barely visible. We

witnessed oscillation on certain bits in the K28.5 bit stream. Small adjustments with the way we

held the board, as well as the positioning of the power supply plugs seemed to vary the amount of

oscillation. After consulting with Dr. Brooke, we decided to reconfigure our power supply jacks

and solder them directly onto the board. We also tied the grounds from both power supplies

together. The results (Figure 21) were somewhat better than before. We noticed interference

between the power jacks when close together. There was also an unusual anomaly [1, Figure 21]

that was witnessed when the board was handled differently or the connectors were moved. We

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were unable to figure out exactly what caused this problem on the board when the connectors

were soldered directly to it.

K28.5 Pattern With Mystery Oscillation K28.5 Eye Diagram

Eye Diagram With Apparent Oscillation

Figure 21. K28.5 Signalling with Power Jacks Soldered Directly to Board

Conclusions

The initial objectives set forth at the beginning of the design project were threefold. An

Intel Fiberoptic NIC test-bed was set up and tested in the lab to verify legacy functionality.

Maxim Evaluation Kits were then utilized to get an understanding of the circuit topography as

well as the test equipment set-up procedures. Finally, a working prototype board was designed,

manufactured, and tested. The overall results met the design specifications.

1

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Continuing work on this design should focus on the problems encountered with the

prototype board. Ground interference and power supply cross-talk were issues that needed to be

investigated further. It displayed abnormalities when more stringent bit pattern tests were

administered. For the most part, though, our board met the specifications for proper Gigabit

Ethernet functionality. Work must also be done to interface the board with an actual

photodetector, which could not be accomplished this semester.

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Bibliography

Background

Gigabit Ethernet Technology and Solutionshttp://www.intel.com/network/connectivity/resources/doc_library/white_papers/gigabit_ethernet/gigabit_ethernet.pdf

Fall 2001 Design Team Web Pageshttp://www.ece.gatech.edu/academic/courses/fall2001/ece4006/

Design/Testing

Maxim Data Sheets for Max3266 and Max3264http://pdfserv.maxim-ic.com/arpdf/MAX3266-MAX3267.pdfhttp://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=1968http://pdfserv.maxim-ic.com/arpdf/MAX3264-MAX3765.pdfhttp://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=2100

Analog Tutorials and FAQ’shttp://www.channel1.com/users/analog/tutor.html

Lectures from Professors Jokerst and Brooke during Spring 2002

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Appendix ATable of Part Values and Components Used

Value Quantity

Resistor 66.7 1

100 2

Capacitor .01 uF 4

.1 uF 4

1000 pF 1

SMA Connector 3

Power Jack 2